PY32F002Zxx.svd 159 KB

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  1. <?xml version="1.0" encoding="utf-8" standalone="no"?>
  2. <device schemaVersion="1.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" noNamespaceSchemaLocation="CMSIS-SVD.xsd">
  3. <vendor>Puya</vendor>
  4. <vendorID>Puya</vendorID>
  5. <name>PY32F002Zxx</name>
  6. <series>PY32F0</series>
  7. <version>1.0.0</version>
  8. <description>Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz.</description>
  9. <cpu>
  10. <name>CM0+</name>
  11. <revision>r0p1</revision>
  12. <endian>little</endian>
  13. <mpuPresent>false</mpuPresent>
  14. <fpuPresent>false</fpuPresent>
  15. <nvicPrioBits>4</nvicPrioBits>
  16. <vendorSystickConfig>false</vendorSystickConfig>
  17. </cpu>
  18. <addressUnitBits>8</addressUnitBits>
  19. <width>32</width>
  20. <size>32</size>
  21. <access>read-write</access>
  22. <resetValue>0x0</resetValue>
  23. <resetMask>0xFFFFFFFF</resetMask>
  24. <peripherals>
  25. <peripheral>
  26. <name>ADC</name>
  27. <description>Analog to Digital Converter</description>
  28. <groupName>ADC</groupName>
  29. <baseAddress>0x40012400</baseAddress>
  30. <addressBlock>
  31. <offset>0x0</offset>
  32. <size>0x400</size>
  33. <usage>registers</usage>
  34. </addressBlock>
  35. <interrupt>
  36. <name>ADC</name>
  37. <description>ADC Interrupts</description>
  38. <value>12</value>
  39. </interrupt>
  40. <registers>
  41. <register>
  42. <name>ISR</name>
  43. <displayName>ISR</displayName>
  44. <description>ADC interrupt and status register</description>
  45. <addressOffset>0x0</addressOffset>
  46. <fields>
  47. <field>
  48. <name>EOSMP</name>
  49. <description>ADC group regular end of sampling flag</description>
  50. <bitRange>[1:1]</bitRange>
  51. </field>
  52. <field>
  53. <name>EOC</name>
  54. <description>ADC group regular end of unitary conversion flag</description>
  55. <bitRange>[2:2]</bitRange>
  56. </field>
  57. <field>
  58. <name>EOSEQ</name>
  59. <description>ADC group regular end of sequence conversions flag</description>
  60. <bitRange>[3:3]</bitRange>
  61. </field>
  62. <field>
  63. <name>OVR</name>
  64. <description>ADC group regular overrun flag</description>
  65. <bitRange>[4:4]</bitRange>
  66. </field>
  67. <field>
  68. <name>AWD</name>
  69. <description>ADC analog watchdog flag</description>
  70. <bitRange>[7:7]</bitRange>
  71. </field>
  72. </fields>
  73. </register>
  74. <register>
  75. <name>IER</name>
  76. <displayName>IER</displayName>
  77. <description>ADC interrupt enable register</description>
  78. <addressOffset>0x4</addressOffset>
  79. <fields>
  80. <field>
  81. <name>EOSMPIE</name>
  82. <description>ADC group regular end of sampling interrupt</description>
  83. <bitRange>[1:1]</bitRange>
  84. </field>
  85. <field>
  86. <name>EOCIE</name>
  87. <description>ADC group regular end of unitary conversion interrupt</description>
  88. <bitRange>[2:2]</bitRange>
  89. </field>
  90. <field>
  91. <name>EOSEQIE</name>
  92. <description>ADC group regular end of sequence conversions interrupt</description>
  93. <bitRange>[3:3]</bitRange>
  94. </field>
  95. <field>
  96. <name>OVRIE</name>
  97. <description>ADC group regular overrun interrupt</description>
  98. <bitRange>[4:4]</bitRange>
  99. </field>
  100. <field>
  101. <name>AWDIE</name>
  102. <description>ADC analog watchdog interrupt</description>
  103. <bitRange>[7:7]</bitRange>
  104. </field>
  105. </fields>
  106. </register>
  107. <register>
  108. <name>CR</name>
  109. <displayName>CR</displayName>
  110. <description>ADC control register</description>
  111. <addressOffset>0x8</addressOffset>
  112. <fields>
  113. <field>
  114. <name>ADEN</name>
  115. <description>ADC enable</description>
  116. <bitRange>[0:0]</bitRange>
  117. </field>
  118. <field>
  119. <name>ADDIS</name>
  120. <description>ADC enable</description>
  121. <bitRange>[1:1]</bitRange>
  122. </field>
  123. <field>
  124. <name>ADSTART</name>
  125. <description>ADC group regular conversion start</description>
  126. <bitRange>[2:2]</bitRange>
  127. </field>
  128. <field>
  129. <name>ADSTP</name>
  130. <description>ADC group regular conversion stop</description>
  131. <bitRange>[4:4]</bitRange>
  132. </field>
  133. <field>
  134. <name>VREF_BUFFERE</name>
  135. <description>desc VREF_BUFFERE</description>
  136. <bitRange>[5:5]</bitRange>
  137. </field>
  138. <field>
  139. <name>VERBUFF_SEL</name>
  140. <description>desc VERBUFF_SEL</description>
  141. <bitRange>[7:6]</bitRange>
  142. </field>
  143. <field>
  144. <name>ADCAL</name>
  145. <description>ADC group regular conversion calibration</description>
  146. <bitRange>[31:31]</bitRange>
  147. </field>
  148. </fields>
  149. </register>
  150. <register>
  151. <name>CFGR1</name>
  152. <displayName>CFGR1</displayName>
  153. <description>ADC configuration register 1</description>
  154. <addressOffset>0xC</addressOffset>
  155. <fields>
  156. <field>
  157. <name>SCANDIR</name>
  158. <description>Scan sequence direction</description>
  159. <bitRange>[2:2]</bitRange>
  160. </field>
  161. <field>
  162. <name>RESSEL</name>
  163. <description>ADC data resolution</description>
  164. <bitRange>[4:3]</bitRange>
  165. </field>
  166. <field>
  167. <name>ALIGN</name>
  168. <description>ADC data alignement</description>
  169. <bitRange>[5:5]</bitRange>
  170. </field>
  171. <field>
  172. <name>EXTSEL</name>
  173. <description>ADC group regular external trigger source</description>
  174. <bitRange>[8:6]</bitRange>
  175. </field>
  176. <field>
  177. <name>EXTEN</name>
  178. <description>ADC group regular external trigger polarity</description>
  179. <bitRange>[11:10]</bitRange>
  180. </field>
  181. <field>
  182. <name>OVRMOD</name>
  183. <description>ADC group regular overrun configuration</description>
  184. <bitRange>[12:12]</bitRange>
  185. </field>
  186. <field>
  187. <name>CONT</name>
  188. <description>ADC group regular continuous conversion mode</description>
  189. <bitRange>[13:13]</bitRange>
  190. </field>
  191. <field>
  192. <name>WAIT</name>
  193. <description>Wait conversion mode</description>
  194. <bitRange>[14:14]</bitRange>
  195. </field>
  196. <field>
  197. <name>DISCEN</name>
  198. <description>ADC group regular sequencer discontinuous mode</description>
  199. <bitRange>[16:16]</bitRange>
  200. </field>
  201. <field>
  202. <name>AWDSGL</name>
  203. <description>ADC analog watchdog monitoring a single channel or all channels</description>
  204. <bitRange>[22:22]</bitRange>
  205. </field>
  206. <field>
  207. <name>AWDEN</name>
  208. <description>ADC analog watchdog enable on scope ADC group regular</description>
  209. <bitRange>[23:23]</bitRange>
  210. </field>
  211. <field>
  212. <name>AWDCH</name>
  213. <description>ADC analog watchdog monitored channel selection</description>
  214. <bitRange>[29:26]</bitRange>
  215. </field>
  216. </fields>
  217. </register>
  218. <register>
  219. <name>CFGR2</name>
  220. <displayName>CFGR2</displayName>
  221. <description>ADC configuration register 2</description>
  222. <addressOffset>0x10</addressOffset>
  223. <fields>
  224. <field>
  225. <name>CKMODE</name>
  226. <description>ADC clock mode</description>
  227. <bitRange>[31:28]</bitRange>
  228. </field>
  229. </fields>
  230. </register>
  231. <register>
  232. <name>SMPR</name>
  233. <displayName>SMPR</displayName>
  234. <description>ADC sampling time register</description>
  235. <addressOffset>0x14</addressOffset>
  236. <fields>
  237. <field>
  238. <name>SMP</name>
  239. <description>Sampling time selection</description>
  240. <bitRange>[2:0]</bitRange>
  241. </field>
  242. </fields>
  243. </register>
  244. <register>
  245. <name>TR</name>
  246. <displayName>TR</displayName>
  247. <description>ADC analog watchdog 1 threshold register</description>
  248. <addressOffset>0x20</addressOffset>
  249. <resetValue>0xFFF0000</resetValue>
  250. <fields>
  251. <field>
  252. <name>LT</name>
  253. <description>ADC analog watchdog threshold low</description>
  254. <bitRange>[11:0]</bitRange>
  255. </field>
  256. <field>
  257. <name>HT</name>
  258. <description>ADC analog watchdog threshold high</description>
  259. <bitRange>[27:16]</bitRange>
  260. </field>
  261. </fields>
  262. </register>
  263. <register>
  264. <name>CHSELR</name>
  265. <displayName>CHSELR</displayName>
  266. <description>ADC group regular sequencer register</description>
  267. <addressOffset>0x28</addressOffset>
  268. <resetValue>0xFFF0000</resetValue>
  269. <fields>
  270. <field>
  271. <name>CHSEL0</name>
  272. <description>Channel-0 selection</description>
  273. <bitRange>[0:0]</bitRange>
  274. </field>
  275. <field>
  276. <name>CHSEL1</name>
  277. <description>Channel-1 selection</description>
  278. <bitRange>[1:1]</bitRange>
  279. </field>
  280. <field>
  281. <name>CHSEL2</name>
  282. <description>Channel-2 selection</description>
  283. <bitRange>[2:2]</bitRange>
  284. </field>
  285. <field>
  286. <name>CHSEL3</name>
  287. <description>Channel-3 selection</description>
  288. <bitRange>[3:3]</bitRange>
  289. </field>
  290. <field>
  291. <name>CHSEL4</name>
  292. <description>Channel-4 selection</description>
  293. <bitRange>[4:4]</bitRange>
  294. </field>
  295. <field>
  296. <name>CHSEL5</name>
  297. <description>Channel-5 selection</description>
  298. <bitRange>[5:5]</bitRange>
  299. </field>
  300. <field>
  301. <name>CHSEL6</name>
  302. <description>Channel-6 selection</description>
  303. <bitRange>[6:6]</bitRange>
  304. </field>
  305. <field>
  306. <name>CHSEL7</name>
  307. <description>Channel-7 selection</description>
  308. <bitRange>[7:7]</bitRange>
  309. </field>
  310. <field>
  311. <name>CHSEL8</name>
  312. <description>Channel-8 selection</description>
  313. <bitRange>[8:8]</bitRange>
  314. </field>
  315. <field>
  316. <name>CHSEL9</name>
  317. <description>Channel-9 selection</description>
  318. <bitRange>[9:9]</bitRange>
  319. </field>
  320. </fields>
  321. </register>
  322. <register>
  323. <name>DR</name>
  324. <displayName>DR</displayName>
  325. <description>ADC group regular data register</description>
  326. <addressOffset>0x40</addressOffset>
  327. <access>read-only</access>
  328. <fields>
  329. <field>
  330. <name>DATA</name>
  331. <description>ADC group regular conversion data</description>
  332. <bitRange>[15:0]</bitRange>
  333. </field>
  334. </fields>
  335. </register>
  336. <register>
  337. <name>CCSR</name>
  338. <displayName>CCSR</displayName>
  339. <description>ADC calibration configuration and status register</description>
  340. <addressOffset>0x44</addressOffset>
  341. <fields>
  342. <field>
  343. <name>CALSEL</name>
  344. <description>Calibration contents selection</description>
  345. <bitRange>[11:11]</bitRange>
  346. </field>
  347. <field>
  348. <name>CALSMP</name>
  349. <description>Calibration sample time selection</description>
  350. <bitRange>[13:12]</bitRange>
  351. </field>
  352. <field>
  353. <name>CALBYP</name>
  354. <description>desc CALBYP</description>
  355. <bitRange>[14:14]</bitRange>
  356. </field>
  357. <field>
  358. <name>CALSET</name>
  359. <description>Calibration factor selection</description>
  360. <bitRange>[15:15]</bitRange>
  361. </field>
  362. <field>
  363. <name>OFFSUC</name>
  364. <description>desc OFFSUC</description>
  365. <bitRange>[29:29]</bitRange>
  366. </field>
  367. <field>
  368. <name>CALSUC</name>
  369. <description>desc CALSUC</description>
  370. <bitRange>[30:30]</bitRange>
  371. </field>
  372. <field>
  373. <name>CALON</name>
  374. <description>Calibration flag</description>
  375. <bitRange>[31:31]</bitRange>
  376. <access>read-only</access>
  377. </field>
  378. </fields>
  379. </register>
  380. <register>
  381. <name>CCR</name>
  382. <displayName>CCR</displayName>
  383. <description>ADC common configuration register</description>
  384. <addressOffset>0x308</addressOffset>
  385. <fields>
  386. <field>
  387. <name>VREFEN</name>
  388. <description>VREFINT enable</description>
  389. <bitRange>[22:22]</bitRange>
  390. </field>
  391. <field>
  392. <name>TSEN</name>
  393. <description>Temperature sensor enable</description>
  394. <bitRange>[23:23]</bitRange>
  395. </field>
  396. </fields>
  397. </register>
  398. </registers>
  399. </peripheral>
  400. <peripheral>
  401. <name>CRC</name>
  402. <description>CRC calculation unit</description>
  403. <groupName>CRC</groupName>
  404. <baseAddress>0x40023000</baseAddress>
  405. <addressBlock>
  406. <offset>0x0</offset>
  407. <size>0x400</size>
  408. <usage>registers</usage>
  409. </addressBlock>
  410. <registers>
  411. <register>
  412. <name>DR</name>
  413. <displayName>DR</displayName>
  414. <description>Data register</description>
  415. <addressOffset>0x0</addressOffset>
  416. <resetValue>0xFFFFFFFF</resetValue>
  417. <fields>
  418. <field>
  419. <name>DR</name>
  420. <description>Data Register</description>
  421. <bitRange>[31:0]</bitRange>
  422. </field>
  423. </fields>
  424. </register>
  425. <register>
  426. <name>IDR</name>
  427. <displayName>IDR</displayName>
  428. <description>Independent Data register</description>
  429. <addressOffset>0x4</addressOffset>
  430. <fields>
  431. <field>
  432. <name>IDR</name>
  433. <description>Independent Data register</description>
  434. <bitRange>[7:0]</bitRange>
  435. </field>
  436. </fields>
  437. </register>
  438. <register>
  439. <name>CR</name>
  440. <displayName>CR</displayName>
  441. <description>Control register</description>
  442. <addressOffset>0x8</addressOffset>
  443. <access>write-only</access>
  444. <fields>
  445. <field>
  446. <name>RESET</name>
  447. <description>Reset bit</description>
  448. <bitRange>[0:0]</bitRange>
  449. </field>
  450. </fields>
  451. </register>
  452. </registers>
  453. </peripheral>
  454. <peripheral>
  455. <name>DBGMCU</name>
  456. <description>Debug support</description>
  457. <groupName>DBGMCU</groupName>
  458. <baseAddress>0x40015800</baseAddress>
  459. <addressBlock>
  460. <offset>0x0</offset>
  461. <size>0x400</size>
  462. <usage>registers</usage>
  463. </addressBlock>
  464. <registers>
  465. <register>
  466. <name>IDCODE</name>
  467. <displayName>IDCODE</displayName>
  468. <description>MCU Device ID Code Register</description>
  469. <addressOffset>0x0</addressOffset>
  470. <access>read-only</access>
  471. <fields>
  472. <field>
  473. <name>REV_ID</name>
  474. <description>REV_ID</description>
  475. <bitRange>[31:0]</bitRange>
  476. </field>
  477. </fields>
  478. </register>
  479. <register>
  480. <name>CR</name>
  481. <displayName>CR</displayName>
  482. <description>Debug MCU Configuration Register</description>
  483. <addressOffset>0x4</addressOffset>
  484. <fields>
  485. <field>
  486. <name>DBG_STOP</name>
  487. <description>Debug Stop Mode</description>
  488. <bitRange>[1:1]</bitRange>
  489. </field>
  490. </fields>
  491. </register>
  492. <register>
  493. <name>APB_FZ1</name>
  494. <displayName>APB_FZ1</displayName>
  495. <description>APB Freeze Register1</description>
  496. <addressOffset>0x8</addressOffset>
  497. <fields>
  498. <field>
  499. <name>DBG_LPTIM_STOP</name>
  500. <description>Debug LPTIM stopped when Core ishalted</description>
  501. <bitRange>[31:31]</bitRange>
  502. </field>
  503. </fields>
  504. </register>
  505. <register>
  506. <name>APB_FZ2</name>
  507. <displayName>APB_FZ2</displayName>
  508. <description>APB Freeze Register2</description>
  509. <addressOffset>0xC</addressOffset>
  510. <fields>
  511. <field>
  512. <name>DBG_TIMER1_STOP</name>
  513. <description>Debug Timer 1 stopped when Core ishalted</description>
  514. <bitRange>[11:11]</bitRange>
  515. </field>
  516. <field>
  517. <name>DBG_TIM14_STOP</name>
  518. <description>Debug TIM 14 stopped whenCore is halted</description>
  519. <bitRange>[15:15]</bitRange>
  520. </field>
  521. </fields>
  522. </register>
  523. </registers>
  524. </peripheral>
  525. <peripheral>
  526. <name>EXTI</name>
  527. <description>External interrupt/event controller</description>
  528. <groupName>EXTI</groupName>
  529. <baseAddress>0x40021800</baseAddress>
  530. <addressBlock>
  531. <offset>0x0</offset>
  532. <size>0x400</size>
  533. <usage>registers</usage>
  534. </addressBlock>
  535. <interrupt>
  536. <name>EXTI0_1</name>
  537. <description>EXTI Line 0 and 1 Interrupt</description>
  538. <value>5</value>
  539. </interrupt>
  540. <interrupt>
  541. <name>EXTI2_3</name>
  542. <description>EXTI Line 2 and 3 Interrupt</description>
  543. <value>6</value>
  544. </interrupt>
  545. <interrupt>
  546. <name>EXTI4_15</name>
  547. <description>EXTI Line 4 to 15 Interrupt</description>
  548. <value>7</value>
  549. </interrupt>
  550. <registers>
  551. <register>
  552. <name>RTSR</name>
  553. <displayName>RTSR</displayName>
  554. <description>EXTI rising trigger selection register</description>
  555. <addressOffset>0x0</addressOffset>
  556. <fields>
  557. <field>
  558. <name>RT0</name>
  559. <description>Rising trigger event configuration bit of Configurable Event input</description>
  560. <bitRange>[0:0]</bitRange>
  561. </field>
  562. <field>
  563. <name>RT1</name>
  564. <description>Rising trigger event configuration bit of Configurable Event input</description>
  565. <bitRange>[1:1]</bitRange>
  566. </field>
  567. <field>
  568. <name>RT2</name>
  569. <description>Rising trigger event configuration bit of Configurable Event input</description>
  570. <bitRange>[2:2]</bitRange>
  571. </field>
  572. <field>
  573. <name>RT3</name>
  574. <description>Rising trigger event configuration bit of Configurable Event input</description>
  575. <bitRange>[3:3]</bitRange>
  576. </field>
  577. <field>
  578. <name>RT4</name>
  579. <description>Rising trigger event configuration bit of Configurable Event input</description>
  580. <bitRange>[4:4]</bitRange>
  581. </field>
  582. <field>
  583. <name>RT5</name>
  584. <description>Rising trigger event configuration bit of Configurable Event input</description>
  585. <bitRange>[5:5]</bitRange>
  586. </field>
  587. <field>
  588. <name>RT6</name>
  589. <description>Rising trigger event configuration bit of Configurable Event input</description>
  590. <bitRange>[6:6]</bitRange>
  591. </field>
  592. <field>
  593. <name>RT7</name>
  594. <description>Rising trigger event configuration bit of Configurable Event input</description>
  595. <bitRange>[7:7]</bitRange>
  596. </field>
  597. <field>
  598. <name>RT17</name>
  599. <description>Rising trigger event configuration bit of Configurable Event input</description>
  600. <bitRange>[17:17]</bitRange>
  601. </field>
  602. <field>
  603. <name>RT18</name>
  604. <description>Rising trigger event configuration bit of Configurable Event input</description>
  605. <bitRange>[18:18]</bitRange>
  606. </field>
  607. </fields>
  608. </register>
  609. <register>
  610. <name>FTSR</name>
  611. <displayName>FTSR</displayName>
  612. <description>EXTI falling trigger selection register</description>
  613. <addressOffset>0x4</addressOffset>
  614. <fields>
  615. <field>
  616. <name>FT0</name>
  617. <description>Falling trigger event configuration bit of Configurable Event input</description>
  618. <bitRange>[0:0]</bitRange>
  619. </field>
  620. <field>
  621. <name>FT1</name>
  622. <description>Falling trigger event configuration bit of Configurable Event input</description>
  623. <bitRange>[1:1]</bitRange>
  624. </field>
  625. <field>
  626. <name>FT2</name>
  627. <description>Falling trigger event configuration bit of Configurable Event input</description>
  628. <bitRange>[2:2]</bitRange>
  629. </field>
  630. <field>
  631. <name>FT3</name>
  632. <description>Falling trigger event configuration bit of Configurable Event input</description>
  633. <bitRange>[3:3]</bitRange>
  634. </field>
  635. <field>
  636. <name>FT4</name>
  637. <description>Falling trigger event configuration bit of Configurable Event input</description>
  638. <bitRange>[4:4]</bitRange>
  639. </field>
  640. <field>
  641. <name>FT5</name>
  642. <description>Falling trigger event configuration bit of Configurable Event input</description>
  643. <bitRange>[5:5]</bitRange>
  644. </field>
  645. <field>
  646. <name>FT6</name>
  647. <description>Falling trigger event configuration bit of Configurable Event input</description>
  648. <bitRange>[6:6]</bitRange>
  649. </field>
  650. <field>
  651. <name>FT7</name>
  652. <description>Falling trigger event configuration bit of Configurable Event input</description>
  653. <bitRange>[7:7]</bitRange>
  654. </field>
  655. <field>
  656. <name>FT17</name>
  657. <description>Falling trigger event configuration bit of Configurable Event input</description>
  658. <bitRange>[17:17]</bitRange>
  659. </field>
  660. <field>
  661. <name>FT18</name>
  662. <description>Falling trigger event configuration bit of Configurable Event input</description>
  663. <bitRange>[18:18]</bitRange>
  664. </field>
  665. </fields>
  666. </register>
  667. <register>
  668. <name>SWIER</name>
  669. <displayName>SWIER</displayName>
  670. <description>EXTI software interrupt event register</description>
  671. <addressOffset>0x8</addressOffset>
  672. <fields>
  673. <field>
  674. <name>SWI0</name>
  675. <description>Rising trigger event configuration bit of Configurable Event input</description>
  676. <bitRange>[0:0]</bitRange>
  677. </field>
  678. <field>
  679. <name>SWI1</name>
  680. <description>Rising trigger event configuration bit of Configurable Event input</description>
  681. <bitRange>[1:1]</bitRange>
  682. </field>
  683. <field>
  684. <name>SWI2</name>
  685. <description>Rising trigger event configuration bit of Configurable Event input</description>
  686. <bitRange>[2:2]</bitRange>
  687. </field>
  688. <field>
  689. <name>SWI3</name>
  690. <description>Rising trigger event configuration bit of Configurable Event input</description>
  691. <bitRange>[3:3]</bitRange>
  692. </field>
  693. <field>
  694. <name>SWI4</name>
  695. <description>Rising trigger event configuration bit of Configurable Event input</description>
  696. <bitRange>[4:4]</bitRange>
  697. </field>
  698. <field>
  699. <name>SWI5</name>
  700. <description>Rising trigger event configuration bit of Configurable Event input</description>
  701. <bitRange>[5:5]</bitRange>
  702. </field>
  703. <field>
  704. <name>SWI6</name>
  705. <description>Rising trigger event configuration bit of Configurable Event input</description>
  706. <bitRange>[6:6]</bitRange>
  707. </field>
  708. <field>
  709. <name>SWI7</name>
  710. <description>Rising trigger event configuration bit of Configurable Event input</description>
  711. <bitRange>[7:7]</bitRange>
  712. </field>
  713. <field>
  714. <name>SWI17</name>
  715. <description>Rising trigger event configuration bit of Configurable Event input</description>
  716. <bitRange>[17:17]</bitRange>
  717. </field>
  718. <field>
  719. <name>SWI18</name>
  720. <description>Rising trigger event configuration bit of Configurable Event input</description>
  721. <bitRange>[18:18]</bitRange>
  722. </field>
  723. </fields>
  724. </register>
  725. <register>
  726. <name>PR</name>
  727. <displayName>PR</displayName>
  728. <description>EXTI pending register</description>
  729. <addressOffset>0xC</addressOffset>
  730. <fields>
  731. <field>
  732. <name>PR0</name>
  733. <description>configurable event inputs x rising edge Pending bit.</description>
  734. <bitRange>[0:0]</bitRange>
  735. </field>
  736. <field>
  737. <name>PR1</name>
  738. <description>configurable event inputs x rising edge Pending bit.</description>
  739. <bitRange>[1:1]</bitRange>
  740. </field>
  741. <field>
  742. <name>PR2</name>
  743. <description>configurable event inputs x rising edge Pending bit.</description>
  744. <bitRange>[2:2]</bitRange>
  745. </field>
  746. <field>
  747. <name>PR3</name>
  748. <description>configurable event inputs x rising edge Pending bit.</description>
  749. <bitRange>[3:3]</bitRange>
  750. </field>
  751. <field>
  752. <name>PR4</name>
  753. <description>configurable event inputs x rising edge Pending bit.</description>
  754. <bitRange>[4:4]</bitRange>
  755. </field>
  756. <field>
  757. <name>PR5</name>
  758. <description>configurable event inputs x rising edge Pending bit.</description>
  759. <bitRange>[5:5]</bitRange>
  760. </field>
  761. <field>
  762. <name>PR6</name>
  763. <description>configurable event inputs x rising edge Pending bit.</description>
  764. <bitRange>[6:6]</bitRange>
  765. </field>
  766. <field>
  767. <name>PR7</name>
  768. <description>configurable event inputs x rising edge Pending bit.</description>
  769. <bitRange>[7:7]</bitRange>
  770. </field>
  771. <field>
  772. <name>PR17</name>
  773. <description>configurable event inputs x rising edge Pending bit.</description>
  774. <bitRange>[17:17]</bitRange>
  775. </field>
  776. <field>
  777. <name>PR18</name>
  778. <description>configurable event inputs x rising edge Pending bit.</description>
  779. <bitRange>[18:18]</bitRange>
  780. </field>
  781. </fields>
  782. </register>
  783. <register>
  784. <name>EXTICR1</name>
  785. <displayName>EXTICR1</displayName>
  786. <description>EXTI external interrupt selection register</description>
  787. <addressOffset>0x60</addressOffset>
  788. <fields>
  789. <field>
  790. <name>EXTI0</name>
  791. <description>GPIO port selection</description>
  792. <bitRange>[1:0]</bitRange>
  793. </field>
  794. <field>
  795. <name>EXTI1</name>
  796. <description>GPIO port selection</description>
  797. <bitRange>[9:8]</bitRange>
  798. </field>
  799. <field>
  800. <name>EXTI2</name>
  801. <description>GPIO port selection</description>
  802. <bitRange>[17:16]</bitRange>
  803. </field>
  804. <field>
  805. <name>EXTI3</name>
  806. <description>GPIO port selection</description>
  807. <bitRange>[25:24]</bitRange>
  808. </field>
  809. </fields>
  810. </register>
  811. <register>
  812. <name>EXTICR2</name>
  813. <displayName>EXTICR2</displayName>
  814. <description>EXTI external interrupt selection register</description>
  815. <addressOffset>0x64</addressOffset>
  816. <fields>
  817. <field>
  818. <name>EXTI4</name>
  819. <description>GPIO port selection</description>
  820. <bitRange>[1:0]</bitRange>
  821. </field>
  822. <field>
  823. <name>EXTI5</name>
  824. <description>GPIO port selection</description>
  825. <bitRange>[8:8]</bitRange>
  826. </field>
  827. <field>
  828. <name>EXTI6</name>
  829. <description>GPIO port selection</description>
  830. <bitRange>[16:16]</bitRange>
  831. </field>
  832. <field>
  833. <name>EXTI7</name>
  834. <description>GPIO port selection</description>
  835. <bitRange>[24:24]</bitRange>
  836. </field>
  837. </fields>
  838. </register>
  839. <register>
  840. <name>IMR</name>
  841. <displayName>IMR</displayName>
  842. <description>EXTI CPU wakeup with interrupt mask register</description>
  843. <addressOffset>0x80</addressOffset>
  844. <resetValue>0xFFF80000</resetValue>
  845. <fields>
  846. <field>
  847. <name>IM0</name>
  848. <description>CPU wakeup with interrupt mask on event input</description>
  849. <bitRange>[0:0]</bitRange>
  850. </field>
  851. <field>
  852. <name>IM1</name>
  853. <description>CPU wakeup with interrupt mask on event input</description>
  854. <bitRange>[1:1]</bitRange>
  855. </field>
  856. <field>
  857. <name>IM2</name>
  858. <description>CPU wakeup with interrupt mask on event input</description>
  859. <bitRange>[2:2]</bitRange>
  860. </field>
  861. <field>
  862. <name>IM3</name>
  863. <description>CPU wakeup with interrupt mask on event input</description>
  864. <bitRange>[3:3]</bitRange>
  865. </field>
  866. <field>
  867. <name>IM4</name>
  868. <description>CPU wakeup with interrupt mask on event input</description>
  869. <bitRange>[4:4]</bitRange>
  870. </field>
  871. <field>
  872. <name>IM5</name>
  873. <description>CPU wakeup with interrupt mask on event input</description>
  874. <bitRange>[5:5]</bitRange>
  875. </field>
  876. <field>
  877. <name>IM6</name>
  878. <description>CPU wakeup with interrupt mask on event input</description>
  879. <bitRange>[6:6]</bitRange>
  880. </field>
  881. <field>
  882. <name>IM7</name>
  883. <description>CPU wakeup with interrupt mask on event input</description>
  884. <bitRange>[7:7]</bitRange>
  885. </field>
  886. <field>
  887. <name>IM17</name>
  888. <description>CPU wakeup with interrupt mask on event input</description>
  889. <bitRange>[17:17]</bitRange>
  890. </field>
  891. <field>
  892. <name>IM18</name>
  893. <description>CPU wakeup with interrupt mask on event input</description>
  894. <bitRange>[18:18]</bitRange>
  895. </field>
  896. <field>
  897. <name>IM29</name>
  898. <description>CPU wakeup with interrupt mask on event input</description>
  899. <bitRange>[29:29]</bitRange>
  900. </field>
  901. </fields>
  902. </register>
  903. <register>
  904. <name>EMR</name>
  905. <displayName>EMR</displayName>
  906. <description>EXTI CPU wakeup with event mask register</description>
  907. <addressOffset>0x84</addressOffset>
  908. <fields>
  909. <field>
  910. <name>EM0</name>
  911. <description>CPU wakeup with event mask on event input</description>
  912. <bitRange>[0:0]</bitRange>
  913. </field>
  914. <field>
  915. <name>EM1</name>
  916. <description>CPU wakeup with event mask on event input</description>
  917. <bitRange>[1:1]</bitRange>
  918. </field>
  919. <field>
  920. <name>EM2</name>
  921. <description>CPU wakeup with event mask on event input</description>
  922. <bitRange>[2:2]</bitRange>
  923. </field>
  924. <field>
  925. <name>EM3</name>
  926. <description>CPU wakeup with event mask on event input</description>
  927. <bitRange>[3:3]</bitRange>
  928. </field>
  929. <field>
  930. <name>EM4</name>
  931. <description>CPU wakeup with event mask on event input</description>
  932. <bitRange>[4:4]</bitRange>
  933. </field>
  934. <field>
  935. <name>EM5</name>
  936. <description>CPU wakeup with event mask on event input</description>
  937. <bitRange>[5:5]</bitRange>
  938. </field>
  939. <field>
  940. <name>EM6</name>
  941. <description>CPU wakeup with event mask on event input</description>
  942. <bitRange>[6:6]</bitRange>
  943. </field>
  944. <field>
  945. <name>EM7</name>
  946. <description>CPU wakeup with event mask on event input</description>
  947. <bitRange>[7:7]</bitRange>
  948. </field>
  949. <field>
  950. <name>EM17</name>
  951. <description>CPU wakeup with event mask on event input</description>
  952. <bitRange>[17:17]</bitRange>
  953. </field>
  954. <field>
  955. <name>EM18</name>
  956. <description>CPU wakeup with event mask on event input</description>
  957. <bitRange>[18:18]</bitRange>
  958. </field>
  959. <field>
  960. <name>EM29</name>
  961. <description>CPU wakeup with event mask on event input</description>
  962. <bitRange>[29:29]</bitRange>
  963. </field>
  964. </fields>
  965. </register>
  966. </registers>
  967. </peripheral>
  968. <peripheral>
  969. <name>FLASH</name>
  970. <description>Flash</description>
  971. <groupName>Flash</groupName>
  972. <baseAddress>0x40022000</baseAddress>
  973. <addressBlock>
  974. <offset>0x0</offset>
  975. <size>0x400</size>
  976. <usage>registers</usage>
  977. </addressBlock>
  978. <interrupt>
  979. <name>FLASH</name>
  980. <description>FLASH global Interrupt</description>
  981. <value>3</value>
  982. </interrupt>
  983. <registers>
  984. <register>
  985. <name>ACR</name>
  986. <displayName>ACR</displayName>
  987. <description>Access control register</description>
  988. <addressOffset>0x0</addressOffset>
  989. <resetValue>0x600</resetValue>
  990. <fields>
  991. <field>
  992. <name>LATENCY</name>
  993. <description>Latency</description>
  994. <bitRange>[0:0]</bitRange>
  995. </field>
  996. </fields>
  997. </register>
  998. <register>
  999. <name>KEYR</name>
  1000. <displayName>KEYR</displayName>
  1001. <description>Flash key register</description>
  1002. <addressOffset>0x8</addressOffset>
  1003. <access>write-only</access>
  1004. <fields>
  1005. <field>
  1006. <name>KEY</name>
  1007. <description>Flash key</description>
  1008. <bitRange>[31:0]</bitRange>
  1009. </field>
  1010. </fields>
  1011. </register>
  1012. <register>
  1013. <name>OPTKEYR</name>
  1014. <displayName>OPTKEYR</displayName>
  1015. <description>Option byte key register</description>
  1016. <addressOffset>0xC</addressOffset>
  1017. <access>write-only</access>
  1018. <fields>
  1019. <field>
  1020. <name>OPTKEY</name>
  1021. <description>Option byte key</description>
  1022. <bitRange>[31:0]</bitRange>
  1023. </field>
  1024. </fields>
  1025. </register>
  1026. <register>
  1027. <name>SR</name>
  1028. <displayName>SR</displayName>
  1029. <description>Status register</description>
  1030. <addressOffset>0x10</addressOffset>
  1031. <fields>
  1032. <field>
  1033. <name>EOP</name>
  1034. <description>End of operation</description>
  1035. <bitRange>[0:0]</bitRange>
  1036. </field>
  1037. <field>
  1038. <name>WRPERR</name>
  1039. <description>Write protected error</description>
  1040. <bitRange>[4:4]</bitRange>
  1041. </field>
  1042. <field>
  1043. <name>OPTVERR</name>
  1044. <description>Option and Engineering bits loading validity error</description>
  1045. <bitRange>[15:15]</bitRange>
  1046. </field>
  1047. <field>
  1048. <name>BSY</name>
  1049. <description>Busy</description>
  1050. <bitRange>[16:16]</bitRange>
  1051. </field>
  1052. </fields>
  1053. </register>
  1054. <register>
  1055. <name>CR</name>
  1056. <displayName>CR</displayName>
  1057. <description>Flash control register</description>
  1058. <addressOffset>0x14</addressOffset>
  1059. <resetValue>0xC0000000</resetValue>
  1060. <fields>
  1061. <field>
  1062. <name>PG</name>
  1063. <description>Programming</description>
  1064. <bitRange>[0:0]</bitRange>
  1065. </field>
  1066. <field>
  1067. <name>PER</name>
  1068. <description>Page erase</description>
  1069. <bitRange>[1:1]</bitRange>
  1070. </field>
  1071. <field>
  1072. <name>MER</name>
  1073. <description>Mass erase</description>
  1074. <bitRange>[2:2]</bitRange>
  1075. </field>
  1076. <field>
  1077. <name>SER</name>
  1078. <description>Sector erase</description>
  1079. <bitRange>[11:11]</bitRange>
  1080. </field>
  1081. <field>
  1082. <name>OPTSTRT</name>
  1083. <description>Option byte program start</description>
  1084. <bitRange>[17:17]</bitRange>
  1085. </field>
  1086. <field>
  1087. <name>PGSTRT</name>
  1088. <description>Flash main memory program start</description>
  1089. <bitRange>[19:19]</bitRange>
  1090. </field>
  1091. <field>
  1092. <name>EOPIE</name>
  1093. <description>End of operation interrupt enable</description>
  1094. <bitRange>[24:24]</bitRange>
  1095. </field>
  1096. <field>
  1097. <name>ERRIE</name>
  1098. <description>Error interrupt enable</description>
  1099. <bitRange>[25:25]</bitRange>
  1100. </field>
  1101. <field>
  1102. <name>OBL_LAUNCH</name>
  1103. <description>Force the option byte loading</description>
  1104. <bitRange>[27:27]</bitRange>
  1105. </field>
  1106. <field>
  1107. <name>OPTLOCK</name>
  1108. <description>Options Lock</description>
  1109. <bitRange>[30:30]</bitRange>
  1110. </field>
  1111. <field>
  1112. <name>LOCK</name>
  1113. <description>FLASH_CR Lock</description>
  1114. <bitRange>[31:31]</bitRange>
  1115. </field>
  1116. </fields>
  1117. </register>
  1118. <register>
  1119. <name>OPTR</name>
  1120. <displayName>OPTR</displayName>
  1121. <description>Flash option register</description>
  1122. <addressOffset>0x20</addressOffset>
  1123. <resetValue>0x4F55B0AA</resetValue>
  1124. <fields>
  1125. <field>
  1126. <name>BOREN</name>
  1127. <description>BOR reset Level</description>
  1128. <bitRange>[8:8]</bitRange>
  1129. </field>
  1130. <field>
  1131. <name>BORF_LEV</name>
  1132. <description>These bits contain the VDD supply level threshold that activates the reset</description>
  1133. <bitRange>[11:9]</bitRange>
  1134. </field>
  1135. <field>
  1136. <name>IWDG_SW</name>
  1137. <description>Independent watchdog selection</description>
  1138. <bitRange>[12:12]</bitRange>
  1139. </field>
  1140. <field>
  1141. <name>SWD_MODE</name>
  1142. <description>SWD_MODE</description>
  1143. <bitRange>[13:13]</bitRange>
  1144. </field>
  1145. <field>
  1146. <name>NRST_MODE</name>
  1147. <description>NRST_MODE</description>
  1148. <bitRange>[14:14]</bitRange>
  1149. </field>
  1150. </fields>
  1151. </register>
  1152. <register>
  1153. <name>SDKR</name>
  1154. <displayName>SDKR</displayName>
  1155. <description>Flash SDK address register</description>
  1156. <addressOffset>0x24</addressOffset>
  1157. <resetValue>0xFFE0001F</resetValue>
  1158. <fields>
  1159. <field>
  1160. <name>SDK_STRT</name>
  1161. <description>SDK area start address</description>
  1162. <bitRange>[3:0]</bitRange>
  1163. </field>
  1164. <field>
  1165. <name>SDK_END</name>
  1166. <description>SDK area end address</description>
  1167. <bitRange>[11:8]</bitRange>
  1168. </field>
  1169. </fields>
  1170. </register>
  1171. <register>
  1172. <name>BTCR</name>
  1173. <displayName>BTCR</displayName>
  1174. <description>FLASH boot control register</description>
  1175. <addressOffset>0x28</addressOffset>
  1176. <fields>
  1177. <field>
  1178. <name>BOOT_SIZE</name>
  1179. <description>desc BOOT_SIZE</description>
  1180. <bitRange>[2:0]</bitRange>
  1181. </field>
  1182. <field>
  1183. <name>BOOT0</name>
  1184. <description>desc BOOT0</description>
  1185. <bitRange>[14:14]</bitRange>
  1186. </field>
  1187. <field>
  1188. <name>NBOOT1</name>
  1189. <description>desc NBOOT1</description>
  1190. <bitRange>[15:15]</bitRange>
  1191. </field>
  1192. </fields>
  1193. </register>
  1194. <register>
  1195. <name>WRPR</name>
  1196. <displayName>WRPR</displayName>
  1197. <description>Flash WRP address register</description>
  1198. <addressOffset>0x2C</addressOffset>
  1199. <resetValue>0xFFFF</resetValue>
  1200. <fields>
  1201. <field>
  1202. <name>WRP</name>
  1203. <description>WRP address</description>
  1204. <bitRange>[5:0]</bitRange>
  1205. </field>
  1206. </fields>
  1207. </register>
  1208. <register>
  1209. <name>STCR</name>
  1210. <displayName>STCR</displayName>
  1211. <description>Flash sleep time config register</description>
  1212. <addressOffset>0x90</addressOffset>
  1213. <resetValue>0x6400</resetValue>
  1214. <fields>
  1215. <field>
  1216. <name>SLEEP_EN</name>
  1217. <description>FLash sleep enable</description>
  1218. <bitRange>[0:0]</bitRange>
  1219. </field>
  1220. <field>
  1221. <name>SLEEP_TIME</name>
  1222. <description>FLash sleep time configuration(counter based on HSI_10M)</description>
  1223. <bitRange>[15:8]</bitRange>
  1224. </field>
  1225. </fields>
  1226. </register>
  1227. <register>
  1228. <name>TS0</name>
  1229. <displayName>TS0</displayName>
  1230. <description>Flash TS0 register</description>
  1231. <addressOffset>0x100</addressOffset>
  1232. <resetValue>0xB4</resetValue>
  1233. <fields>
  1234. <field>
  1235. <name>TS0</name>
  1236. <description>FLash TS0 register</description>
  1237. <bitRange>[8:0]</bitRange>
  1238. </field>
  1239. </fields>
  1240. </register>
  1241. <register>
  1242. <name>TS1</name>
  1243. <displayName>TS1</displayName>
  1244. <description>Flash TS1 register</description>
  1245. <addressOffset>0x104</addressOffset>
  1246. <resetValue>0x1B0</resetValue>
  1247. <fields>
  1248. <field>
  1249. <name>TS1</name>
  1250. <description>FLash TS1 register</description>
  1251. <bitRange>[9:0]</bitRange>
  1252. </field>
  1253. </fields>
  1254. </register>
  1255. <register>
  1256. <name>TS2P</name>
  1257. <displayName>TS2P</displayName>
  1258. <description>Flash TS2P register</description>
  1259. <addressOffset>0x108</addressOffset>
  1260. <resetValue>0xB4</resetValue>
  1261. <fields>
  1262. <field>
  1263. <name>TS2P</name>
  1264. <description>FLash TS2P register</description>
  1265. <bitRange>[8:0]</bitRange>
  1266. </field>
  1267. </fields>
  1268. </register>
  1269. <register>
  1270. <name>TPS3</name>
  1271. <displayName>TPS3</displayName>
  1272. <description>Flash TPS3 register</description>
  1273. <addressOffset>0x10C</addressOffset>
  1274. <resetValue>0x6C0</resetValue>
  1275. <fields>
  1276. <field>
  1277. <name>TPS3</name>
  1278. <description>FLash TPS3 register</description>
  1279. <bitRange>[11:0]</bitRange>
  1280. </field>
  1281. </fields>
  1282. </register>
  1283. <register>
  1284. <name>TS3</name>
  1285. <displayName>TS3</displayName>
  1286. <description>Flash TS3 register</description>
  1287. <addressOffset>0x110</addressOffset>
  1288. <resetValue>0xB4</resetValue>
  1289. <fields>
  1290. <field>
  1291. <name>TS3</name>
  1292. <description>FLash TS3 register</description>
  1293. <bitRange>[8:0]</bitRange>
  1294. </field>
  1295. </fields>
  1296. </register>
  1297. <register>
  1298. <name>PERTPE</name>
  1299. <displayName>PERTPE</displayName>
  1300. <description>Flash PERTPE register</description>
  1301. <addressOffset>0x114</addressOffset>
  1302. <resetValue>0x14820</resetValue>
  1303. <fields>
  1304. <field>
  1305. <name>PERTPE</name>
  1306. <description>FLash PERTPE register</description>
  1307. <bitRange>[17:0]</bitRange>
  1308. </field>
  1309. </fields>
  1310. </register>
  1311. <register>
  1312. <name>SMERTPE</name>
  1313. <displayName>SMERTPE</displayName>
  1314. <description>Flash SMERTPE register</description>
  1315. <addressOffset>0x118</addressOffset>
  1316. <resetValue>0x14820</resetValue>
  1317. <fields>
  1318. <field>
  1319. <name>SMERTPE</name>
  1320. <description>FLash SMERTPE register</description>
  1321. <bitRange>[17:0]</bitRange>
  1322. </field>
  1323. </fields>
  1324. </register>
  1325. <register>
  1326. <name>PRGTPE</name>
  1327. <displayName>PRGTPE</displayName>
  1328. <description>Flash PRGTPE register</description>
  1329. <addressOffset>0x11C</addressOffset>
  1330. <resetValue>0x5DC0</resetValue>
  1331. <fields>
  1332. <field>
  1333. <name>PRGTPE</name>
  1334. <description>FLash PRGTPE register</description>
  1335. <bitRange>[15:0]</bitRange>
  1336. </field>
  1337. </fields>
  1338. </register>
  1339. <register>
  1340. <name>PRETPE</name>
  1341. <displayName>PRETPE</displayName>
  1342. <description>Flash PRETPE register</description>
  1343. <addressOffset>0x120</addressOffset>
  1344. <resetValue>0x12C0</resetValue>
  1345. <fields>
  1346. <field>
  1347. <name>PRETPE</name>
  1348. <description>FLash PRETPE register</description>
  1349. <bitRange>[13:0]</bitRange>
  1350. </field>
  1351. </fields>
  1352. </register>
  1353. </registers>
  1354. </peripheral>
  1355. <peripheral>
  1356. <name>GPIOA</name>
  1357. <description>General-purpose I/Os</description>
  1358. <groupName>GPIO</groupName>
  1359. <baseAddress>0x50000000</baseAddress>
  1360. <addressBlock>
  1361. <offset>0x0</offset>
  1362. <size>0x400</size>
  1363. <usage>registers</usage>
  1364. </addressBlock>
  1365. <registers>
  1366. <register>
  1367. <name>MODER</name>
  1368. <displayName>MODER</displayName>
  1369. <description>GPIO port mode register</description>
  1370. <addressOffset>0x0</addressOffset>
  1371. <resetValue>0xEBFFFFFF</resetValue>
  1372. <fields>
  1373. <field>
  1374. <name>MODE0</name>
  1375. <description>Port x configuration bits (y = 0..15)</description>
  1376. <bitRange>[1:0]</bitRange>
  1377. </field>
  1378. <field>
  1379. <name>MODE1</name>
  1380. <description>Port x configuration bits (y = 0..15)</description>
  1381. <bitRange>[3:2]</bitRange>
  1382. </field>
  1383. <field>
  1384. <name>MODE2</name>
  1385. <description>Port x configuration bits (y = 0..15)</description>
  1386. <bitRange>[5:4]</bitRange>
  1387. </field>
  1388. <field>
  1389. <name>MODE3</name>
  1390. <description>Port x configuration bits (y = 0..15)</description>
  1391. <bitRange>[7:6]</bitRange>
  1392. </field>
  1393. <field>
  1394. <name>MODE4</name>
  1395. <description>Port x configuration bits (y = 0..15)</description>
  1396. <bitRange>[9:8]</bitRange>
  1397. </field>
  1398. <field>
  1399. <name>MODE5</name>
  1400. <description>Port x configuration bits (y = 0..15)</description>
  1401. <bitRange>[11:10]</bitRange>
  1402. </field>
  1403. <field>
  1404. <name>MODE6</name>
  1405. <description>Port x configuration bits (y = 0..15)</description>
  1406. <bitRange>[13:12]</bitRange>
  1407. </field>
  1408. <field>
  1409. <name>MODE7</name>
  1410. <description>Port x configuration bits (y = 0..15)</description>
  1411. <bitRange>[15:14]</bitRange>
  1412. </field>
  1413. </fields>
  1414. </register>
  1415. <register>
  1416. <name>OTYPER</name>
  1417. <displayName>OTYPER</displayName>
  1418. <description>GPIO port output type register</description>
  1419. <addressOffset>0x4</addressOffset>
  1420. <fields>
  1421. <field>
  1422. <name>OT0</name>
  1423. <description>Port x configuration bits (y = 0..15)</description>
  1424. <bitRange>[0:0]</bitRange>
  1425. </field>
  1426. <field>
  1427. <name>OT1</name>
  1428. <description>Port x configuration bits (y = 0..15)</description>
  1429. <bitRange>[1:1]</bitRange>
  1430. </field>
  1431. <field>
  1432. <name>OT2</name>
  1433. <description>Port x configuration bits (y = 0..15)</description>
  1434. <bitRange>[2:2]</bitRange>
  1435. </field>
  1436. <field>
  1437. <name>OT3</name>
  1438. <description>Port x configuration bits (y = 0..15)</description>
  1439. <bitRange>[3:3]</bitRange>
  1440. </field>
  1441. <field>
  1442. <name>OT4</name>
  1443. <description>Port x configuration bits (y = 0..15)</description>
  1444. <bitRange>[4:4]</bitRange>
  1445. </field>
  1446. <field>
  1447. <name>OT5</name>
  1448. <description>Port x configuration bits (y = 0..15)</description>
  1449. <bitRange>[5:5]</bitRange>
  1450. </field>
  1451. <field>
  1452. <name>OT6</name>
  1453. <description>Port x configuration bits (y = 0..15)</description>
  1454. <bitRange>[6:6]</bitRange>
  1455. </field>
  1456. <field>
  1457. <name>OT7</name>
  1458. <description>Port x configuration bits (y = 0..15)</description>
  1459. <bitRange>[7:7]</bitRange>
  1460. </field>
  1461. </fields>
  1462. </register>
  1463. <register>
  1464. <name>OSPEEDR</name>
  1465. <displayName>OSPEEDR</displayName>
  1466. <description>GPIO port output speed register</description>
  1467. <addressOffset>0x8</addressOffset>
  1468. <resetValue>0xC000000</resetValue>
  1469. <fields>
  1470. <field>
  1471. <name>OSPEED0</name>
  1472. <description>Port x configuration bits (y = 0..15)</description>
  1473. <bitRange>[1:0]</bitRange>
  1474. </field>
  1475. <field>
  1476. <name>OSPEED1</name>
  1477. <description>Port x configuration bits (y = 0..15)</description>
  1478. <bitRange>[3:2]</bitRange>
  1479. </field>
  1480. <field>
  1481. <name>OSPEED2</name>
  1482. <description>Port x configuration bits (y = 0..15)</description>
  1483. <bitRange>[5:4]</bitRange>
  1484. </field>
  1485. <field>
  1486. <name>OSPEED3</name>
  1487. <description>Port x configuration bits (y = 0..15)</description>
  1488. <bitRange>[7:6]</bitRange>
  1489. </field>
  1490. <field>
  1491. <name>OSPEED4</name>
  1492. <description>Port x configuration bits (y = 0..15)</description>
  1493. <bitRange>[9:8]</bitRange>
  1494. </field>
  1495. <field>
  1496. <name>OSPEED5</name>
  1497. <description>Port x configuration bits (y = 0..15)</description>
  1498. <bitRange>[11:10]</bitRange>
  1499. </field>
  1500. <field>
  1501. <name>OSPEED6</name>
  1502. <description>Port x configuration bits (y = 0..15)</description>
  1503. <bitRange>[13:12]</bitRange>
  1504. </field>
  1505. <field>
  1506. <name>OSPEED7</name>
  1507. <description>Port x configuration bits (y = 0..15)</description>
  1508. <bitRange>[15:14]</bitRange>
  1509. </field>
  1510. </fields>
  1511. </register>
  1512. <register>
  1513. <name>PUPDR</name>
  1514. <displayName>PUPDR</displayName>
  1515. <description>GPIO port pull-up/pull-down register</description>
  1516. <addressOffset>0xC</addressOffset>
  1517. <resetValue>0x24000000</resetValue>
  1518. <fields>
  1519. <field>
  1520. <name>PUPD0</name>
  1521. <description>Port x configuration bits (y = 0..15)</description>
  1522. <bitRange>[1:0]</bitRange>
  1523. </field>
  1524. <field>
  1525. <name>PUPD1</name>
  1526. <description>Port x configuration bits (y = 0..15)</description>
  1527. <bitRange>[3:2]</bitRange>
  1528. </field>
  1529. <field>
  1530. <name>PUPD2</name>
  1531. <description>Port x configuration bits (y = 0..15)</description>
  1532. <bitRange>[5:4]</bitRange>
  1533. </field>
  1534. <field>
  1535. <name>PUPD3</name>
  1536. <description>Port x configuration bits (y = 0..15)</description>
  1537. <bitRange>[7:6]</bitRange>
  1538. </field>
  1539. <field>
  1540. <name>PUPD4</name>
  1541. <description>Port x configuration bits (y = 0..15)</description>
  1542. <bitRange>[9:8]</bitRange>
  1543. </field>
  1544. <field>
  1545. <name>PUPD5</name>
  1546. <description>Port x configuration bits (y = 0..15)</description>
  1547. <bitRange>[11:10]</bitRange>
  1548. </field>
  1549. <field>
  1550. <name>PUPD6</name>
  1551. <description>Port x configuration bits (y = 0..15)</description>
  1552. <bitRange>[13:12]</bitRange>
  1553. </field>
  1554. <field>
  1555. <name>PUPD7</name>
  1556. <description>Port x configuration bits (y = 0..15)</description>
  1557. <bitRange>[15:14]</bitRange>
  1558. </field>
  1559. </fields>
  1560. </register>
  1561. <register>
  1562. <name>IDR</name>
  1563. <displayName>IDR</displayName>
  1564. <description>GPIO port input data register</description>
  1565. <addressOffset>0x10</addressOffset>
  1566. <access>read-only</access>
  1567. <fields>
  1568. <field>
  1569. <name>ID0</name>
  1570. <description>Port input data (y = 0..15)</description>
  1571. <bitRange>[0:0]</bitRange>
  1572. </field>
  1573. <field>
  1574. <name>ID1</name>
  1575. <description>Port input data (y = 0..15)</description>
  1576. <bitRange>[1:1]</bitRange>
  1577. </field>
  1578. <field>
  1579. <name>ID2</name>
  1580. <description>Port input data (y = 0..15)</description>
  1581. <bitRange>[2:2]</bitRange>
  1582. </field>
  1583. <field>
  1584. <name>ID3</name>
  1585. <description>Port input data (y = 0..15)</description>
  1586. <bitRange>[3:3]</bitRange>
  1587. </field>
  1588. <field>
  1589. <name>ID4</name>
  1590. <description>Port input data (y = 0..15)</description>
  1591. <bitRange>[4:4]</bitRange>
  1592. </field>
  1593. <field>
  1594. <name>ID5</name>
  1595. <description>Port input data (y = 0..15)</description>
  1596. <bitRange>[5:5]</bitRange>
  1597. </field>
  1598. <field>
  1599. <name>ID6</name>
  1600. <description>Port input data (y = 0..15)</description>
  1601. <bitRange>[6:6]</bitRange>
  1602. </field>
  1603. <field>
  1604. <name>ID7</name>
  1605. <description>Port input data (y = 0..15)</description>
  1606. <bitRange>[7:7]</bitRange>
  1607. </field>
  1608. </fields>
  1609. </register>
  1610. <register>
  1611. <name>ODR</name>
  1612. <displayName>ODR</displayName>
  1613. <description>GPIO port output data register</description>
  1614. <addressOffset>0x14</addressOffset>
  1615. <fields>
  1616. <field>
  1617. <name>OD0</name>
  1618. <description>Port output data (y = 0..15)</description>
  1619. <bitRange>[0:0]</bitRange>
  1620. </field>
  1621. <field>
  1622. <name>OD1</name>
  1623. <description>Port output data (y = 0..15)</description>
  1624. <bitRange>[1:1]</bitRange>
  1625. </field>
  1626. <field>
  1627. <name>OD2</name>
  1628. <description>Port output data (y = 0..15)</description>
  1629. <bitRange>[2:2]</bitRange>
  1630. </field>
  1631. <field>
  1632. <name>OD3</name>
  1633. <description>Port output data (y = 0..15)</description>
  1634. <bitRange>[3:3]</bitRange>
  1635. </field>
  1636. <field>
  1637. <name>OD4</name>
  1638. <description>Port output data (y = 0..15)</description>
  1639. <bitRange>[4:4]</bitRange>
  1640. </field>
  1641. <field>
  1642. <name>OD5</name>
  1643. <description>Port output data (y = 0..15)</description>
  1644. <bitRange>[5:5]</bitRange>
  1645. </field>
  1646. <field>
  1647. <name>OD6</name>
  1648. <description>Port output data (y = 0..15)</description>
  1649. <bitRange>[6:6]</bitRange>
  1650. </field>
  1651. <field>
  1652. <name>OD7</name>
  1653. <description>Port output data (y = 0..15)</description>
  1654. <bitRange>[7:7]</bitRange>
  1655. </field>
  1656. </fields>
  1657. </register>
  1658. <register>
  1659. <name>BSRR</name>
  1660. <displayName>BSRR</displayName>
  1661. <description>GPIO port bit set/reset register</description>
  1662. <addressOffset>0x18</addressOffset>
  1663. <access>write-only</access>
  1664. <fields>
  1665. <field>
  1666. <name>BS0</name>
  1667. <description>Port x set bit y (y= 0..15)</description>
  1668. <bitRange>[0:0]</bitRange>
  1669. </field>
  1670. <field>
  1671. <name>BS1</name>
  1672. <description>Port x set bit y (y= 0..15)</description>
  1673. <bitRange>[1:1]</bitRange>
  1674. </field>
  1675. <field>
  1676. <name>BS2</name>
  1677. <description>Port x set bit y (y= 0..15)</description>
  1678. <bitRange>[2:2]</bitRange>
  1679. </field>
  1680. <field>
  1681. <name>BS3</name>
  1682. <description>Port x set bit y (y= 0..15)</description>
  1683. <bitRange>[3:3]</bitRange>
  1684. </field>
  1685. <field>
  1686. <name>BS4</name>
  1687. <description>Port x set bit y (y= 0..15)</description>
  1688. <bitRange>[4:4]</bitRange>
  1689. </field>
  1690. <field>
  1691. <name>BS5</name>
  1692. <description>Port x set bit y (y= 0..15)</description>
  1693. <bitRange>[5:5]</bitRange>
  1694. </field>
  1695. <field>
  1696. <name>BS6</name>
  1697. <description>Port x set bit y (y= 0..15)</description>
  1698. <bitRange>[6:6]</bitRange>
  1699. </field>
  1700. <field>
  1701. <name>BS7</name>
  1702. <description>Port x set bit y (y= 0..15)</description>
  1703. <bitRange>[7:7]</bitRange>
  1704. </field>
  1705. <field>
  1706. <name>BR0</name>
  1707. <description>Port x set bit y (y= 0..15)</description>
  1708. <bitRange>[16:16]</bitRange>
  1709. </field>
  1710. <field>
  1711. <name>BR1</name>
  1712. <description>Port x reset bit y (y = 0..15)</description>
  1713. <bitRange>[17:17]</bitRange>
  1714. </field>
  1715. <field>
  1716. <name>BR2</name>
  1717. <description>Port x reset bit y (y = 0..15)</description>
  1718. <bitRange>[18:18]</bitRange>
  1719. </field>
  1720. <field>
  1721. <name>BR3</name>
  1722. <description>Port x reset bit y (y = 0..15)</description>
  1723. <bitRange>[19:19]</bitRange>
  1724. </field>
  1725. <field>
  1726. <name>BR4</name>
  1727. <description>Port x reset bit y (y = 0..15)</description>
  1728. <bitRange>[20:20]</bitRange>
  1729. </field>
  1730. <field>
  1731. <name>BR5</name>
  1732. <description>Port x reset bit y (y = 0..15)</description>
  1733. <bitRange>[21:21]</bitRange>
  1734. </field>
  1735. <field>
  1736. <name>BR6</name>
  1737. <description>Port x reset bit y (y = 0..15)</description>
  1738. <bitRange>[22:22]</bitRange>
  1739. </field>
  1740. <field>
  1741. <name>BR7</name>
  1742. <description>Port x reset bit y (y = 0..15)</description>
  1743. <bitRange>[23:23]</bitRange>
  1744. </field>
  1745. </fields>
  1746. </register>
  1747. <register>
  1748. <name>LCKR</name>
  1749. <displayName>LCKR</displayName>
  1750. <description>GPIO port configuration lock register</description>
  1751. <addressOffset>0x1C</addressOffset>
  1752. <fields>
  1753. <field>
  1754. <name>LCK0</name>
  1755. <description>Port x lock bit y (y= 0..15)</description>
  1756. <bitRange>[0:0]</bitRange>
  1757. </field>
  1758. <field>
  1759. <name>LCK1</name>
  1760. <description>Port x lock bit y (y= 0..15)</description>
  1761. <bitRange>[1:1]</bitRange>
  1762. </field>
  1763. <field>
  1764. <name>LCK2</name>
  1765. <description>Port x lock bit y (y= 0..15)</description>
  1766. <bitRange>[2:2]</bitRange>
  1767. </field>
  1768. <field>
  1769. <name>LCK3</name>
  1770. <description>Port x lock bit y (y= 0..15)</description>
  1771. <bitRange>[3:3]</bitRange>
  1772. </field>
  1773. <field>
  1774. <name>LCK4</name>
  1775. <description>Port x lock bit y (y= 0..15)</description>
  1776. <bitRange>[4:4]</bitRange>
  1777. </field>
  1778. <field>
  1779. <name>LCK5</name>
  1780. <description>Port x lock bit y (y= 0..15)</description>
  1781. <bitRange>[5:5]</bitRange>
  1782. </field>
  1783. <field>
  1784. <name>LCK6</name>
  1785. <description>Port x lock bit y (y= 0..15)</description>
  1786. <bitRange>[6:6]</bitRange>
  1787. </field>
  1788. <field>
  1789. <name>LCK7</name>
  1790. <description>Port x lock bit y (y= 0..15)</description>
  1791. <bitRange>[7:7]</bitRange>
  1792. </field>
  1793. <field>
  1794. <name>LCKK</name>
  1795. <description>Port x lock bit y (y= 0..15)</description>
  1796. <bitRange>[16:16]</bitRange>
  1797. </field>
  1798. </fields>
  1799. </register>
  1800. <register>
  1801. <name>AFRL</name>
  1802. <displayName>AFRL</displayName>
  1803. <description>GPIO alternate function low register</description>
  1804. <addressOffset>0x20</addressOffset>
  1805. <fields>
  1806. <field>
  1807. <name>AFSEL0</name>
  1808. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1809. <bitRange>[3:0]</bitRange>
  1810. </field>
  1811. <field>
  1812. <name>AFSEL1</name>
  1813. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1814. <bitRange>[7:4]</bitRange>
  1815. </field>
  1816. <field>
  1817. <name>AFSEL2</name>
  1818. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1819. <bitRange>[11:8]</bitRange>
  1820. </field>
  1821. <field>
  1822. <name>AFSEL3</name>
  1823. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1824. <bitRange>[15:12]</bitRange>
  1825. </field>
  1826. <field>
  1827. <name>AFSEL4</name>
  1828. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1829. <bitRange>[19:16]</bitRange>
  1830. </field>
  1831. <field>
  1832. <name>AFSEL5</name>
  1833. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1834. <bitRange>[23:20]</bitRange>
  1835. </field>
  1836. <field>
  1837. <name>AFSEL6</name>
  1838. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1839. <bitRange>[27:24]</bitRange>
  1840. </field>
  1841. <field>
  1842. <name>AFSEL7</name>
  1843. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  1844. <bitRange>[31:28]</bitRange>
  1845. </field>
  1846. </fields>
  1847. </register>
  1848. <register>
  1849. <name>BRR</name>
  1850. <displayName>BRR</displayName>
  1851. <description>port bit reset register</description>
  1852. <addressOffset>0x28</addressOffset>
  1853. <access>write-only</access>
  1854. <fields>
  1855. <field>
  1856. <name>BR0</name>
  1857. <description>Port Reset bit</description>
  1858. <bitRange>[0:0]</bitRange>
  1859. </field>
  1860. <field>
  1861. <name>BR1</name>
  1862. <description>Port Reset bit</description>
  1863. <bitRange>[1:1]</bitRange>
  1864. </field>
  1865. <field>
  1866. <name>BR2</name>
  1867. <description>Port Reset bit</description>
  1868. <bitRange>[2:2]</bitRange>
  1869. </field>
  1870. <field>
  1871. <name>BR3</name>
  1872. <description>Port Reset bit</description>
  1873. <bitRange>[3:3]</bitRange>
  1874. </field>
  1875. <field>
  1876. <name>BR4</name>
  1877. <description>Port Reset bit</description>
  1878. <bitRange>[4:4]</bitRange>
  1879. </field>
  1880. <field>
  1881. <name>BR5</name>
  1882. <description>Port Reset bit</description>
  1883. <bitRange>[5:5]</bitRange>
  1884. </field>
  1885. <field>
  1886. <name>BR6</name>
  1887. <description>Port Reset bit</description>
  1888. <bitRange>[6:6]</bitRange>
  1889. </field>
  1890. <field>
  1891. <name>BR7</name>
  1892. <description>Port Reset bit</description>
  1893. <bitRange>[7:7]</bitRange>
  1894. </field>
  1895. </fields>
  1896. </register>
  1897. </registers>
  1898. </peripheral>
  1899. <peripheral derivedFrom="GPIOA">
  1900. <name>GPIOB</name>
  1901. <baseAddress>0x50000400</baseAddress>
  1902. </peripheral>
  1903. <peripheral>
  1904. <name>GPIOC</name>
  1905. <description>General-purpose I/Os</description>
  1906. <groupName>GPIO</groupName>
  1907. <baseAddress>0x50000800</baseAddress>
  1908. <addressBlock>
  1909. <offset>0x0</offset>
  1910. <size>0x400</size>
  1911. <usage>registers</usage>
  1912. </addressBlock>
  1913. <registers>
  1914. <register>
  1915. <name>MODER</name>
  1916. <displayName>MODER</displayName>
  1917. <description>GPIO port mode register</description>
  1918. <addressOffset>0x0</addressOffset>
  1919. <resetValue>0xEBFFFFFF</resetValue>
  1920. <fields>
  1921. <field>
  1922. <name>MODE0</name>
  1923. <description>Port x configuration bits (y = 0..15)</description>
  1924. <bitRange>[1:0]</bitRange>
  1925. </field>
  1926. <field>
  1927. <name>MODE1</name>
  1928. <description>Port x configuration bits (y = 0..15)</description>
  1929. <bitRange>[3:2]</bitRange>
  1930. </field>
  1931. </fields>
  1932. </register>
  1933. <register>
  1934. <name>OTYPER</name>
  1935. <displayName>OTYPER</displayName>
  1936. <description>GPIO port output type register</description>
  1937. <addressOffset>0x4</addressOffset>
  1938. <fields>
  1939. <field>
  1940. <name>OT0</name>
  1941. <description>Port x configuration bits (y = 0..15)</description>
  1942. <bitRange>[0:0]</bitRange>
  1943. </field>
  1944. <field>
  1945. <name>OT1</name>
  1946. <description>Port x configuration bits (y = 0..15)</description>
  1947. <bitRange>[1:1]</bitRange>
  1948. </field>
  1949. </fields>
  1950. </register>
  1951. <register>
  1952. <name>OSPEEDR</name>
  1953. <displayName>OSPEEDR</displayName>
  1954. <description>GPIO port output speed register</description>
  1955. <addressOffset>0x8</addressOffset>
  1956. <resetValue>0xC000000</resetValue>
  1957. <fields>
  1958. <field>
  1959. <name>OSPEED0</name>
  1960. <description>Port x configuration bits (y = 0..15)</description>
  1961. <bitRange>[1:0]</bitRange>
  1962. </field>
  1963. <field>
  1964. <name>OSPEED1</name>
  1965. <description>Port x configuration bits (y = 0..15)</description>
  1966. <bitRange>[3:2]</bitRange>
  1967. </field>
  1968. </fields>
  1969. </register>
  1970. <register>
  1971. <name>PUPDR</name>
  1972. <displayName>PUPDR</displayName>
  1973. <description>GPIO port pull-up/pull-down register</description>
  1974. <addressOffset>0xC</addressOffset>
  1975. <resetValue>0x24000000</resetValue>
  1976. <fields>
  1977. <field>
  1978. <name>PUPD0</name>
  1979. <description>Port x configuration bits (y = 0..15)</description>
  1980. <bitRange>[1:0]</bitRange>
  1981. </field>
  1982. <field>
  1983. <name>PUPD1</name>
  1984. <description>Port x configuration bits (y = 0..15)</description>
  1985. <bitRange>[3:2]</bitRange>
  1986. </field>
  1987. </fields>
  1988. </register>
  1989. <register>
  1990. <name>IDR</name>
  1991. <displayName>IDR</displayName>
  1992. <description>GPIO port input data register</description>
  1993. <addressOffset>0x10</addressOffset>
  1994. <access>read-only</access>
  1995. <fields>
  1996. <field>
  1997. <name>ID0</name>
  1998. <description>Port input data (y = 0..15)</description>
  1999. <bitRange>[0:0]</bitRange>
  2000. </field>
  2001. <field>
  2002. <name>ID1</name>
  2003. <description>Port input data (y = 0..15)</description>
  2004. <bitRange>[1:1]</bitRange>
  2005. </field>
  2006. </fields>
  2007. </register>
  2008. <register>
  2009. <name>ODR</name>
  2010. <displayName>ODR</displayName>
  2011. <description>GPIO port output data register</description>
  2012. <addressOffset>0x14</addressOffset>
  2013. <fields>
  2014. <field>
  2015. <name>OD0</name>
  2016. <description>Port output data (y = 0..15)</description>
  2017. <bitRange>[0:0]</bitRange>
  2018. </field>
  2019. <field>
  2020. <name>OD1</name>
  2021. <description>Port output data (y = 0..15)</description>
  2022. <bitRange>[1:1]</bitRange>
  2023. </field>
  2024. </fields>
  2025. </register>
  2026. <register>
  2027. <name>BSRR</name>
  2028. <displayName>BSRR</displayName>
  2029. <description>GPIO port bit set/reset register</description>
  2030. <addressOffset>0x18</addressOffset>
  2031. <access>write-only</access>
  2032. <fields>
  2033. <field>
  2034. <name>BS0</name>
  2035. <description>Port x set bit y (y= 0..15)</description>
  2036. <bitRange>[0:0]</bitRange>
  2037. </field>
  2038. <field>
  2039. <name>BS1</name>
  2040. <description>Port x set bit y (y= 0..15)</description>
  2041. <bitRange>[1:1]</bitRange>
  2042. </field>
  2043. <field>
  2044. <name>BR0</name>
  2045. <description>Port x set bit y (y= 0..15)</description>
  2046. <bitRange>[16:16]</bitRange>
  2047. </field>
  2048. <field>
  2049. <name>BR1</name>
  2050. <description>Port x reset bit y (y = 0..15)</description>
  2051. <bitRange>[17:17]</bitRange>
  2052. </field>
  2053. </fields>
  2054. </register>
  2055. <register>
  2056. <name>LCKR</name>
  2057. <displayName>LCKR</displayName>
  2058. <description>GPIO port configuration lock register</description>
  2059. <addressOffset>0x1C</addressOffset>
  2060. <fields>
  2061. <field>
  2062. <name>LCK0</name>
  2063. <description>Port x lock bit y (y= 0..15)</description>
  2064. <bitRange>[0:0]</bitRange>
  2065. </field>
  2066. <field>
  2067. <name>LCK1</name>
  2068. <description>Port x lock bit y (y= 0..15)</description>
  2069. <bitRange>[1:1]</bitRange>
  2070. </field>
  2071. <field>
  2072. <name>LCKK</name>
  2073. <description>Port x lock bit y (y= 0..15)</description>
  2074. <bitRange>[16:16]</bitRange>
  2075. </field>
  2076. </fields>
  2077. </register>
  2078. <register>
  2079. <name>AFRL</name>
  2080. <displayName>AFRL</displayName>
  2081. <description>GPIO alternate function low register</description>
  2082. <addressOffset>0x20</addressOffset>
  2083. <fields>
  2084. <field>
  2085. <name>AFSEL0</name>
  2086. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  2087. <bitRange>[3:0]</bitRange>
  2088. </field>
  2089. <field>
  2090. <name>AFSEL1</name>
  2091. <description>Alternate function selection for port x bit y (y = 0..7)</description>
  2092. <bitRange>[7:4]</bitRange>
  2093. </field>
  2094. </fields>
  2095. </register>
  2096. <register>
  2097. <name>BRR</name>
  2098. <displayName>BRR</displayName>
  2099. <description>port bit reset register</description>
  2100. <addressOffset>0x28</addressOffset>
  2101. <access>write-only</access>
  2102. <fields>
  2103. <field>
  2104. <name>BR0</name>
  2105. <description>Port Reset bit</description>
  2106. <bitRange>[0:0]</bitRange>
  2107. </field>
  2108. <field>
  2109. <name>BR1</name>
  2110. <description>Port Reset bit</description>
  2111. <bitRange>[1:1]</bitRange>
  2112. </field>
  2113. </fields>
  2114. </register>
  2115. </registers>
  2116. </peripheral>
  2117. <peripheral>
  2118. <name>I2C</name>
  2119. <description>Inter integrated circuit</description>
  2120. <groupName>I2C</groupName>
  2121. <baseAddress>0x40005400</baseAddress>
  2122. <addressBlock>
  2123. <offset>0x0</offset>
  2124. <size>0x400</size>
  2125. <usage>registers</usage>
  2126. </addressBlock>
  2127. <interrupt>
  2128. <name>I2C1</name>
  2129. <description>I2C1 global Interrupt</description>
  2130. <value>23</value>
  2131. </interrupt>
  2132. <registers>
  2133. <register>
  2134. <name>CR1</name>
  2135. <displayName>CR1</displayName>
  2136. <description>Control register 1</description>
  2137. <addressOffset>0x0</addressOffset>
  2138. <fields>
  2139. <field>
  2140. <name>PE</name>
  2141. <description>Peripheral enable</description>
  2142. <bitRange>[0:0]</bitRange>
  2143. </field>
  2144. <field>
  2145. <name>ENGC</name>
  2146. <description>General call enable</description>
  2147. <bitRange>[6:6]</bitRange>
  2148. </field>
  2149. <field>
  2150. <name>NOSTRETCH</name>
  2151. <description>Clock stretching disable (Slavemode)</description>
  2152. <bitRange>[7:7]</bitRange>
  2153. </field>
  2154. <field>
  2155. <name>START</name>
  2156. <description>Start generation</description>
  2157. <bitRange>[8:8]</bitRange>
  2158. </field>
  2159. <field>
  2160. <name>STOP</name>
  2161. <description>Stop generation</description>
  2162. <bitRange>[9:9]</bitRange>
  2163. </field>
  2164. <field>
  2165. <name>ACK</name>
  2166. <description>Acknowledge enable</description>
  2167. <bitRange>[10:10]</bitRange>
  2168. </field>
  2169. <field>
  2170. <name>POS</name>
  2171. <description>Acknowledge/PEC Position (for datareception)</description>
  2172. <bitRange>[11:11]</bitRange>
  2173. </field>
  2174. <field>
  2175. <name>SWRST</name>
  2176. <description>Software reset</description>
  2177. <bitRange>[15:15]</bitRange>
  2178. </field>
  2179. </fields>
  2180. </register>
  2181. <register>
  2182. <name>CR2</name>
  2183. <displayName>CR2</displayName>
  2184. <description>Control register 2</description>
  2185. <addressOffset>0x4</addressOffset>
  2186. <fields>
  2187. <field>
  2188. <name>FREQ</name>
  2189. <description>Peripheral clock frequency</description>
  2190. <bitRange>[5:0]</bitRange>
  2191. </field>
  2192. <field>
  2193. <name>ITERREN</name>
  2194. <description>Error interrupt enable</description>
  2195. <bitRange>[8:8]</bitRange>
  2196. </field>
  2197. <field>
  2198. <name>ITEVTEN</name>
  2199. <description>Event interrupt enable</description>
  2200. <bitRange>[9:9]</bitRange>
  2201. </field>
  2202. <field>
  2203. <name>ITBUFEN</name>
  2204. <description>Buffer interrupt enable</description>
  2205. <bitRange>[10:10]</bitRange>
  2206. </field>
  2207. </fields>
  2208. </register>
  2209. <register>
  2210. <name>OAR1</name>
  2211. <displayName>OAR1</displayName>
  2212. <description>Own address register 1</description>
  2213. <addressOffset>0x8</addressOffset>
  2214. <fields>
  2215. <field>
  2216. <name>ADD</name>
  2217. <description>Interface address</description>
  2218. <bitRange>[7:1]</bitRange>
  2219. </field>
  2220. </fields>
  2221. </register>
  2222. <register>
  2223. <name>DR</name>
  2224. <displayName>DR</displayName>
  2225. <description>Data register</description>
  2226. <addressOffset>0x10</addressOffset>
  2227. <fields>
  2228. <field>
  2229. <name>DR</name>
  2230. <description>8-bit data register</description>
  2231. <bitRange>[7:0]</bitRange>
  2232. </field>
  2233. </fields>
  2234. </register>
  2235. <register>
  2236. <name>SR1</name>
  2237. <displayName>SR1</displayName>
  2238. <description>Status register 1</description>
  2239. <addressOffset>0x14</addressOffset>
  2240. <fields>
  2241. <field>
  2242. <name>SB</name>
  2243. <description>Start bit (Master mode)</description>
  2244. <bitRange>[0:0]</bitRange>
  2245. <access>read-only</access>
  2246. </field>
  2247. <field>
  2248. <name>ADDR</name>
  2249. <description>Address sent (master mode)/matched(slave mode)</description>
  2250. <bitRange>[1:1]</bitRange>
  2251. <access>read-only</access>
  2252. </field>
  2253. <field>
  2254. <name>BTF</name>
  2255. <description>Byte transfer finished</description>
  2256. <bitRange>[2:2]</bitRange>
  2257. <access>read-only</access>
  2258. </field>
  2259. <field>
  2260. <name>STOPF</name>
  2261. <description>Stop detection (slavemode)</description>
  2262. <bitRange>[4:4]</bitRange>
  2263. <access>read-only</access>
  2264. </field>
  2265. <field>
  2266. <name>RxNE</name>
  2267. <description>Data register not empty(receivers)</description>
  2268. <bitRange>[6:6]</bitRange>
  2269. <access>read-only</access>
  2270. </field>
  2271. <field>
  2272. <name>TxE</name>
  2273. <description>Data register empty(transmitters)</description>
  2274. <bitRange>[7:7]</bitRange>
  2275. <access>read-only</access>
  2276. </field>
  2277. <field>
  2278. <name>BERR</name>
  2279. <description>Bus error</description>
  2280. <bitRange>[8:8]</bitRange>
  2281. </field>
  2282. <field>
  2283. <name>ARLO</name>
  2284. <description>Arbitration lost (mastermode)</description>
  2285. <bitRange>[9:9]</bitRange>
  2286. </field>
  2287. <field>
  2288. <name>AF</name>
  2289. <description>Acknowledge failure</description>
  2290. <bitRange>[10:10]</bitRange>
  2291. </field>
  2292. <field>
  2293. <name>OVR</name>
  2294. <description>Overrun/Underrun</description>
  2295. <bitRange>[11:11]</bitRange>
  2296. </field>
  2297. </fields>
  2298. </register>
  2299. <register>
  2300. <name>SR2</name>
  2301. <displayName>SR2</displayName>
  2302. <description>Status register 2</description>
  2303. <addressOffset>0x18</addressOffset>
  2304. <access>read-only</access>
  2305. <fields>
  2306. <field>
  2307. <name>MSL</name>
  2308. <description>Master/slave</description>
  2309. <bitRange>[0:0]</bitRange>
  2310. </field>
  2311. <field>
  2312. <name>BUSY</name>
  2313. <description>Bus busy</description>
  2314. <bitRange>[1:1]</bitRange>
  2315. </field>
  2316. <field>
  2317. <name>TRA</name>
  2318. <description>Transmitter/receiver</description>
  2319. <bitRange>[2:2]</bitRange>
  2320. </field>
  2321. <field>
  2322. <name>GENCALL</name>
  2323. <description>General call address (Slavemode)</description>
  2324. <bitRange>[4:4]</bitRange>
  2325. </field>
  2326. </fields>
  2327. </register>
  2328. <register>
  2329. <name>CCR</name>
  2330. <displayName>CCR</displayName>
  2331. <description>Clock control register</description>
  2332. <addressOffset>0x1C</addressOffset>
  2333. <fields>
  2334. <field>
  2335. <name>CCR</name>
  2336. <description>Clock control register in Fast/Standardmode (Master mode)</description>
  2337. <bitRange>[11:0]</bitRange>
  2338. </field>
  2339. <field>
  2340. <name>DUTY</name>
  2341. <description>Fast mode duty cycle</description>
  2342. <bitRange>[14:14]</bitRange>
  2343. </field>
  2344. <field>
  2345. <name>F_S</name>
  2346. <description>I2C master mode selection</description>
  2347. <bitRange>[15:15]</bitRange>
  2348. </field>
  2349. </fields>
  2350. </register>
  2351. <register>
  2352. <name>TRISE</name>
  2353. <displayName>TRISE</displayName>
  2354. <description>TRISE register</description>
  2355. <addressOffset>0x20</addressOffset>
  2356. <resetValue>0x2</resetValue>
  2357. <fields>
  2358. <field>
  2359. <name>TRISE</name>
  2360. <description>Maximum rise time in Fast/Standard mode(Master mode)</description>
  2361. <bitRange>[5:0]</bitRange>
  2362. </field>
  2363. </fields>
  2364. </register>
  2365. </registers>
  2366. </peripheral>
  2367. <peripheral>
  2368. <name>IWDG</name>
  2369. <description>Independent watchdog</description>
  2370. <groupName>IWDG</groupName>
  2371. <baseAddress>0x40003000</baseAddress>
  2372. <addressBlock>
  2373. <offset>0x0</offset>
  2374. <size>0x400</size>
  2375. <usage>registers</usage>
  2376. </addressBlock>
  2377. <registers>
  2378. <register>
  2379. <name>KR</name>
  2380. <displayName>KR</displayName>
  2381. <description>Key register (IWDG_KR)</description>
  2382. <addressOffset>0x0</addressOffset>
  2383. <access>write-only</access>
  2384. <fields>
  2385. <field>
  2386. <name>KEY</name>
  2387. <description>Key value</description>
  2388. <bitRange>[15:0]</bitRange>
  2389. </field>
  2390. </fields>
  2391. </register>
  2392. <register>
  2393. <name>PR</name>
  2394. <displayName>PR</displayName>
  2395. <description>Prescaler register (IWDG_PR)</description>
  2396. <addressOffset>0x4</addressOffset>
  2397. <fields>
  2398. <field>
  2399. <name>PR</name>
  2400. <description>Prescaler divider</description>
  2401. <bitRange>[2:0]</bitRange>
  2402. </field>
  2403. </fields>
  2404. </register>
  2405. <register>
  2406. <name>RLR</name>
  2407. <displayName>RLR</displayName>
  2408. <description>Reload register (IWDG_RLR)</description>
  2409. <addressOffset>0x8</addressOffset>
  2410. <resetValue>0xFFF</resetValue>
  2411. <fields>
  2412. <field>
  2413. <name>RL</name>
  2414. <description>Watchdog counter reload value</description>
  2415. <bitRange>[11:0]</bitRange>
  2416. </field>
  2417. </fields>
  2418. </register>
  2419. <register>
  2420. <name>SR</name>
  2421. <displayName>SR</displayName>
  2422. <description>Status register (IWDG_SR)</description>
  2423. <addressOffset>0xC</addressOffset>
  2424. <access>read-only</access>
  2425. <fields>
  2426. <field>
  2427. <name>PVU</name>
  2428. <description>Watchdog prescaler value update</description>
  2429. <bitRange>[0:0]</bitRange>
  2430. </field>
  2431. <field>
  2432. <name>RVU</name>
  2433. <description>Watchdog counter reload value update</description>
  2434. <bitRange>[1:1]</bitRange>
  2435. </field>
  2436. </fields>
  2437. </register>
  2438. </registers>
  2439. </peripheral>
  2440. <peripheral>
  2441. <name>LPTIM1</name>
  2442. <description>Low power timer</description>
  2443. <groupName>LPTIM1</groupName>
  2444. <baseAddress>0x40007C00</baseAddress>
  2445. <addressBlock>
  2446. <offset>0x0</offset>
  2447. <size>0x400</size>
  2448. <usage>registers</usage>
  2449. </addressBlock>
  2450. <interrupt>
  2451. <name>LPTIM1_DAC</name>
  2452. <description>LPTIM1, DAC global Interrupts</description>
  2453. <value>17</value>
  2454. </interrupt>
  2455. <registers>
  2456. <register>
  2457. <name>ISR</name>
  2458. <displayName>ISR</displayName>
  2459. <description>Interrupt and Status Register</description>
  2460. <addressOffset>0x0</addressOffset>
  2461. <access>read-only</access>
  2462. <fields>
  2463. <field>
  2464. <name>ARRM</name>
  2465. <description>Autoreload match</description>
  2466. <bitRange>[1:1]</bitRange>
  2467. </field>
  2468. <field>
  2469. <name>ARROK</name>
  2470. <description>Autoreload match update OK</description>
  2471. <bitRange>[4:4]</bitRange>
  2472. </field>
  2473. </fields>
  2474. </register>
  2475. <register>
  2476. <name>ICR</name>
  2477. <displayName>ICR</displayName>
  2478. <description>Interrupt Clear Register</description>
  2479. <addressOffset>0x4</addressOffset>
  2480. <access>write-only</access>
  2481. <fields>
  2482. <field>
  2483. <name>ARRMCF</name>
  2484. <description>Autoreload match Clear Flag</description>
  2485. <bitRange>[1:1]</bitRange>
  2486. </field>
  2487. <field>
  2488. <name>ARROKCF</name>
  2489. <description>Autoreload match update OK Clear Flag</description>
  2490. <bitRange>[4:4]</bitRange>
  2491. </field>
  2492. </fields>
  2493. </register>
  2494. <register>
  2495. <name>IER</name>
  2496. <displayName>IER</displayName>
  2497. <description>Interrupt Enable Register</description>
  2498. <addressOffset>0x8</addressOffset>
  2499. <fields>
  2500. <field>
  2501. <name>ARRMIE</name>
  2502. <description>Autoreload matchInterrupt Enable</description>
  2503. <bitRange>[1:1]</bitRange>
  2504. </field>
  2505. <field>
  2506. <name>ARROKIE</name>
  2507. <description>Autoreload match update OK Interrupt Enable</description>
  2508. <bitRange>[4:4]</bitRange>
  2509. </field>
  2510. </fields>
  2511. </register>
  2512. <register>
  2513. <name>CFGR</name>
  2514. <displayName>CFGR</displayName>
  2515. <description>Configuration Register</description>
  2516. <addressOffset>0xC</addressOffset>
  2517. <fields>
  2518. <field>
  2519. <name>PRESC</name>
  2520. <description>Clock prescaler</description>
  2521. <bitRange>[11:9]</bitRange>
  2522. </field>
  2523. <field>
  2524. <name>PRELOAD</name>
  2525. <description>Registers update mode</description>
  2526. <bitRange>[22:22]</bitRange>
  2527. </field>
  2528. </fields>
  2529. </register>
  2530. <register>
  2531. <name>CR</name>
  2532. <displayName>CR</displayName>
  2533. <description>Control Register</description>
  2534. <addressOffset>0x10</addressOffset>
  2535. <fields>
  2536. <field>
  2537. <name>ENABLE</name>
  2538. <description>LPTIM Enable</description>
  2539. <bitRange>[0:0]</bitRange>
  2540. </field>
  2541. <field>
  2542. <name>SNGSTRT</name>
  2543. <description>LPTIM start in single mode</description>
  2544. <bitRange>[1:1]</bitRange>
  2545. </field>
  2546. <field>
  2547. <name>CNTSTRT</name>
  2548. <description>CNTSTRT</description>
  2549. <bitRange>[2:2]</bitRange>
  2550. </field>
  2551. <field>
  2552. <name>COUNTRST</name>
  2553. <description>Reset counter</description>
  2554. <bitRange>[3:3]</bitRange>
  2555. </field>
  2556. <field>
  2557. <name>RSTARE</name>
  2558. <description>Reset after read enable</description>
  2559. <bitRange>[4:4]</bitRange>
  2560. </field>
  2561. </fields>
  2562. </register>
  2563. <register>
  2564. <name>ARR</name>
  2565. <displayName>ARR</displayName>
  2566. <description>Autoreload Register</description>
  2567. <addressOffset>0x18</addressOffset>
  2568. <resetValue>0x1</resetValue>
  2569. <fields>
  2570. <field>
  2571. <name>ARR</name>
  2572. <description>Auto reload value</description>
  2573. <bitRange>[15:0]</bitRange>
  2574. </field>
  2575. </fields>
  2576. </register>
  2577. <register>
  2578. <name>CNT</name>
  2579. <displayName>CNT</displayName>
  2580. <description>Counter Register</description>
  2581. <addressOffset>0x1C</addressOffset>
  2582. <access>read-only</access>
  2583. <fields>
  2584. <field>
  2585. <name>CNT</name>
  2586. <description>Counter value</description>
  2587. <bitRange>[15:0]</bitRange>
  2588. </field>
  2589. </fields>
  2590. </register>
  2591. </registers>
  2592. </peripheral>
  2593. <peripheral>
  2594. <name>PWR</name>
  2595. <description>Power control</description>
  2596. <groupName>PWR</groupName>
  2597. <baseAddress>0x40007000</baseAddress>
  2598. <addressBlock>
  2599. <offset>0x0</offset>
  2600. <size>0x400</size>
  2601. <usage>registers</usage>
  2602. </addressBlock>
  2603. <registers>
  2604. <register>
  2605. <name>CR1</name>
  2606. <displayName>CR1</displayName>
  2607. <description>Power control register 1</description>
  2608. <addressOffset>0x0</addressOffset>
  2609. <resetValue>0x30000</resetValue>
  2610. <fields>
  2611. <field>
  2612. <name>BIAS_CR</name>
  2613. <description>MR Bias current</description>
  2614. <bitRange>[3:0]</bitRange>
  2615. </field>
  2616. <field>
  2617. <name>BIAS_CR_SEL</name>
  2618. <description>MR Bias current selection</description>
  2619. <bitRange>[4:4]</bitRange>
  2620. </field>
  2621. <field>
  2622. <name>DBP</name>
  2623. <description>Disable backup domain write protection</description>
  2624. <bitRange>[7:7]</bitRange>
  2625. </field>
  2626. <field>
  2627. <name>VOS</name>
  2628. <description>Voltage scaling range selection</description>
  2629. <bitRange>[9:8]</bitRange>
  2630. </field>
  2631. <field>
  2632. <name>MRRDY_TIME</name>
  2633. <description>Time selection wakeup from LP to VR</description>
  2634. <bitRange>[11:10]</bitRange>
  2635. </field>
  2636. <field>
  2637. <name>FLS_SLPTIME</name>
  2638. <description>Flash wait time after wakeup from the stop mode</description>
  2639. <bitRange>[13:12]</bitRange>
  2640. </field>
  2641. <field>
  2642. <name>LPR</name>
  2643. <description>Low-power run</description>
  2644. <bitRange>[15:14]</bitRange>
  2645. </field>
  2646. <field>
  2647. <name>SRAM_RETV</name>
  2648. <description>SRAM retention voltage control</description>
  2649. <bitRange>[18:16]</bitRange>
  2650. </field>
  2651. <field>
  2652. <name>HSION_CTRL</name>
  2653. <description>HSI open time control</description>
  2654. <bitRange>[19:19]</bitRange>
  2655. </field>
  2656. </fields>
  2657. </register>
  2658. <register>
  2659. <name>CR2</name>
  2660. <displayName>CR2</displayName>
  2661. <description>Power control register 2</description>
  2662. <addressOffset>0x4</addressOffset>
  2663. <resetValue>0x500</resetValue>
  2664. <fields>
  2665. <field>
  2666. <name>FLTEN</name>
  2667. <description>Digital filter enable</description>
  2668. <bitRange>[8:8]</bitRange>
  2669. </field>
  2670. <field>
  2671. <name>FLT_TIME</name>
  2672. <description>Digital filter time configuration</description>
  2673. <bitRange>[11:9]</bitRange>
  2674. </field>
  2675. </fields>
  2676. </register>
  2677. </registers>
  2678. </peripheral>
  2679. <peripheral>
  2680. <name>RCC</name>
  2681. <description>Reset and clock control</description>
  2682. <groupName>RCC</groupName>
  2683. <baseAddress>0x40021000</baseAddress>
  2684. <addressBlock>
  2685. <offset>0x0</offset>
  2686. <size>0x400</size>
  2687. <usage>registers</usage>
  2688. </addressBlock>
  2689. <interrupt>
  2690. <name>RCC</name>
  2691. <description>RCC global Interrupt</description>
  2692. <value>4</value>
  2693. </interrupt>
  2694. <registers>
  2695. <register>
  2696. <name>CR</name>
  2697. <displayName>CR</displayName>
  2698. <description>Clock control register</description>
  2699. <addressOffset>0x0</addressOffset>
  2700. <resetValue>0x100</resetValue>
  2701. <fields>
  2702. <field>
  2703. <name>HSION</name>
  2704. <description>HSI16 clock enable</description>
  2705. <bitRange>[8:8]</bitRange>
  2706. </field>
  2707. <field>
  2708. <name>HSIRDY</name>
  2709. <description>HSI16 clock ready flag</description>
  2710. <bitRange>[10:10]</bitRange>
  2711. </field>
  2712. <field>
  2713. <name>HSIDIV</name>
  2714. <description>HSI16 clock division factor</description>
  2715. <bitRange>[13:11]</bitRange>
  2716. </field>
  2717. <field>
  2718. <name>HSEEN</name>
  2719. <bitRange>[18:18]</bitRange>
  2720. </field>
  2721. </fields>
  2722. </register>
  2723. <register>
  2724. <name>ICSCR</name>
  2725. <displayName>ICSCR</displayName>
  2726. <description>Internal clock sources calibration register</description>
  2727. <addressOffset>0x4</addressOffset>
  2728. <resetValue>0x10000000</resetValue>
  2729. <fields>
  2730. <field>
  2731. <name>HSI_TRIM</name>
  2732. <description>HSI clock trimming</description>
  2733. <bitRange>[12:0]</bitRange>
  2734. </field>
  2735. <field>
  2736. <name>HSI_FS</name>
  2737. <description>HSI frequency selection</description>
  2738. <bitRange>[15:13]</bitRange>
  2739. </field>
  2740. <field>
  2741. <name>LSI_TRIM</name>
  2742. <description>LSI clock trimming</description>
  2743. <bitRange>[24:16]</bitRange>
  2744. </field>
  2745. <field>
  2746. <name>LSI_STARTUP</name>
  2747. <description>LSI startup time</description>
  2748. <bitRange>[27:26]</bitRange>
  2749. </field>
  2750. </fields>
  2751. </register>
  2752. <register>
  2753. <name>CFGR</name>
  2754. <displayName>CFGR</displayName>
  2755. <description>Clock configuration register</description>
  2756. <addressOffset>0x8</addressOffset>
  2757. <fields>
  2758. <field>
  2759. <name>SW</name>
  2760. <description>System clock switch</description>
  2761. <bitRange>[2:0]</bitRange>
  2762. </field>
  2763. <field>
  2764. <name>SWS</name>
  2765. <description>System clock switch status</description>
  2766. <bitRange>[5:3]</bitRange>
  2767. <access>read-only</access>
  2768. </field>
  2769. <field>
  2770. <name>HPRE</name>
  2771. <description>AHB prescaler</description>
  2772. <bitRange>[11:8]</bitRange>
  2773. </field>
  2774. <field>
  2775. <name>PPRE</name>
  2776. <description>APB prescaler</description>
  2777. <bitRange>[14:12]</bitRange>
  2778. </field>
  2779. <field>
  2780. <name>MCOSEL</name>
  2781. <description>Microcontroller clock output</description>
  2782. <bitRange>[26:24]</bitRange>
  2783. </field>
  2784. <field>
  2785. <name>MCOPRE</name>
  2786. <description>Microcontroller clock output prescaler</description>
  2787. <bitRange>[30:28]</bitRange>
  2788. </field>
  2789. </fields>
  2790. </register>
  2791. <register>
  2792. <name>ECSCR</name>
  2793. <displayName>ECSCR</displayName>
  2794. <description>External clock source control register</description>
  2795. <addressOffset>0x10</addressOffset>
  2796. <fields>
  2797. <field>
  2798. <name>LSE_DRIVER</name>
  2799. <description>desc LSE_DRIVER</description>
  2800. <bitRange>[17:16]</bitRange>
  2801. </field>
  2802. <field>
  2803. <name>LSE_STARTUP</name>
  2804. <description>desc LSE_STARTUP</description>
  2805. <bitRange>[21:20]</bitRange>
  2806. </field>
  2807. </fields>
  2808. </register>
  2809. <register>
  2810. <name>CIER</name>
  2811. <displayName>CIER</displayName>
  2812. <description>Clock interrupt enable register</description>
  2813. <addressOffset>0x18</addressOffset>
  2814. <fields>
  2815. <field>
  2816. <name>LSIRDYIE</name>
  2817. <description>LSI ready interrupt enable</description>
  2818. <bitRange>[0:0]</bitRange>
  2819. </field>
  2820. <field>
  2821. <name>LSERDYIE</name>
  2822. <description>LSE ready interrupt enable</description>
  2823. <bitRange>[1:1]</bitRange>
  2824. </field>
  2825. <field>
  2826. <name>HSIRDYIE</name>
  2827. <description>HSI ready interrupt enable</description>
  2828. <bitRange>[3:3]</bitRange>
  2829. </field>
  2830. </fields>
  2831. </register>
  2832. <register>
  2833. <name>CIFR</name>
  2834. <displayName>CIFR</displayName>
  2835. <description>Clock interrupt flag register</description>
  2836. <addressOffset>0x1C</addressOffset>
  2837. <access>read-only</access>
  2838. <fields>
  2839. <field>
  2840. <name>LSIRDYF</name>
  2841. <description>LSI ready interrupt flag</description>
  2842. <bitRange>[0:0]</bitRange>
  2843. </field>
  2844. <field>
  2845. <name>LSERDYF</name>
  2846. <description>LSE ready interrupt flag</description>
  2847. <bitRange>[2:2]</bitRange>
  2848. </field>
  2849. <field>
  2850. <name>HSIRDYF</name>
  2851. <description>HSI ready interrupt flag</description>
  2852. <bitRange>[3:3]</bitRange>
  2853. </field>
  2854. <field>
  2855. <name>LSECSSF</name>
  2856. <description>LSE clock secure system interrupt flag</description>
  2857. <bitRange>[9:9]</bitRange>
  2858. </field>
  2859. </fields>
  2860. </register>
  2861. <register>
  2862. <name>CICR</name>
  2863. <displayName>CICR</displayName>
  2864. <description>Clock interrupt clear register</description>
  2865. <addressOffset>0x20</addressOffset>
  2866. <access>write-only</access>
  2867. <fields>
  2868. <field>
  2869. <name>LSIRDYC</name>
  2870. <description>LSI ready interrupt clear</description>
  2871. <bitRange>[0:0]</bitRange>
  2872. </field>
  2873. <field>
  2874. <name>LSERDYC</name>
  2875. <description>LSE ready interrupt clear</description>
  2876. <bitRange>[1:1]</bitRange>
  2877. </field>
  2878. <field>
  2879. <name>HSIRDYC</name>
  2880. <description>HSI ready interrupt clear</description>
  2881. <bitRange>[3:3]</bitRange>
  2882. </field>
  2883. <field>
  2884. <name>LSECSSC</name>
  2885. <description>LSE clock secure system interrupt flag clear</description>
  2886. <bitRange>[9:9]</bitRange>
  2887. </field>
  2888. </fields>
  2889. </register>
  2890. <register>
  2891. <name>IOPRSTR</name>
  2892. <displayName>IOPRSTR</displayName>
  2893. <description>GPIO reset register</description>
  2894. <addressOffset>0x24</addressOffset>
  2895. <fields>
  2896. <field>
  2897. <name>GPIOARST</name>
  2898. <description>I/O port A reset</description>
  2899. <bitRange>[0:0]</bitRange>
  2900. </field>
  2901. <field>
  2902. <name>GPIOBRST</name>
  2903. <description>I/O port B reset</description>
  2904. <bitRange>[1:1]</bitRange>
  2905. </field>
  2906. <field>
  2907. <name>GPIOCRST</name>
  2908. <description>I/O port C reset</description>
  2909. <bitRange>[2:2]</bitRange>
  2910. </field>
  2911. </fields>
  2912. </register>
  2913. <register>
  2914. <name>AHBRSTR</name>
  2915. <displayName>AHBRSTR</displayName>
  2916. <description>AHB peripheral reset register</description>
  2917. <addressOffset>0x28</addressOffset>
  2918. <fields>
  2919. <field>
  2920. <name>FLASHRST</name>
  2921. <description>FLASH reset</description>
  2922. <bitRange>[8:8]</bitRange>
  2923. </field>
  2924. <field>
  2925. <name>CRCRST</name>
  2926. <description>CRC reset</description>
  2927. <bitRange>[12:12]</bitRange>
  2928. </field>
  2929. </fields>
  2930. </register>
  2931. <register>
  2932. <name>APBRSTR1</name>
  2933. <displayName>APBRSTR1</displayName>
  2934. <description>APB peripheral reset register 1</description>
  2935. <addressOffset>0x2C</addressOffset>
  2936. <fields>
  2937. <field>
  2938. <name>I2CRST</name>
  2939. <description>I2C reset</description>
  2940. <bitRange>[21:21]</bitRange>
  2941. </field>
  2942. <field>
  2943. <name>DBGRST</name>
  2944. <description>Debug support reset</description>
  2945. <bitRange>[27:27]</bitRange>
  2946. </field>
  2947. <field>
  2948. <name>PWRRST</name>
  2949. <description>Power interface reset</description>
  2950. <bitRange>[28:28]</bitRange>
  2951. </field>
  2952. <field>
  2953. <name>LPTIMRST</name>
  2954. <description>Low Power Timer reset</description>
  2955. <bitRange>[31:31]</bitRange>
  2956. </field>
  2957. </fields>
  2958. </register>
  2959. <register>
  2960. <name>APBRSTR2</name>
  2961. <displayName>APBRSTR2</displayName>
  2962. <description>APB peripheral reset register 2</description>
  2963. <addressOffset>0x30</addressOffset>
  2964. <fields>
  2965. <field>
  2966. <name>SYSCFGRST</name>
  2967. <description>SYSCFG reset</description>
  2968. <bitRange>[0:0]</bitRange>
  2969. </field>
  2970. <field>
  2971. <name>TIM1RST</name>
  2972. <description>TIM1 timer reset</description>
  2973. <bitRange>[11:11]</bitRange>
  2974. </field>
  2975. <field>
  2976. <name>USART1RST</name>
  2977. <description>USART1 reset</description>
  2978. <bitRange>[14:14]</bitRange>
  2979. </field>
  2980. <field>
  2981. <name>TIM14RST</name>
  2982. <description>TIM14 reset</description>
  2983. <bitRange>[15:15]</bitRange>
  2984. </field>
  2985. <field>
  2986. <name>ADCRST</name>
  2987. <description>ADC reset</description>
  2988. <bitRange>[20:20]</bitRange>
  2989. </field>
  2990. </fields>
  2991. </register>
  2992. <register>
  2993. <name>IOPENR</name>
  2994. <displayName>IOPENR</displayName>
  2995. <description>GPIO clock enable register</description>
  2996. <addressOffset>0x34</addressOffset>
  2997. <fields>
  2998. <field>
  2999. <name>GPIOAEN</name>
  3000. <description>I/O port A clock enable</description>
  3001. <bitRange>[0:0]</bitRange>
  3002. </field>
  3003. <field>
  3004. <name>GPIOBEN</name>
  3005. <description>I/O port B clock enable</description>
  3006. <bitRange>[1:1]</bitRange>
  3007. </field>
  3008. <field>
  3009. <name>GPIOCEN</name>
  3010. <description>I/O port C clock enable</description>
  3011. <bitRange>[2:2]</bitRange>
  3012. </field>
  3013. </fields>
  3014. </register>
  3015. <register>
  3016. <name>AHBENR</name>
  3017. <displayName>AHBENR</displayName>
  3018. <description>AHB peripheral clock enable register</description>
  3019. <addressOffset>0x38</addressOffset>
  3020. <fields>
  3021. <field>
  3022. <name>FLASHEN</name>
  3023. <description>Flash memory interface clock enable</description>
  3024. <bitRange>[8:8]</bitRange>
  3025. </field>
  3026. <field>
  3027. <name>SRAMEN</name>
  3028. <description>SRAM memory interface clock enable</description>
  3029. <bitRange>[9:9]</bitRange>
  3030. </field>
  3031. <field>
  3032. <name>CRCEN</name>
  3033. <description>CRC clock enable</description>
  3034. <bitRange>[12:12]</bitRange>
  3035. </field>
  3036. </fields>
  3037. </register>
  3038. <register>
  3039. <name>APBENR1</name>
  3040. <displayName>APBENR1</displayName>
  3041. <description>APB peripheral clock enable register 1</description>
  3042. <addressOffset>0x3C</addressOffset>
  3043. <fields>
  3044. <field>
  3045. <name>I2CEN</name>
  3046. <description>I2C clock enable</description>
  3047. <bitRange>[21:21]</bitRange>
  3048. </field>
  3049. <field>
  3050. <name>DBGEN</name>
  3051. <description>Debug support clock enable</description>
  3052. <bitRange>[27:27]</bitRange>
  3053. </field>
  3054. <field>
  3055. <name>PWREN</name>
  3056. <description>Power interface clock enable</description>
  3057. <bitRange>[28:28]</bitRange>
  3058. </field>
  3059. <field>
  3060. <name>LPTIMEN</name>
  3061. <description>LPTIM clock enable</description>
  3062. <bitRange>[31:31]</bitRange>
  3063. </field>
  3064. </fields>
  3065. </register>
  3066. <register>
  3067. <name>APBENR2</name>
  3068. <displayName>APBENR2</displayName>
  3069. <description>APB peripheral clock enable register 2</description>
  3070. <addressOffset>0x40</addressOffset>
  3071. <fields>
  3072. <field>
  3073. <name>SYSCFGEN</name>
  3074. <description>SYSCFG and VREFBUF clock enable</description>
  3075. <bitRange>[0:0]</bitRange>
  3076. </field>
  3077. <field>
  3078. <name>TIM1EN</name>
  3079. <description>TIM1 timer clock enable</description>
  3080. <bitRange>[11:11]</bitRange>
  3081. </field>
  3082. <field>
  3083. <name>USART1EN</name>
  3084. <description>USART1 clock enable</description>
  3085. <bitRange>[14:14]</bitRange>
  3086. </field>
  3087. <field>
  3088. <name>TIM14EN</name>
  3089. <description>TIM14 clock enable</description>
  3090. <bitRange>[15:15]</bitRange>
  3091. </field>
  3092. <field>
  3093. <name>ADCEN</name>
  3094. <description>ADC clock enable</description>
  3095. <bitRange>[20:20]</bitRange>
  3096. </field>
  3097. </fields>
  3098. </register>
  3099. <register>
  3100. <name>CCIPR</name>
  3101. <displayName>CCIPR</displayName>
  3102. <description>Peripherals independent clock configuration register</description>
  3103. <addressOffset>0x54</addressOffset>
  3104. <fields>
  3105. <field>
  3106. <name>LPTIM1SEL</name>
  3107. <description>LPTIM1 clock source selection</description>
  3108. <bitRange>[19:18]</bitRange>
  3109. </field>
  3110. </fields>
  3111. </register>
  3112. <register>
  3113. <name>BDCR</name>
  3114. <displayName>BDCR</displayName>
  3115. <description>RTC domain control register</description>
  3116. <addressOffset>0x5C</addressOffset>
  3117. <fields>
  3118. <field>
  3119. <name>LSEON</name>
  3120. <description>LSE oscillator enable</description>
  3121. <bitRange>[0:0]</bitRange>
  3122. </field>
  3123. <field>
  3124. <name>LSERDY</name>
  3125. <description>LSE oscillator ready</description>
  3126. <bitRange>[1:1]</bitRange>
  3127. </field>
  3128. <field>
  3129. <name>LSEBYP</name>
  3130. <description>LSE oscillator bypass</description>
  3131. <bitRange>[2:2]</bitRange>
  3132. </field>
  3133. <field>
  3134. <name>LSECSSON</name>
  3135. <description>LSE CSS enable</description>
  3136. <bitRange>[5:5]</bitRange>
  3137. </field>
  3138. <field>
  3139. <name>LSECSSD</name>
  3140. <description>LSE CSS detect</description>
  3141. <bitRange>[6:6]</bitRange>
  3142. </field>
  3143. <field>
  3144. <name>LSCOEN</name>
  3145. <description>Low-speed clock output (LSCO) enable</description>
  3146. <bitRange>[24:24]</bitRange>
  3147. </field>
  3148. <field>
  3149. <name>LSCOSEL</name>
  3150. <description>Low-speed clock output selection</description>
  3151. <bitRange>[25:25]</bitRange>
  3152. </field>
  3153. </fields>
  3154. </register>
  3155. <register>
  3156. <name>CSR</name>
  3157. <displayName>CSR</displayName>
  3158. <description>Control/status register</description>
  3159. <addressOffset>0x60</addressOffset>
  3160. <fields>
  3161. <field>
  3162. <name>LSION</name>
  3163. <description>LSI oscillator enable</description>
  3164. <bitRange>[0:0]</bitRange>
  3165. </field>
  3166. <field>
  3167. <name>LSIRDY</name>
  3168. <description>LSI oscillator ready</description>
  3169. <bitRange>[1:1]</bitRange>
  3170. </field>
  3171. <field>
  3172. <name>PINRST_FLTDIS</name>
  3173. <description>desc PINRST_FLTDIS</description>
  3174. <bitRange>[8:8]</bitRange>
  3175. </field>
  3176. <field>
  3177. <name>RMVF</name>
  3178. <description>Remove reset flags</description>
  3179. <bitRange>[23:23]</bitRange>
  3180. </field>
  3181. <field>
  3182. <name>OBLRSTF</name>
  3183. <description>Option byte loader reset flag</description>
  3184. <bitRange>[25:25]</bitRange>
  3185. </field>
  3186. <field>
  3187. <name>PINRSTF</name>
  3188. <description>Pin reset flag</description>
  3189. <bitRange>[26:26]</bitRange>
  3190. </field>
  3191. <field>
  3192. <name>PWRRSTF</name>
  3193. <description>BOR or POR/PDR flag</description>
  3194. <bitRange>[27:27]</bitRange>
  3195. </field>
  3196. <field>
  3197. <name>SFTRSTF</name>
  3198. <description>Software reset flag</description>
  3199. <bitRange>[28:28]</bitRange>
  3200. </field>
  3201. <field>
  3202. <name>IWDGRSTF</name>
  3203. <description>Independent window watchdog reset flag</description>
  3204. <bitRange>[29:29]</bitRange>
  3205. </field>
  3206. </fields>
  3207. </register>
  3208. </registers>
  3209. </peripheral>
  3210. <peripheral>
  3211. <name>SYSCFG</name>
  3212. <description>System configuration controller</description>
  3213. <groupName>SYSCFG</groupName>
  3214. <baseAddress>0x40010000</baseAddress>
  3215. <addressBlock>
  3216. <offset>0x0</offset>
  3217. <size>0x30</size>
  3218. <usage>registers</usage>
  3219. </addressBlock>
  3220. <registers>
  3221. <register>
  3222. <name>CFGR1</name>
  3223. <displayName>CFGR1</displayName>
  3224. <description>SYSCFG configuration register 1</description>
  3225. <addressOffset>0x0</addressOffset>
  3226. <fields>
  3227. <field>
  3228. <name>MEM_MODE</name>
  3229. <description>Memory mapping selection bits</description>
  3230. <bitRange>[1:0]</bitRange>
  3231. </field>
  3232. <field>
  3233. <name>I2C_PA2_FMP</name>
  3234. <description>desc I2C_PA2_FMP</description>
  3235. <bitRange>[16:16]</bitRange>
  3236. </field>
  3237. <field>
  3238. <name>I2C_PB3_FMP</name>
  3239. <description>desc I2C_PB3_FMP</description>
  3240. <bitRange>[17:17]</bitRange>
  3241. </field>
  3242. <field>
  3243. <name>I2C_PB4_FMP</name>
  3244. <description>desc I2C_PB4_FMP</description>
  3245. <bitRange>[18:18]</bitRange>
  3246. </field>
  3247. <field>
  3248. <name>I2C_PB6_FMP</name>
  3249. <description>desc I2C_PB6_FMP</description>
  3250. <bitRange>[19:19]</bitRange>
  3251. </field>
  3252. </fields>
  3253. </register>
  3254. <register>
  3255. <name>CFGR2</name>
  3256. <displayName>CFGR2</displayName>
  3257. <description>SYSCFG configuration register 2</description>
  3258. <addressOffset>0x18</addressOffset>
  3259. <fields>
  3260. <field>
  3261. <name>LOCKUP_LOCK</name>
  3262. <description>Cortex-M0+ LOCKUP bit enable bit</description>
  3263. <bitRange>[0:0]</bitRange>
  3264. </field>
  3265. <field>
  3266. <name>ETR_SRC_TIM1</name>
  3267. <description>TIM1 ETR source selection</description>
  3268. <bitRange>[10:9]</bitRange>
  3269. </field>
  3270. </fields>
  3271. </register>
  3272. <register>
  3273. <name>GPIO_ENS</name>
  3274. <description>desc GPIO_ENS</description>
  3275. <addressOffset>0x1C</addressOffset>
  3276. <fields>
  3277. <field>
  3278. <name>PA_ENS</name>
  3279. <description>desc PA_ENS</description>
  3280. <bitRange>[7:0]</bitRange>
  3281. </field>
  3282. <field>
  3283. <name>PB_ENS</name>
  3284. <description>desc PB_ENS</description>
  3285. <bitRange>[15:8]</bitRange>
  3286. </field>
  3287. <field>
  3288. <name>PC_ENS</name>
  3289. <description>desc PC_ENS</description>
  3290. <bitRange>[17:16]</bitRange>
  3291. </field>
  3292. </fields>
  3293. </register>
  3294. </registers>
  3295. </peripheral>
  3296. <peripheral>
  3297. <name>TIM1</name>
  3298. <description>Advanced timer</description>
  3299. <groupName>TIM</groupName>
  3300. <baseAddress>0x40012C00</baseAddress>
  3301. <addressBlock>
  3302. <offset>0x0</offset>
  3303. <size>0x400</size>
  3304. <usage>registers</usage>
  3305. </addressBlock>
  3306. <interrupt>
  3307. <name>TIM1_BRK_UP_TRG_COM</name>
  3308. <description>TIM1 Break, Update, Trigger and Commutation Interrupt</description>
  3309. <value>13</value>
  3310. </interrupt>
  3311. <interrupt>
  3312. <name>TIM1_CC</name>
  3313. <description>TIM1 Capture Compare Interrupt</description>
  3314. <value>14</value>
  3315. </interrupt>
  3316. <registers>
  3317. <register>
  3318. <name>CR1</name>
  3319. <description>desc CR1</description>
  3320. <addressOffset>0x0</addressOffset>
  3321. <resetMask>0x3FF</resetMask>
  3322. <fields>
  3323. <field>
  3324. <name>CEN</name>
  3325. <description>desc CEN</description>
  3326. <bitRange>[0:0]</bitRange>
  3327. </field>
  3328. <field>
  3329. <name>UDIS</name>
  3330. <description>desc UDIS</description>
  3331. <bitRange>[1:1]</bitRange>
  3332. </field>
  3333. <field>
  3334. <name>URS</name>
  3335. <description>desc URS</description>
  3336. <bitRange>[2:2]</bitRange>
  3337. </field>
  3338. <field>
  3339. <name>OPM</name>
  3340. <description>desc OPM</description>
  3341. <bitRange>[3:3]</bitRange>
  3342. </field>
  3343. <field>
  3344. <name>DIR</name>
  3345. <description>desc DIR</description>
  3346. <bitRange>[4:4]</bitRange>
  3347. </field>
  3348. <field>
  3349. <name>CMS</name>
  3350. <description>desc CMS</description>
  3351. <bitRange>[6:5]</bitRange>
  3352. </field>
  3353. <field>
  3354. <name>ARPE</name>
  3355. <description>desc ARPE</description>
  3356. <bitRange>[7:7]</bitRange>
  3357. </field>
  3358. <field>
  3359. <name>CKD</name>
  3360. <description>desc CKD</description>
  3361. <bitRange>[9:8]</bitRange>
  3362. </field>
  3363. </fields>
  3364. </register>
  3365. <register>
  3366. <name>CR2</name>
  3367. <description>desc CR2</description>
  3368. <addressOffset>0x4</addressOffset>
  3369. <resetMask>0xF8</resetMask>
  3370. <fields>
  3371. <field>
  3372. <name>CCPC</name>
  3373. <description>desc CCPC</description>
  3374. <bitRange>[0:0]</bitRange>
  3375. </field>
  3376. <field>
  3377. <name>CCUS</name>
  3378. <description>desc CCUS</description>
  3379. <bitRange>[2:2]</bitRange>
  3380. </field>
  3381. <field>
  3382. <name>MMS</name>
  3383. <description>desc MMS</description>
  3384. <bitRange>[6:4]</bitRange>
  3385. </field>
  3386. <field>
  3387. <name>TI1S</name>
  3388. <description>desc TI1S</description>
  3389. <bitRange>[7:7]</bitRange>
  3390. </field>
  3391. <field>
  3392. <name>OIS1</name>
  3393. <description>desc OIS1</description>
  3394. <bitRange>[8:8]</bitRange>
  3395. </field>
  3396. <field>
  3397. <name>OIS1N</name>
  3398. <description>desc OIS1N</description>
  3399. <bitRange>[9:9]</bitRange>
  3400. </field>
  3401. <field>
  3402. <name>OIS2</name>
  3403. <description>desc OIS2</description>
  3404. <bitRange>[10:10]</bitRange>
  3405. </field>
  3406. <field>
  3407. <name>OIS2N</name>
  3408. <description>desc OIS2N</description>
  3409. <bitRange>[11:11]</bitRange>
  3410. </field>
  3411. <field>
  3412. <name>OIS3</name>
  3413. <description>desc OIS3</description>
  3414. <bitRange>[12:12]</bitRange>
  3415. </field>
  3416. <field>
  3417. <name>OIS3N</name>
  3418. <description>desc OIS3N</description>
  3419. <bitRange>[13:13]</bitRange>
  3420. </field>
  3421. <field>
  3422. <name>OIS4</name>
  3423. <description>desc OIS4</description>
  3424. <bitRange>[14:14]</bitRange>
  3425. </field>
  3426. </fields>
  3427. </register>
  3428. <register>
  3429. <name>SMCR</name>
  3430. <description>desc SMCR</description>
  3431. <addressOffset>0x8</addressOffset>
  3432. <resetMask>0xFFF7</resetMask>
  3433. <fields>
  3434. <field>
  3435. <name>SMS</name>
  3436. <description>desc SMS</description>
  3437. <bitRange>[2:0]</bitRange>
  3438. </field>
  3439. <field>
  3440. <name>OCCS</name>
  3441. <description>desc OCCS</description>
  3442. <bitRange>[3:3]</bitRange>
  3443. </field>
  3444. <field>
  3445. <name>TS</name>
  3446. <description>desc TS</description>
  3447. <bitRange>[6:4]</bitRange>
  3448. </field>
  3449. <field>
  3450. <name>MSM</name>
  3451. <description>desc MSM</description>
  3452. <bitRange>[7:7]</bitRange>
  3453. </field>
  3454. <field>
  3455. <name>ETF</name>
  3456. <description>desc ETF</description>
  3457. <bitRange>[11:8]</bitRange>
  3458. </field>
  3459. <field>
  3460. <name>ETPS</name>
  3461. <description>desc ETPS</description>
  3462. <bitRange>[13:12]</bitRange>
  3463. </field>
  3464. <field>
  3465. <name>ECE</name>
  3466. <description>desc ECE</description>
  3467. <bitRange>[14:14]</bitRange>
  3468. </field>
  3469. <field>
  3470. <name>ETP</name>
  3471. <description>desc ETP</description>
  3472. <bitRange>[15:15]</bitRange>
  3473. </field>
  3474. </fields>
  3475. </register>
  3476. <register>
  3477. <name>DIER</name>
  3478. <description>desc DIER</description>
  3479. <addressOffset>0xC</addressOffset>
  3480. <resetMask>0x5F5F</resetMask>
  3481. <fields>
  3482. <field>
  3483. <name>UIE</name>
  3484. <description>desc UIE</description>
  3485. <bitRange>[0:0]</bitRange>
  3486. </field>
  3487. <field>
  3488. <name>CC1IE</name>
  3489. <description>desc CC1IE</description>
  3490. <bitRange>[1:1]</bitRange>
  3491. </field>
  3492. <field>
  3493. <name>CC2IE</name>
  3494. <description>desc CC2IE</description>
  3495. <bitRange>[2:2]</bitRange>
  3496. </field>
  3497. <field>
  3498. <name>CC3IE</name>
  3499. <description>desc CC3IE</description>
  3500. <bitRange>[3:3]</bitRange>
  3501. </field>
  3502. <field>
  3503. <name>CC4IE</name>
  3504. <description>desc CC4IE</description>
  3505. <bitRange>[4:4]</bitRange>
  3506. </field>
  3507. <field>
  3508. <name>COMIE</name>
  3509. <description>desc COMIE</description>
  3510. <bitRange>[5:5]</bitRange>
  3511. </field>
  3512. <field>
  3513. <name>TIE</name>
  3514. <description>desc TIE</description>
  3515. <bitRange>[6:6]</bitRange>
  3516. </field>
  3517. <field>
  3518. <name>BIE</name>
  3519. <description>desc BIE</description>
  3520. <bitRange>[7:7]</bitRange>
  3521. </field>
  3522. </fields>
  3523. </register>
  3524. <register>
  3525. <name>SR</name>
  3526. <description>desc SR</description>
  3527. <addressOffset>0x10</addressOffset>
  3528. <resetMask>0x1E5F</resetMask>
  3529. <fields>
  3530. <field>
  3531. <name>UIF</name>
  3532. <description>desc UIF</description>
  3533. <bitRange>[0:0]</bitRange>
  3534. </field>
  3535. <field>
  3536. <name>CC1IF</name>
  3537. <description>desc CC1IF</description>
  3538. <bitRange>[1:1]</bitRange>
  3539. </field>
  3540. <field>
  3541. <name>CC2IF</name>
  3542. <description>desc CC2IF</description>
  3543. <bitRange>[2:2]</bitRange>
  3544. </field>
  3545. <field>
  3546. <name>CC3IF</name>
  3547. <description>desc CC3IF</description>
  3548. <bitRange>[3:3]</bitRange>
  3549. </field>
  3550. <field>
  3551. <name>CC4IF</name>
  3552. <description>desc CC4IF</description>
  3553. <bitRange>[4:4]</bitRange>
  3554. </field>
  3555. <field>
  3556. <name>COMIF</name>
  3557. <description>desc COMIF</description>
  3558. <bitRange>[5:5]</bitRange>
  3559. </field>
  3560. <field>
  3561. <name>TIF</name>
  3562. <description>desc TIF</description>
  3563. <bitRange>[6:6]</bitRange>
  3564. </field>
  3565. <field>
  3566. <name>BIF</name>
  3567. <description>desc BIF</description>
  3568. <bitRange>[7:7]</bitRange>
  3569. </field>
  3570. <field>
  3571. <name>CC1OF</name>
  3572. <description>desc CC1OF</description>
  3573. <bitRange>[9:9]</bitRange>
  3574. </field>
  3575. <field>
  3576. <name>CC2OF</name>
  3577. <description>desc CC2OF</description>
  3578. <bitRange>[10:10]</bitRange>
  3579. </field>
  3580. <field>
  3581. <name>CC3OF</name>
  3582. <description>desc CC3OF</description>
  3583. <bitRange>[11:11]</bitRange>
  3584. </field>
  3585. <field>
  3586. <name>CC4OF</name>
  3587. <description>desc CC4OF</description>
  3588. <bitRange>[12:12]</bitRange>
  3589. </field>
  3590. <field>
  3591. <name>IC1IR</name>
  3592. <description>desc IC1IR</description>
  3593. <bitRange>[16:16]</bitRange>
  3594. </field>
  3595. <field>
  3596. <name>IC2IR</name>
  3597. <description>desc IC2IR</description>
  3598. <bitRange>[17:17]</bitRange>
  3599. </field>
  3600. <field>
  3601. <name>IC3IR</name>
  3602. <description>desc IC3IR</description>
  3603. <bitRange>[18:18]</bitRange>
  3604. </field>
  3605. <field>
  3606. <name>IC4IR</name>
  3607. <description>desc IC3IR</description>
  3608. <bitRange>[19:19]</bitRange>
  3609. </field>
  3610. <field>
  3611. <name>IC1IF</name>
  3612. <description>desc IC1IF</description>
  3613. <bitRange>[20:20]</bitRange>
  3614. </field>
  3615. <field>
  3616. <name>IC2IF</name>
  3617. <description>desc IC2IF</description>
  3618. <bitRange>[21:21]</bitRange>
  3619. </field>
  3620. <field>
  3621. <name>IC3IF</name>
  3622. <description>desc IC3IF</description>
  3623. <bitRange>[22:22]</bitRange>
  3624. </field>
  3625. <field>
  3626. <name>IC4IF</name>
  3627. <description>desc IC3IF</description>
  3628. <bitRange>[23:23]</bitRange>
  3629. </field>
  3630. </fields>
  3631. </register>
  3632. <register>
  3633. <name>EGR</name>
  3634. <description>desc EGR</description>
  3635. <addressOffset>0x14</addressOffset>
  3636. <access>write-only</access>
  3637. <resetMask>0x5F</resetMask>
  3638. <fields>
  3639. <field>
  3640. <name>UG</name>
  3641. <description>desc UG</description>
  3642. <bitRange>[0:0]</bitRange>
  3643. <access>write-only</access>
  3644. </field>
  3645. <field>
  3646. <name>CC1G</name>
  3647. <description>Capture/Compare 1 Generation</description>
  3648. <bitRange>[1:1]</bitRange>
  3649. <access>write-only</access>
  3650. </field>
  3651. <field>
  3652. <name>CC2G</name>
  3653. <description>desc CC2G</description>
  3654. <bitRange>[2:2]</bitRange>
  3655. <access>write-only</access>
  3656. </field>
  3657. <field>
  3658. <name>CC3G</name>
  3659. <description>desc CC3G</description>
  3660. <bitRange>[3:3]</bitRange>
  3661. <access>write-only</access>
  3662. </field>
  3663. <field>
  3664. <name>CC4G</name>
  3665. <description>desc CC4G</description>
  3666. <bitRange>[4:4]</bitRange>
  3667. <access>write-only</access>
  3668. </field>
  3669. <field>
  3670. <name>COMG</name>
  3671. <description>desc COMG</description>
  3672. <bitRange>[5:5]</bitRange>
  3673. <access>write-only</access>
  3674. </field>
  3675. <field>
  3676. <name>TG</name>
  3677. <description>desc TG</description>
  3678. <bitRange>[6:6]</bitRange>
  3679. <access>write-only</access>
  3680. </field>
  3681. <field>
  3682. <name>BG</name>
  3683. <description>desc BG</description>
  3684. <bitRange>[7:7]</bitRange>
  3685. <access>write-only</access>
  3686. </field>
  3687. </fields>
  3688. </register>
  3689. <register>
  3690. <name>CCMR1_OUTPUT</name>
  3691. <description>desc CCMR1:OUTPUT</description>
  3692. <addressOffset>0x18</addressOffset>
  3693. <resetMask>0xFFFF</resetMask>
  3694. <fields>
  3695. <field>
  3696. <name>CC1S</name>
  3697. <description>desc CC1S</description>
  3698. <bitRange>[1:0]</bitRange>
  3699. </field>
  3700. <field>
  3701. <name>OC1FE</name>
  3702. <description>desc OC1FE</description>
  3703. <bitRange>[2:2]</bitRange>
  3704. </field>
  3705. <field>
  3706. <name>OC1PE</name>
  3707. <description>desc OC1PE</description>
  3708. <bitRange>[3:3]</bitRange>
  3709. </field>
  3710. <field>
  3711. <name>OC1M</name>
  3712. <description>desc OC1M</description>
  3713. <bitRange>[6:4]</bitRange>
  3714. </field>
  3715. <field>
  3716. <name>OC1CE</name>
  3717. <description>desc OC1CE</description>
  3718. <bitRange>[7:7]</bitRange>
  3719. </field>
  3720. <field>
  3721. <name>CC2S</name>
  3722. <description>desc CC2S</description>
  3723. <bitRange>[9:8]</bitRange>
  3724. </field>
  3725. <field>
  3726. <name>OC2FE</name>
  3727. <description>desc OC2FE</description>
  3728. <bitRange>[10:10]</bitRange>
  3729. </field>
  3730. <field>
  3731. <name>OC2PE</name>
  3732. <description>desc OC2PE</description>
  3733. <bitRange>[11:11]</bitRange>
  3734. </field>
  3735. <field>
  3736. <name>OC2M</name>
  3737. <description>desc OC2M</description>
  3738. <bitRange>[14:12]</bitRange>
  3739. </field>
  3740. <field>
  3741. <name>OC2CE</name>
  3742. <description>desc OC2CE</description>
  3743. <bitRange>[15:15]</bitRange>
  3744. </field>
  3745. </fields>
  3746. </register>
  3747. <register>
  3748. <name>CCMR1_INPUT</name>
  3749. <description>desc CCMR1:INPUT</description>
  3750. <alternateRegister>CCMR1_OUTPUT</alternateRegister>
  3751. <addressOffset>0x18</addressOffset>
  3752. <resetMask>0xFFFF</resetMask>
  3753. <fields>
  3754. <field>
  3755. <name>CC1S</name>
  3756. <description>desc CC1S</description>
  3757. <bitRange>[1:0]</bitRange>
  3758. </field>
  3759. <field>
  3760. <name>IC1PSC</name>
  3761. <description>desc IC1PSC</description>
  3762. <bitRange>[3:2]</bitRange>
  3763. </field>
  3764. <field>
  3765. <name>IC1F</name>
  3766. <description>desc IC1F</description>
  3767. <bitRange>[7:4]</bitRange>
  3768. </field>
  3769. <field>
  3770. <name>CC2S</name>
  3771. <description>desc CC2S</description>
  3772. <bitRange>[9:8]</bitRange>
  3773. </field>
  3774. <field>
  3775. <name>IC2PSC</name>
  3776. <description>desc IC2PSC</description>
  3777. <bitRange>[11:10]</bitRange>
  3778. </field>
  3779. <field>
  3780. <name>IC2F</name>
  3781. <description>desc IC2F</description>
  3782. <bitRange>[15:12]</bitRange>
  3783. </field>
  3784. </fields>
  3785. </register>
  3786. <register>
  3787. <name>CCMR2_OUTPUT</name>
  3788. <description>desc CCMR2:OUTPUT</description>
  3789. <addressOffset>0x1C</addressOffset>
  3790. <resetMask>0xFFFF</resetMask>
  3791. <fields>
  3792. <field>
  3793. <name>CC3S</name>
  3794. <description>desc CC3S</description>
  3795. <bitRange>[1:0]</bitRange>
  3796. </field>
  3797. <field>
  3798. <name>OC3FE</name>
  3799. <description>desc OC3FE</description>
  3800. <bitRange>[2:2]</bitRange>
  3801. </field>
  3802. <field>
  3803. <name>OC3PE</name>
  3804. <description>desc OC3PE</description>
  3805. <bitRange>[3:3]</bitRange>
  3806. </field>
  3807. <field>
  3808. <name>OC3M</name>
  3809. <description>desc OC3M</description>
  3810. <bitRange>[6:4]</bitRange>
  3811. </field>
  3812. <field>
  3813. <name>OC3CE</name>
  3814. <description>desc OC3CE</description>
  3815. <bitRange>[7:7]</bitRange>
  3816. </field>
  3817. <field>
  3818. <name>CC4S</name>
  3819. <description>desc CC4S</description>
  3820. <bitRange>[9:8]</bitRange>
  3821. </field>
  3822. <field>
  3823. <name>OC4FE</name>
  3824. <description>desc OC4FE</description>
  3825. <bitRange>[10:10]</bitRange>
  3826. </field>
  3827. <field>
  3828. <name>OC4PE</name>
  3829. <description>desc OC4PE</description>
  3830. <bitRange>[11:11]</bitRange>
  3831. </field>
  3832. <field>
  3833. <name>OC4M</name>
  3834. <description>desc OC4M</description>
  3835. <bitRange>[14:12]</bitRange>
  3836. </field>
  3837. <field>
  3838. <name>OC4CE</name>
  3839. <description>desc OC4CE</description>
  3840. <bitRange>[15:15]</bitRange>
  3841. </field>
  3842. </fields>
  3843. </register>
  3844. <register>
  3845. <name>CCMR2_INPUT</name>
  3846. <description>desc CCMR2:INPUT</description>
  3847. <alternateRegister>CCMR2_OUTPUT</alternateRegister>
  3848. <addressOffset>0x1C</addressOffset>
  3849. <resetMask>0xFFFF</resetMask>
  3850. <fields>
  3851. <field>
  3852. <name>CC3S</name>
  3853. <description>desc CC3S</description>
  3854. <bitRange>[1:0]</bitRange>
  3855. </field>
  3856. <field>
  3857. <name>IC3PSC</name>
  3858. <description>desc IC3PSC</description>
  3859. <bitRange>[3:2]</bitRange>
  3860. </field>
  3861. <field>
  3862. <name>IC3F</name>
  3863. <description>desc IC3F</description>
  3864. <bitRange>[7:4]</bitRange>
  3865. </field>
  3866. <field>
  3867. <name>CC4S</name>
  3868. <description>desc CC4S</description>
  3869. <bitRange>[9:8]</bitRange>
  3870. </field>
  3871. <field>
  3872. <name>IC4PSC</name>
  3873. <description>desc IC4PSC</description>
  3874. <bitRange>[11:10]</bitRange>
  3875. </field>
  3876. <field>
  3877. <name>IC4F</name>
  3878. <description>desc IC4F</description>
  3879. <bitRange>[15:12]</bitRange>
  3880. </field>
  3881. </fields>
  3882. </register>
  3883. <register>
  3884. <name>CCER</name>
  3885. <description>desc CCER</description>
  3886. <addressOffset>0x20</addressOffset>
  3887. <resetMask>0x3333</resetMask>
  3888. <fields>
  3889. <field>
  3890. <name>CC1E</name>
  3891. <description>desc CC1E</description>
  3892. <bitRange>[0:0]</bitRange>
  3893. </field>
  3894. <field>
  3895. <name>CC1P</name>
  3896. <description>desc CC1P</description>
  3897. <bitRange>[1:1]</bitRange>
  3898. </field>
  3899. <field>
  3900. <name>CC1NE</name>
  3901. <description>desc CC1NE</description>
  3902. <bitRange>[2:2]</bitRange>
  3903. </field>
  3904. <field>
  3905. <name>CC1NP</name>
  3906. <description>desc CC1NP</description>
  3907. <bitRange>[3:3]</bitRange>
  3908. </field>
  3909. <field>
  3910. <name>CC2E</name>
  3911. <description>desc CC2E</description>
  3912. <bitRange>[4:4]</bitRange>
  3913. </field>
  3914. <field>
  3915. <name>CC2P</name>
  3916. <description>desc CC2P</description>
  3917. <bitRange>[5:5]</bitRange>
  3918. </field>
  3919. <field>
  3920. <name>CC2NE</name>
  3921. <description>desc CC2NE</description>
  3922. <bitRange>[6:6]</bitRange>
  3923. </field>
  3924. <field>
  3925. <name>CC2NP</name>
  3926. <description>desc CC2NP</description>
  3927. <bitRange>[7:7]</bitRange>
  3928. </field>
  3929. <field>
  3930. <name>CC3E</name>
  3931. <description>desc CC3E</description>
  3932. <bitRange>[8:8]</bitRange>
  3933. </field>
  3934. <field>
  3935. <name>CC3P</name>
  3936. <description>desc CC3P</description>
  3937. <bitRange>[9:9]</bitRange>
  3938. </field>
  3939. <field>
  3940. <name>CC3NE</name>
  3941. <description>desc CC3NE</description>
  3942. <bitRange>[10:10]</bitRange>
  3943. </field>
  3944. <field>
  3945. <name>CC3NP</name>
  3946. <description>desc CC3NP</description>
  3947. <bitRange>[11:11]</bitRange>
  3948. </field>
  3949. <field>
  3950. <name>CC4E</name>
  3951. <description>desc CC4E</description>
  3952. <bitRange>[12:12]</bitRange>
  3953. </field>
  3954. <field>
  3955. <name>CC4P</name>
  3956. <description>desc CC4P</description>
  3957. <bitRange>[13:13]</bitRange>
  3958. </field>
  3959. </fields>
  3960. </register>
  3961. <register>
  3962. <name>CNT</name>
  3963. <description>desc CNT</description>
  3964. <addressOffset>0x24</addressOffset>
  3965. <resetMask>0xFFFF</resetMask>
  3966. <fields>
  3967. <field>
  3968. <name>CNT</name>
  3969. <description>desc CNT</description>
  3970. <bitRange>[15:0]</bitRange>
  3971. </field>
  3972. </fields>
  3973. </register>
  3974. <register>
  3975. <name>PSC</name>
  3976. <description>desc PSC</description>
  3977. <addressOffset>0x28</addressOffset>
  3978. <resetMask>0xFFFF</resetMask>
  3979. <fields>
  3980. <field>
  3981. <name>PSC</name>
  3982. <description>desc PSC</description>
  3983. <bitRange>[15:0]</bitRange>
  3984. </field>
  3985. </fields>
  3986. </register>
  3987. <register>
  3988. <name>ARR</name>
  3989. <description>desc ARR</description>
  3990. <addressOffset>0x2C</addressOffset>
  3991. <resetValue>0xFFFF</resetValue>
  3992. <resetMask>0xFFFF</resetMask>
  3993. <fields>
  3994. <field>
  3995. <name>ARR</name>
  3996. <description>desc ARR</description>
  3997. <bitRange>[15:0]</bitRange>
  3998. </field>
  3999. </fields>
  4000. </register>
  4001. <register>
  4002. <name>RCR</name>
  4003. <description>desc RCR</description>
  4004. <addressOffset>0x30</addressOffset>
  4005. <resetValue>0xFFFF</resetValue>
  4006. <resetMask>0xFFFF</resetMask>
  4007. <fields>
  4008. <field>
  4009. <name>REP</name>
  4010. <description>desc REP</description>
  4011. <bitRange>[7:0]</bitRange>
  4012. </field>
  4013. </fields>
  4014. </register>
  4015. <register>
  4016. <name>CCR1</name>
  4017. <description>desc CCR1</description>
  4018. <addressOffset>0x34</addressOffset>
  4019. <resetMask>0xFFFF</resetMask>
  4020. <fields>
  4021. <field>
  4022. <name>CCR1</name>
  4023. <description>desc CCR1</description>
  4024. <bitRange>[15:0]</bitRange>
  4025. </field>
  4026. </fields>
  4027. </register>
  4028. <register>
  4029. <name>CCR2</name>
  4030. <description>desc CCR2</description>
  4031. <addressOffset>0x38</addressOffset>
  4032. <resetMask>0xFFFF</resetMask>
  4033. <fields>
  4034. <field>
  4035. <name>CCR2</name>
  4036. <description>desc CCR2</description>
  4037. <bitRange>[15:0]</bitRange>
  4038. </field>
  4039. </fields>
  4040. </register>
  4041. <register>
  4042. <name>CCR3</name>
  4043. <description>desc CCR3</description>
  4044. <addressOffset>0x3C</addressOffset>
  4045. <resetMask>0xFFFF</resetMask>
  4046. <fields>
  4047. <field>
  4048. <name>CCR3</name>
  4049. <description>desc CCR3</description>
  4050. <bitRange>[15:0]</bitRange>
  4051. </field>
  4052. </fields>
  4053. </register>
  4054. <register>
  4055. <name>CCR4</name>
  4056. <description>desc CCR4</description>
  4057. <addressOffset>0x40</addressOffset>
  4058. <resetMask>0xFFFF</resetMask>
  4059. <fields>
  4060. <field>
  4061. <name>CCR4</name>
  4062. <description>desc CCR4</description>
  4063. <bitRange>[15:0]</bitRange>
  4064. </field>
  4065. </fields>
  4066. </register>
  4067. <register>
  4068. <name>BDTR</name>
  4069. <description>desc BDTR</description>
  4070. <addressOffset>0x44</addressOffset>
  4071. <resetMask>0xFFFF</resetMask>
  4072. <fields>
  4073. <field>
  4074. <name>DTG</name>
  4075. <description>desc DTG</description>
  4076. <bitRange>[7:0]</bitRange>
  4077. </field>
  4078. <field>
  4079. <name>LOCK</name>
  4080. <description>desc LOCK</description>
  4081. <bitRange>[9:8]</bitRange>
  4082. </field>
  4083. <field>
  4084. <name>OSSI</name>
  4085. <description>desc OSSI</description>
  4086. <bitRange>[10:10]</bitRange>
  4087. </field>
  4088. <field>
  4089. <name>OSSR</name>
  4090. <description>desc OSSR</description>
  4091. <bitRange>[11:11]</bitRange>
  4092. </field>
  4093. <field>
  4094. <name>BKE</name>
  4095. <description>desc BKE</description>
  4096. <bitRange>[12:12]</bitRange>
  4097. </field>
  4098. <field>
  4099. <name>BKP</name>
  4100. <description>desc BKP</description>
  4101. <bitRange>[13:13]</bitRange>
  4102. </field>
  4103. <field>
  4104. <name>AOE</name>
  4105. <description>desc AOE</description>
  4106. <bitRange>[14:14]</bitRange>
  4107. </field>
  4108. <field>
  4109. <name>MOE</name>
  4110. <description>desc MOE</description>
  4111. <bitRange>[15:15]</bitRange>
  4112. </field>
  4113. </fields>
  4114. </register>
  4115. </registers>
  4116. </peripheral>
  4117. <peripheral>
  4118. <name>TIM14</name>
  4119. <description>General purpose timer</description>
  4120. <groupName>TIM</groupName>
  4121. <baseAddress>0x40002000</baseAddress>
  4122. <addressBlock>
  4123. <offset>0x0</offset>
  4124. <size>0x400</size>
  4125. <usage>registers</usage>
  4126. </addressBlock>
  4127. <interrupt>
  4128. <name>TIM14</name>
  4129. <description>TIM14 global Interrupt</description>
  4130. <value>19</value>
  4131. </interrupt>
  4132. <registers>
  4133. <register>
  4134. <name>CR1</name>
  4135. <description>desc CR1</description>
  4136. <addressOffset>0x0</addressOffset>
  4137. <resetMask>0x3FF</resetMask>
  4138. <fields>
  4139. <field>
  4140. <name>CEN</name>
  4141. <description>desc CEN</description>
  4142. <bitRange>[0:0]</bitRange>
  4143. </field>
  4144. <field>
  4145. <name>UDIS</name>
  4146. <description>desc UDIS</description>
  4147. <bitRange>[1:1]</bitRange>
  4148. </field>
  4149. <field>
  4150. <name>URS</name>
  4151. <description>desc URS</description>
  4152. <bitRange>[2:2]</bitRange>
  4153. </field>
  4154. <field>
  4155. <name>OPM</name>
  4156. <description>desc OPM</description>
  4157. <bitRange>[3:3]</bitRange>
  4158. </field>
  4159. <field>
  4160. <name>ARPE</name>
  4161. <description>desc ARPE</description>
  4162. <bitRange>[7:7]</bitRange>
  4163. </field>
  4164. <field>
  4165. <name>CKD</name>
  4166. <description>desc CKD</description>
  4167. <bitRange>[9:8]</bitRange>
  4168. </field>
  4169. </fields>
  4170. </register>
  4171. <register>
  4172. <name>DIER</name>
  4173. <description>desc DIER</description>
  4174. <addressOffset>0xC</addressOffset>
  4175. <resetMask>0x5F5F</resetMask>
  4176. <fields>
  4177. <field>
  4178. <name>UIE</name>
  4179. <description>desc UIE</description>
  4180. <bitRange>[0:0]</bitRange>
  4181. </field>
  4182. <field>
  4183. <name>CC1IE</name>
  4184. <description>desc CC1IE</description>
  4185. <bitRange>[1:1]</bitRange>
  4186. </field>
  4187. </fields>
  4188. </register>
  4189. <register>
  4190. <name>SR</name>
  4191. <description>desc SR</description>
  4192. <addressOffset>0x10</addressOffset>
  4193. <resetMask>0x1E5F</resetMask>
  4194. <fields>
  4195. <field>
  4196. <name>UIF</name>
  4197. <description>desc UIF</description>
  4198. <bitRange>[0:0]</bitRange>
  4199. </field>
  4200. <field>
  4201. <name>CC1IF</name>
  4202. <description>desc CC1IF</description>
  4203. <bitRange>[1:1]</bitRange>
  4204. </field>
  4205. <field>
  4206. <name>CC1OF</name>
  4207. <description>desc CC1OF</description>
  4208. <bitRange>[9:9]</bitRange>
  4209. </field>
  4210. <field>
  4211. <name>IC1IR</name>
  4212. <description>desc IC1IR</description>
  4213. <bitRange>[16:16]</bitRange>
  4214. </field>
  4215. <field>
  4216. <name>IC1IF</name>
  4217. <description>desc IC1IF</description>
  4218. <bitRange>[20:20]</bitRange>
  4219. </field>
  4220. </fields>
  4221. </register>
  4222. <register>
  4223. <name>EGR</name>
  4224. <description>desc EGR</description>
  4225. <addressOffset>0x14</addressOffset>
  4226. <access>write-only</access>
  4227. <resetMask>0x5F</resetMask>
  4228. <fields>
  4229. <field>
  4230. <name>UG</name>
  4231. <description>desc UG</description>
  4232. <bitRange>[0:0]</bitRange>
  4233. <access>write-only</access>
  4234. </field>
  4235. <field>
  4236. <name>CC1G</name>
  4237. <description>Capture/Compare 1 Generation</description>
  4238. <bitRange>[1:1]</bitRange>
  4239. <access>write-only</access>
  4240. </field>
  4241. </fields>
  4242. </register>
  4243. <register>
  4244. <name>CCMR1_OUTPUT</name>
  4245. <description>desc CCMR1:OUTPUT</description>
  4246. <addressOffset>0x18</addressOffset>
  4247. <resetMask>0xFFFF</resetMask>
  4248. <fields>
  4249. <field>
  4250. <name>CC1S</name>
  4251. <description>desc CC1S</description>
  4252. <bitRange>[1:0]</bitRange>
  4253. </field>
  4254. <field>
  4255. <name>OC1PE</name>
  4256. <description>desc OC1PE</description>
  4257. <bitRange>[3:3]</bitRange>
  4258. </field>
  4259. <field>
  4260. <name>OC1M</name>
  4261. <description>desc OC1M</description>
  4262. <bitRange>[6:4]</bitRange>
  4263. </field>
  4264. </fields>
  4265. </register>
  4266. <register>
  4267. <name>CCMR1_INPUT</name>
  4268. <description>desc CCMR1:INPUT</description>
  4269. <alternateRegister>CCMR1_OUTPUT</alternateRegister>
  4270. <addressOffset>0x18</addressOffset>
  4271. <resetMask>0xFFFF</resetMask>
  4272. <fields>
  4273. <field>
  4274. <name>CC1S</name>
  4275. <description>desc CC1S</description>
  4276. <bitRange>[1:0]</bitRange>
  4277. </field>
  4278. <field>
  4279. <name>IC1PSC</name>
  4280. <description>desc IC1PSC</description>
  4281. <bitRange>[3:2]</bitRange>
  4282. </field>
  4283. <field>
  4284. <name>IC1F</name>
  4285. <description>desc IC1F</description>
  4286. <bitRange>[7:4]</bitRange>
  4287. </field>
  4288. </fields>
  4289. </register>
  4290. <register>
  4291. <name>CCER</name>
  4292. <description>desc CCER</description>
  4293. <addressOffset>0x20</addressOffset>
  4294. <resetMask>0x3333</resetMask>
  4295. <fields>
  4296. <field>
  4297. <name>CC1E</name>
  4298. <description>desc CC1E</description>
  4299. <bitRange>[0:0]</bitRange>
  4300. </field>
  4301. <field>
  4302. <name>CC1P</name>
  4303. <description>desc CC1P</description>
  4304. <bitRange>[1:1]</bitRange>
  4305. </field>
  4306. <field>
  4307. <name>CC1NP</name>
  4308. <description>desc CC1NP</description>
  4309. <bitRange>[3:3]</bitRange>
  4310. </field>
  4311. </fields>
  4312. </register>
  4313. <register>
  4314. <name>CNT</name>
  4315. <description>desc CNT</description>
  4316. <addressOffset>0x24</addressOffset>
  4317. <resetMask>0xFFFF</resetMask>
  4318. <fields>
  4319. <field>
  4320. <name>CNT</name>
  4321. <description>desc CNT</description>
  4322. <bitRange>[15:0]</bitRange>
  4323. </field>
  4324. </fields>
  4325. </register>
  4326. <register>
  4327. <name>PSC</name>
  4328. <description>desc PSC</description>
  4329. <addressOffset>0x28</addressOffset>
  4330. <resetMask>0xFFFF</resetMask>
  4331. <fields>
  4332. <field>
  4333. <name>PSC</name>
  4334. <description>desc PSC</description>
  4335. <bitRange>[15:0]</bitRange>
  4336. </field>
  4337. </fields>
  4338. </register>
  4339. <register>
  4340. <name>ARR</name>
  4341. <description>desc ARR</description>
  4342. <addressOffset>0x2C</addressOffset>
  4343. <resetValue>0xFFFF</resetValue>
  4344. <resetMask>0xFFFF</resetMask>
  4345. <fields>
  4346. <field>
  4347. <name>ARR</name>
  4348. <description>desc ARR</description>
  4349. <bitRange>[15:0]</bitRange>
  4350. </field>
  4351. </fields>
  4352. </register>
  4353. <register>
  4354. <name>CCR1</name>
  4355. <description>desc CCR1</description>
  4356. <addressOffset>0x34</addressOffset>
  4357. <resetMask>0xFFFF</resetMask>
  4358. <fields>
  4359. <field>
  4360. <name>CCR1</name>
  4361. <description>desc CCR1</description>
  4362. <bitRange>[15:0]</bitRange>
  4363. </field>
  4364. </fields>
  4365. </register>
  4366. <register>
  4367. <name>OR</name>
  4368. <description>desc OR</description>
  4369. <addressOffset>0x50</addressOffset>
  4370. <fields>
  4371. <field>
  4372. <name>TI1_RMP</name>
  4373. <description>desc TI1_RMP</description>
  4374. <bitRange>[1:0]</bitRange>
  4375. </field>
  4376. </fields>
  4377. </register>
  4378. </registers>
  4379. </peripheral>
  4380. <peripheral>
  4381. <name>USART1</name>
  4382. <description>Universal synchronous asynchronous receiver transmitter</description>
  4383. <groupName>USART</groupName>
  4384. <baseAddress>0x40013800</baseAddress>
  4385. <addressBlock>
  4386. <offset>0x0</offset>
  4387. <size>0x400</size>
  4388. <usage>registers</usage>
  4389. </addressBlock>
  4390. <interrupt>
  4391. <name>USART1</name>
  4392. <description>USART1 global Interrupt</description>
  4393. <value>27</value>
  4394. </interrupt>
  4395. <registers>
  4396. <register>
  4397. <name>SR</name>
  4398. <displayName>SR</displayName>
  4399. <description>Status register</description>
  4400. <addressOffset>0x0</addressOffset>
  4401. <resetValue>0xC0</resetValue>
  4402. <fields>
  4403. <field>
  4404. <name>PE</name>
  4405. <description>Parity error</description>
  4406. <bitRange>[0:0]</bitRange>
  4407. <access>read-only</access>
  4408. </field>
  4409. <field>
  4410. <name>FE</name>
  4411. <description>Framing error</description>
  4412. <bitRange>[1:1]</bitRange>
  4413. <access>read-only</access>
  4414. </field>
  4415. <field>
  4416. <name>NE</name>
  4417. <description>Noise error flag</description>
  4418. <bitRange>[2:2]</bitRange>
  4419. <access>read-only</access>
  4420. </field>
  4421. <field>
  4422. <name>ORE</name>
  4423. <description>Overrun error</description>
  4424. <bitRange>[3:3]</bitRange>
  4425. <access>read-only</access>
  4426. </field>
  4427. <field>
  4428. <name>IDLE</name>
  4429. <description>IDLE line detected</description>
  4430. <bitRange>[4:4]</bitRange>
  4431. <access>read-only</access>
  4432. </field>
  4433. <field>
  4434. <name>RXNE</name>
  4435. <description>Read data register not empty</description>
  4436. <bitRange>[5:5]</bitRange>
  4437. </field>
  4438. <field>
  4439. <name>TC</name>
  4440. <description>Transmission complete</description>
  4441. <bitRange>[6:6]</bitRange>
  4442. </field>
  4443. <field>
  4444. <name>TXE</name>
  4445. <description>Transmit data register empty</description>
  4446. <bitRange>[7:7]</bitRange>
  4447. <access>read-only</access>
  4448. </field>
  4449. <field>
  4450. <name>CTS</name>
  4451. <description>CTS flag</description>
  4452. <bitRange>[9:9]</bitRange>
  4453. </field>
  4454. <field>
  4455. <name>ABRF</name>
  4456. <description>Automate baudrate detection flag</description>
  4457. <bitRange>[10:10]</bitRange>
  4458. <access>read-only</access>
  4459. </field>
  4460. <field>
  4461. <name>ABRE</name>
  4462. <description>Automate baudrate detection error flag</description>
  4463. <bitRange>[11:11]</bitRange>
  4464. <access>read-only</access>
  4465. </field>
  4466. <field>
  4467. <name>ABRRQ</name>
  4468. <description>Automate baudrate detection requeset</description>
  4469. <bitRange>[12:12]</bitRange>
  4470. <access>write-only</access>
  4471. </field>
  4472. </fields>
  4473. </register>
  4474. <register>
  4475. <name>DR</name>
  4476. <displayName>DR</displayName>
  4477. <description>Data register</description>
  4478. <addressOffset>0x4</addressOffset>
  4479. <fields>
  4480. <field>
  4481. <name>DR</name>
  4482. <description>Data value</description>
  4483. <bitRange>[8:0]</bitRange>
  4484. </field>
  4485. </fields>
  4486. </register>
  4487. <register>
  4488. <name>BRR</name>
  4489. <displayName>BRR</displayName>
  4490. <description>Baud rate register</description>
  4491. <addressOffset>0x8</addressOffset>
  4492. <fields>
  4493. <field>
  4494. <name>DIV_Fraction</name>
  4495. <description>fraction of USARTDIV</description>
  4496. <bitRange>[3:0]</bitRange>
  4497. </field>
  4498. <field>
  4499. <name>DIV_Mantissa</name>
  4500. <description>mantissa of USARTDIV</description>
  4501. <bitRange>[15:4]</bitRange>
  4502. </field>
  4503. </fields>
  4504. </register>
  4505. <register>
  4506. <name>CR1</name>
  4507. <displayName>CR1</displayName>
  4508. <description>Control register 1</description>
  4509. <addressOffset>0xC</addressOffset>
  4510. <fields>
  4511. <field>
  4512. <name>RWU</name>
  4513. <description>Receiver wakeup</description>
  4514. <bitRange>[1:1]</bitRange>
  4515. </field>
  4516. <field>
  4517. <name>RE</name>
  4518. <description>Receiver enable</description>
  4519. <bitRange>[2:2]</bitRange>
  4520. </field>
  4521. <field>
  4522. <name>TE</name>
  4523. <description>Transmitter enable</description>
  4524. <bitRange>[3:3]</bitRange>
  4525. </field>
  4526. <field>
  4527. <name>IDLEIE</name>
  4528. <description>IDLE interrupt enable</description>
  4529. <bitRange>[4:4]</bitRange>
  4530. </field>
  4531. <field>
  4532. <name>RXNEIE</name>
  4533. <description>RXNE interrupt enable</description>
  4534. <bitRange>[5:5]</bitRange>
  4535. </field>
  4536. <field>
  4537. <name>TCIE</name>
  4538. <description>Transmission complete interrupt enable</description>
  4539. <bitRange>[6:6]</bitRange>
  4540. </field>
  4541. <field>
  4542. <name>TXEIE</name>
  4543. <description>TXE interrupt enable</description>
  4544. <bitRange>[7:7]</bitRange>
  4545. </field>
  4546. <field>
  4547. <name>PEIE</name>
  4548. <description>PE interrupt enable</description>
  4549. <bitRange>[8:8]</bitRange>
  4550. </field>
  4551. <field>
  4552. <name>PS</name>
  4553. <description>Parity selection</description>
  4554. <bitRange>[9:9]</bitRange>
  4555. </field>
  4556. <field>
  4557. <name>PCE</name>
  4558. <description>Parity control enable</description>
  4559. <bitRange>[10:10]</bitRange>
  4560. </field>
  4561. <field>
  4562. <name>WAKE</name>
  4563. <description>Wakeup method</description>
  4564. <bitRange>[11:11]</bitRange>
  4565. </field>
  4566. <field>
  4567. <name>M</name>
  4568. <description>Word length</description>
  4569. <bitRange>[12:12]</bitRange>
  4570. </field>
  4571. <field>
  4572. <name>UE</name>
  4573. <description>USART enable</description>
  4574. <bitRange>[13:13]</bitRange>
  4575. </field>
  4576. </fields>
  4577. </register>
  4578. <register>
  4579. <name>CR2</name>
  4580. <displayName>CR2</displayName>
  4581. <description>Control register 2</description>
  4582. <addressOffset>0x10</addressOffset>
  4583. <fields>
  4584. <field>
  4585. <name>ADD</name>
  4586. <description>Address of the USART node</description>
  4587. <bitRange>[3:0]</bitRange>
  4588. </field>
  4589. <field>
  4590. <name>LBCL</name>
  4591. <description>Last bit clock pulse</description>
  4592. <bitRange>[8:8]</bitRange>
  4593. </field>
  4594. <field>
  4595. <name>CPHA</name>
  4596. <description>Clock phase</description>
  4597. <bitRange>[9:9]</bitRange>
  4598. </field>
  4599. <field>
  4600. <name>CPOL</name>
  4601. <description>Clock polarity</description>
  4602. <bitRange>[10:10]</bitRange>
  4603. </field>
  4604. <field>
  4605. <name>CLKEN</name>
  4606. <description>Clock enable</description>
  4607. <bitRange>[11:11]</bitRange>
  4608. </field>
  4609. <field>
  4610. <name>STOP</name>
  4611. <description>STOP bits</description>
  4612. <bitRange>[13:12]</bitRange>
  4613. </field>
  4614. </fields>
  4615. </register>
  4616. <register>
  4617. <name>CR3</name>
  4618. <displayName>CR3</displayName>
  4619. <description>Control register 3</description>
  4620. <addressOffset>0x14</addressOffset>
  4621. <fields>
  4622. <field>
  4623. <name>EIE</name>
  4624. <description>Error interrupt enable</description>
  4625. <bitRange>[0:0]</bitRange>
  4626. </field>
  4627. <field>
  4628. <name>HDSEL</name>
  4629. <description>Half-duplex selection</description>
  4630. <bitRange>[3:3]</bitRange>
  4631. </field>
  4632. <field>
  4633. <name>RTSE</name>
  4634. <description>RTS enable</description>
  4635. <bitRange>[8:8]</bitRange>
  4636. </field>
  4637. <field>
  4638. <name>CTSE</name>
  4639. <description>CTS enable</description>
  4640. <bitRange>[9:9]</bitRange>
  4641. </field>
  4642. <field>
  4643. <name>CTSIE</name>
  4644. <description>CTS interrupt enable</description>
  4645. <bitRange>[10:10]</bitRange>
  4646. </field>
  4647. <field>
  4648. <name>OVER8</name>
  4649. <description>Oversampling mode</description>
  4650. <bitRange>[11:11]</bitRange>
  4651. </field>
  4652. <field>
  4653. <name>ABREN</name>
  4654. <description>Auto baudrate enable</description>
  4655. <bitRange>[12:12]</bitRange>
  4656. </field>
  4657. <field>
  4658. <name>ABRMOD</name>
  4659. <description>Auto baudrate mode</description>
  4660. <bitRange>[14:13]</bitRange>
  4661. </field>
  4662. </fields>
  4663. </register>
  4664. </registers>
  4665. </peripheral>
  4666. </peripherals>
  4667. </device>