py32f0xx_ll_wwdg.h 10 KB

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  1. /**
  2. ******************************************************************************
  3. * @file py32f0xx_ll_wwdg.h
  4. * @author MCU Application Team
  5. * @brief Header file of WWDG LL module.
  6. ******************************************************************************
  7. * @attention
  8. *
  9. * <h2><center>&copy; Copyright (c) 2023 Puya Semiconductor Co.
  10. * All rights reserved.</center></h2>
  11. *
  12. * This software component is licensed by Puya under BSD 3-Clause license,
  13. * the "License"; You may not use this file except in compliance with the
  14. * License. You may obtain a copy of the License at:
  15. * opensource.org/licenses/BSD-3-Clause
  16. *
  17. ******************************************************************************
  18. * @attention
  19. *
  20. * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  21. * All rights reserved.</center></h2>
  22. *
  23. * This software component is licensed by ST under BSD 3-Clause license,
  24. * the "License"; You may not use this file except in compliance with the
  25. * License. You may obtain a copy of the License at:
  26. * opensource.org/licenses/BSD-3-Clause
  27. *
  28. ******************************************************************************
  29. */
  30. /* Define to prevent recursive inclusion -------------------------------------*/
  31. #ifndef PY32F0XX_LL_WWDG_H
  32. #define PY32F0XX_LL_WWDG_H
  33. #ifdef __cplusplus
  34. extern "C" {
  35. #endif
  36. /* Includes ------------------------------------------------------------------*/
  37. #include "py32f0xx.h"
  38. /** @addtogroup PY32F0xx_LL_Driver
  39. * @{
  40. */
  41. #if defined (WWDG)
  42. /** @defgroup WWDG_LL WWDG
  43. * @{
  44. */
  45. /* Private types -------------------------------------------------------------*/
  46. /* Private variables ---------------------------------------------------------*/
  47. /* Private constants ---------------------------------------------------------*/
  48. /* Private macros ------------------------------------------------------------*/
  49. /* Exported types ------------------------------------------------------------*/
  50. /* Exported constants --------------------------------------------------------*/
  51. /** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants
  52. * @{
  53. */
  54. /** @defgroup WWDG_LL_EC_IT IT Defines
  55. * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions
  56. * @{
  57. */
  58. #define LL_WWDG_CFR_EWI WWDG_CFR_EWI
  59. /**
  60. * @}
  61. */
  62. /** @defgroup WWDG_LL_EC_PRESCALER PRESCALER
  63. * @{
  64. */
  65. #define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */
  66. #define LL_WWDG_PRESCALER_2 ( WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/2 */
  67. #define LL_WWDG_PRESCALER_4 (WWDG_CFR_WDGTB_1 ) /*!< WWDG counter clock = (PCLK1/4096)/4 */
  68. #define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */
  69. /**
  70. * @}
  71. */
  72. /**
  73. * @}
  74. */
  75. /* Exported macro ------------------------------------------------------------*/
  76. /** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros
  77. * @{
  78. */
  79. /** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros
  80. * @{
  81. */
  82. /**
  83. * @brief Write a value in WWDG register
  84. * @param __INSTANCE__ WWDG Instance
  85. * @param __REG__ Register to be written
  86. * @param __VALUE__ Value to be written in the register
  87. * @retval None
  88. */
  89. #define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
  90. /**
  91. * @brief Read a value in WWDG register
  92. * @param __INSTANCE__ WWDG Instance
  93. * @param __REG__ Register to be read
  94. * @retval Register value
  95. */
  96. #define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
  97. /**
  98. * @}
  99. */
  100. /**
  101. * @}
  102. */
  103. /* Exported functions --------------------------------------------------------*/
  104. /** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions
  105. * @{
  106. */
  107. /** @defgroup WWDG_LL_EF_Configuration Configuration
  108. * @{
  109. */
  110. /**
  111. * @brief Enable Window Watchdog. The watchdog is always disabled after a reset.
  112. * @note It is enabled by setting the WDGA bit in the WWDG_CR register,
  113. * then it cannot be disabled again except by a reset.
  114. * This bit is set by software and only cleared by hardware after a reset.
  115. * When WDGA = 1, the watchdog can generate a reset.
  116. * @rmtoll CR WDGA LL_WWDG_Enable
  117. * @param WWDGx WWDG Instance
  118. * @retval None
  119. */
  120. __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)
  121. {
  122. SET_BIT(WWDGx->CR, WWDG_CR_WDGA);
  123. }
  124. /**
  125. * @brief Checks if Window Watchdog is enabled
  126. * @rmtoll CR WDGA LL_WWDG_IsEnabled
  127. * @param WWDGx WWDG Instance
  128. * @retval State of bit (1 or 0).
  129. */
  130. __STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)
  131. {
  132. return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA));
  133. }
  134. /**
  135. * @brief Set the Watchdog counter value to provided value (7-bits T[6:0])
  136. * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset
  137. * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles
  138. * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)
  139. * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)
  140. * @rmtoll CR T LL_WWDG_SetCounter
  141. * @param WWDGx WWDG Instance
  142. * @param Counter 0..0x7F (7 bit counter value)
  143. * @retval None
  144. */
  145. __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)
  146. {
  147. MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);
  148. }
  149. /**
  150. * @brief Return current Watchdog Counter Value (7 bits counter value)
  151. * @rmtoll CR T LL_WWDG_GetCounter
  152. * @param WWDGx WWDG Instance
  153. * @retval 7 bit Watchdog Counter value
  154. */
  155. __STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)
  156. {
  157. return (READ_BIT(WWDGx->CR, WWDG_CR_T));
  158. }
  159. /**
  160. * @brief Set the time base of the prescaler (WDGTB).
  161. * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter
  162. * is decremented every (4096 x 2expWDGTB) PCLK cycles
  163. * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler
  164. * @param WWDGx WWDG Instance
  165. * @param Prescaler This parameter can be one of the following values:
  166. * @arg @ref LL_WWDG_PRESCALER_1
  167. * @arg @ref LL_WWDG_PRESCALER_2
  168. * @arg @ref LL_WWDG_PRESCALER_4
  169. * @arg @ref LL_WWDG_PRESCALER_8
  170. * @retval None
  171. */
  172. __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)
  173. {
  174. MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);
  175. }
  176. /**
  177. * @brief Return current Watchdog Prescaler Value
  178. * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler
  179. * @param WWDGx WWDG Instance
  180. * @retval Returned value can be one of the following values:
  181. * @arg @ref LL_WWDG_PRESCALER_1
  182. * @arg @ref LL_WWDG_PRESCALER_2
  183. * @arg @ref LL_WWDG_PRESCALER_4
  184. * @arg @ref LL_WWDG_PRESCALER_8
  185. */
  186. __STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)
  187. {
  188. return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));
  189. }
  190. /**
  191. * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).
  192. * @note This window value defines when write in the WWDG_CR register
  193. * to program Watchdog counter is allowed.
  194. * Watchdog counter value update must occur only when the counter value
  195. * is lower than the Watchdog window register value.
  196. * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value
  197. * (in the control register) is refreshed before the downcounter has reached
  198. * the watchdog window register value.
  199. * Physically is possible to set the Window lower then 0x40 but it is not recommended.
  200. * To generate an immediate reset, it is possible to set the Counter lower than 0x40.
  201. * @rmtoll CFR W LL_WWDG_SetWindow
  202. * @param WWDGx WWDG Instance
  203. * @param Window 0x00..0x7F (7 bit Window value)
  204. * @retval None
  205. */
  206. __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)
  207. {
  208. MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);
  209. }
  210. /**
  211. * @brief Return current Watchdog Window Value (7 bits value)
  212. * @rmtoll CFR W LL_WWDG_GetWindow
  213. * @param WWDGx WWDG Instance
  214. * @retval 7 bit Watchdog Window value
  215. */
  216. __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)
  217. {
  218. return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));
  219. }
  220. /**
  221. * @}
  222. */
  223. /** @defgroup WWDG_LL_EF_FLAG_Management FLAG Management
  224. * @{
  225. */
  226. /**
  227. * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.
  228. * @note This bit is set by hardware when the counter has reached the value 0x40.
  229. * It must be cleared by software by writing 0.
  230. * A write of 1 has no effect. This bit is also set if the interrupt is not enabled.
  231. * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP
  232. * @param WWDGx WWDG Instance
  233. * @retval State of bit (1 or 0).
  234. */
  235. __STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)
  236. {
  237. return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF));
  238. }
  239. /**
  240. * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF)
  241. * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP
  242. * @param WWDGx WWDG Instance
  243. * @retval None
  244. */
  245. __STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)
  246. {
  247. WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);
  248. }
  249. /**
  250. * @}
  251. */
  252. /** @defgroup WWDG_LL_EF_IT_Management IT Management
  253. * @{
  254. */
  255. /**
  256. * @brief Enable the Early Wakeup Interrupt.
  257. * @note When set, an interrupt occurs whenever the counter reaches value 0x40.
  258. * This interrupt is only cleared by hardware after a reset
  259. * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP
  260. * @param WWDGx WWDG Instance
  261. * @retval None
  262. */
  263. __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)
  264. {
  265. SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);
  266. }
  267. /**
  268. * @brief Check if Early Wakeup Interrupt is enabled
  269. * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP
  270. * @param WWDGx WWDG Instance
  271. * @retval State of bit (1 or 0).
  272. */
  273. __STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)
  274. {
  275. return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI));
  276. }
  277. /**
  278. * @}
  279. */
  280. /**
  281. * @}
  282. */
  283. /**
  284. * @}
  285. */
  286. #endif /* WWDG */
  287. /**
  288. * @}
  289. */
  290. #ifdef __cplusplus
  291. }
  292. #endif
  293. #endif /* PY32F0XX_LL_WWDG_H */
  294. /************************ (C) COPYRIGHT Puya *****END OF FILE****/