Puya Puya PY32F071Cxx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 SR desc SR 0x0 AWD desc AWD [0:0] EOC desc EOC [1:1] JEOC desc JEOC [2:2] JSTRT desc JSTRT [3:3] STRT desc STRT [4:4] OVER desc OVER [5:5] read-only CR1 desc CR1 0x4 AWDCH desc AWDCH [4:0] EOCIE desc EOCIE [5:5] AWDIE desc AWDIE [6:6] JEOCIE desc JEOCIE [7:7] SCAN desc SCAN [8:8] AWDSGL desc AWDSGL [9:9] JAUTO desc JAUTO [10:10] DISCEN desc DISCEN [11:11] JDISCEN desc JDISCEN [12:12] DISCNUM desc DISCNUM [15:13] JAWDEN desc JAWDEN [22:22] AWDEN desc AWDEN [23:23] RESSEL desc RESSEL [25:24] ADSTP desc ADSTP [27:27] OVETIE desc OVETIE [29:29] CR2 desc CR2 0x8 ADON desc ADON [0:0] CONT desc CONT [1:1] CAL desc CAL [2:2] RSTCAL desc RSTCAL [3:3] DMA desc DMA [8:8] ALIGN desc ALIGN [11:11] JEXTSEL desc JEXTSEL [14:12] JEXTTRIG desc JEXTTRIG [15:15] EXTSEL desc EXTSEL [19:17] EXTTRIG desc EXTTRIG [20:20] JSWSTART desc JSWSTART [21:21] SWSTART desc SWSTART [22:22] TSVREFE desc TSVREFE [23:23] VERFBUFFERE desc VERFBUFFERE [25:25] VERFBUFFERSEL desc VERFBUFFERSEL [27:26] SMPR1 desc SMPR1 0xC SMP20 desc SMP20 [2:0] SMP21 desc SMP21 [5:3] SMP22 desc SMP22 [8:6] SMP23 desc SMP23 [11:9] SMPR2 desc SMPR2 0x10 SMP10 desc SMP10 [2:0] SMP11 desc SMP11 [5:3] SMP12 desc SMP12 [8:6] SMP13 desc SMP13 [11:9] SMP14 desc SMP14 [14:12] SMP15 desc SMP15 [17:15] SMP16 desc SMP16 [20:18] SMP17 desc SMP17 [23:21] SMP18 desc SMP18 [26:24] SMP19 desc SMP19 [29:27] SMPR3 desc SMPR2 0x14 SMP0 desc SMP0 [2:0] SMP1 desc SMP1 [5:3] SMP2 desc SMP2 [8:6] SMP3 desc SMP3 [11:9] SMP4 desc SMP4 [14:12] SMP5 desc SMP5 [17:15] SMP6 desc SMP6 [20:18] SMP7 desc SMP7 [23:21] SMP8 desc SMP8 [26:24] SMP9 desc SMP9 [29:27] JOFR1 desc JOFR1 0x18 JOFFSET1 desc JOFFSET1 [11:0] JOFR2 desc JOFR2 0x1C JOFFSET2 desc JOFFSET2 [11:0] JOFR3 desc JOFR3 0x20 JOFFSET3 desc JOFFSET3 [11:0] JOFR4 desc JOFR4 0x24 JOFFSET4 desc JOFFSET4 [11:0] HTR desc HTR 0x28 HT desc HT [11:0] LTR desc LTR 0x2C LT desc LT [11:0] SQR1 desc SQR1 0x30 SQ13 desc SQ13 [4:0] SQ14 desc SQ14 [9:5] SQ15 desc SQ15 [14:10] SQ16 desc SQ16 [19:15] L desc L [23:20] SQR2 desc SQR2 0x34 SQ7 desc SQ7 [4:0] SQ8 desc SQ8 [9:5] SQ9 desc SQ9 [14:10] SQ10 desc SQ10 [19:15] SQ11 desc SQ11 [24:20] SQ12 desc SQ12 [29:25] SQR3 desc SQR3 0x38 SQ1 desc SQ1 [4:0] SQ2 desc SQ2 [9:5] SQ3 desc SQ3 [14:10] SQ4 desc SQ4 [19:15] SQ5 desc SQ5 [24:20] SQ6 desc SQ6 [29:25] JSQR desc JSQR 0x3C JSQ1 desc JSQ1 [4:0] JSQ2 desc JSQ2 [9:5] JSQ3 desc JSQ3 [14:10] JSQ4 desc JSQ4 [19:15] JL desc JL [23:20] JDR1 desc JDR1 0x40 read-only JDR1 desc JDR1 [15:0] read-only JDR2 desc JDR2 0x44 read-only JDR2 desc JDR2 [15:0] read-only JDR3 desc JDR3 0x48 read-only JDR3 desc JDR3 [15:0] read-only JDR4 desc JDR4 0x4C read-only JDR4 desc JDR4 [15:0] read-only DR desc DR 0x50 read-only DATA desc DATA [15:0] read-only CCSR desc CCSR 0x54 CALSEL desc CALSEL [11:11] CALSMP desc CALSMP [13:12] CALBYP desc CALBYP [14:14] CALSET desc CALSET [15:15] OFFSUC desc OFFSUC [29:29] CAPSUC desc CAPSUC [30:30] CALON desc CALON [31:31] read-only COMP1 Comparator 1 COMP 0x40010200 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] INMSEL Comparator signal selector for inverting input INM [5:2] INPSEL Comparator signal selector for non-inverting input [9:6] WINMODE Comparator non-inverting input selector for window mode [11:11] POLARITY Comparator polarity selector [15:15] HYST Comparator hysteresis enable selector [16:16] PWRMODE Comparator power mode selector [19:18] VCDIV VCDIV [25:20] COMP_VCSEL COMP_VCSEL [27:26] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN1 Filter enable bit [0:0] FLTCNT1 Comparator filter and counter [31:16] COMP2 Comparator2 COMP 0x40010210 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] HYST Comparator hysteresis enable selector [1:1] INMSEL Comparator signal selector for inverting input INM [5:2] INPSEL Comparator signal selector for non-inverting input [9:6] WINMODE Comparator non-inverting input selector for window mode [11:11] POLARITY Comparator polarity selector [15:15] PWRMODE Comparator power mode selector [19:18] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN2 Filter enable bit [0:0] FLTCNT2 Comparator filter and counter [31:16] COMP3 Comparator3 COMP 0x40010220 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] HYST Comparator hysteresis enable selector [1:1] INMSEL Comparator signal selector for inverting input INM [5:2] INPSEL Comparator signal selector for non-inverting input [9:6] POLARITY Comparator polarity selector [15:15] PWRMODE Comparator power mode selector [19:18] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN3 Filter enable bit [0:0] FLTCNT3 Comparator filter and counter [31:16] CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0xFFFFFFFF DR Data Register [31:0] IDR IDR Independent Data register 0x4 IDR Independent Data register [7:0] CR CR Control register 0x8 write-only RESET Reset bit [0:0] CTC desc CTC CTC 0x40006C00 0x0 0x400 registers RCC_CTC RCC and CTC global Interrupts 4 CTL0 desc CTL0 0x0 0x4000 CKOKIE desc CKOKIE [0:0] CKWARNIE desc CKWARNIE [1:1] ERRIE desc ERRIE [2:2] EREFIE desc EREFIE [3:3] CNTEN desc CNTEN [5:5] AUTOTRIM desc AUTOTRIM [6:6] SWREFPUL desc SWREFPUL [7:7] write-only TRIMVALUE desc TRIMVALUE [14:8] CTL1 desc CTL1 0x4 0x2022BB7F RLVALUE desc RLVALUE [15:0] CKLIM desc CKLIM [23:16] REFPSC desc REFPSC [26:24] REFSEL desc REFSEL [29:28] REFPOL desc REFPOL [31:31] SR desc SR 0x8 read-only CKOKIF desc CKOKIF [0:0] read-only CKWARNIF desc CKWARNIF [1:1] read-only ERRIF desc ERRIF [2:2] read-only EREFIF desc EREFIF [3:3] read-only CKERR desc CKERR [8:8] read-only REFMISS desc REFMISS [9:9] read-only TRIMERR desc TRIMERR [10:10] read-only REFDIR desc REFDIR [15:15] read-only REFCAP desc REFCAP [31:16] read-only INTC desc INTC 0xC write-only CKOKIC desc CKOKIC [0:0] write-only CKWARNIC desc CKWARNIC [1:1] write-only ERRIC desc ERRIC [2:2] write-only EREFIC desc EREFIC [3:3] write-only DAC desc DAC DAC 0x40007400 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR desc CR 0x0 EN1 desc EN1 [0:0] BOFF1 desc BOFF1 [1:1] TEN1 desc TEN1 [2:2] TSEL1 desc TSEL1 [5:3] WAVE1 desc WAVE1 [7:6] MAMP1 desc MAMP1 [11:8] DMAEN1 desc DMAEN1 [12:12] DMAUDRIE1 desc DMAUDRIE1 [13:13] EN2 desc EN2 [16:16] BOFF2 desc BOFF2 [17:17] TEN2 desc TEN2 [18:18] TSEL2 desc TSEL2 [21:19] WAVE2 desc WAVE2 [23:22] MAMP2 desc MAMP2 [27:24] DMAEN2 desc DMAEN2 [28:28] DMAUDRIE2 desc DMAUDRIE2 [29:29] SWTRIGR desc SWTRIGR 0x4 SWTRIG1 desc SWTRIG1 [0:0] SWTRIG2 desc SWTRIG2 [1:1] DHR12R1 desc DHR12R1 0x8 DACC1DHR desc DACC1DHR [11:0] DHR12L1 desc DHR12L1 0xC DACC1DHR desc DACC1DHR [15:4] DHR8R1 desc DHR8R1 0x10 DACC1DHR desc DACC1DHR [7:0] DHR12R2 desc DHR12R2 0x14 DACC2DHR desc DACC2DHR [11:0] DHR12L2 desc DHR12L2 0x18 DACC2DHR desc DACC2DHR [15:4] DHR8R2 desc DHR8R2 0x1C DACC2DHR desc DACC2DHR [7:0] DHR12RD desc DHR12RD 0x20 DACC1DHR desc DACC1DHR [11:0] DACC2DHR desc DACC2DHR [27:16] DHR12LD desc DHR12LD 0x24 DACC1DHR desc DACC1DHR [15:4] DACC2DHR desc DACC2DHR [31:20] DHR8RD desc DHR8RD 0x28 DACC1DHR desc DACC1DHR [7:0] DACC2DHR desc DACC2DHR [15:8] DOR1 desc DOR1 0x2C read-only DACC1DOR desc DACC1DOR [11:0] read-only DOR2 desc DOR2 0x30 read-only DACC2DOR desc DACC2DOR [11:0] read-only SR desc SR 0x34 DMAUDR1 desc DMAUDR1 [13:13] DMAUDR2 desc DMAUDR2 [29:29] DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 read-only REV_ID REV_ID [30:0] CR CR Debug MCU Configuration Register 0x4 DBG_SLEEP Debug Sleep Mode [0:0] DBG_STOP Debug Stop Mode [1:1] APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted [0:0] DBG_TIMER3_STOP Debug Timer 3 stopped when Core is halted [1:1] DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted [4:4] DBG_TIMER7_STOP Debug Timer 7 stopped when Core is halted [5:5] DBG_RTC_STOP Debug RTC stopped when Core is halted [10:10] DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted [11:11] DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted [12:12] DBG_I2C1_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT [21:21] DBG_I2C2_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT [22:22] read-only DBG_LPTIM_STOP Debug LPTIM stopped when Core is halted [31:31] APB_FZ2 APB_FZ2 APB Freeze Register2 0xC DBG_TIMER1_STOP Debug Timer 1 stopped when Core is halted [11:11] DBG_TIMER14_STOP Debug Timer 14 stopped when Core is halted [15:15] DBG_TIMER15_STOP Debug Timer 15 stopped when Core is halted [16:16] DBG_TIMER16_STOP Debug Timer 16 stopped when Core is halted [17:17] DBG_TIMER17_STOP Debug Timer 17 stopped when Core is halted [18:18] DIV Hardware Divider DIV 0x40023800 0x0 0x400 registers DEND DEND Dividend 0x0 DEND Dividend [31:0] SOR SOR Divisor 0x4 SOR Divisor [31:0] QUOT QUOT Quotient 0x8 read-only QUOT Quotient [31:0] REMA REMA Remainder 0xC read-only REMA Remainder [31:0] read-only SIGN SIGN des SIGN 0x10 DIV_SIGN des DIV_SIGN [0:0] STAT STAT des SIGN 0x14 DIV_END des DIV_END [0:0] DIV_ZERO des DIV_ZERO [1:1] DMA Direct memory access DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel 1 Interrupt 9 DMA1_Channel2_3 DMA1 Channel 2 and Channel 3 Interrupt 10 DMA1_Channel4_5_6_7 DMA1 Channel 4, 5, 6, 7 Interrupts 11 ISR desc ISR 0x0 read-only GIF1 desc GIF1 [0:0] read-only TCIF1 desc TCIF1 [1:1] read-only HTIF1 desc HTIF1 [2:2] read-only TEIF1 desc TEIF1 [3:3] read-only GIF2 desc GIF2 [4:4] read-only TCIF2 desc TCIF2 [5:5] read-only HTIF2 desc HTIF2 [6:6] read-only TEIF2 desc TEIF2 [7:7] read-only GIF3 desc GIF3 [8:8] read-only TCIF3 desc TCIF3 [9:9] read-only HTIF3 desc HTIF3 [10:10] read-only TEIF3 desc TEIF3 [11:11] read-only GIF4 desc GIF4 [12:12] read-only TCIF4 desc TCIF4 [13:13] read-only HTIF4 desc HTIF4 [14:14] read-only TEIF4 desc TEIF4 [15:15] read-only GIF5 desc GIF5 [16:16] read-only TCIF5 desc TCIF5 [17:17] read-only HTIF5 desc HTIF5 [18:18] read-only TEIF5 desc TEIF5 [19:19] read-only GIF6 desc GIF6 [20:20] read-only TCIF6 desc TCIF6 [21:21] read-only HTIF6 desc HTIF6 [22:22] read-only TEIF6 desc TEIF6 [23:23] read-only GIF7 desc GIF7 [24:24] read-only TCIF7 desc TCIF7 [25:25] read-only HTIF7 desc HTIF7 [26:26] read-only TEIF7 desc TEIF7 [27:27] read-only IFCR desc IFCR 0x4 write-only CGIF1 desc CGIF1 [0:0] write-only CTCIF1 desc CTCIF1 [1:1] write-only CHTIF1 desc CHTIF1 [2:2] write-only CTEIF1 desc CTEIF1 [3:3] write-only CGIF2 desc CGIF2 [4:4] write-only CTCIF2 desc CTCIF2 [5:5] write-only CHTIF2 desc CHTIF2 [6:6] write-only CTEIF2 desc CTEIF2 [7:7] write-only CGIF3 desc CGIF3 [8:8] write-only CTCIF3 desc CTCIF3 [9:9] write-only CHTIF3 desc CHTIF3 [10:10] write-only CTEIF3 desc CTEIF3 [11:11] write-only CGIF4 desc CGIF4 [12:12] write-only CTCIF4 desc CTCIF4 [13:13] write-only CHTIF4 desc CHTIF4 [14:14] write-only CTEIF4 desc CTEIF4 [15:15] write-only CGIF5 desc CGIF5 [16:16] write-only CTCIF5 desc CTCIF5 [17:17] write-only CHTIF5 desc CHTIF5 [18:18] write-only CTEIF5 desc CTEIF5 [19:19] write-only CGIF6 desc CGIF6 [20:20] write-only CTCIF6 desc CTCIF6 [21:21] write-only CHTIF6 desc CHTIF6 [22:22] write-only CTEIF6 desc CTEIF6 [23:23] write-only CGIF7 desc CGIF7 [24:24] write-only CTCIF7 desc CTCIF7 [25:25] write-only CHTIF7 desc CHTIF7 [26:26] write-only CTEIF7 desc CTEIF7 [27:27] write-only CCR1 desc CCR1 0x8 EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR1 desc CNDTR1 0xC NDT desc NDT [15:0] CPAR1 desc CPAR1 0x10 PA desc PA [31:0] CMAR1 desc CMAR1 0x14 MA desc MA [31:0] CCR2 desc CCR2 0x1C EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR2 desc CNDTR2 0x20 NDT desc NDT [15:0] CPAR2 desc CPAR2 0x24 PA desc PA [31:0] CMAR2 desc CMAR2 0x28 MA desc MA [31:0] CCR3 desc CCR3 0x30 EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR3 desc CNDTR3 0x34 NDT desc NDT [15:0] CPAR3 desc CPAR3 0x38 PA desc PA [31:0] CMAR3 desc CMAR3 0x3C MA desc MA [31:0] CCR4 desc CCR4 0x44 EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR4 desc CNDTR4 0x48 NDT desc NDT [15:0] CPAR4 desc CPAR4 0x4C PA desc PA [31:0] CMAR4 desc CMAR4 0x50 MA desc MA [31:0] CCR5 desc CCR5 0x58 EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR5 desc CNDTR5 0x5C NDT desc NDT [15:0] CPAR5 desc CPAR5 0x60 PA desc PA [31:0] CMAR5 desc CMAR5 0x64 MA desc MA [31:0] CCR6 desc CCR6 0x6C EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR6 desc CNDTR6 0x70 NDT desc NDT [15:0] CPAR6 desc CPAR6 0x74 PA desc PA [31:0] CMAR6 desc CMAR6 0x78 MA desc MA [31:0] CCR7 desc CCR7 0x80 EN desc EN [0:0] TCIE desc TCIE [1:1] HTIE desc HTIE [2:2] TEIE desc TEIE [3:3] DIR desc DIR [4:4] CIRC desc CIRC [5:5] PINC desc PINC [6:6] MINC desc MINC [7:7] PSIZE desc PSIZE [9:8] MSIZE desc MSIZE [11:10] PL desc PL [13:12] MEM2MEM desc MEM2MEM [14:14] CNDTR7 desc CNDTR7 0x84 NDT desc NDT [15:0] CPAR7 desc CPAR7 0x88 PA desc PA [31:0] CMAR7 desc CMAR7 0x8C MA desc MA [31:0] EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers PVD PVD Interrupt through EXTI Lines 16 1 EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR RTSR EXTI rising trigger selection register 0x0 RT0 Rising trigger event configuration bit of Configurable Event input [0:0] RT1 Rising trigger event configuration bit of Configurable Event input [1:1] RT2 Rising trigger event configuration bit of Configurable Event input [2:2] RT3 Rising trigger event configuration bit of Configurable Event input [3:3] RT4 Rising trigger event configuration bit of Configurable Event input [4:4] RT5 Rising trigger event configuration bit of Configurable Event input [5:5] RT6 Rising trigger event configuration bit of Configurable Event input [6:6] RT7 Rising trigger event configuration bit of Configurable Event input [7:7] RT8 Rising trigger event configuration bit of Configurable Event input [8:8] RT9 Rising trigger event configuration bit of Configurable Event input [9:9] RT10 Rising trigger event configuration bit of Configurable Event input [10:10] RT11 Rising trigger event configuration bit of Configurable Event input [11:11] RT12 Rising trigger event configuration bit of Configurable Event input [12:12] RT13 Rising trigger event configuration bit of Configurable Event input [13:13] RT14 Rising trigger event configuration bit of Configurable Event input [14:14] RT15 Rising trigger event configuration bit of Configurable Event input [15:15] RT16 Rising trigger event configuration bit of Configurable Event input [16:16] RT17 Rising trigger event configuration bit of Configurable Event input [17:17] RT18 Rising trigger event configuration bit of Configurable Event input [18:18] RT20 Rising trigger event configuration bit of Configurable Event input [20:20] FTSR FTSR EXTI falling trigger selection register 0x4 FT0 Falling trigger event configuration bit of Configurable Event input [0:0] FT1 Falling trigger event configuration bit of Configurable Event input [1:1] FT2 Falling trigger event configuration bit of Configurable Event input [2:2] FT3 Falling trigger event configuration bit of Configurable Event input [3:3] FT4 Falling trigger event configuration bit of Configurable Event input [4:4] FT5 Falling trigger event configuration bit of Configurable Event input [5:5] FT6 Falling trigger event configuration bit of Configurable Event input [6:6] FT7 Falling trigger event configuration bit of Configurable Event input [7:7] FT8 Falling trigger event configuration bit of Configurable Event input [8:8] FT9 Falling trigger event configuration bit of Configurable Event input [9:9] FT10 Falling trigger event configuration bit of Configurable Event input [10:10] FT11 Falling trigger event configuration bit of Configurable Event input [11:11] FT12 Falling trigger event configuration bit of Configurable Event input [12:12] FT13 Falling trigger event configuration bit of Configurable Event input [13:13] FT14 Falling trigger event configuration bit of Configurable Event input [14:14] FT15 Falling trigger event configuration bit of Configurable Event input [15:15] FT16 Falling trigger event configuration bit of Configurable Event input [16:16] FT17 Falling trigger event configuration bit of Configurable Event input [17:17] FT18 Falling trigger event configuration bit of Configurable Event input [18:18] FT20 Falling trigger event configuration bit of Configurable Event input [20:20] SWIER SWIER EXTI software interrupt event register 0x8 SWI0 Rising trigger event configuration bit of Configurable Event input [0:0] SWI1 Rising trigger event configuration bit of Configurable Event input [1:1] SWI2 Rising trigger event configuration bit of Configurable Event input [2:2] SWI3 Rising trigger event configuration bit of Configurable Event input [3:3] SWI4 Rising trigger event configuration bit of Configurable Event input [4:4] SWI5 Rising trigger event configuration bit of Configurable Event input [5:5] SWI6 Rising trigger event configuration bit of Configurable Event input [6:6] SWI7 Rising trigger event configuration bit of Configurable Event input [7:7] SWI8 Rising trigger event configuration bit of Configurable Event input [8:8] SWI9 Rising trigger event configuration bit of Configurable Event input [9:9] SWI10 Rising trigger event configuration bit of Configurable Event input [10:10] SWI11 Rising trigger event configuration bit of Configurable Event input [11:11] SWI12 Rising trigger event configuration bit of Configurable Event input [12:12] SWI13 Rising trigger event configuration bit of Configurable Event input [13:13] SWI14 Rising trigger event configuration bit of Configurable Event input [14:14] SWI15 Rising trigger event configuration bit of Configurable Event input [15:15] SWI16 Rising trigger event configuration bit of Configurable Event input [16:16] SWI17 Rising trigger event configuration bit of Configurable Event input [17:17] SWI18 Rising trigger event configuration bit of Configurable Event input [18:18] SWI20 Rising trigger event configuration bit of Configurable Event input [20:20] PR PR EXTI pending register 0xC PR0 configurable event inputs x rising edge Pending bit. [0:0] PR1 configurable event inputs x rising edge Pending bit. [1:1] PR2 configurable event inputs x rising edge Pending bit. [2:2] PR3 configurable event inputs x rising edge Pending bit. [3:3] PR4 configurable event inputs x rising edge Pending bit. [4:4] PR5 configurable event inputs x rising edge Pending bit. [5:5] PR6 configurable event inputs x rising edge Pending bit. [6:6] PR7 configurable event inputs x rising edge Pending bit. [7:7] PR8 configurable event inputs x rising edge Pending bit. [8:8] PR9 configurable event inputs x rising edge Pending bit. [9:9] PR10 configurable event inputs x rising edge Pending bit. [10:10] PR11 configurable event inputs x rising edge Pending bit. [11:11] PR12 configurable event inputs x rising edge Pending bit. [12:12] PR13 configurable event inputs x rising edge Pending bit [13:13] PR14 configurable event inputs x rising edge Pending bit. [14:14] PR15 configurable event inputs x rising edge Pending bit. [15:15] PR16 configurable event inputs x rising edge Pending bit. [16:16] PR17 configurable event inputs x rising edge Pending bit. [17:17] PR18 configurable event inputs x rising edge Pending bit. [18:18] PR20 configurable event inputs x rising edge Pending bit. [20:20] EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 EXTI0 GPIO port selection [1:0] EXTI1 GPIO port selection [9:8] EXTI2 GPIO port selection [17:16] EXTI3 GPIO port selection [25:24] EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 EXTI4 GPIO port selection [1:0] EXTI5 GPIO port selection [9:8] EXTI6 GPIO port selection [17:16] EXTI7 GPIO port selection [25:24] EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 EXTI8 GPIO port selection [1:0] EXTI9 GPIO port selection [9:8] EXTI10 GPIO port selection [17:16] EXTI11 GPIO port selection [25:24] EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C EXTI12 GPIO port selection [1:0] EXTI13 GPIO port selection [9:8] EXTI14 GPIO port selection [17:16] EXTI15 GPIO port selection [25:24] IMR IMR EXTI CPU wakeup with interrupt mask register 0x80 0xFFF80000 IM0 CPU wakeup with interrupt mask on event input [0:0] IM1 CPU wakeup with interrupt mask on event input [1:1] IM2 CPU wakeup with interrupt mask on event input [2:2] IM3 CPU wakeup with interrupt mask on event input [3:3] IM4 CPU wakeup with interrupt mask on event input [4:4] IM5 CPU wakeup with interrupt mask on event input [5:5] IM6 CPU wakeup with interrupt mask on event input [6:6] IM7 CPU wakeup with interrupt mask on event input [7:7] IM8 CPU wakeup with interrupt mask on event input [8:8] IM9 CPU wakeup with interrupt mask on event input [9:9] IM10 CPU wakeup with interrupt mask on event input [10:10] IM11 CPU wakeup with interrupt mask on event input [11:11] IM12 CPU wakeup with interrupt mask on event input [12:12] IM13 CPU wakeup with interrupt mask on event input [13:13] IM14 CPU wakeup with interrupt mask on event input [14:14] IM15 CPU wakeup with interrupt mask on event input [15:15] IM16 CPU wakeup with interrupt mask on event input [16:16] IM17 CPU wakeup with interrupt mask on event input [17:17] IM18 CPU wakeup with interrupt mask on event input [18:18] IM19 CPU wakeup with interrupt mask on event input [19:19] IM20 CPU wakeup with interrupt mask on event input [20:20] IM29 CPU wakeup with interrupt mask on event input [29:29] EMR EMR EXTI CPU wakeup with event mask register 0x84 EM0 CPU wakeup with event mask on event input [0:0] EM1 CPU wakeup with event mask on event input [1:1] EM2 CPU wakeup with event mask on event input [2:2] EM3 CPU wakeup with event mask on event input [3:3] EM4 CPU wakeup with event mask on event input [4:4] EM5 CPU wakeup with event mask on event input [5:5] EM6 CPU wakeup with event mask on event input [6:6] EM7 CPU wakeup with event mask on event input [7:7] EM8 CPU wakeup with event mask on event input [8:8] EM9 CPU wakeup with event mask on event input [9:9] EM10 CPU wakeup with event mask on event input [10:10] EM11 CPU wakeup with event mask on event input [11:11] EM12 CPU wakeup with event mask on event input [12:12] EM13 CPU wakeup with event mask on event input [13:13] EM14 CPU wakeup with event mask on event input [14:14] EM15 CPU wakeup with event mask on event input [15:15] EM16 CPU wakeup with event mask on event input [16:16] EM17 CPU wakeup with event mask on event input [17:17] EM18 CPU wakeup with event mask on event input [18:18] EM19 CPU wakeup with event mask on event input [19:19] EM20 CPU wakeup with event mask on event input [20:20] EM29 CPU wakeup with event mask on event input [29:29] FLASH desc FLASH FLASH 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR desc ACR 0x0 0x500 LATENCY desc LATENCY [1:0] KEYR desc KEYR 0x8 write-only KEY desc KEY [31:0] write-only OPTKEYR desc OPTKEYR 0xC write-only OPTKEY desc OPTKEY [31:0] write-only SR desc SR 0x10 EOP desc EOP [0:0] WRPERR desc WRPERR [4:4] OPTVERR desc OPTVERR [15:15] BSY desc BSY [16:16] read-only CR desc CR 0x14 PG desc PG [0:0] PER desc PER [1:1] MER desc MER [2:2] SER desc SER [11:11] OPTSTRT desc OPTSTRT [17:17] PGSTRT desc PGSTRT [19:19] EOPIE desc EOPIE [24:24] ERRIE desc ERRIE [25:25] OBL_LAUNCH desc OBL_LAUNCH [27:27] OPTLOCK desc OPTLOCK [30:30] LOCK desc LOCK [31:31] OPTR desc OPTR 0x20 read-only RDP desc RDP [7:0] read-only IWDG_SW desc IWDG_SW [11:11] read-only WWDG_SW desc WWDG_SW [12:12] read-only NRST_MODE desc NRST_MODE [13:13] read-only NBOOT1 desc nBOOT1 [14:14] read-only IWDG_STOP desc IWDG_STOP [15:15] read-only BORCR desc BORCR 0x24 read-only BOR_EN desc BOR_EN [5:5] read-only BOR_LEV desc BOR_LEV [15:13] read-only WRPR desc WRPR 0x2C WRP desc WRP [15:0] STCR desc STCR 0x90 0x6400 SLEEP_EN desc SLEEP_EN [0:0] SLEEP_TIME desc SLEEP_TIME [15:8] TS0 desc TS0 0x100 0xB4 TS0 desc TS0 [7:0] TS1 desc TS1 0x104 0x1B0 TS1 desc TS1 [8:0] TS2P desc TS2P 0x108 0xB4 TS2P desc TS2P [7:0] TPS3 desc TPS3 0x10C 0x6C0 TPS3 desc TPS3 [10:0] TS3 desc TS3 0x110 0xB4 TS3 desc TS3 [7:0] PERTPE desc PERTPE 0x114 0xEA60 PERTPE desc PERTPE [16:0] SMERTPE desc SMERTPE 0x118 0xFD20 SMERTPE desc SMERTPE [16:0] PRGTPE desc PRGTPE 0x11C 0x8CA0 PRGTPE desc PRGTPE [15:0] PRETPE desc PRETPE 0x120 0x12C0 PRETPE desc PRETPE [13:0] GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0xEBFFFFFF MODE0 Port x configuration bits (y=0-15) [1:0] MODE1 Port x configuration bits (y=0-15) [3:2] MODE2 Port x configuration bits (y=0-15) [5:4] MODE3 Port x configuration bits (y=0-15) [7:6] MODE4 Port x configuration bits (y=0-15) [9:8] MODE5 Port x configuration bits (y=0-15) [11:10] MODE6 Port x configuration bits (y=0-15) [13:12] MODE7 Port x configuration bits (y=0-15) [15:14] MODE8 Port x configuration bits (y=0-15) [17:16] MODE9 Port x configuration bits (y=0-15) [19:18] MODE10 Port x configuration bits (y=0-15) [21:20] MODE11 Port x configuration bits (y=0-15) [23:22] MODE12 Port x configuration bits (y=0-15) [25:24] MODE13 Port x configuration bits (y=0-15) [27:26] MODE14 Port x configuration bits (y=0-15) [29:28] MODE15 Port x configuration bits (y=0-15) [31:30] OTYPER OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y=0-15) [0:0] OT1 Port x configuration bits (y=0-15) [1:1] OT2 Port x configuration bits (y=0-15) [2:2] OT3 Port x configuration bits (y=0-15) [3:3] OT4 Port x configuration bits (y=0-15) [4:4] OT5 Port x configuration bits (y=0-15) [5:5] OT6 Port x configuration bits (y=0-15) [6:6] OT7 Port x configuration bits (y=0-15) [7:7] OT8 Port x configuration bits (y=0-15) [8:8] OT9 Port x configuration bits (y=0-15) [9:9] OT10 Port x configuration bits (y=0-15) [10:10] OT11 Port x configuration bits (y=0-15) [11:11] OT12 Port x configuration bits (y=0-15) [12:12] OT13 Port x configuration bits (y=0-15) [13:13] OT14 Port x configuration bits (y=0-15) [14:14] OT15 Port x configuration bits (y=0-15) [15:15] OSPEEDR OSPEEDR GPIO port output speed register 0x8 0xC000000 OSPEED0 Port x configuration bits (y=0-15) [1:0] OSPEED1 Port x configuration bits (y=0-15) [3:2] OSPEED2 Port x configuration bits (y=0-15) [5:4] OSPEED3 Port x configuration bits (y=0-15) [7:6] OSPEED4 Port x configuration bits (y=0-15) [9:8] OSPEED5 Port x configuration bits (y=0-15) [11:10] OSPEED6 Port x configuration bits (y=0-15) [13:12] OSPEED7 Port x configuration bits (y=0-15) [15:14] OSPEED8 Port x configuration bits (y=0-15) [17:16] OSPEED9 Port x configuration bits (y=0-15) [19:18] OSPEED10 Port x configuration bits (y=0-15) [21:20] OSPEED11 Port x configuration bits (y=0-15) [23:22] OSPEED12 Port x configuration bits (y=0-15) [25:24] OSPEED13 Port x configuration bits (y=0-15) [27:26] OSPEED14 Port x configuration bits (y=0-15) [29:28] OSPEED15 Port x configuration bits (y=0-15) [31:30] PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x24000000 PUPD0 Port x configuration bits (y=0-15) [1:0] PUPD1 Port x configuration bits (y=0-15) [3:2] PUPD2 Port x configuration bits (y=0-15) [5:4] PUPD3 Port x configuration bits (y=0-15) [7:6] PUPD4 Port x configuration bits (y=0-15) [9:8] PUPD5 Port x configuration bits (y=0-15) [11:10] PUPD6 Port x configuration bits (y=0-15) [13:12] PUPD7 Port x configuration bits (y=0-15) [15:14] PUPD8 Port x configuration bits (y=0-15) [17:16] PUPD9 Port x configuration bits (y=0-15) [19:18] PUPD10 Port x configuration bits (y=0-15) [21:20] PUPD11 Port x configuration bits (y=0-15) [23:22] PUPD12 Port x configuration bits (y=0-15) [25:24] PUPD13 Port x configuration bits (y=0-15) [27:26] PUPD14 Port x configuration bits (y=0-15) [29:28] PUPD15 Port x configuration bits (y=0-15) [31:30] IDR IDR GPIO port input data register 0x10 read-only ID0 Port input data (y=0-15) [0:0] ID1 Port input data (y=0-15) [1:1] ID2 Port input data (y=0-15) [2:2] ID3 Port input data (y=0-15) [3:3] ID4 Port input data (y=0-15) [4:4] ID5 Port input data (y=0-15) [5:5] ID6 Port input data (y=0-15) [6:6] ID7 Port input data (y=0-15) [7:7] ID8 Port input data (y=0-15) [8:8] ID9 Port input data (y=0-15) [9:9] ID10 Port input data (y=0-15) [10:10] ID11 Port input data (y=0-15) [11:11] ID12 Port input data (y=0-15) [12:12] ID13 Port input data (y=0-15) [13:13] ID14 Port input data (y=0-15) [14:14] ID15 Port input data (y=0-15) [15:15] ODR ODR GPIO port output data register 0x14 OD0 Port output data (y=0-15) [0:0] OD1 Port output data (y=0-15) [1:1] OD2 Port output data (y=0-15) [2:2] OD3 Port output data (y=0-15) [3:3] OD4 Port output data (y=0-15) [4:4] OD5 Port output data (y=0-15) [5:5] OD6 Port output data (y=0-15) [6:6] OD7 Port output data (y=0-15) [7:7] OD8 Port output data (y=0-15) [8:8] OD9 Port output data (y=0-15) [9:9] OD10 Port output data (y=0-15) [10:10] OD11 Port output data (y=0-15) [11:11] OD12 Port output data (y=0-15) [12:12] OD13 Port output data (y=0-15) [13:13] OD14 Port output data (y=0-15) [14:14] OD15 Port output data (y=0-15) [15:15] BSRR BSRR GPIO port bit set/reset register 0x18 write-only BS0 Port x set bit y (y=0-15) [0:0] BS1 Port x set bit y (y=0-15) [1:1] BS2 Port x set bit y (y=0-15) [2:2] BS3 Port x set bit y (y=0-15) [3:3] BS4 Port x set bit y (y=0-15) [4:4] BS5 Port x set bit y (y=0-15) [5:5] BS6 Port x set bit y (y=0-15) [6:6] BS7 Port x set bit y (y=0-15) [7:7] BS8 Port x set bit y (y=0-15) [8:8] BS9 Port x set bit y (y=0-15) [9:9] BS10 Port x set bit y (y=0-15) [10:10] BS11 Port x set bit y (y=0-15) [11:11] BS12 Port x set bit y (y=0-15) [12:12] BS13 Port x set bit y (y=0-15) [13:13] BS14 Port x set bit y (y=0-15) [14:14] BS15 Port x set bit y (y=0-15) [15:15] BR0 Port x set bit y (y=0-15) [16:16] BR1 Port x reset bit y (y=0-15) [17:17] BR2 Port x reset bit y (y=0-15) [18:18] BR3 Port x reset bit y (y=0-15) [19:19] BR4 Port x reset bit y (y=0-15) [20:20] BR5 Port x reset bit y (y=0-15) [21:21] BR6 Port x reset bit y (y=0-15) [22:22] BR7 Port x reset bit y (y=0-15) [23:23] BR8 Port x reset bit y (y=0-15) [24:24] BR9 Port x reset bit y (y=0-15) [25:25] BR10 Port x reset bit y (y=0-15) [26:26] BR11 Port x reset bit y (y=0-15) [27:27] BR12 Port x reset bit y (y=0-15) [28:28] BR13 Port x reset bit y (y=0-15) [29:29] BR14 Port x reset bit y (y=0-15) [30:30] BR15 Port x reset bit y (y=0-15) [31:31] LCKR LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y=0-15) [0:0] LCK1 Port x lock bit y (y=0-15) [1:1] LCK2 Port x lock bit y (y=0-15) [2:2] LCK3 Port x lock bit y (y=0-15) [3:3] LCK4 Port x lock bit y (y=0-15) [4:4] LCK5 Port x lock bit y (y=0-15) [5:5] LCK6 Port x lock bit y (y=0-15) [6:6] LCK7 Port x lock bit y (y=0-15) [7:7] LCK8 Port x lock bit y (y=0-15) [8:8] LCK9 Port x lock bit y (y=0-15) [9:9] LCK10 Port x lock bit y (y=0-15) [10:10] LCK11 Port x lock bit y (y=0-15) [11:11] LCK12 Port x lock bit y (y=0-15) [12:12] LCK13 Port x lock bit y (y=0-15) [13:13] LCK14 Port x lock bit y (y=0-15) [14:14] LCK15 Port x lock bit y (y=0-15) [15:15] LCKK Port x lock (LCKK) [16:16] AFRL AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y=0-7) [3:0] AFSEL1 Alternate function selection for port x bit y (y=0-7) [7:4] AFSEL2 Alternate function selection for port x bit y (y=0-7) [11:8] AFSEL3 Alternate function selection for port x bit y (y=0-7) [15:12] AFSEL4 Alternate function selection for port x bit y (y=0-7) [19:16] AFSEL5 Alternate function selection for port x bit y (y=0-7) [23:20] AFSEL6 Alternate function selection for port x bit y (y=0-7) [27:24] AFSEL7 Alternate function selection for port x bit y (y=0-7) [31:28] AFRH AFRH GPIO alternate function high register 0x24 AFSEL8 Alternate function selection for port x bit y (y=8-15) [3:0] AFSEL9 Alternate function selection for port x bit y (y=8-15) [7:4] AFSEL10 Alternate function selection for port x bit y (y=8-15) [11:8] AFSEL11 Alternate function selection for port x bit y (y=8-15) [15:12] AFSEL12 Alternate function selection for port x bit y (y=8-15) [19:16] AFSEL13 Alternate function selection for port x bit y (y=8-15) [23:20] AFSEL14 Alternate function selection for port x bit y (y=8-15) [27:24] AFSEL15 Alternate function selection for port x bit y (y=8-15) [31:28] BRR BRR port bit reset register 0x28 write-only BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] BR8 Port Reset bit [8:8] BR9 Port Reset bit [9:9] BR10 Port Reset bit [10:10] BR11 Port Reset bit [11:11] BR12 Port Reset bit [12:12] BR13 Port Reset bit [13:13] BR14 Port Reset bit [14:14] BR15 Port Reset bit [15:15] GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers GPIOC General-purpose I/Os GPIO 0x50000800 0x0 0x400 registers GPIOF General-purpose I/Os GPIO 0x50001400 0x0 0x400 registers I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 desc CR1 0x0 PE desc PE [0:0] SMBUS desc SMBUS [1:1] SMBTYPE desc SMBTYPE [3:3] ENARP desc ENARP [4:4] ENPEC desc ENPEC [5:5] ENGC desc ENGC [6:6] NOSTRETCH desc NOSTRETCH [7:7] START desc START [8:8] STOP desc STOP [9:9] ACK desc ACK [10:10] POS desc POS [11:11] PEC desc PEC [12:12] ALERT desc ALERT [13:13] SWRST desc SWRST [15:15] CR2 desc CR2 0x4 FREQ desc FREQ [5:0] ITERREN desc ITERREN [8:8] ITEVTEN desc ITEVTEN [9:9] ITBUFEN desc ITBUFEN [10:10] DMAEN desc DMAEN [11:11] LAST desc LAST [12:12] OAR1 desc OAR1 0x8 ADD0 desc ADD0 [0:0] ADD1_7 desc ADD1_7 [7:1] ADD8_9 desc ADD8_9 [9:8] ADDMODE desc ADDMODE [15:15] OAR2 desc OAR2 0xC ENDUAL desc ENDUAL [0:0] ADD2 desc ADD2 [7:1] DR desc DR 0x10 DR desc DR [7:0] SR1 desc SR1 0x14 SB desc SB [0:0] read-only ADDR desc ADDR [1:1] read-only BTF desc BTF [2:2] read-only ADD10 desc ADD10 [3:3] read-only STOPF desc STOPF [4:4] read-only RXNE desc RXNE [6:6] read-only TXE desc TXE [7:7] read-only BERR desc BERR [8:8] ARLO desc ARLO [9:9] AF desc AF [10:10] OVR desc OVR [11:11] PECERR desc PECERR [12:12] TIMEOUT desc TIMEOUT [14:14] SMBALERT desc SMBALERT [15:15] SR2 desc SR2 0x18 read-only MSL desc MSL [0:0] read-only BUSY desc BUSY [1:1] read-only TRA desc TRA [2:2] read-only GENCALL desc GENCALL [4:4] read-only SMBDEFAULT desc SMBDEFAULT [5:5] read-only SMBHOST desc SMBHOST [6:6] read-only DUALF desc DUALF [7:7] read-only PEC desc PEC [15:8] read-only CCR desc CCR 0x1C CCR desc CCR [11:0] DUTY desc DUTY [14:14] FS desc FS [15:15] TRISE desc TRISE 0x20 0x2 TRISE desc TRISE [5:0] I2C2 desc I2C I2C 0x40005800 0x0 0x400 registers I2C2 I2C2 Event Interrupt 24 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 write-only KEY Key value [15:0] PR PR Prescaler register (IWDG_PR) 0x4 PR Prescaler divider [2:0] RLR RLR Reload register (IWDG_RLR) 0x8 0xFFF RL Watchdog counter reload value [11:0] SR SR Status register (IWDG_SR) 0xC read-only PVU Watchdog prescaler value update [0:0] RVU Watchdog counter reload value update [1:1] LCD LCD CONTROLLER LCD 0x40002400 0x0 0x400 registers LCD LCD global Interrupt 8 CR0 CR0 Control register 0x0 EN EN [0:0] LCDCLK LCDCLK [2:1] BIAS BIAS [5:5] DUTY DUTY [8:6] BSEL BSEL [11:9] CONTRAST CONTRAST [15:12] CR1 CR1 CR1 0x4 BLINKCNT BLINKCNT [5:0] BLINKEN BLINKEN [6:6] MODE MODE [8:8] IE IE [9:9] DMAEN DMAEN [10:10] INTF INTF [11:11] INTCLR INTCLR INTCLR 0x8 INTF_CLR INTF_CLR [10:10] POEN0 POEN0 POEN0 0xC S0 S0 [0:0] S1 S1 [1:1] S2 S2 [2:2] S3 S3 [3:3] S4 S4 [4:4] S5 S5 [5:5] S6 S6 [6:6] S7 S7 [7:7] S8 S8 [8:8] S9 S9 [9:9] S10 S10 [10:10] S11 S11 [11:11] S12 S12 [12:12] S13 S13 [13:13] S14 S14 [14:14] S15 S15 [15:15] S16 S16 [16:16] S17 S17 [17:17] S18 S18 [18:18] S19 S19 [19:19] S20 S20 [20:20] S21 S21 [21:21] S22 S22 [22:22] S23 S23 [23:23] S24 S24 [24:24] S25 S25 [25:25] S26 S26 [26:26] S27 S27 [27:27] S28 S28 [28:28] S29 S29 [29:29] S30 S30 [30:30] S31 S31 [31:31] POEN1 POEN1 POEN1 0x10 S32 S32 [0:0] S33 S33 [1:1] S34 S34 [2:2] S35 S35 [3:3] S39C4 S39 [4:4] S38C5 S38 [5:5] S37C6 S37 [6:6] S36C7 S36 [7:7] C0 C0 [8:8] C1 C1 [9:9] C2 C2 [10:10] C3 C3 [11:11] MUX MUX [12:12] RAM0 RAM0 des RAM0 0x14 D des D [31:0] RAM1 RAM1 des RAM1 0x18 D des D [31:0] RAM2 RAM2 des RAM2 0x1C D des D [31:0] RAM3 RAM3 des RAM3 0x20 D des D [31:0] RAM4 RAM4 des RAM4 0x24 D des D [31:0] RAM5 RAM5 des RAM5 0x28 D des D [31:0] RAM6 RAM6 des RAM6 0x2C D des D [31:0] RAM7 RAM7 des RAM7 0x30 D des D [31:0] RAM8 RAM8 des RAM8 0x34 D des D [7:0] RAM9 RAM9 des RAM9 0x38 D des D [7:0] RAM10 RAM10 des RAM10 0x3C D des D [7:0] RAM11 RAM11 des RAM11 0x40 D des D [7:0] RAM12 RAM12 des RAM12 0x44 D des D [7:0] RAM13 RAM13 des RAM13 0x48 D des D [7:0] RAM14 RAM14 des RAM14 0x4C D des D [7:0] RAM15 RAM15 des RAM15 0x50 D des D [7:0] LPTIM1 Low power timer LPTIM1 0x40007C00 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 ISR ISR Interrupt and Status Register 0x0 read-only ARRM Autoreload match [1:1] ARROK Autoreload match update OK [4:4] ICR ICR Interrupt Clear Register 0x4 write-only ARRMCF Autoreload match Clear Flag [1:1] ARROKCF Autoreload match update OK Clear Flag [4:4] IER IER Interrupt Enable Register 0x8 ARRMIE Autoreload matchInterrupt Enable [1:1] ARROKIE Autoreload match update OK Interrupt Enable [4:4] CFGR CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR CR Control Register 0x10 ENABLE LPTIM Enable [0:0] SNGSTRT LPTIM start in single mode [1:1] CNTSTRT CNTSTRT [2:2] COUNTRST LPTIM counter reset [3:3] RSTARE Reset after read enable [4:4] ARR ARR Autoreload Register 0x18 0x1 ARR Auto reload value [15:0] CNT CNT Counter Register 0x1C read-only CNT Counter value [15:0] OPA des OPA OPA 0x40010300 0x0 0x400 registers CR0 CR0 CR0 register 0x30 0xFFFFFFFF OP1OEN1 OP1OEN1 [1:1] OP2OEN1 OP2OEN1 [6:6] OP3OEN1 OP3OEN1 [11:11] CR1 CR1 CR1 register 0x34 EN1 EN1 [5:5] EN2 EN2 [6:6] EN3 EN3 [7:7] PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x30000 BIAS_CR MR Bias current [2:0] BIAS_CR_SEL MR Bias current selection [4:4] DBP Disable backup domain write protection [8:8] VOS Voltage scaling range selection [10:9] FLS_SLPTIME Flash wait time after wakeup from the stop mode [13:12] LPR Low-power run [14:14] HSION_CTRL HSI open time control [19:19] CR2 CR2 Power control register 2 0x4 0x500 PVDE Power voltage detector enable [0:0] SRCSEL Power voltage detector volatage selection [2:2] PVDT Power voltage detector threshold selection [6:4] FLTEN Digital filter enable [8:8] FLT_TIME Digital filter time configuration [11:9] SR SR Power status register 0x14 read-only PVDO PVD output [11:11] RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC_CTC RCC and CTC global Interrupts 4 CR CR Clock control register 0x0 0x100 HSION HSI16 clock enable [8:8] HSIRDY HSI16 clock ready flag [10:10] HSEON HSE clock enable [16:16] HSERDY HSE clock ready flag [17:17] HSEBYP HSE crystal oscillator bypass [18:18] CSSON Clock security system enable [19:19] ADC_DIV ADC Frequency Division [22:21] PLLON PLL enable [24:24] PLLRDY PLL clock ready flag [25:25] ICSCR ICSCR Internal clock sources calibration register 0x4 0x10000000 HSI_TRIM HSI clock trimming [12:0] HSI_FS HSI frequency selection [15:13] LSI_TRIM LSI clock trimming [24:16] CFGR CFGR Clock configuration register 0x8 SW System clock switch [2:0] SWS System clock switch status [5:3] read-only HPRE AHB prescaler [11:8] PPRE APB prescaler [14:12] MCOSEL Microcontroller clock output [26:24] MCOPRE Microcontroller clock output prescaler [30:28] PLLCFGR PLLCFGR PLL configuration register 0xC PLLSRC PLL clock source selection [1:0] PLLMUL PLLMUL [3:2] ECSCR ECSCR External clock source control register 0x10 HSE_DRV HSE_DRV [1:0] HSE_STARTUP HSE_STARTUP [4:3] LSE_DRIVER LSE clock driver selection [17:16] LSE_STARTUP LSE_STARTUP [21:20] CIER CIER Clock interrupt enable register 0x18 LSIRDYIE LSI ready interrupt enable [0:0] LSERDYIE LSE ready interrupt enable [1:1] HSIRDYIE HSI ready interrupt enable [3:3] HSERDYIE HSE ready interrupt enable [4:4] PLLRDYIE PLL ready interrupt enable [5:5] CIFR CIFR Clock interrupt flag register 0x1C read-only LSIRDYF LSI ready interrupt flag [0:0] LSERDYF LSE ready interrupt flag [1:1] HSIRDYF HSI ready interrupt flag [3:3] HSERDYF HSE ready interrupt flag [4:4] PLLRDYF PLL ready interrupt flag [5:5] CSSF HSE clock secure system interrupt flag [8:8] LSECSSF LSE clock secure system interrupt flag [9:9] CICR CICR Clock interrupt clear register 0x20 write-only LSIRDYC LSI ready interrupt clear [0:0] LSERDYC LSE ready interrupt clear [1:1] HSIRDYC HSI ready interrupt clear [3:3] HSERDYC HSE ready interrupt clear [4:4] PLLRDYC PLL ready interrupt clear [5:5] CSSC clock secure system interrupt flag clear [8:8] LSECSSC LSE clock secure system interrupt flag clear [9:9] IOPRSTR IOPRSTR GPIO reset register 0x24 GPIOARST I/O port A reset [0:0] GPIOBRST I/O port B reset [1:1] GPIOCRST I/O port F reset [2:2] GPIOFRST I/O port F reset [5:5] AHBRSTR AHBRSTR AHB peripheral reset register 0x28 DMARST DMA reset [0:0] CRCRST CRC reset [12:12] DIVRST DIV reset [24:24] APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C TIM2RST TIM2 timer reset [0:0] TIM3RST TIM3 timer reset [1:1] TIM6RST TIM6 timer reset [4:4] TIM7RST TIM7 timer reset [5:5] RTCAPBRST RTCAPB reset [10:10] WWDGRST WWDG reset [11:11] SPI2RST SPI2 reset [14:14] USART2RST USART2 reset [17:17] USART3RST USART3 reset [18:18] USART4RST USART4 reset [19:19] I2C1RST I2C1 reset [21:21] I2C2RST I2C2 reset [22:22] USBRST USB reset [23:23] CTCRST CTCRST [27:27] PWRRST Power interface reset [28:28] DACRST DACRST [29:29] OPARST OPARST [30:30] LPTIMRST Low Power Timer reset [31:31] APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 SYSCFGRST SYSCFG reset [0:0] ADCRST ADC reset [9:9] DBGRST DBG reset [10:10] TIM1RST TIM1 reset [11:11] SPI1RST SPI1 reset [12:12] USART1RST USART1 reset [14:14] TIM14RST TIM14 reset [15:15] TIM15RST TIM15 reset [16:16] TIM16RST TIM16 reset [17:17] TIM17RST TIM17 reset [18:18] COMP1RST COMP1 reset [20:20] COMP2RST COMP2 reset [21:21] COMP3RST COMP3 reset [22:22] LCDRST LCD reset [23:23] IOPENR IOPENR GPIO clock enable register 0x34 GPIOAEN I/O port A clock enable [0:0] GPIOBEN I/O port B clock enable [1:1] GPIOCEN I/O port C clock enable [2:2] GPIOFEN I/O port F clock enable [5:5] AHBENR AHBENR AHB peripheral clock enable register 0x38 DMAEN DMA clock enable [0:0] FLASHEN Flash memory interface clock enable [8:8] SRAMEN SRAM memory interface clock enable [9:9] CRCEN CRC clock enable [12:12] DIVEN DIVEN [24:24] APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C TIM2EN TIM2 timer clock enable [0:0] TIM3EN TIM3 timer clock enable [1:1] TIM6EN TIM6 timer clock enable [4:4] TIM7EN TIM7 timer clock enable [5:5] TIMDIVEN desc TIMDIVEN [10:10] WWDGEN WWDG clock enable [11:11] SPI2EN SPI2 clock enable [14:14] USART2EN USART2 clock enable [17:17] USART3EN USART3 clock enable [18:18] USART4EN USART4 clock enable [19:19] I2C1EN I2C1 clock enable [21:21] I2C2EN I2C2 clock enable [22:22] USBEN USB clock enable [23:23] CTCEN CTC clock enable [27:27] PWREN Power interface clock enable [28:28] DACEN DAC clock enable [29:29] OPAEN OPA clock enable [30:30] LPTIMEN LPTIM clock enable [31:31] APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable [0:0] ADCEN ADCEN clock enable [9:9] DBGEN DBG clock enable [10:10] TIM1EN TIM1 clock enable [11:11] SPI1EN SPI1 clock enable [12:12] USART1EN USART1 clock enable [14:14] TIM14EN TIM14 clock enable [15:15] TIM15EN TIM15 clock enable [16:16] TIM16EN TIM16 clock enable [17:17] TIM17EN TIM17 clock enable [18:18] COMP1EN COMP1 clock enable [20:20] COMP2EN COMP2 clock enable [21:21] COMP3EN COMP3 clock enable [22:22] LCDEN LCD clock enable [23:23] CCIPR CCIPR Peripherals independent clock configuration register 0x54 PVDSEL PVD detect clock source selection [7:7] COMP1SEL COMP1 clock source selection [8:8] COMP2SEL COMP2 clock source selection [9:9] COMP3SEL COMP3 clock source selection [10:10] LPTIM1SEL LPTIM1 clock source selection [19:18] BDCR BDCR RTC domain control register 0x5C LSEON LSE oscillator enable [0:0] LSERDY LSE oscillator ready [1:1] LSEBYP LSE oscillator bypass [2:2] LSECSSON LSE CSS enable [5:5] LSECSSD LSE CSS detect [6:6] RTCSEL RTC clock source selection [9:8] RTCEN RTC clock source enable [15:15] BDRST RTC domain software reset [16:16] LSCOEN Low-speed clock output (LSCO) enable [24:24] LSCOSEL Low-speed clock output selection [25:25] CSR CSR Control/status register 0x60 LSION LSI oscillator enable [0:0] LSIRDY LSI oscillator ready [1:1] NRST_FLTDIS NRST_FLTDIS oscillator ready [8:8] RMVF Remove reset flags [23:23] OBLRSTF Option byte loader reset flag [25:25] PINRSTF Pin reset flag [26:26] PWRRSTF BOR or POR/PDR flag [27:27] SFTRSTF Software reset flag [28:28] IWDGRSTF Independent window watchdog reset flag [29:29] WWDGRSTF Window watchdog reset flag [30:30] RTC desc RTC RTC 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 CRH desc CRH 0x0 SECIE desc SECIE [0:0] ALRIE desc ALRIE [1:1] OWIE desc OWIE [2:2] CRL desc CRL 0x4 0x20 SECF desc SECF [0:0] ALRF desc ALRF [1:1] OWF desc OWF [2:2] RSF desc RSF [3:3] CNF desc CNF [4:4] RTOFF desc RTOFF [5:5] read-only PRLH desc PRLH 0x8 write-only PRL desc PRL [3:0] write-only PRLL desc PRLL 0xC write-only 0x8000 PRL desc PRL [15:0] write-only DIVH desc DIVH 0x10 read-only DIV desc DIV [3:0] read-only DIVL desc DIVL 0x14 read-only 0x8000 DIV desc DIV [15:0] read-only CNTH desc CNTH 0x18 RTC_CNT desc RTC_CNT [15:0] CNTL desc CNTL 0x1C RTC_CNT desc RTC_CNT [15:0] ALRH desc ALRH 0x20 0xFFFF RTC_ALR desc RTC_ALR [15:0] ALRL desc ALRL 0x24 0xFFFF RTC_ALR desc RTC_ALR [15:0] BKP_RTCCR desc BKP_RTCCR 0x2C CAL desc CAL [6:0] CCO desc CCO [7:7] ASOE desc ASOE [8:8] ASOS desc ASOS [9:9] SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 desc CR1 0x0 CPHA desc CPHA [0:0] CPOL desc CPOL [1:1] MSTR desc MSTR [2:2] BR desc BR [5:3] SPE desc SPE [6:6] LSBFIRST desc LSBFIRST [7:7] SSI desc SSI [8:8] SSM desc SSM [9:9] RXONLY desc RXONLY [10:10] DDF desc DDF [11:11] CRCNEXT desc CRCNEXT [12:12] CRCEN desc CRCEN [13:13] BIDIOE desc BIDIOE [14:14] BIDIMODE desc BIDIMODE [15:15] CR2 desc CR2 0x4 RXDMAEN desc RXDMAEN [0:0] TXDMAEN desc TXDMAEN [1:1] SSOE desc SSOE [2:2] CLRTXFIFO desc CLRTXFIFO [4:4] ERRIE desc ERRIE [5:5] RXNEIE desc RXNEIE [6:6] TXEIE desc TXEIE [7:7] FRXTH desc FRXTH [12:12] LDMA_RX desc LDMA_RX [13:13] LDMA_TX desc LDMA_TX [14:14] SR desc SR 0x8 0x2 RXNE desc RXNE [0:0] read-only TXE desc TXE [1:1] read-only CHSIDE desc CHSIDE [2:2] read-only UDR desc UDR [3:3] read-only CRCERR desc CRCERR [4:4] MODF desc MODF [5:5] read-only OVR desc OVR [6:6] read-only BSY desc BSY [7:7] read-only FRLVL desc FRLVL [10:9] read-only FTLVL desc FTLVL [12:11] read-only DR desc DR 0xC DR desc DR [15:0] CRCPR desc CRCPR 0x10 0x7 CRCPOLY desc CRCPOLY [15:0] RXCRCR desc RXCRCR 0x14 read-only RXCRC desc RXCRC [15:0] read-only TXCRCR desc TXCRCR 0x18 read-only TXCRC desc TXCRC [15:0] read-only I2SCFGR desc I2SCFGR 0x1C CHLEN desc CHLEN [0:0] DATLEN desc DATLEN [2:1] CKPOL desc CKPOL [3:3] I2SSTD desc I2SSTD [5:4] PCMSYNC desc PCMSYNC [7:7] I2SCFG desc I2SCFG [9:8] I2SE desc I2SE [10:10] I2SMOD desc I2SMOD [11:11] I2SPR desc I2SPR 0x20 0x2 I2SDIV desc I2SDIV [7:0] ODD desc ODD [8:8] MCKOE desc MCKOE [9:9] SPI2 0x40003800 SPI2 SPI2 global Interrupt 26 SYSCFG desc SYSCFG SYSCFG 0x40010000 0x0 0x200 registers CFGR1 desc CFGR1 0x0 0xFF0000 MEM_MODE desc MEM_MODE [1:0] TIM1_IC1_SRC desc TIM1_IC1_SRC [3:2] TIM2_IC4_SRC desc TIM2_IC4_SRC [5:4] TIM3_IC1_SRC desc TIM3_IC1_SRC [7:6] ETR_SRC_TIM1 desc ETR_SRC_TIM1 [10:8] ETR_SRC_TIM2 desc ETR_SRC_TIM2 [14:12] ETR_SRC_TIM3 desc ETR_SRC_TIM3 [18:16] GPIO_AHB_SEL desc GPIO_AHB_SEL [24:24] CFGR2 desc CFGR2 0x4 0x4 LOCKUP_LOCK desc LOCKUP_LOCK [0:0] PVD_LOCK desc PVD_LOCK [2:2] COMP1_BRK_TIM1 desc COMP1_BRK_TIM1 [3:3] COMP2_BRK_TIM1 desc COMP2_BRK_TIM1 [4:4] COMP3_BRK_TIM1 desc COMP3_BRK_TIM1 [5:5] COMP1_BRK_TIM15 desc COMP1_BRK_TIM15 [6:6] COMP2_BRK_TIM15 desc COMP2_BRK_TIM15 [7:7] COMP3_BRK_TIM15 desc COMP3_BRK_TIM15 [8:8] COMP1_BRK_TIM16 desc COMP1_BRK_TIM16 [9:9] COMP2_BRK_TIM16 desc COMP2_BRK_TIM16 [10:10] COMP3_BRK_TIM16 desc COMP3_BRK_TIM16 [11:11] COMP1_BRK_TIM17 desc COMP1_BRK_TIM17 [12:12] COMP2_BRK_TIM17 desc COMP2_BRK_TIM17 [13:13] COMP3_BRK_TIM17 desc COMP3_BRK_TIM17 [14:14] COMP1_OCREF_CLR_TIM1 desc COMP1_OCREF_CLR_TIM1 [15:15] COMP1_OCREF_CLR_TIM2 desc COMP1_OCREF_CLR_TIM2 [16:16] COMP1_OCREF_CLR_TIM3 desc COMP1_OCREF_CLR_TIM3 [17:17] COMP2_OCREF_CLR_TIM1 desc COMP2_OCREF_CLR_TIM1 [18:18] COMP2_OCREF_CLR_TIM2 desc COMP2_OCREF_CLR_TIM2 [19:19] COMP2_OCREF_CLR_TIM3 desc COMP2_OCREF_CLR_TIM3 [20:20] COMP3_OCREF_CLR_TIM1 desc COMP3_OCREF_CLR_TIM1 [21:21] COMP3_OCREF_CLR_TIM2 desc COMP3_OCREF_CLR_TIM2 [22:22] COMP3_OCREF_CLR_TIM3 desc COMP3_OCREF_CLR_TIM3 [23:23] CFGR3 desc CFGR3 0x8 DMA1_MAP desc DMA1_MAP [5:0] DMA2_MAP desc DMA2_MAP [13:8] DMA3_MAP desc DMA3_MAP [21:16] DMA4_MAP desc DMA4_MAP [29:24] CFGR4 desc CFGR4 0xC DMA5_MAP desc DMA5_MAP [5:0] DMA6_MAP desc DMA6_MAP [13:8] DMA7_MAP desc DMA7_MAP [21:16] PAENS desc PAENS 0x10 PA_ENS desc PA_ENS [15:0] PBENS desc PBENS 0x14 PB_ENS desc PB_ENS [15:0] PCENS desc PCENS 0x18 PC_ENS desc PC_ENS [15:0] PFENS desc PFENS 0x1C PF_ENS desc PF_ENS [15:0] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0x7FFD CCPC desc CCPC [0:0] CCUS desc CCUS [2:2] CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] OIS1 desc OIS1 [8:8] OIS1N desc OIS1N [9:9] OIS2 desc OIS2 [10:10] OIS2N desc OIS2N [11:11] OIS3 desc OIS3 [12:12] OIS3N desc OIS3N [13:13] OIS4 desc OIS4 [14:14] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] OCCS desc OCCS [3:3] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] OC3FE desc OC3FE [2:2] OC3PE desc OC3PE [3:3] OC3M desc OC3M [6:4] OC3CE desc OC3CE [7:7] CC4S desc CC4S [9:8] OC4FE desc OC4FE [10:10] OC4PE desc OC4PE [11:11] OC4M desc OC4M [14:12] OC4CE desc OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] IC3PSC desc IC3PSC [3:2] IC3F desc IC3F [7:4] CC4S desc CC4S [9:8] IC4PSC desc IC4PSC [11:10] IC4F desc IC4F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NE desc CC1NE [2:2] CC1NP desc CC1NP [3:3] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC2NE desc CC2NE [6:6] CC2NP desc CC2NP [7:7] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC3NE desc CC3NE [10:10] CC3NP desc CC3NP [11:11] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] RCR desc RCR 0x30 0xFFFF 0xFFFF REP desc REP [7:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] CCR3 desc CCR3 0x3C 0xFFFF CCR3 desc CCR3 [15:0] CCR4 desc CCR4 0x40 0xFFFF CCR4 desc CCR4 [15:0] BDTR desc BDTR 0x44 0xFFFF DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM2 desc TIM TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global Interrupt 15 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] OC3FE desc OC3FE [2:2] OC3PE desc OC3PE [3:3] OC3M desc OC3M [6:4] OC3CE desc OC3CE [7:7] CC4S desc CC4S [9:8] OC4FE desc OC4FE [10:10] OC4PE desc OC4PE [11:11] OC4M desc OC4M [14:12] OC4CE desc OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] IC3PSC desc IC3PSC [3:2] IC3F desc IC3F [7:4] CC4S desc CC4S [9:8] IC4PSC desc IC4PSC [11:10] IC4F desc IC4F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CC4NP desc CC4NP [15:15] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] CCR3 desc CCR3 0x3C 0xFFFF CCR3 desc CCR3 [15:0] CCR4 desc CCR4 0x40 0xFFFF CCR4 desc CCR4 [15:0] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM3 desc TIM TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global Interrupt 16 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] OC3FE desc OC3FE [2:2] OC3PE desc OC3PE [3:3] OC3M desc OC3M [6:4] OC3CE desc OC3CE [7:7] CC4S desc CC4S [9:8] OC4FE desc OC4FE [10:10] OC4PE desc OC4PE [11:11] OC4M desc OC4M [14:12] OC4CE desc OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] IC3PSC desc IC3PSC [3:2] IC3F desc IC3F [7:4] CC4S desc CC4S [9:8] IC4PSC desc IC4PSC [11:10] IC4F desc IC4F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CC4NP desc CC4NP [15:15] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] CCR3 desc CCR3 0x3C 0xFFFF CCR3 desc CCR3 [15:0] CCR4 desc CCR4 0x40 0xFFFF CCR4 desc CCR4 [15:0] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM6 desc TIM TIM 0x40001000 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] TIM7 desc TIM TIM 0x40001400 0x0 0x400 registers TIM7 TIM7 global Interrupt 18 TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] TIF desc TIF [6:6] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NP desc CC1NP [3:3] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] OR desc OR 0x50 TI1_RMP desc TI1_RMP [1:0] TIM15 0x40014000 0x0 0x400 registers TIM15 TIM15 global Interrupt 20 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NE desc CC1NE [2:2] CC1NP desc CC1NP [3:3] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC2NP desc CC2NP [7:7] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] RCR desc RCR 0x30 0xFFFF 0xFFFF REP desc REP [7:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] BDTR desc BDTR 0x44 0xFFFF DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM16 General purpose timer TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global Interrupt 21 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NE desc CC1NE [2:2] CC1NP desc CC1NP [3:3] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] RCR desc RCR 0x30 0xFFFF 0xFFFF REP desc REP [7:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] BDTR desc BDTR 0x44 0xFFFF DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM17 0x40014800 TIM17 TIM17 global Interrupt 22 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR desc SR 0x0 0xC0 PE desc PE [0:0] read-only FE desc FE [1:1] read-only NE desc NE [2:2] read-only ORE desc ORE [3:3] read-only IDLE desc IDLE [4:4] read-only RXNE desc RXNE [5:5] TC desc TC [6:6] TXE desc TXE [7:7] read-only LBD desc LBD [8:8] CTS desc CTS [9:9] ABRF desc ABRF [10:10] read-only ABRE desc ABRE [11:11] read-only ABRRQ desc ABRRQ [12:12] write-only DR desc DR 0x4 DR desc DR [8:0] BRR desc BRR 0x8 DIV_FRACTION desc DIV_Fraction [3:0] DIV_MANTISSA desc DIV_Mantissa [15:4] CR1 desc CR1 0xC SBK desc SBK [0:0] RWU desc RWU [1:1] RE desc RE [2:2] TE desc TE [3:3] IDLEIE desc IDLEIE [4:4] RXNEIE desc RXNEIE [5:5] TCIE desc TCIE [6:6] TXEIE desc TXEIE [7:7] PEIE desc PEIE [8:8] PS desc PS [9:9] PCE desc PCE [10:10] WAKE desc WAKE [11:11] M desc M [12:12] UE desc UE [13:13] CR2 desc CR2 0x10 ADD desc ADD [3:0] LBDL desc LBDL [5:5] LBDIE desc LBDIE [6:6] LBCL desc LBCL [8:8] CPHA desc CPHA [9:9] CPOL desc CPOL [10:10] CLKEN desc CLKEN [11:11] STOP desc STOP [13:12] LINEN desc LINEN [14:14] CR3 desc CR3 0x14 EIE desc EIE [0:0] IREN desc IREN [1:1] IRLP desc IRLP [2:2] HDSEL desc HDSEL [3:3] NACK desc NACK [4:4] SCEN desc SCEN [5:5] DMAR desc DMAR [6:6] DMAT desc DMAT [7:7] RTSE desc RTSE [8:8] CTSE desc CTSE [9:9] CTSIE desc CTSIE [10:10] OVER8 desc OVER8 [11:11] ABREN desc ABREN [12:12] ABRMODE desc ABRMODE [14:13] GTPR desc GTPR 0x18 PSC desc PSC [7:0] GT desc GT [15:8] USART2 0x40004400 USART2 USART2 global Interrupt 28 USART3 desc USART USART 0x40004800 0x0 0x400 registers USART3_4 USART3, 4 global Interrupts 29 USART4 desc USART USART 0x40004C00 0x0 0x400 registers USART3_4 USART3, 4 global Interrupts 29 USB USB USB 0x40005C00 0x0 0x400 registers USB USB global Interrupts 31 CR CR CR 0x0 0xFFFFFFFF ADD ADD [6:0] UPDATE UPDATE [7:7] Enable_Suspend Enable_Suspend [8:8] Suspend_Mode Suspend_Mode [9:9] Resume Resume [10:10] Reset Reset [11:11] ISO_Update ISO_Update [15:15] INTR INTR INTR 0x4 Suspend Suspend [0:0] Resume Resume [1:1] Reset Reset [2:2] SOF SOF [3:3] EP1OUT EP1OUT [9:9] EP2OUT EP2OUT [10:10] EP3OUT EP3OUT [11:11] EP4OUT EP4OUT [12:12] EP5OUT EP5OUT [13:13] EP0 EP0 [16:16] EP1IN EP1IN [17:17] EP2IN EP2IN [18:18] EP3IN EP3IN [19:19] EP4IN EP4IN [20:20] EP5IN EP5IN [21:21] INTRE INTRE INTRE 0x8 EN_Suspend EN_Suspend [0:0] EN_Resume EN_Resume [1:1] EN_Reset EN_Reset [2:2] EN_SOF EN_SOF [3:3] EP1OUTE EP1OUTE [9:9] EP2OUTE EP2OUTE [10:10] EP3OUTE EP3OUTE [11:11] EP4OUTE EP4OUTE [12:12] EP5OUTE EP5OUTE [13:13] EP0 EP0 [16:16] EP1INE EP1INE [17:17] EP2INE EP2INE [18:18] EP3INE EP3INE [19:19] EP4INE EP4INE [20:20] EP5INE EP5INE [21:21] FRAME FRAME FRAME 0xC write-only FramNUM FramNUM [10:0] INDEX INDEX [19:16] EP0CSR EP0CSR EP0CSR 0x10 write-only OutPktRdy OutPktRdy [0:0] InPktRdy InPktRdy [1:1] SentStall SentStall [2:2] DataEnd DataEnd [3:3] SetupEnd SetupEnd [4:4] SendStall OutPktRdy [5:5] ServicedOutPktRdy ServicedOutPktRdy [6:6] ServicedSetupEnd ServicedSetupEnd [7:7] COUNT0 COUNT0 [8:8] INEPxCSR INEPxCSR INEPxCSR 0x14 write-only FrcDataTog FrcDataTog [3:3] DMAEnab DMAEnab [4:4] Mode Mode [5:5] ISO ISO [6:6] AutoSet AutoSet [7:7] InPktRdy InPktRdy [8:8] FIFONotEmpty FIFONotEmpty [9:9] UnderRun UnderRun [10:10] FlushFIFO FlushFIFO [11:11] SendStall SendStall [12:12] SentStall SentStall [13:13] ClrDataTog ClrDataTog [14:14] INMAXP INMAXP [16:16] OUTEPxCSR OUTEPxCSR OUTEPxCSR 0x18 write-only DMAMode DMAMode [4:4] DMAEnab DMAEnab [5:5] ISO ISO [6:6] AutoClear AutoClear [7:7] OutPktRdy OutPktRdy [8:8] FIFOFull FIFOFull [9:9] OverRun OverRun [10:10] DataError DataError [11:11] FlushFIFO FlushFIFO [12:12] SendStall SendStall [13:13] SentStall SentStall [14:14] ClrDataTog ClrDataTog [15:15] INMAXP INMAXP [16:16] OUTCOUNT OUTCOUNT OUTCOUNT 0x1C write-only OUTCOUNT OUTCOUNT [9:0] WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window WatchDog Interrupt 0 CR CR Control register (WWDG_CR) 0x0 0x7F T 7-bit counter (MSB to LSB) [6:0] WDGA Activation bit [7:7] CFR CFR Configuration register (WWDG_CFR) 0x4 0x7F W 7-bit window value [6:0] WDGTB Timer Base [8:7] EWI Early Wakeup Interrupt [9:9] SR SR Status register (WWDG_SR) 0x8 EWIF Early Wakeup Interrupt flag [0:0]