/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F021xx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:15:00 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F021xx.svd',
* last modified on Sat Oct 11 17:45:45 2025
*/
// ----------------------------- Register Item Address: ADC_ISR ---------------------------------
// SVD Line: 41
unsigned int ADC_ISR __AT (0x40012400);
// -------------------------------- Field Item: ADC_ISR_EOSMP -----------------------------------
// SVD Line: 47
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// EOSMP
//
// [Bit 1] RW (@ 0x40012400) ADC group regular end of sampling flag
//
// ( (unsigned int) ADC_ISR )
// EOSMP
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOC ------------------------------------
// SVD Line: 52
// - SFDITEM_FIELD__ADC_ISR_EOC
// EOC
//
// [Bit 2] RW (@ 0x40012400) ADC group regular end of unitary conversion flag
//
// ( (unsigned int) ADC_ISR )
// EOC
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOSEQ -----------------------------------
// SVD Line: 57
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// EOSEQ
//
// [Bit 3] RW (@ 0x40012400) ADC group regular end of sequence conversions flag
//
// ( (unsigned int) ADC_ISR )
// EOSEQ
//
//
//
// --------------------------------- Field Item: ADC_ISR_OVR ------------------------------------
// SVD Line: 62
// - SFDITEM_FIELD__ADC_ISR_OVR
// OVR
//
// [Bit 4] RW (@ 0x40012400) ADC group regular overrun flag
//
// ( (unsigned int) ADC_ISR )
// OVR
//
//
//
// --------------------------------- Field Item: ADC_ISR_AWD ------------------------------------
// SVD Line: 67
// - SFDITEM_FIELD__ADC_ISR_AWD
// AWD
//
// [Bit 7] RW (@ 0x40012400) ADC analog watchdog flag
//
// ( (unsigned int) ADC_ISR )
// AWD
//
//
//
// --------------------------------- Register RTree: ADC_ISR ------------------------------------
// SVD Line: 41
// SFDITEM_REG__ADC_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40012400) ADC interrupt and status register
// ( (unsigned int)((ADC_ISR >> 0) & 0xFFFFFFFF), ((ADC_ISR = (ADC_ISR & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// - SFDITEM_FIELD__ADC_ISR_EOC
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// - SFDITEM_FIELD__ADC_ISR_OVR
// - SFDITEM_FIELD__ADC_ISR_AWD
//
//
// ----------------------------- Register Item Address: ADC_IER ---------------------------------
// SVD Line: 74
unsigned int ADC_IER __AT (0x40012404);
// ------------------------------- Field Item: ADC_IER_EOSMPIE ----------------------------------
// SVD Line: 80
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// EOSMPIE
//
// [Bit 1] RW (@ 0x40012404) ADC group regular end of sampling interrupt
//
// ( (unsigned int) ADC_IER )
// EOSMPIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOCIE -----------------------------------
// SVD Line: 85
// - SFDITEM_FIELD__ADC_IER_EOCIE
// EOCIE
//
// [Bit 2] RW (@ 0x40012404) ADC group regular end of unitary conversion interrupt
//
// ( (unsigned int) ADC_IER )
// EOCIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOSEQIE ----------------------------------
// SVD Line: 90
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// EOSEQIE
//
// [Bit 3] RW (@ 0x40012404) ADC group regular end of sequence conversions interrupt
//
// ( (unsigned int) ADC_IER )
// EOSEQIE
//
//
//
// -------------------------------- Field Item: ADC_IER_OVRIE -----------------------------------
// SVD Line: 95
// - SFDITEM_FIELD__ADC_IER_OVRIE
// OVRIE
//
// [Bit 4] RW (@ 0x40012404) ADC group regular overrun interrupt
//
// ( (unsigned int) ADC_IER )
// OVRIE
//
//
//
// -------------------------------- Field Item: ADC_IER_AWDIE -----------------------------------
// SVD Line: 100
// - SFDITEM_FIELD__ADC_IER_AWDIE
// AWDIE
//
// [Bit 7] RW (@ 0x40012404) ADC analog watchdog interrupt
//
// ( (unsigned int) ADC_IER )
// AWDIE
//
//
//
// --------------------------------- Register RTree: ADC_IER ------------------------------------
// SVD Line: 74
// SFDITEM_REG__ADC_IER
// IER
//
// [Bits 31..0] RW (@ 0x40012404) ADC interrupt enable register
// ( (unsigned int)((ADC_IER >> 0) & 0xFFFFFFFF), ((ADC_IER = (ADC_IER & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// - SFDITEM_FIELD__ADC_IER_EOCIE
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// - SFDITEM_FIELD__ADC_IER_OVRIE
// - SFDITEM_FIELD__ADC_IER_AWDIE
//
//
// ------------------------------ Register Item Address: ADC_CR ---------------------------------
// SVD Line: 107
unsigned int ADC_CR __AT (0x40012408);
// --------------------------------- Field Item: ADC_CR_ADEN ------------------------------------
// SVD Line: 113
// - SFDITEM_FIELD__ADC_CR_ADEN
// ADEN
//
// [Bit 0] RW (@ 0x40012408) ADC enable
//
// ( (unsigned int) ADC_CR )
// ADEN
//
//
//
// -------------------------------- Field Item: ADC_CR_ADDIS ------------------------------------
// SVD Line: 118
// - SFDITEM_FIELD__ADC_CR_ADDIS
// ADDIS
//
// [Bit 1] RW (@ 0x40012408) ADC disable
//
// ( (unsigned int) ADC_CR )
// ADDIS
//
//
//
// ------------------------------- Field Item: ADC_CR_ADSTART -----------------------------------
// SVD Line: 123
// - SFDITEM_FIELD__ADC_CR_ADSTART
// ADSTART
//
// [Bit 2] RW (@ 0x40012408) ADC group regular conversion start
//
// ( (unsigned int) ADC_CR )
// ADSTART
//
//
//
// -------------------------------- Field Item: ADC_CR_MSBSEL -----------------------------------
// SVD Line: 128
// - SFDITEM_FIELD__ADC_CR_MSBSEL
// MSBSEL
//
// [Bit 3] RW (@ 0x40012408) ADC resolution highest bit conversion time control
//
// ( (unsigned int) ADC_CR )
// MSBSEL
//
//
//
// -------------------------------- Field Item: ADC_CR_ADSTP ------------------------------------
// SVD Line: 133
// - SFDITEM_FIELD__ADC_CR_ADSTP
// ADSTP
//
// [Bit 4] RW (@ 0x40012408) ADC group regular conversion stop
//
// ( (unsigned int) ADC_CR )
// ADSTP
//
//
//
// ------------------------------ Field Item: ADC_CR_VREFBUF_EN ---------------------------------
// SVD Line: 138
// - SFDITEM_FIELD__ADC_CR_VREFBUF_EN
// VREFBUF_EN
//
// [Bit 5] RW (@ 0x40012408) ADC VrefBuffer enable
//
// ( (unsigned int) ADC_CR )
// VREFBUF_EN
//
//
//
// ----------------------------- Field Item: ADC_CR_VREFBUF_SEL ---------------------------------
// SVD Line: 143
// - SFDITEM_FIELD__ADC_CR_VREFBUF_SEL
// VREFBUF_SEL
//
// [Bits 7..6] RW (@ 0x40012408) ADC VrefBuffer output voltage select
//
// ( (unsigned char)((ADC_CR >> 6) & 0x3), ((ADC_CR = (ADC_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_CR_ADCAL ------------------------------------
// SVD Line: 148
// - SFDITEM_FIELD__ADC_CR_ADCAL
// ADCAL
//
// [Bit 31] RW (@ 0x40012408) ADC group regular conversion calibration
//
// ( (unsigned int) ADC_CR )
// ADCAL
//
//
//
// --------------------------------- Register RTree: ADC_CR -------------------------------------
// SVD Line: 107
// SFDITEM_REG__ADC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40012408) ADC control register
// ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0x800000FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800000FF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CR_ADEN
// - SFDITEM_FIELD__ADC_CR_ADDIS
// - SFDITEM_FIELD__ADC_CR_ADSTART
// - SFDITEM_FIELD__ADC_CR_MSBSEL
// - SFDITEM_FIELD__ADC_CR_ADSTP
// - SFDITEM_FIELD__ADC_CR_VREFBUF_EN
// - SFDITEM_FIELD__ADC_CR_VREFBUF_SEL
// - SFDITEM_FIELD__ADC_CR_ADCAL
//
//
// ---------------------------- Register Item Address: ADC_CFGR1 --------------------------------
// SVD Line: 155
unsigned int ADC_CFGR1 __AT (0x4001240C);
// ------------------------------- Field Item: ADC_CFGR1_DMAEN ----------------------------------
// SVD Line: 161
// - SFDITEM_FIELD__ADC_CFGR1_DMAEN
// DMAEN
//
// [Bit 0] RW (@ 0x4001240C) ADC DMA transfer enable
//
// ( (unsigned int) ADC_CFGR1 )
// DMAEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_DMACFG ----------------------------------
// SVD Line: 166
// - SFDITEM_FIELD__ADC_CFGR1_DMACFG
// DMACFG
//
// [Bit 1] RW (@ 0x4001240C) ADC DMA transfer configuration
//
// ( (unsigned int) ADC_CFGR1 )
// DMACFG
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_SCANDIR ---------------------------------
// SVD Line: 171
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// SCANDIR
//
// [Bit 2] RW (@ 0x4001240C) Scan sequence direction
//
// ( (unsigned int) ADC_CFGR1 )
// SCANDIR
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_RESSEL ----------------------------------
// SVD Line: 176
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// RESSEL
//
// [Bits 4..3] RW (@ 0x4001240C) ADC data resolution
//
// ( (unsigned char)((ADC_CFGR1 >> 3) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_ALIGN ----------------------------------
// SVD Line: 181
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// ALIGN
//
// [Bit 5] RW (@ 0x4001240C) ADC data alignement
//
// ( (unsigned int) ADC_CFGR1 )
// ALIGN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_EXTSEL ----------------------------------
// SVD Line: 186
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// EXTSEL
//
// [Bits 8..6] RW (@ 0x4001240C) ADC group regular external trigger source
//
// ( (unsigned char)((ADC_CFGR1 >> 6) & 0x7), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_EXTEN ----------------------------------
// SVD Line: 191
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// EXTEN
//
// [Bits 11..10] RW (@ 0x4001240C) ADC group regular external trigger polarity
//
// ( (unsigned char)((ADC_CFGR1 >> 10) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_OVRMOD ----------------------------------
// SVD Line: 196
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// OVRMOD
//
// [Bit 12] RW (@ 0x4001240C) ADC group regular overrun configuration
//
// ( (unsigned int) ADC_CFGR1 )
// OVRMOD
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_CONT -----------------------------------
// SVD Line: 201
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// CONT
//
// [Bit 13] RW (@ 0x4001240C) ADC group regular continuous conversion mode
//
// ( (unsigned int) ADC_CFGR1 )
// CONT
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_WAIT -----------------------------------
// SVD Line: 206
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// WAIT
//
// [Bit 14] RW (@ 0x4001240C) Wait conversion mode
//
// ( (unsigned int) ADC_CFGR1 )
// WAIT
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_DISCEN ----------------------------------
// SVD Line: 211
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// DISCEN
//
// [Bit 16] RW (@ 0x4001240C) ADC group regular sequencer discontinuous mode
//
// ( (unsigned int) ADC_CFGR1 )
// DISCEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_AWDSGL ----------------------------------
// SVD Line: 216
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// AWDSGL
//
// [Bit 22] RW (@ 0x4001240C) ADC analog watchdog monitoring a single channel or all channels
//
// ( (unsigned int) ADC_CFGR1 )
// AWDSGL
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDEN ----------------------------------
// SVD Line: 221
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// AWDEN
//
// [Bit 23] RW (@ 0x4001240C) ADC analog watchdog enable on scope ADC group regular
//
// ( (unsigned int) ADC_CFGR1 )
// AWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDCH ----------------------------------
// SVD Line: 226
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
// AWDCH
//
// [Bits 29..26] RW (@ 0x4001240C) ADC analog watchdog monitored channel selection
//
// ( (unsigned char)((ADC_CFGR1 >> 26) & 0xF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR1 -----------------------------------
// SVD Line: 155
// SFDITEM_REG__ADC_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x4001240C) ADC configuration register 1
// ( (unsigned int)((ADC_CFGR1 >> 0) & 0xFFFFFFFF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3CC17DFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CC17DFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR1_DMAEN
// - SFDITEM_FIELD__ADC_CFGR1_DMACFG
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
//
//
// ---------------------------- Register Item Address: ADC_CFGR2 --------------------------------
// SVD Line: 233
unsigned int ADC_CFGR2 __AT (0x40012410);
// ------------------------------ Field Item: ADC_CFGR2_CKMODE ----------------------------------
// SVD Line: 239
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
// CKMODE
//
// [Bits 31..28] RW (@ 0x40012410) ADC clock mode
//
// ( (unsigned char)((ADC_CFGR2 >> 28) & 0xF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR2 -----------------------------------
// SVD Line: 233
// SFDITEM_REG__ADC_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40012410) ADC configuration register 2
// ( (unsigned int)((ADC_CFGR2 >> 0) & 0xFFFFFFFF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xF0000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0000000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
//
//
// ---------------------------- Register Item Address: ADC_SMPR0 --------------------------------
// SVD Line: 246
unsigned int ADC_SMPR0 __AT (0x40012414);
// ------------------------------- Field Item: ADC_SMPR0_SMP0 -----------------------------------
// SVD Line: 252
// - SFDITEM_FIELD__ADC_SMPR0_SMP0
// SMP0
//
// [Bits 2..0] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 0) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP1 -----------------------------------
// SVD Line: 257
// - SFDITEM_FIELD__ADC_SMPR0_SMP1
// SMP1
//
// [Bits 5..3] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 3) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP2 -----------------------------------
// SVD Line: 262
// - SFDITEM_FIELD__ADC_SMPR0_SMP2
// SMP2
//
// [Bits 8..6] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 6) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP3 -----------------------------------
// SVD Line: 267
// - SFDITEM_FIELD__ADC_SMPR0_SMP3
// SMP3
//
// [Bits 11..9] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 9) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP4 -----------------------------------
// SVD Line: 272
// - SFDITEM_FIELD__ADC_SMPR0_SMP4
// SMP4
//
// [Bits 14..12] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 12) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP5 -----------------------------------
// SVD Line: 277
// - SFDITEM_FIELD__ADC_SMPR0_SMP5
// SMP5
//
// [Bits 17..15] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 15) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 15 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 15 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP6 -----------------------------------
// SVD Line: 282
// - SFDITEM_FIELD__ADC_SMPR0_SMP6
// SMP6
//
// [Bits 20..18] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 18) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 18 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP7 -----------------------------------
// SVD Line: 287
// - SFDITEM_FIELD__ADC_SMPR0_SMP7
// SMP7
//
// [Bits 23..21] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 21) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 21 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 21 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP8 -----------------------------------
// SVD Line: 292
// - SFDITEM_FIELD__ADC_SMPR0_SMP8
// SMP8
//
// [Bits 26..24] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 24) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR0_SMP9 -----------------------------------
// SVD Line: 297
// - SFDITEM_FIELD__ADC_SMPR0_SMP9
// SMP9
//
// [Bits 29..27] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR0 >> 27) & 0x7), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x7UL << 27 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 27 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR0 -----------------------------------
// SVD Line: 246
// SFDITEM_REG__ADC_SMPR0
// SMPR0
//
// [Bits 31..0] RW (@ 0x40012414) ADC sampling time register 0
// ( (unsigned int)((ADC_SMPR0 >> 0) & 0xFFFFFFFF), ((ADC_SMPR0 = (ADC_SMPR0 & ~(0x3FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR0_SMP0
// - SFDITEM_FIELD__ADC_SMPR0_SMP1
// - SFDITEM_FIELD__ADC_SMPR0_SMP2
// - SFDITEM_FIELD__ADC_SMPR0_SMP3
// - SFDITEM_FIELD__ADC_SMPR0_SMP4
// - SFDITEM_FIELD__ADC_SMPR0_SMP5
// - SFDITEM_FIELD__ADC_SMPR0_SMP6
// - SFDITEM_FIELD__ADC_SMPR0_SMP7
// - SFDITEM_FIELD__ADC_SMPR0_SMP8
// - SFDITEM_FIELD__ADC_SMPR0_SMP9
//
//
// ---------------------------- Register Item Address: ADC_SMPR1 --------------------------------
// SVD Line: 304
unsigned int ADC_SMPR1 __AT (0x40012418);
// ------------------------------- Field Item: ADC_SMPR1_SMP10 ----------------------------------
// SVD Line: 310
// - SFDITEM_FIELD__ADC_SMPR1_SMP10
// SMP10
//
// [Bits 2..0] RW (@ 0x40012418) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR1 >> 0) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP11 ----------------------------------
// SVD Line: 315
// - SFDITEM_FIELD__ADC_SMPR1_SMP11
// SMP11
//
// [Bits 5..3] RW (@ 0x40012418) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR1 >> 3) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP12 ----------------------------------
// SVD Line: 320
// - SFDITEM_FIELD__ADC_SMPR1_SMP12
// SMP12
//
// [Bits 8..6] RW (@ 0x40012418) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR1 >> 6) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP13 ----------------------------------
// SVD Line: 325
// - SFDITEM_FIELD__ADC_SMPR1_SMP13
// SMP13
//
// [Bits 11..9] RW (@ 0x40012418) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR1 >> 9) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP14 ----------------------------------
// SVD Line: 330
// - SFDITEM_FIELD__ADC_SMPR1_SMP14
// SMP14
//
// [Bits 14..12] RW (@ 0x40012418) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR1 >> 12) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR1 -----------------------------------
// SVD Line: 304
// SFDITEM_REG__ADC_SMPR1
// SMPR1
//
// [Bits 31..0] RW (@ 0x40012418) ADC sampling time register 1
// ( (unsigned int)((ADC_SMPR1 >> 0) & 0xFFFFFFFF), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR1_SMP10
// - SFDITEM_FIELD__ADC_SMPR1_SMP11
// - SFDITEM_FIELD__ADC_SMPR1_SMP12
// - SFDITEM_FIELD__ADC_SMPR1_SMP13
// - SFDITEM_FIELD__ADC_SMPR1_SMP14
//
//
// ------------------------------ Register Item Address: ADC_TR ---------------------------------
// SVD Line: 337
unsigned int ADC_TR __AT (0x40012420);
// ---------------------------------- Field Item: ADC_TR_LT -------------------------------------
// SVD Line: 344
// - SFDITEM_FIELD__ADC_TR_LT
// LT
//
// [Bits 11..0] RW (@ 0x40012420) ADC analog watchdog threshold low
//
// ( (unsigned short)((ADC_TR >> 0) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ---------------------------------- Field Item: ADC_TR_HT -------------------------------------
// SVD Line: 349
// - SFDITEM_FIELD__ADC_TR_HT
// HT
//
// [Bits 27..16] RW (@ 0x40012420) ADC analog watchdog threshold high
//
// ( (unsigned short)((ADC_TR >> 16) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_TR -------------------------------------
// SVD Line: 337
// SFDITEM_REG__ADC_TR
// TR
//
// [Bits 31..0] RW (@ 0x40012420) ADC analog watchdog 1 threshold register
// ( (unsigned int)((ADC_TR >> 0) & 0xFFFFFFFF), ((ADC_TR = (ADC_TR & ~(0xFFF0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF0FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_TR_LT
// - SFDITEM_FIELD__ADC_TR_HT
//
//
// ---------------------------- Register Item Address: ADC_CHSELR -------------------------------
// SVD Line: 356
unsigned int ADC_CHSELR __AT (0x40012424);
// ------------------------------ Field Item: ADC_CHSELR_CHSEL0 ---------------------------------
// SVD Line: 363
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL0
// CHSEL0
//
// [Bit 0] RW (@ 0x40012424) Channel-0 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL0
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL1 ---------------------------------
// SVD Line: 368
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL1
// CHSEL1
//
// [Bit 1] RW (@ 0x40012424) Channel-1 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL1
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL2 ---------------------------------
// SVD Line: 373
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL2
// CHSEL2
//
// [Bit 2] RW (@ 0x40012424) Channel-2 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL2
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL3 ---------------------------------
// SVD Line: 378
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL3
// CHSEL3
//
// [Bit 3] RW (@ 0x40012424) Channel-3 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL3
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL4 ---------------------------------
// SVD Line: 383
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL4
// CHSEL4
//
// [Bit 4] RW (@ 0x40012424) Channel-4 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL4
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL5 ---------------------------------
// SVD Line: 388
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL5
// CHSEL5
//
// [Bit 5] RW (@ 0x40012424) Channel-5 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL5
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL6 ---------------------------------
// SVD Line: 393
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL6
// CHSEL6
//
// [Bit 6] RW (@ 0x40012424) Channel-6 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL6
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL7 ---------------------------------
// SVD Line: 398
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL7
// CHSEL7
//
// [Bit 7] RW (@ 0x40012424) Channel-7 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL7
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL8 ---------------------------------
// SVD Line: 403
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL8
// CHSEL8
//
// [Bit 8] RW (@ 0x40012424) Channel-8 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL8
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL9 ---------------------------------
// SVD Line: 408
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL9
// CHSEL9
//
// [Bit 9] RW (@ 0x40012424) Channel-9 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL9
//
//
//
// ----------------------------- Field Item: ADC_CHSELR_CHSEL10 ---------------------------------
// SVD Line: 413
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL10
// CHSEL10
//
// [Bit 10] RW (@ 0x40012424) Channel-10 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL10
//
//
//
// ----------------------------- Field Item: ADC_CHSELR_CHSEL11 ---------------------------------
// SVD Line: 418
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL11
// CHSEL11
//
// [Bit 11] RW (@ 0x40012424) Channel-11 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL11
//
//
//
// ----------------------------- Field Item: ADC_CHSELR_CHSEL12 ---------------------------------
// SVD Line: 423
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL12
// CHSEL12
//
// [Bit 12] RW (@ 0x40012424) Channel-12 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL12
//
//
//
// ----------------------------- Field Item: ADC_CHSELR_CHSEL13 ---------------------------------
// SVD Line: 428
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL13
// CHSEL13
//
// [Bit 13] RW (@ 0x40012424) Channel-13 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL13
//
//
//
// ----------------------------- Field Item: ADC_CHSELR_CHSEL14 ---------------------------------
// SVD Line: 433
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL14
// CHSEL14
//
// [Bit 14] RW (@ 0x40012424) Channel-14 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL14
//
//
//
// ------------------------------- Register RTree: ADC_CHSELR -----------------------------------
// SVD Line: 356
// SFDITEM_REG__ADC_CHSELR
// CHSELR
//
// [Bits 31..0] RW (@ 0x40012424) ADC group regular sequencer register
// ( (unsigned int)((ADC_CHSELR >> 0) & 0xFFFFFFFF), ((ADC_CHSELR = (ADC_CHSELR & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL0
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL1
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL2
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL3
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL4
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL5
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL6
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL7
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL8
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL9
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL10
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL11
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL12
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL13
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL14
//
//
// ---------------------------- Register Item Address: ADC_SEQR0 --------------------------------
// SVD Line: 440
unsigned int ADC_SEQR0 __AT (0x40012428);
// -------------------------------- Field Item: ADC_SEQR0_SQ0 -----------------------------------
// SVD Line: 446
// - SFDITEM_FIELD__ADC_SEQR0_SQ0
// SQ0
//
// [Bits 3..0] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 0) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ1 -----------------------------------
// SVD Line: 451
// - SFDITEM_FIELD__ADC_SEQR0_SQ1
// SQ1
//
// [Bits 7..4] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 4) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ2 -----------------------------------
// SVD Line: 456
// - SFDITEM_FIELD__ADC_SEQR0_SQ2
// SQ2
//
// [Bits 11..8] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 8) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ3 -----------------------------------
// SVD Line: 461
// - SFDITEM_FIELD__ADC_SEQR0_SQ3
// SQ3
//
// [Bits 15..12] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 12) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ4 -----------------------------------
// SVD Line: 466
// - SFDITEM_FIELD__ADC_SEQR0_SQ4
// SQ4
//
// [Bits 19..16] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 16) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ5 -----------------------------------
// SVD Line: 471
// - SFDITEM_FIELD__ADC_SEQR0_SQ5
// SQ5
//
// [Bits 23..20] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 20) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ6 -----------------------------------
// SVD Line: 476
// - SFDITEM_FIELD__ADC_SEQR0_SQ6
// SQ6
//
// [Bits 27..24] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 24) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR0_SQ7 -----------------------------------
// SVD Line: 481
// - SFDITEM_FIELD__ADC_SEQR0_SQ7
// SQ7
//
// [Bits 31..28] RW (@ 0x40012428) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR0 >> 28) & 0xF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SEQR0 -----------------------------------
// SVD Line: 440
// SFDITEM_REG__ADC_SEQR0
// SEQR0
//
// [Bits 31..0] RW (@ 0x40012428) ADC sequence select register 0
// ( (unsigned int)((ADC_SEQR0 >> 0) & 0xFFFFFFFF), ((ADC_SEQR0 = (ADC_SEQR0 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SEQR0_SQ0
// - SFDITEM_FIELD__ADC_SEQR0_SQ1
// - SFDITEM_FIELD__ADC_SEQR0_SQ2
// - SFDITEM_FIELD__ADC_SEQR0_SQ3
// - SFDITEM_FIELD__ADC_SEQR0_SQ4
// - SFDITEM_FIELD__ADC_SEQR0_SQ5
// - SFDITEM_FIELD__ADC_SEQR0_SQ6
// - SFDITEM_FIELD__ADC_SEQR0_SQ7
//
//
// ---------------------------- Register Item Address: ADC_SEQR1 --------------------------------
// SVD Line: 488
unsigned int ADC_SEQR1 __AT (0x4001242C);
// -------------------------------- Field Item: ADC_SEQR1_SQ8 -----------------------------------
// SVD Line: 494
// - SFDITEM_FIELD__ADC_SEQR1_SQ8
// SQ8
//
// [Bits 3..0] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 0) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SEQR1_SQ9 -----------------------------------
// SVD Line: 499
// - SFDITEM_FIELD__ADC_SEQR1_SQ9
// SQ9
//
// [Bits 7..4] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 4) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SEQR1_SQ10 -----------------------------------
// SVD Line: 504
// - SFDITEM_FIELD__ADC_SEQR1_SQ10
// SQ10
//
// [Bits 11..8] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 8) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SEQR1_SQ11 -----------------------------------
// SVD Line: 509
// - SFDITEM_FIELD__ADC_SEQR1_SQ11
// SQ11
//
// [Bits 15..12] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 12) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SEQR1_SQ12 -----------------------------------
// SVD Line: 514
// - SFDITEM_FIELD__ADC_SEQR1_SQ12
// SQ12
//
// [Bits 19..16] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 16) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SEQR1_SQ13 -----------------------------------
// SVD Line: 519
// - SFDITEM_FIELD__ADC_SEQR1_SQ13
// SQ13
//
// [Bits 23..20] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 20) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SEQR1_SQ14 -----------------------------------
// SVD Line: 524
// - SFDITEM_FIELD__ADC_SEQR1_SQ14
// SQ14
//
// [Bits 27..24] RW (@ 0x4001242C) ADC sequence select
//
// ( (unsigned char)((ADC_SEQR1 >> 24) & 0xF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SEQR1 -----------------------------------
// SVD Line: 488
// SFDITEM_REG__ADC_SEQR1
// SEQR1
//
// [Bits 31..0] RW (@ 0x4001242C) ADC sequence select register 1
// ( (unsigned int)((ADC_SEQR1 >> 0) & 0xFFFFFFFF), ((ADC_SEQR1 = (ADC_SEQR1 & ~(0xFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SEQR1_SQ8
// - SFDITEM_FIELD__ADC_SEQR1_SQ9
// - SFDITEM_FIELD__ADC_SEQR1_SQ10
// - SFDITEM_FIELD__ADC_SEQR1_SQ11
// - SFDITEM_FIELD__ADC_SEQR1_SQ12
// - SFDITEM_FIELD__ADC_SEQR1_SQ13
// - SFDITEM_FIELD__ADC_SEQR1_SQ14
//
//
// ------------------------------ Register Item Address: ADC_DR ---------------------------------
// SVD Line: 531
unsigned int ADC_DR __AT (0x40012440);
// --------------------------------- Field Item: ADC_DR_DATA ------------------------------------
// SVD Line: 538
// - SFDITEM_FIELD__ADC_DR_DATA
// DATA
//
// [Bits 15..0] RO (@ 0x40012440) ADC group regular conversion data
//
// ( (unsigned short)((ADC_DR >> 0) & 0xFFFF) )
//
//
//
// --------------------------------- Register RTree: ADC_DR -------------------------------------
// SVD Line: 531
// SFDITEM_REG__ADC_DR
// DR
//
// [Bits 31..0] RO (@ 0x40012440) ADC group regular data register
// ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_DR_DATA
//
//
// ----------------------------- Register Item Address: ADC_CCSR --------------------------------
// SVD Line: 545
unsigned int ADC_CCSR __AT (0x40012444);
// ------------------------------- Field Item: ADC_CCSR_CALSEL ----------------------------------
// SVD Line: 551
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// CALSEL
//
// [Bit 11] RW (@ 0x40012444) Calibration contents selection
//
// ( (unsigned int) ADC_CCSR )
// CALSEL
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSMP ----------------------------------
// SVD Line: 556
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// CALSMP
//
// [Bits 13..12] RW (@ 0x40012444) Calibration sample time selection
//
// ( (unsigned char)((ADC_CCSR >> 12) & 0x3), ((ADC_CCSR = (ADC_CCSR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSET ----------------------------------
// SVD Line: 561
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// CALSET
//
// [Bit 15] RW (@ 0x40012444) Calibration factor selection
//
// ( (unsigned int) ADC_CCSR )
// CALSET
//
//
//
// ------------------------------- Field Item: ADC_CCSR_OFFSUC ----------------------------------
// SVD Line: 566
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// OFFSUC
//
// [Bit 29] RW (@ 0x40012444) Offset calibration status flag
//
// ( (unsigned int) ADC_CCSR )
// OFFSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CAPSUC ----------------------------------
// SVD Line: 571
// - SFDITEM_FIELD__ADC_CCSR_CAPSUC
// CAPSUC
//
// [Bit 30] RW (@ 0x40012444) Cap calibration status flag
//
// ( (unsigned int) ADC_CCSR )
// CAPSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALON -----------------------------------
// SVD Line: 576
// - SFDITEM_FIELD__ADC_CCSR_CALON
// CALON
//
// [Bit 31] RO (@ 0x40012444) Calibration flag
//
// ( (unsigned int) ADC_CCSR )
// CALON
//
//
//
// -------------------------------- Register RTree: ADC_CCSR ------------------------------------
// SVD Line: 545
// SFDITEM_REG__ADC_CCSR
// CCSR
//
// [Bits 31..0] RW (@ 0x40012444) ADC calibration configuration and status register
// ( (unsigned int)((ADC_CCSR >> 0) & 0xFFFFFFFF), ((ADC_CCSR = (ADC_CCSR & ~(0x6000B800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6000B800) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// - SFDITEM_FIELD__ADC_CCSR_CAPSUC
// - SFDITEM_FIELD__ADC_CCSR_CALON
//
//
// ---------------------------- Register Item Address: ADC_CALRR1 -------------------------------
// SVD Line: 584
unsigned int ADC_CALRR1 __AT (0x40012448);
// ----------------------------- Field Item: ADC_CALRR1_CALC4OUT --------------------------------
// SVD Line: 591
// - SFDITEM_FIELD__ADC_CALRR1_CALC4OUT
// CALC4OUT
//
// [Bits 7..0] RO (@ 0x40012448) C4 result
//
// ( (unsigned char)((ADC_CALRR1 >> 0) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR1_CALC5OUT --------------------------------
// SVD Line: 596
// - SFDITEM_FIELD__ADC_CALRR1_CALC5OUT
// CALC5OUT
//
// [Bits 15..8] RO (@ 0x40012448) C5 result
//
// ( (unsigned char)((ADC_CALRR1 >> 8) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR1_CALBOUT ---------------------------------
// SVD Line: 601
// - SFDITEM_FIELD__ADC_CALRR1_CALBOUT
// CALBOUT
//
// [Bits 22..16] RO (@ 0x40012448) offset result
//
// ( (unsigned char)((ADC_CALRR1 >> 16) & 0x7F) )
//
//
//
// ------------------------------- Register RTree: ADC_CALRR1 -----------------------------------
// SVD Line: 584
// SFDITEM_REG__ADC_CALRR1
// CALRR1
//
// [Bits 31..0] RO (@ 0x40012448) ADC calibration result register 1
// ( (unsigned int)((ADC_CALRR1 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_CALRR1_CALC4OUT
// - SFDITEM_FIELD__ADC_CALRR1_CALC5OUT
// - SFDITEM_FIELD__ADC_CALRR1_CALBOUT
//
//
// ---------------------------- Register Item Address: ADC_CALRR2 -------------------------------
// SVD Line: 608
unsigned int ADC_CALRR2 __AT (0x4001244C);
// ----------------------------- Field Item: ADC_CALRR2_CALC0OUT --------------------------------
// SVD Line: 615
// - SFDITEM_FIELD__ADC_CALRR2_CALC0OUT
// CALC0OUT
//
// [Bits 7..0] RO (@ 0x4001244C) C0 result
//
// ( (unsigned char)((ADC_CALRR2 >> 0) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC1OUT --------------------------------
// SVD Line: 620
// - SFDITEM_FIELD__ADC_CALRR2_CALC1OUT
// CALC1OUT
//
// [Bits 15..8] RO (@ 0x4001244C) C1 result
//
// ( (unsigned char)((ADC_CALRR2 >> 8) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC2OUT --------------------------------
// SVD Line: 625
// - SFDITEM_FIELD__ADC_CALRR2_CALC2OUT
// CALC2OUT
//
// [Bits 23..16] RO (@ 0x4001244C) C2 result
//
// ( (unsigned char)((ADC_CALRR2 >> 16) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC3OUT --------------------------------
// SVD Line: 630
// - SFDITEM_FIELD__ADC_CALRR2_CALC3OUT
// CALC3OUT
//
// [Bits 31..24] RO (@ 0x4001244C) C3 result
//
// ( (unsigned char)((ADC_CALRR2 >> 24) & 0xFF) )
//
//
//
// ------------------------------- Register RTree: ADC_CALRR2 -----------------------------------
// SVD Line: 608
// SFDITEM_REG__ADC_CALRR2
// CALRR2
//
// [Bits 31..0] RO (@ 0x4001244C) ADC calibration result register 2
// ( (unsigned int)((ADC_CALRR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_CALRR2_CALC0OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC1OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC2OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC3OUT
//
//
// --------------------------- Register Item Address: ADC_CALFIR1 -------------------------------
// SVD Line: 637
unsigned int ADC_CALFIR1 __AT (0x40012450);
// ----------------------------- Field Item: ADC_CALFIR1_CALC4IO --------------------------------
// SVD Line: 643
// - SFDITEM_FIELD__ADC_CALFIR1_CALC4IO
// CALC4IO
//
// [Bits 7..0] RW (@ 0x40012450) Calibration C4 factor input
//
// ( (unsigned char)((ADC_CALFIR1 >> 0) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR1_CALC5IO --------------------------------
// SVD Line: 648
// - SFDITEM_FIELD__ADC_CALFIR1_CALC5IO
// CALC5IO
//
// [Bits 15..8] RW (@ 0x40012450) Calibration C5 factor input
//
// ( (unsigned char)((ADC_CALFIR1 >> 8) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR1_CALBIO ---------------------------------
// SVD Line: 653
// - SFDITEM_FIELD__ADC_CALFIR1_CALBIO
// CALBIO
//
// [Bits 22..16] RW (@ 0x40012450) Calibration offset factor input
//
// ( (unsigned char)((ADC_CALFIR1 >> 16) & 0x7F), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0x7FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: ADC_CALFIR1 ----------------------------------
// SVD Line: 637
// SFDITEM_REG__ADC_CALFIR1
// CALFIR1
//
// [Bits 31..0] RW (@ 0x40012450) ADC calibration factor input register 1
// ( (unsigned int)((ADC_CALFIR1 >> 0) & 0xFFFFFFFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0x7FFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFIR1_CALC4IO
// - SFDITEM_FIELD__ADC_CALFIR1_CALC5IO
// - SFDITEM_FIELD__ADC_CALFIR1_CALBIO
//
//
// --------------------------- Register Item Address: ADC_CALFIR2 -------------------------------
// SVD Line: 660
unsigned int ADC_CALFIR2 __AT (0x40012454);
// ----------------------------- Field Item: ADC_CALFIR2_CALC0IO --------------------------------
// SVD Line: 666
// - SFDITEM_FIELD__ADC_CALFIR2_CALC0IO
// CALC0IO
//
// [Bits 7..0] RW (@ 0x40012454) Calibration C0 factor input
//
// ( (unsigned char)((ADC_CALFIR2 >> 0) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC1IO --------------------------------
// SVD Line: 671
// - SFDITEM_FIELD__ADC_CALFIR2_CALC1IO
// CALC1IO
//
// [Bits 15..8] RW (@ 0x40012454) Calibration C1 factor input
//
// ( (unsigned char)((ADC_CALFIR2 >> 8) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC2IO --------------------------------
// SVD Line: 676
// - SFDITEM_FIELD__ADC_CALFIR2_CALC2IO
// CALC2IO
//
// [Bits 23..16] RW (@ 0x40012454) Calibration C2 factor input
//
// ( (unsigned char)((ADC_CALFIR2 >> 16) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC3IO --------------------------------
// SVD Line: 681
// - SFDITEM_FIELD__ADC_CALFIR2_CALC3IO
// CALC3IO
//
// [Bits 31..24] RW (@ 0x40012454) Calibration C3 factor input
//
// ( (unsigned char)((ADC_CALFIR2 >> 24) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: ADC_CALFIR2 ----------------------------------
// SVD Line: 660
// SFDITEM_REG__ADC_CALFIR2
// CALFIR2
//
// [Bits 31..0] RW (@ 0x40012454) ADC calibration factor input register 2
// ( (unsigned int)((ADC_CALFIR2 >> 0) & 0xFFFFFFFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFIR2_CALC0IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC1IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC2IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC3IO
//
//
// ----------------------------- Register Item Address: ADC_CCR ---------------------------------
// SVD Line: 688
unsigned int ADC_CCR __AT (0x40012708);
// ----------------------------- Field Item: ADC_CCR_TSVREFINTEN --------------------------------
// SVD Line: 694
// - SFDITEM_FIELD__ADC_CCR_TSVREFINTEN
// TSVREFINTEN
//
// [Bit 23] RW (@ 0x40012708) Temperature sensor and VREFINT enable
//
// ( (unsigned int) ADC_CCR )
// TSVREFINTEN
//
//
//
// --------------------------------- Register RTree: ADC_CCR ------------------------------------
// SVD Line: 688
// SFDITEM_REG__ADC_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x40012708) ADC common configuration register
// ( (unsigned int)((ADC_CCR >> 0) & 0xFFFFFFFF), ((ADC_CCR = (ADC_CCR & ~(0x800000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCR_TSVREFINTEN
//
//
// ---------------------------------- Peripheral View: ADC --------------------------------------
// SVD Line: 25
// ADC
// ADC
// - SFDITEM_REG__ADC_ISR
// - SFDITEM_REG__ADC_IER
// - SFDITEM_REG__ADC_CR
// - SFDITEM_REG__ADC_CFGR1
// - SFDITEM_REG__ADC_CFGR2
// - SFDITEM_REG__ADC_SMPR0
// - SFDITEM_REG__ADC_SMPR1
// - SFDITEM_REG__ADC_TR
// - SFDITEM_REG__ADC_CHSELR
// - SFDITEM_REG__ADC_SEQR0
// - SFDITEM_REG__ADC_SEQR1
// - SFDITEM_REG__ADC_DR
// - SFDITEM_REG__ADC_CCSR
// - SFDITEM_REG__ADC_CALRR1
// - SFDITEM_REG__ADC_CALRR2
// - SFDITEM_REG__ADC_CALFIR1
// - SFDITEM_REG__ADC_CALFIR2
// - SFDITEM_REG__ADC_CCR
//
//
// ---------------------------- Register Item Address: COMP1_CSR --------------------------------
// SVD Line: 714
unsigned int COMP1_CSR __AT (0x40010200);
// ------------------------------ Field Item: COMP1_CSR_COMP_EN ---------------------------------
// SVD Line: 720
// - SFDITEM_FIELD__COMP1_CSR_COMP_EN
// COMP_EN
//
// [Bit 0] RW (@ 0x40010200) COMP enable bit
//
// ( (unsigned int) COMP1_CSR )
// COMP_EN
//
//
//
// ------------------------------ Field Item: COMP1_CSR_INMSEL ----------------------------------
// SVD Line: 725
// - SFDITEM_FIELD__COMP1_CSR_INMSEL
// INMSEL
//
// [Bits 7..5] RW (@ 0x40010200) Comparator signal selector for inverting input INM
//
// ( (unsigned char)((COMP1_CSR >> 5) & 0x7), ((COMP1_CSR = (COMP1_CSR & ~(0x7UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 5 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP1_CSR_INPSEL ----------------------------------
// SVD Line: 730
// - SFDITEM_FIELD__COMP1_CSR_INPSEL
// INPSEL
//
// [Bits 10..8] RW (@ 0x40010200) Comparator signal selector for non-inverting input
//
// ( (unsigned char)((COMP1_CSR >> 8) & 0x7), ((COMP1_CSR = (COMP1_CSR & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP1_CSR_WINMODE ---------------------------------
// SVD Line: 735
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010200) Comparator non-inverting input selector for window mode
//
// ( (unsigned int) COMP1_CSR )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP1_CSR_POLARITY ---------------------------------
// SVD Line: 740
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010200) Comparator polarity selector
//
// ( (unsigned int) COMP1_CSR )
// POLARITY
//
//
//
// ------------------------------- Field Item: COMP1_CSR_HYST -----------------------------------
// SVD Line: 745
// - SFDITEM_FIELD__COMP1_CSR_HYST
// HYST
//
// [Bit 16] RW (@ 0x40010200) Comparator hysteresis enable selector
//
// ( (unsigned int) COMP1_CSR )
// HYST
//
//
//
// ------------------------------ Field Item: COMP1_CSR_PWRMODE ---------------------------------
// SVD Line: 750
// - SFDITEM_FIELD__COMP1_CSR_PWRMODE
// PWRMODE
//
// [Bits 19..18] RW (@ 0x40010200) Comparator power mode selector
//
// ( (unsigned char)((COMP1_CSR >> 18) & 0x3), ((COMP1_CSR = (COMP1_CSR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ------------------------------- Field Item: COMP1_CSR_VCDIV ----------------------------------
// SVD Line: 755
// - SFDITEM_FIELD__COMP1_CSR_VCDIV
// VCDIV
//
// [Bits 25..20] RW (@ 0x40010200) Comparator vcdiv
//
// ( (unsigned char)((COMP1_CSR >> 20) & 0x3F), ((COMP1_CSR = (COMP1_CSR & ~(0x3FUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: COMP1_CSR_VCDIV_EN ---------------------------------
// SVD Line: 760
// - SFDITEM_FIELD__COMP1_CSR_VCDIV_EN
// VCDIV_EN
//
// [Bit 26] RW (@ 0x40010200) Comparator vcdiv enable
//
// ( (unsigned int) COMP1_CSR )
// VCDIV_EN
//
//
//
// ------------------------------- Field Item: COMP1_CSR_VCSEL ----------------------------------
// SVD Line: 765
// - SFDITEM_FIELD__COMP1_CSR_VCSEL
// VCSEL
//
// [Bit 27] RW (@ 0x40010200) Comparator vcsel
//
// ( (unsigned int) COMP1_CSR )
// VCSEL
//
//
//
// ----------------------------- Field Item: COMP1_CSR_COMP_OUT ---------------------------------
// SVD Line: 770
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RW (@ 0x40010200) Comparator output status
//
// ( (unsigned int) COMP1_CSR )
// COMP_OUT
//
//
//
// ------------------------------- Field Item: COMP1_CSR_LOCK -----------------------------------
// SVD Line: 775
// - SFDITEM_FIELD__COMP1_CSR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40010200) CSR register lock
//
// ( (unsigned int) COMP1_CSR )
// LOCK
//
//
//
// -------------------------------- Register RTree: COMP1_CSR -----------------------------------
// SVD Line: 714
// SFDITEM_REG__COMP1_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010200) COMP control and status register
// ( (unsigned int)((COMP1_CSR >> 0) & 0xFFFFFFFF), ((COMP1_CSR = (COMP1_CSR & ~(0xCFFD8FE1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCFFD8FE1) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_CSR_COMP_EN
// - SFDITEM_FIELD__COMP1_CSR_INMSEL
// - SFDITEM_FIELD__COMP1_CSR_INPSEL
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// - SFDITEM_FIELD__COMP1_CSR_HYST
// - SFDITEM_FIELD__COMP1_CSR_PWRMODE
// - SFDITEM_FIELD__COMP1_CSR_VCDIV
// - SFDITEM_FIELD__COMP1_CSR_VCDIV_EN
// - SFDITEM_FIELD__COMP1_CSR_VCSEL
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
// - SFDITEM_FIELD__COMP1_CSR_LOCK
//
//
// ----------------------------- Register Item Address: COMP1_FR --------------------------------
// SVD Line: 782
unsigned int COMP1_FR __AT (0x40010204);
// ------------------------------- Field Item: COMP1_FR_FLTEN -----------------------------------
// SVD Line: 788
// - SFDITEM_FIELD__COMP1_FR_FLTEN
// FLTEN
//
// [Bit 0] RW (@ 0x40010204) Filter enable bit
//
// ( (unsigned int) COMP1_FR )
// FLTEN
//
//
//
// ------------------------------- Field Item: COMP1_FR_FLTCNT ----------------------------------
// SVD Line: 793
// - SFDITEM_FIELD__COMP1_FR_FLTCNT
// FLTCNT
//
// [Bits 31..16] RW (@ 0x40010204) Comparator filter and counter
//
// ( (unsigned short)((COMP1_FR >> 16) & 0xFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP1_FR ------------------------------------
// SVD Line: 782
// SFDITEM_REG__COMP1_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010204) Comparator Filterregister
// ( (unsigned int)((COMP1_FR >> 0) & 0xFFFFFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_FR_FLTEN
// - SFDITEM_FIELD__COMP1_FR_FLTCNT
//
//
// --------------------------------- Peripheral View: COMP1 -------------------------------------
// SVD Line: 703
// COMP1
// COMP1
// - SFDITEM_REG__COMP1_CSR
// - SFDITEM_REG__COMP1_FR
//
//
// ---------------------------- Register Item Address: COMP2_CSR --------------------------------
// SVD Line: 813
unsigned int COMP2_CSR __AT (0x40010210);
// ------------------------------ Field Item: COMP2_CSR_COMP_EN ---------------------------------
// SVD Line: 819
// - SFDITEM_FIELD__COMP2_CSR_COMP_EN
// COMP_EN
//
// [Bit 0] RW (@ 0x40010210) COMP enable bit
//
// ( (unsigned int) COMP2_CSR )
// COMP_EN
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INMSEL ----------------------------------
// SVD Line: 824
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// INMSEL
//
// [Bits 7..5] RW (@ 0x40010210) Comparator signal selector for inverting input INM
//
// ( (unsigned char)((COMP2_CSR >> 5) & 0x7), ((COMP2_CSR = (COMP2_CSR & ~(0x7UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 5 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INPSEL ----------------------------------
// SVD Line: 829
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// INPSEL
//
// [Bits 10..8] RW (@ 0x40010210) Comparator signal selector for non-inverting input
//
// ( (unsigned char)((COMP2_CSR >> 8) & 0x7), ((COMP2_CSR = (COMP2_CSR & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP2_CSR_WINMODE ---------------------------------
// SVD Line: 834
// - SFDITEM_FIELD__COMP2_CSR_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010210) Comparator non-inverting input selector for window mode
//
// ( (unsigned int) COMP2_CSR )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP2_CSR_POLARITY ---------------------------------
// SVD Line: 839
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010210) Comparator polarity selector
//
// ( (unsigned int) COMP2_CSR )
// POLARITY
//
//
//
// ------------------------------- Field Item: COMP2_CSR_HYST -----------------------------------
// SVD Line: 844
// - SFDITEM_FIELD__COMP2_CSR_HYST
// HYST
//
// [Bit 16] RW (@ 0x40010210) Comparator hysteresis enable selector
//
// ( (unsigned int) COMP2_CSR )
// HYST
//
//
//
// ------------------------------ Field Item: COMP2_CSR_PWRMODE ---------------------------------
// SVD Line: 849
// - SFDITEM_FIELD__COMP2_CSR_PWRMODE
// PWRMODE
//
// [Bits 19..18] RW (@ 0x40010210) Comparator power mode selector
//
// ( (unsigned char)((COMP2_CSR >> 18) & 0x3), ((COMP2_CSR = (COMP2_CSR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ------------------------------- Field Item: COMP2_CSR_VCDIV ----------------------------------
// SVD Line: 854
// - SFDITEM_FIELD__COMP2_CSR_VCDIV
// VCDIV
//
// [Bits 25..20] RW (@ 0x40010210) Comparator vcdiv
//
// ( (unsigned char)((COMP2_CSR >> 20) & 0x3F), ((COMP2_CSR = (COMP2_CSR & ~(0x3FUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: COMP2_CSR_VCDIV_EN ---------------------------------
// SVD Line: 859
// - SFDITEM_FIELD__COMP2_CSR_VCDIV_EN
// VCDIV_EN
//
// [Bit 26] RW (@ 0x40010210) Comparator vcdiv enable
//
// ( (unsigned int) COMP2_CSR )
// VCDIV_EN
//
//
//
// ------------------------------- Field Item: COMP2_CSR_VCSEL ----------------------------------
// SVD Line: 864
// - SFDITEM_FIELD__COMP2_CSR_VCSEL
// VCSEL
//
// [Bit 27] RW (@ 0x40010210) Comparator vcsel
//
// ( (unsigned int) COMP2_CSR )
// VCSEL
//
//
//
// ----------------------------- Field Item: COMP2_CSR_COMP_OUT ---------------------------------
// SVD Line: 869
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RW (@ 0x40010210) Comparator output status
//
// ( (unsigned int) COMP2_CSR )
// COMP_OUT
//
//
//
// ------------------------------- Field Item: COMP2_CSR_LOCK -----------------------------------
// SVD Line: 874
// - SFDITEM_FIELD__COMP2_CSR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40010210) CSR register lock
//
// ( (unsigned int) COMP2_CSR )
// LOCK
//
//
//
// -------------------------------- Register RTree: COMP2_CSR -----------------------------------
// SVD Line: 813
// SFDITEM_REG__COMP2_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010210) COMP control and status register
// ( (unsigned int)((COMP2_CSR >> 0) & 0xFFFFFFFF), ((COMP2_CSR = (COMP2_CSR & ~(0xCFFD8FE1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCFFD8FE1) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_CSR_COMP_EN
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// - SFDITEM_FIELD__COMP2_CSR_WINMODE
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// - SFDITEM_FIELD__COMP2_CSR_HYST
// - SFDITEM_FIELD__COMP2_CSR_PWRMODE
// - SFDITEM_FIELD__COMP2_CSR_VCDIV
// - SFDITEM_FIELD__COMP2_CSR_VCDIV_EN
// - SFDITEM_FIELD__COMP2_CSR_VCSEL
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
// - SFDITEM_FIELD__COMP2_CSR_LOCK
//
//
// ----------------------------- Register Item Address: COMP2_FR --------------------------------
// SVD Line: 881
unsigned int COMP2_FR __AT (0x40010214);
// ------------------------------- Field Item: COMP2_FR_FLTEN -----------------------------------
// SVD Line: 887
// - SFDITEM_FIELD__COMP2_FR_FLTEN
// FLTEN
//
// [Bit 0] RW (@ 0x40010214) Filter enable bit
//
// ( (unsigned int) COMP2_FR )
// FLTEN
//
//
//
// ------------------------------- Field Item: COMP2_FR_FLTCNT ----------------------------------
// SVD Line: 892
// - SFDITEM_FIELD__COMP2_FR_FLTCNT
// FLTCNT
//
// [Bits 31..16] RW (@ 0x40010214) Comparator filter and counter
//
// ( (unsigned short)((COMP2_FR >> 16) & 0xFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP2_FR ------------------------------------
// SVD Line: 881
// SFDITEM_REG__COMP2_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010214) Comparator Filterregister
// ( (unsigned int)((COMP2_FR >> 0) & 0xFFFFFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_FR_FLTEN
// - SFDITEM_FIELD__COMP2_FR_FLTCNT
//
//
// --------------------------------- Peripheral View: COMP2 -------------------------------------
// SVD Line: 802
// COMP2
// COMP2
// - SFDITEM_REG__COMP2_CSR
// - SFDITEM_REG__COMP2_FR
//
//
// ---------------------------- Register Item Address: CORDIC_CR --------------------------------
// SVD Line: 922
unsigned int CORDIC_CR __AT (0x40023400);
// ----------------------------- Field Item: CORDIC_CR_ITERATION --------------------------------
// SVD Line: 928
// - SFDITEM_FIELD__CORDIC_CR_ITERATION
// ITERATION
//
// [Bits 4..0] RW (@ 0x40023400) desc ITERATION
//
// ( (unsigned char)((CORDIC_CR >> 0) & 0x1F), ((CORDIC_CR = (CORDIC_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: CORDIC_CR_CORDIC_INT --------------------------------
// SVD Line: 933
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_INT
// CORDIC_INT
//
// [Bit 5] RW (@ 0x40023400) desc CORDIC_INT
//
// ( (unsigned int) CORDIC_CR )
// CORDIC_INT
//
//
//
// ----------------------------- Field Item: CORDIC_CR_SQRT_INT ---------------------------------
// SVD Line: 938
// - SFDITEM_FIELD__CORDIC_CR_SQRT_INT
// SQRT_INT
//
// [Bit 6] RW (@ 0x40023400) desc SQRT_INT
//
// ( (unsigned int) CORDIC_CR )
// SQRT_INT
//
//
//
// ---------------------------- Field Item: CORDIC_CR_CORDIC_MODE -------------------------------
// SVD Line: 943
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_MODE
// CORDIC_MODE
//
// [Bit 7] RW (@ 0x40023400) desc CORDIC_MODE
//
// ( (unsigned int) CORDIC_CR )
// CORDIC_MODE
//
//
//
// ------------------------------- Field Item: CORDIC_CR_START ----------------------------------
// SVD Line: 948
// - SFDITEM_FIELD__CORDIC_CR_START
// START
//
// [Bit 8] RW (@ 0x40023400) desc START
//
// ( (unsigned int) CORDIC_CR )
// START
//
//
//
// ---------------------------- Field Item: CORDIC_CR_START_MODE --------------------------------
// SVD Line: 953
// - SFDITEM_FIELD__CORDIC_CR_START_MODE
// START_MODE
//
// [Bit 9] RW (@ 0x40023400) desc START_MODE
//
// ( (unsigned int) CORDIC_CR )
// START_MODE
//
//
//
// ------------------------------ Field Item: CORDIC_CR_VECSIZE ---------------------------------
// SVD Line: 958
// - SFDITEM_FIELD__CORDIC_CR_VECSIZE
// VECSIZE
//
// [Bit 20] RW (@ 0x40023400) desc VECSIZE
//
// ( (unsigned int) CORDIC_CR )
// VECSIZE
//
//
//
// ------------------------------ Field Item: CORDIC_CR_RESSIZE ---------------------------------
// SVD Line: 963
// - SFDITEM_FIELD__CORDIC_CR_RESSIZE
// RESSIZE
//
// [Bit 21] RW (@ 0x40023400) desc RESSIZE
//
// ( (unsigned int) CORDIC_CR )
// RESSIZE
//
//
//
// ------------------------------ Field Item: CORDIC_CR_ARGSIZE ---------------------------------
// SVD Line: 968
// - SFDITEM_FIELD__CORDIC_CR_ARGSIZE
// ARGSIZE
//
// [Bit 22] RW (@ 0x40023400) desc ARGSIZE
//
// ( (unsigned int) CORDIC_CR )
// ARGSIZE
//
//
//
// -------------------------- Field Item: CORDIC_CR_CORDIC_INT_MASK -----------------------------
// SVD Line: 973
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_INT_MASK
// CORDIC_INT_MASK
//
// [Bit 28] RW (@ 0x40023400) desc CORDIC_INT_MASK
//
// ( (unsigned int) CORDIC_CR )
// CORDIC_INT_MASK
//
//
//
// --------------------------- Field Item: CORDIC_CR_SQRT_INT_MASK ------------------------------
// SVD Line: 978
// - SFDITEM_FIELD__CORDIC_CR_SQRT_INT_MASK
// SQRT_INT_MASK
//
// [Bit 29] RW (@ 0x40023400) desc SQRT_INT_MASK
//
// ( (unsigned int) CORDIC_CR )
// SQRT_INT_MASK
//
//
//
// ----------------------- Field Item: CORDIC_CR_CORDIC_ERROR_INT_MASK --------------------------
// SVD Line: 983
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_ERROR_INT_MASK
// CORDIC_ERROR_INT_MASK
//
// [Bit 30] RW (@ 0x40023400) desc CORDIC_ERROR_INT_MASK
//
// ( (unsigned int) CORDIC_CR )
// CORDIC_ERROR_INT_MASK
//
//
//
// ------------------------ Field Item: CORDIC_CR_ARCTAN_MOD_OV_MASK ----------------------------
// SVD Line: 988
// - SFDITEM_FIELD__CORDIC_CR_ARCTAN_MOD_OV_MASK
// ARCTAN_MOD_OV_MASK
//
// [Bit 31] RW (@ 0x40023400) desc ARCTAN_MOD_OV_MASK
//
// ( (unsigned int) CORDIC_CR )
// ARCTAN_MOD_OV_MASK
//
//
//
// -------------------------------- Register RTree: CORDIC_CR -----------------------------------
// SVD Line: 922
// SFDITEM_REG__CORDIC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40023400) CORDIC control register
// ( (unsigned int)((CORDIC_CR >> 0) & 0xFFFFFFFF), ((CORDIC_CR = (CORDIC_CR & ~(0xF07003FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF07003FF) << 0 ) ) ))
// - SFDITEM_FIELD__CORDIC_CR_ITERATION
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_INT
// - SFDITEM_FIELD__CORDIC_CR_SQRT_INT
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_MODE
// - SFDITEM_FIELD__CORDIC_CR_START
// - SFDITEM_FIELD__CORDIC_CR_START_MODE
// - SFDITEM_FIELD__CORDIC_CR_VECSIZE
// - SFDITEM_FIELD__CORDIC_CR_RESSIZE
// - SFDITEM_FIELD__CORDIC_CR_ARGSIZE
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_INT_MASK
// - SFDITEM_FIELD__CORDIC_CR_SQRT_INT_MASK
// - SFDITEM_FIELD__CORDIC_CR_CORDIC_ERROR_INT_MASK
// - SFDITEM_FIELD__CORDIC_CR_ARCTAN_MOD_OV_MASK
//
//
// --------------------------- Register Item Address: CORDIC_THETA ------------------------------
// SVD Line: 995
unsigned int CORDIC_THETA __AT (0x40023404);
// ----------------------------- Field Item: CORDIC_THETA_THETA ---------------------------------
// SVD Line: 1001
// - SFDITEM_FIELD__CORDIC_THETA_THETA
// THETA
//
// [Bits 31..0] RW (@ 0x40023404) THETA
//
// ( (unsigned int)((CORDIC_THETA >> 0) & 0xFFFFFFFF), ((CORDIC_THETA = (CORDIC_THETA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: CORDIC_THETA ----------------------------------
// SVD Line: 995
// SFDITEM_REG__CORDIC_THETA
// THETA
//
// [Bits 31..0] RW (@ 0x40023404) SIN or COS input theta register
// ( (unsigned int)((CORDIC_THETA >> 0) & 0xFFFFFFFF), ((CORDIC_THETA = (CORDIC_THETA & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CORDIC_THETA_THETA
//
//
// ---------------------------- Register Item Address: CORDIC_SIN -------------------------------
// SVD Line: 1008
unsigned int CORDIC_SIN __AT (0x40023408);
// ------------------------------- Field Item: CORDIC_SIN_SIN -----------------------------------
// SVD Line: 1015
// - SFDITEM_FIELD__CORDIC_SIN_SIN
// SIN
//
// [Bits 23..0] RO (@ 0x40023408) SIN result
//
// ( (unsigned int)((CORDIC_SIN >> 0) & 0xFFFFFF) )
//
//
//
// ------------------------------- Register RTree: CORDIC_SIN -----------------------------------
// SVD Line: 1008
// SFDITEM_REG__CORDIC_SIN
// SIN
//
// [Bits 31..0] RO (@ 0x40023408) CORDIC SIN result register
// ( (unsigned int)((CORDIC_SIN >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_SIN_SIN
//
//
// ---------------------------- Register Item Address: CORDIC_COS -------------------------------
// SVD Line: 1022
unsigned int CORDIC_COS __AT (0x4002340C);
// ------------------------------- Field Item: CORDIC_COS_COS -----------------------------------
// SVD Line: 1029
// - SFDITEM_FIELD__CORDIC_COS_COS
// COS
//
// [Bits 23..0] RO (@ 0x4002340C) COS result
//
// ( (unsigned int)((CORDIC_COS >> 0) & 0xFFFFFF) )
//
//
//
// ------------------------------- Register RTree: CORDIC_COS -----------------------------------
// SVD Line: 1022
// SFDITEM_REG__CORDIC_COS
// COS
//
// [Bits 31..0] RO (@ 0x4002340C) CORDIC COS result register
// ( (unsigned int)((CORDIC_COS >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_COS_COS
//
//
// ----------------------------- Register Item Address: CORDIC_X --------------------------------
// SVD Line: 1037
unsigned int CORDIC_X __AT (0x40023410);
// --------------------------------- Field Item: CORDIC_X_X -------------------------------------
// SVD Line: 1043
// - SFDITEM_FIELD__CORDIC_X_X
// X
//
// [Bits 23..0] RW (@ 0x40023410) arctan or module X register
//
// ( (unsigned int)((CORDIC_X >> 0) & 0xFFFFFF), ((CORDIC_X = (CORDIC_X & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: CORDIC_X ------------------------------------
// SVD Line: 1037
// SFDITEM_REG__CORDIC_X
// X
//
// [Bits 31..0] RW (@ 0x40023410) Arctan input coordinate register
// ( (unsigned int)((CORDIC_X >> 0) & 0xFFFFFFFF), ((CORDIC_X = (CORDIC_X & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CORDIC_X_X
//
//
// ----------------------------- Register Item Address: CORDIC_Y --------------------------------
// SVD Line: 1050
unsigned int CORDIC_Y __AT (0x40023414);
// --------------------------------- Field Item: CORDIC_Y_Y -------------------------------------
// SVD Line: 1056
// - SFDITEM_FIELD__CORDIC_Y_Y
// Y
//
// [Bits 23..0] RW (@ 0x40023414) arctan or module Y register
//
// ( (unsigned int)((CORDIC_Y >> 0) & 0xFFFFFF), ((CORDIC_Y = (CORDIC_Y & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: CORDIC_Y ------------------------------------
// SVD Line: 1050
// SFDITEM_REG__CORDIC_Y
// Y
//
// [Bits 31..0] RW (@ 0x40023414) Arctan input coordinate register
// ( (unsigned int)((CORDIC_Y >> 0) & 0xFFFFFFFF), ((CORDIC_Y = (CORDIC_Y & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CORDIC_Y_Y
//
//
// ---------------------------- Register Item Address: CORDIC_MOD -------------------------------
// SVD Line: 1063
unsigned int CORDIC_MOD __AT (0x40023418);
// ------------------------------- Field Item: CORDIC_MOD_MOD -----------------------------------
// SVD Line: 1070
// - SFDITEM_FIELD__CORDIC_MOD_MOD
// MOD
//
// [Bits 24..0] RO (@ 0x40023418) mod result
//
// ( (unsigned int)((CORDIC_MOD >> 0) & 0x1FFFFFF) )
//
//
//
// ------------------------------- Register RTree: CORDIC_MOD -----------------------------------
// SVD Line: 1063
// SFDITEM_REG__CORDIC_MOD
// MOD
//
// [Bits 31..0] RO (@ 0x40023418) CORDIC Mod result register
// ( (unsigned int)((CORDIC_MOD >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_MOD_MOD
//
//
// -------------------------- Register Item Address: CORDIC_ARCTAN ------------------------------
// SVD Line: 1077
unsigned int CORDIC_ARCTAN __AT (0x4002341C);
// ---------------------------- Field Item: CORDIC_ARCTAN_ARCTAN --------------------------------
// SVD Line: 1084
// - SFDITEM_FIELD__CORDIC_ARCTAN_ARCTAN
// ARCTAN
//
// [Bits 15..0] RO (@ 0x4002341C) arctan result
//
// ( (unsigned short)((CORDIC_ARCTAN >> 0) & 0xFFFF) )
//
//
//
// ------------------------------ Register RTree: CORDIC_ARCTAN ---------------------------------
// SVD Line: 1077
// SFDITEM_REG__CORDIC_ARCTAN
// ARCTAN
//
// [Bits 31..0] RO (@ 0x4002341C) CORDIC ARCTAN result register
// ( (unsigned int)((CORDIC_ARCTAN >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_ARCTAN_ARCTAN
//
//
// -------------------------- Register Item Address: CORDIC_DSP_RAD -----------------------------
// SVD Line: 1091
unsigned int CORDIC_DSP_RAD __AT (0x40023420);
// ----------------------------- Field Item: CORDIC_DSP_RAD_RAD ---------------------------------
// SVD Line: 1097
// - SFDITEM_FIELD__CORDIC_DSP_RAD_RAD
// RAD
//
// [Bits 31..0] RW (@ 0x40023420) Number of open parties
//
// ( (unsigned int)((CORDIC_DSP_RAD >> 0) & 0xFFFFFFFF), ((CORDIC_DSP_RAD = (CORDIC_DSP_RAD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ----------------------------- Register RTree: CORDIC_DSP_RAD ---------------------------------
// SVD Line: 1091
// SFDITEM_REG__CORDIC_DSP_RAD
// DSP_RAD
//
// [Bits 31..0] RW (@ 0x40023420) CORDIC Radicand register
// ( (unsigned int)((CORDIC_DSP_RAD >> 0) & 0xFFFFFFFF), ((CORDIC_DSP_RAD = (CORDIC_DSP_RAD & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CORDIC_DSP_RAD_RAD
//
//
// ------------------------- Register Item Address: CORDIC_DSP_SQRT -----------------------------
// SVD Line: 1104
unsigned int CORDIC_DSP_SQRT __AT (0x40023424);
// ---------------------------- Field Item: CORDIC_DSP_SQRT_SQRT --------------------------------
// SVD Line: 1111
// - SFDITEM_FIELD__CORDIC_DSP_SQRT_SQRT
// SQRT
//
// [Bits 15..0] RO (@ 0x40023424) sqrt result
//
// ( (unsigned short)((CORDIC_DSP_SQRT >> 0) & 0xFFFF) )
//
//
//
// ----------------------------- Register RTree: CORDIC_DSP_SQRT --------------------------------
// SVD Line: 1104
// SFDITEM_REG__CORDIC_DSP_SQRT
// DSP_SQRT
//
// [Bits 31..0] RO (@ 0x40023424) CORDIC SQRT result register
// ( (unsigned int)((CORDIC_DSP_SQRT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_DSP_SQRT_SQRT
//
//
// ---------------------------- Register Item Address: CORDIC_SR --------------------------------
// SVD Line: 1118
unsigned int CORDIC_SR __AT (0x40023428);
// ------------------------------- Field Item: CORDIC_SR_CCFF -----------------------------------
// SVD Line: 1125
// - SFDITEM_FIELD__CORDIC_SR_CCFF
// CCFF
//
// [Bit 0] RO (@ 0x40023428) desc CCFF
//
// ( (unsigned int) CORDIC_SR )
// CCFF
//
//
//
// ------------------------------- Field Item: CORDIC_SR_SCFF -----------------------------------
// SVD Line: 1130
// - SFDITEM_FIELD__CORDIC_SR_SCFF
// SCFF
//
// [Bit 1] RO (@ 0x40023428) desc SCFF
//
// ( (unsigned int) CORDIC_SR )
// SCFF
//
//
//
// ------------------------------- Field Item: CORDIC_SR_CCEF -----------------------------------
// SVD Line: 1135
// - SFDITEM_FIELD__CORDIC_SR_CCEF
// CCEF
//
// [Bit 2] RO (@ 0x40023428) desc CCFF
//
// ( (unsigned int) CORDIC_SR )
// CCEF
//
//
//
// ------------------------------- Field Item: CORDIC_SR_ACEF -----------------------------------
// SVD Line: 1140
// - SFDITEM_FIELD__CORDIC_SR_ACEF
// ACEF
//
// [Bit 3] RO (@ 0x40023428) desc ACFF
//
// ( (unsigned int) CORDIC_SR )
// ACEF
//
//
//
// -------------------------------- Field Item: CORDIC_SR_BSY -----------------------------------
// SVD Line: 1145
// - SFDITEM_FIELD__CORDIC_SR_BSY
// BSY
//
// [Bit 4] RO (@ 0x40023428) desc BSY
//
// ( (unsigned int) CORDIC_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: CORDIC_SR -----------------------------------
// SVD Line: 1118
// SFDITEM_REG__CORDIC_SR
// SR
//
// [Bits 31..0] RO (@ 0x40023428) CORDIC Status register
// ( (unsigned int)((CORDIC_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__CORDIC_SR_CCFF
// - SFDITEM_FIELD__CORDIC_SR_SCFF
// - SFDITEM_FIELD__CORDIC_SR_CCEF
// - SFDITEM_FIELD__CORDIC_SR_ACEF
// - SFDITEM_FIELD__CORDIC_SR_BSY
//
//
// --------------------------------- Peripheral View: CORDIC ------------------------------------
// SVD Line: 901
// CORDIC
// CORDIC
// - SFDITEM_REG__CORDIC_CR
// - SFDITEM_REG__CORDIC_THETA
// - SFDITEM_REG__CORDIC_SIN
// - SFDITEM_REG__CORDIC_COS
// - SFDITEM_REG__CORDIC_X
// - SFDITEM_REG__CORDIC_Y
// - SFDITEM_REG__CORDIC_MOD
// - SFDITEM_REG__CORDIC_ARCTAN
// - SFDITEM_REG__CORDIC_DSP_RAD
// - SFDITEM_REG__CORDIC_DSP_SQRT
// - SFDITEM_REG__CORDIC_SR
//
//
// ------------------------------ Register Item Address: CRC_DR ---------------------------------
// SVD Line: 1165
unsigned int CRC_DR __AT (0x40023000);
// ---------------------------------- Field Item: CRC_DR_DR -------------------------------------
// SVD Line: 1172
// - SFDITEM_FIELD__CRC_DR_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data Register
//
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_DR -------------------------------------
// SVD Line: 1165
// SFDITEM_REG__CRC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_DR_DR
//
//
// ----------------------------- Register Item Address: CRC_IDR ---------------------------------
// SVD Line: 1179
unsigned int CRC_IDR __AT (0x40023004);
// --------------------------------- Field Item: CRC_IDR_IDR ------------------------------------
// SVD Line: 1185
// - SFDITEM_FIELD__CRC_IDR_IDR
// IDR
//
// [Bits 7..0] RW (@ 0x40023004) Independent Data register
//
// ( (unsigned char)((CRC_IDR >> 0) & 0xFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_IDR ------------------------------------
// SVD Line: 1179
// SFDITEM_REG__CRC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x40023004) Independent Data register
// ( (unsigned int)((CRC_IDR >> 0) & 0xFFFFFFFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_IDR_IDR
//
//
// ------------------------------ Register Item Address: CRC_CR ---------------------------------
// SVD Line: 1192
unsigned int CRC_CR __AT (0x40023008);
// -------------------------------- Field Item: CRC_CR_RESET ------------------------------------
// SVD Line: 1199
// - SFDITEM_FIELD__CRC_CR_RESET
// RESET
//
// [Bit 0] WO (@ 0x40023008) Reset bit
//
// ( (unsigned int) CRC_CR )
// RESET
//
//
//
// --------------------------------- Register RTree: CRC_CR -------------------------------------
// SVD Line: 1192
// SFDITEM_REG__CRC_CR
// CR
//
// [Bits 31..0] WO (@ 0x40023008) Control register
// ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_CR_RESET
//
//
// ---------------------------------- Peripheral View: CRC --------------------------------------
// SVD Line: 1154
// CRC
// CRC
// - SFDITEM_REG__CRC_DR
// - SFDITEM_REG__CRC_IDR
// - SFDITEM_REG__CRC_CR
//
//
// -------------------------- Register Item Address: DBGMCU_IDCODE ------------------------------
// SVD Line: 1219
unsigned int DBGMCU_IDCODE __AT (0x40015800);
// ------------------------------ Register Item: DBGMCU_IDCODE ----------------------------------
// SVD Line: 1219
// - SFDITEM_REG__DBGMCU_IDCODE
// IDCODE
// [Bits 31..0] RO (@ 0x40015800) MCU Device ID Code Register
//
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF), ((DBGMCU_IDCODE = (DBGMCU_IDCODE & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 1226
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_SLEEP --------------------------------
// SVD Line: 1232
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// DBG_SLEEP
//
// [Bit 0] RW (@ 0x40015804) Debug Sleep Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_SLEEP
//
//
//
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 1237
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) Debug Stop Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 1226
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ1 -----------------------------
// SVD Line: 1244
unsigned int DBGMCU_APB_FZ1 __AT (0x40015808);
// ----------------------- Field Item: DBGMCU_APB_FZ1_DBG_TIMER3_STOP ---------------------------
// SVD Line: 1250
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_TIMER3_STOP
// DBG_TIMER3_STOP
//
// [Bit 1] RW (@ 0x40015808) Debug Timer 3 stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_TIMER3_STOP
//
//
//
// ------------------------- Field Item: DBGMCU_APB_FZ1_DBG_RTC_STOP ----------------------------
// SVD Line: 1255
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_RTC_STOP
// DBG_RTC_STOP
//
// [Bit 10] RW (@ 0x40015808) Debug RTC stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_RTC_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_WWDG_STOP ----------------------------
// SVD Line: 1260
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_WWDG_STOP
// DBG_WWDG_STOP
//
// [Bit 11] RW (@ 0x40015808) Debug Window Wachdog stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_WWDG_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_IWDG_STOP ----------------------------
// SVD Line: 1265
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
// DBG_IWDG_STOP
//
// [Bit 12] RW (@ 0x40015808) Debug Independent Wachdog stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_IWDG_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_LPTIM_STOP ---------------------------
// SVD Line: 1270
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
// DBG_LPTIM_STOP
//
// [Bit 31] RW (@ 0x40015808) Debug LPTIM stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_LPTIM_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ1 ---------------------------------
// SVD Line: 1244
// SFDITEM_REG__DBGMCU_APB_FZ1
// APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) APB Freeze Register1
// ( (unsigned int)((DBGMCU_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ1 = (DBGMCU_APB_FZ1 & ~(0x80001C02UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80001C02) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_TIMER3_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_RTC_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_WWDG_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ2 -----------------------------
// SVD Line: 1277
unsigned int DBGMCU_APB_FZ2 __AT (0x4001580C);
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER1_STOP ---------------------------
// SVD Line: 1283
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// DBG_TIMER1_STOP
//
// [Bit 11] RW (@ 0x4001580C) Debug Timer 1 stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER1_STOP
//
//
//
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER14_STOP --------------------------
// SVD Line: 1288
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER14_STOP
// DBG_TIMER14_STOP
//
// [Bit 15] RW (@ 0x4001580C) Debug Timer 14 stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER14_STOP
//
//
//
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER16_STOP --------------------------
// SVD Line: 1293
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER16_STOP
// DBG_TIMER16_STOP
//
// [Bit 17] RW (@ 0x4001580C) Debug Timer 16 stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER16_STOP
//
//
//
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER17_STOP --------------------------
// SVD Line: 1298
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER17_STOP
// DBG_TIMER17_STOP
//
// [Bit 18] RW (@ 0x4001580C) Debug Timer 17 stopped when Core is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER17_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ2 ---------------------------------
// SVD Line: 1277
// SFDITEM_REG__DBGMCU_APB_FZ2
// APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) APB Freeze Register2
// ( (unsigned int)((DBGMCU_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ2 = (DBGMCU_APB_FZ2 & ~(0x68800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x68800) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER14_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER16_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER17_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 1208
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_APB_FZ1
// - SFDITEM_REG__DBGMCU_APB_FZ2
//
//
// ----------------------------- Register Item Address: DIV_DEND --------------------------------
// SVD Line: 1318
unsigned int DIV_DEND __AT (0x40023800);
// -------------------------------- Field Item: DIV_DEND_DEND -----------------------------------
// SVD Line: 1324
// - SFDITEM_FIELD__DIV_DEND_DEND
// DEND
//
// [Bits 31..0] RW (@ 0x40023800) Dividend
//
// ( (unsigned int)((DIV_DEND >> 0) & 0xFFFFFFFF), ((DIV_DEND = (DIV_DEND & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DIV_DEND ------------------------------------
// SVD Line: 1318
// SFDITEM_REG__DIV_DEND
// DEND
//
// [Bits 31..0] RW (@ 0x40023800) Dividend
// ( (unsigned int)((DIV_DEND >> 0) & 0xFFFFFFFF), ((DIV_DEND = (DIV_DEND & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DIV_DEND_DEND
//
//
// ----------------------------- Register Item Address: DIV_SOR ---------------------------------
// SVD Line: 1331
unsigned int DIV_SOR __AT (0x40023804);
// --------------------------------- Field Item: DIV_SOR_SOR ------------------------------------
// SVD Line: 1337
// - SFDITEM_FIELD__DIV_SOR_SOR
// SOR
//
// [Bits 31..0] RW (@ 0x40023804) Divisor
//
// ( (unsigned int)((DIV_SOR >> 0) & 0xFFFFFFFF), ((DIV_SOR = (DIV_SOR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: DIV_SOR ------------------------------------
// SVD Line: 1331
// SFDITEM_REG__DIV_SOR
// SOR
//
// [Bits 31..0] RW (@ 0x40023804) Divisor
// ( (unsigned int)((DIV_SOR >> 0) & 0xFFFFFFFF), ((DIV_SOR = (DIV_SOR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DIV_SOR_SOR
//
//
// ----------------------------- Register Item Address: DIV_QUOT --------------------------------
// SVD Line: 1344
unsigned int DIV_QUOT __AT (0x40023808);
// -------------------------------- Field Item: DIV_QUOT_QUOT -----------------------------------
// SVD Line: 1351
// - SFDITEM_FIELD__DIV_QUOT_QUOT
// QUOT
//
// [Bits 31..0] RO (@ 0x40023808) Quotient
//
// ( (unsigned int)((DIV_QUOT >> 0) & 0xFFFFFFFF) )
//
//
//
// -------------------------------- Register RTree: DIV_QUOT ------------------------------------
// SVD Line: 1344
// SFDITEM_REG__DIV_QUOT
// QUOT
//
// [Bits 31..0] RO (@ 0x40023808) Quotient
// ( (unsigned int)((DIV_QUOT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DIV_QUOT_QUOT
//
//
// ----------------------------- Register Item Address: DIV_REMD --------------------------------
// SVD Line: 1358
unsigned int DIV_REMD __AT (0x4002380C);
// -------------------------------- Field Item: DIV_REMD_REMD -----------------------------------
// SVD Line: 1365
// - SFDITEM_FIELD__DIV_REMD_REMD
// REMD
//
// [Bits 31..0] RO (@ 0x4002380C) Remainder
//
// ( (unsigned int)((DIV_REMD >> 0) & 0xFFFFFFFF) )
//
//
//
// -------------------------------- Register RTree: DIV_REMD ------------------------------------
// SVD Line: 1358
// SFDITEM_REG__DIV_REMD
// REMD
//
// [Bits 31..0] RO (@ 0x4002380C) Remainder
// ( (unsigned int)((DIV_REMD >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DIV_REMD_REMD
//
//
// ----------------------------- Register Item Address: DIV_SIGN --------------------------------
// SVD Line: 1373
unsigned int DIV_SIGN __AT (0x40023810);
// -------------------------------- Field Item: DIV_SIGN_SIGN -----------------------------------
// SVD Line: 1379
// - SFDITEM_FIELD__DIV_SIGN_SIGN
// SIGN
//
// [Bit 0] RW (@ 0x40023810) des SIGN
//
// ( (unsigned int) DIV_SIGN )
// SIGN
//
//
//
// -------------------------------- Register RTree: DIV_SIGN ------------------------------------
// SVD Line: 1373
// SFDITEM_REG__DIV_SIGN
// SIGN
//
// [Bits 31..0] RW (@ 0x40023810) des SIGN
// ( (unsigned int)((DIV_SIGN >> 0) & 0xFFFFFFFF), ((DIV_SIGN = (DIV_SIGN & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__DIV_SIGN_SIGN
//
//
// ----------------------------- Register Item Address: DIV_STAT --------------------------------
// SVD Line: 1386
unsigned int DIV_STAT __AT (0x40023814);
// -------------------------------- Field Item: DIV_STAT_END ------------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__DIV_STAT_END
// END
//
// [Bit 0] RW (@ 0x40023814) des END
//
// ( (unsigned int) DIV_STAT )
// END
//
//
//
// -------------------------------- Field Item: DIV_STAT_ZERO -----------------------------------
// SVD Line: 1397
// - SFDITEM_FIELD__DIV_STAT_ZERO
// ZERO
//
// [Bit 1] RW (@ 0x40023814) des ZERO
//
// ( (unsigned int) DIV_STAT )
// ZERO
//
//
//
// -------------------------------- Register RTree: DIV_STAT ------------------------------------
// SVD Line: 1386
// SFDITEM_REG__DIV_STAT
// STAT
//
// [Bits 31..0] RW (@ 0x40023814) des SIGN
// ( (unsigned int)((DIV_STAT >> 0) & 0xFFFFFFFF), ((DIV_STAT = (DIV_STAT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DIV_STAT_END
// - SFDITEM_FIELD__DIV_STAT_ZERO
//
//
// ---------------------------------- Peripheral View: DIV --------------------------------------
// SVD Line: 1307
// DIV
// DIV
// - SFDITEM_REG__DIV_DEND
// - SFDITEM_REG__DIV_SOR
// - SFDITEM_REG__DIV_QUOT
// - SFDITEM_REG__DIV_REMD
// - SFDITEM_REG__DIV_SIGN
// - SFDITEM_REG__DIV_STAT
//
//
// ----------------------------- Register Item Address: DMA_ISR ---------------------------------
// SVD Line: 1427
unsigned int DMA_ISR __AT (0x40020000);
// -------------------------------- Field Item: DMA_ISR_GIF1 ------------------------------------
// SVD Line: 1434
// - SFDITEM_FIELD__DMA_ISR_GIF1
// GIF1
//
// [Bit 0] RO (@ 0x40020000) Channel 1 Global interrupt flag
//
// ( (unsigned int) DMA_ISR )
// GIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_TCIF1 -----------------------------------
// SVD Line: 1439
// - SFDITEM_FIELD__DMA_ISR_TCIF1
// TCIF1
//
// [Bit 1] RO (@ 0x40020000) Channel 1 Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// TCIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_HTIF1 -----------------------------------
// SVD Line: 1444
// - SFDITEM_FIELD__DMA_ISR_HTIF1
// HTIF1
//
// [Bit 2] RO (@ 0x40020000) Channel 1 Half Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// HTIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF1 -----------------------------------
// SVD Line: 1449
// - SFDITEM_FIELD__DMA_ISR_TEIF1
// TEIF1
//
// [Bit 3] RO (@ 0x40020000) Channel 1 Transfer Error flag
//
// ( (unsigned int) DMA_ISR )
// TEIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_GIF2 ------------------------------------
// SVD Line: 1454
// - SFDITEM_FIELD__DMA_ISR_GIF2
// GIF2
//
// [Bit 4] RO (@ 0x40020000) Channel 2 Global interrupt flag
//
// ( (unsigned int) DMA_ISR )
// GIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_TCIF2 -----------------------------------
// SVD Line: 1459
// - SFDITEM_FIELD__DMA_ISR_TCIF2
// TCIF2
//
// [Bit 5] RO (@ 0x40020000) Channel 2 Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// TCIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_HTIF2 -----------------------------------
// SVD Line: 1464
// - SFDITEM_FIELD__DMA_ISR_HTIF2
// HTIF2
//
// [Bit 6] RO (@ 0x40020000) Channel 2 Half Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// HTIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF2 -----------------------------------
// SVD Line: 1469
// - SFDITEM_FIELD__DMA_ISR_TEIF2
// TEIF2
//
// [Bit 7] RO (@ 0x40020000) Channel 2 Transfer Error flag
//
// ( (unsigned int) DMA_ISR )
// TEIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_GIF3 ------------------------------------
// SVD Line: 1474
// - SFDITEM_FIELD__DMA_ISR_GIF3
// GIF3
//
// [Bit 8] RO (@ 0x40020000) Channel 3 Global interrupt flag
//
// ( (unsigned int) DMA_ISR )
// GIF3
//
//
//
// -------------------------------- Field Item: DMA_ISR_TCIF3 -----------------------------------
// SVD Line: 1479
// - SFDITEM_FIELD__DMA_ISR_TCIF3
// TCIF3
//
// [Bit 9] RO (@ 0x40020000) Channel 3 Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// TCIF3
//
//
//
// -------------------------------- Field Item: DMA_ISR_HTIF3 -----------------------------------
// SVD Line: 1484
// - SFDITEM_FIELD__DMA_ISR_HTIF3
// HTIF3
//
// [Bit 10] RO (@ 0x40020000) Channel 3 Half Transfer Complete flag
//
// ( (unsigned int) DMA_ISR )
// HTIF3
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF3 -----------------------------------
// SVD Line: 1489
// - SFDITEM_FIELD__DMA_ISR_TEIF3
// TEIF3
//
// [Bit 11] RO (@ 0x40020000) Channel 3 Transfer Error flag
//
// ( (unsigned int) DMA_ISR )
// TEIF3
//
//
//
// --------------------------------- Register RTree: DMA_ISR ------------------------------------
// SVD Line: 1427
// SFDITEM_REG__DMA_ISR
// ISR
//
// [Bits 31..0] RO (@ 0x40020000) DMA interrupt status register(DMA_ISR)
// ( (unsigned int)((DMA_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DMA_ISR_GIF1
// - SFDITEM_FIELD__DMA_ISR_TCIF1
// - SFDITEM_FIELD__DMA_ISR_HTIF1
// - SFDITEM_FIELD__DMA_ISR_TEIF1
// - SFDITEM_FIELD__DMA_ISR_GIF2
// - SFDITEM_FIELD__DMA_ISR_TCIF2
// - SFDITEM_FIELD__DMA_ISR_HTIF2
// - SFDITEM_FIELD__DMA_ISR_TEIF2
// - SFDITEM_FIELD__DMA_ISR_GIF3
// - SFDITEM_FIELD__DMA_ISR_TCIF3
// - SFDITEM_FIELD__DMA_ISR_HTIF3
// - SFDITEM_FIELD__DMA_ISR_TEIF3
//
//
// ----------------------------- Register Item Address: DMA_IFCR --------------------------------
// SVD Line: 1496
unsigned int DMA_IFCR __AT (0x40020004);
// ------------------------------- Field Item: DMA_IFCR_CGIF1 -----------------------------------
// SVD Line: 1503
// - SFDITEM_FIELD__DMA_IFCR_CGIF1
// CGIF1
//
// [Bit 0] WO (@ 0x40020004) Channel 1 Global interrupt clear
//
// ( (unsigned int) DMA_IFCR )
// CGIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTCIF1 ----------------------------------
// SVD Line: 1508
// - SFDITEM_FIELD__DMA_IFCR_CTCIF1
// CTCIF1
//
// [Bit 1] WO (@ 0x40020004) Channel 1 Transfer Complete clear
//
// ( (unsigned int) DMA_IFCR )
// CTCIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CHTIF1 ----------------------------------
// SVD Line: 1513
// - SFDITEM_FIELD__DMA_IFCR_CHTIF1
// CHTIF1
//
// [Bit 2] WO (@ 0x40020004) Channel 1 Half Transfer clear
//
// ( (unsigned int) DMA_IFCR )
// CHTIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF1 ----------------------------------
// SVD Line: 1518
// - SFDITEM_FIELD__DMA_IFCR_CTEIF1
// CTEIF1
//
// [Bit 3] WO (@ 0x40020004) Channel 1 Transfer Error clear
//
// ( (unsigned int) DMA_IFCR )
// CTEIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CGIF2 -----------------------------------
// SVD Line: 1523
// - SFDITEM_FIELD__DMA_IFCR_CGIF2
// CGIF2
//
// [Bit 4] WO (@ 0x40020004) Channel 2 Global interrupt clear
//
// ( (unsigned int) DMA_IFCR )
// CGIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTCIF2 ----------------------------------
// SVD Line: 1528
// - SFDITEM_FIELD__DMA_IFCR_CTCIF2
// CTCIF2
//
// [Bit 5] WO (@ 0x40020004) Channel 2 Transfer Complete clear
//
// ( (unsigned int) DMA_IFCR )
// CTCIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CHTIF2 ----------------------------------
// SVD Line: 1533
// - SFDITEM_FIELD__DMA_IFCR_CHTIF2
// CHTIF2
//
// [Bit 6] WO (@ 0x40020004) Channel 2 Half Transfer clear
//
// ( (unsigned int) DMA_IFCR )
// CHTIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF2 ----------------------------------
// SVD Line: 1538
// - SFDITEM_FIELD__DMA_IFCR_CTEIF2
// CTEIF2
//
// [Bit 7] WO (@ 0x40020004) Channel 2 Transfer Error clear
//
// ( (unsigned int) DMA_IFCR )
// CTEIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CGIF3 -----------------------------------
// SVD Line: 1543
// - SFDITEM_FIELD__DMA_IFCR_CGIF3
// CGIF3
//
// [Bit 8] WO (@ 0x40020004) Channel 3 Global interrupt clear
//
// ( (unsigned int) DMA_IFCR )
// CGIF3
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTCIF3 ----------------------------------
// SVD Line: 1548
// - SFDITEM_FIELD__DMA_IFCR_CTCIF3
// CTCIF3
//
// [Bit 9] WO (@ 0x40020004) Channel 3 Transfer Complete clear
//
// ( (unsigned int) DMA_IFCR )
// CTCIF3
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CHTIF3 ----------------------------------
// SVD Line: 1553
// - SFDITEM_FIELD__DMA_IFCR_CHTIF3
// CHTIF3
//
// [Bit 10] WO (@ 0x40020004) Channel 3 Half Transfer clear
//
// ( (unsigned int) DMA_IFCR )
// CHTIF3
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF3 ----------------------------------
// SVD Line: 1558
// - SFDITEM_FIELD__DMA_IFCR_CTEIF3
// CTEIF3
//
// [Bit 11] WO (@ 0x40020004) Channel 3 Transfer Error clear
//
// ( (unsigned int) DMA_IFCR )
// CTEIF3
//
//
//
// -------------------------------- Register RTree: DMA_IFCR ------------------------------------
// SVD Line: 1496
// SFDITEM_REG__DMA_IFCR
// IFCR
//
// [Bits 31..0] WO (@ 0x40020004) DMA interrupt flag clear register(DMA_IFCR)
// ( (unsigned int)((DMA_IFCR >> 0) & 0xFFFFFFFF), ((DMA_IFCR = (DMA_IFCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_IFCR_CGIF1
// - SFDITEM_FIELD__DMA_IFCR_CTCIF1
// - SFDITEM_FIELD__DMA_IFCR_CHTIF1
// - SFDITEM_FIELD__DMA_IFCR_CTEIF1
// - SFDITEM_FIELD__DMA_IFCR_CGIF2
// - SFDITEM_FIELD__DMA_IFCR_CTCIF2
// - SFDITEM_FIELD__DMA_IFCR_CHTIF2
// - SFDITEM_FIELD__DMA_IFCR_CTEIF2
// - SFDITEM_FIELD__DMA_IFCR_CGIF3
// - SFDITEM_FIELD__DMA_IFCR_CTCIF3
// - SFDITEM_FIELD__DMA_IFCR_CHTIF3
// - SFDITEM_FIELD__DMA_IFCR_CTEIF3
//
//
// ----------------------------- Register Item Address: DMA_CCR1 --------------------------------
// SVD Line: 1565
unsigned int DMA_CCR1 __AT (0x40020008);
// --------------------------------- Field Item: DMA_CCR1_EN ------------------------------------
// SVD Line: 1571
// - SFDITEM_FIELD__DMA_CCR1_EN
// EN
//
// [Bit 0] RW (@ 0x40020008) Channel enable
//
// ( (unsigned int) DMA_CCR1 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR1_TCIE -----------------------------------
// SVD Line: 1576
// - SFDITEM_FIELD__DMA_CCR1_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x40020008) Transfer complete interrupt enable
//
// ( (unsigned int) DMA_CCR1 )
// TCIE
//
//
//
// -------------------------------- Field Item: DMA_CCR1_HTIE -----------------------------------
// SVD Line: 1581
// - SFDITEM_FIELD__DMA_CCR1_HTIE
// HTIE
//
// [Bit 2] RW (@ 0x40020008) Half Transfer interrupt enable
//
// ( (unsigned int) DMA_CCR1 )
// HTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR1_TEIE -----------------------------------
// SVD Line: 1586
// - SFDITEM_FIELD__DMA_CCR1_TEIE
// TEIE
//
// [Bit 3] RW (@ 0x40020008) Transfer error interrupt enable
//
// ( (unsigned int) DMA_CCR1 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR1_DIR ------------------------------------
// SVD Line: 1591
// - SFDITEM_FIELD__DMA_CCR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40020008) Data transfer direction
//
// ( (unsigned int) DMA_CCR1 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR1_CIRC -----------------------------------
// SVD Line: 1596
// - SFDITEM_FIELD__DMA_CCR1_CIRC
// CIRC
//
// [Bit 5] RW (@ 0x40020008) Circular mode
//
// ( (unsigned int) DMA_CCR1 )
// CIRC
//
//
//
// -------------------------------- Field Item: DMA_CCR1_PINC -----------------------------------
// SVD Line: 1601
// - SFDITEM_FIELD__DMA_CCR1_PINC
// PINC
//
// [Bit 6] RW (@ 0x40020008) Peripheral increment mode
//
// ( (unsigned int) DMA_CCR1 )
// PINC
//
//
//
// -------------------------------- Field Item: DMA_CCR1_MINC -----------------------------------
// SVD Line: 1606
// - SFDITEM_FIELD__DMA_CCR1_MINC
// MINC
//
// [Bit 7] RW (@ 0x40020008) Memory increment mode
//
// ( (unsigned int) DMA_CCR1 )
// MINC
//
//
//
// ------------------------------- Field Item: DMA_CCR1_PSIZE -----------------------------------
// SVD Line: 1611
// - SFDITEM_FIELD__DMA_CCR1_PSIZE
// PSIZE
//
// [Bits 9..8] RW (@ 0x40020008) Peripheral size
//
// ( (unsigned char)((DMA_CCR1 >> 8) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR1_MSIZE -----------------------------------
// SVD Line: 1616
// - SFDITEM_FIELD__DMA_CCR1_MSIZE
// MSIZE
//
// [Bits 11..10] RW (@ 0x40020008) Memory size
//
// ( (unsigned char)((DMA_CCR1 >> 10) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR1_PL ------------------------------------
// SVD Line: 1621
// - SFDITEM_FIELD__DMA_CCR1_PL
// PL
//
// [Bits 13..12] RW (@ 0x40020008) Channel Priority level
//
// ( (unsigned char)((DMA_CCR1 >> 12) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR1_MEM2MEM ----------------------------------
// SVD Line: 1626
// - SFDITEM_FIELD__DMA_CCR1_MEM2MEM
// MEM2MEM
//
// [Bit 14] RW (@ 0x40020008) Memory to memory mode
//
// ( (unsigned int) DMA_CCR1 )
// MEM2MEM
//
//
//
// -------------------------------- Register RTree: DMA_CCR1 ------------------------------------
// SVD Line: 1565
// SFDITEM_REG__DMA_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40020008) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR1 >> 0) & 0xFFFFFFFF), ((DMA_CCR1 = (DMA_CCR1 & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR1_EN
// - SFDITEM_FIELD__DMA_CCR1_TCIE
// - SFDITEM_FIELD__DMA_CCR1_HTIE
// - SFDITEM_FIELD__DMA_CCR1_TEIE
// - SFDITEM_FIELD__DMA_CCR1_DIR
// - SFDITEM_FIELD__DMA_CCR1_CIRC
// - SFDITEM_FIELD__DMA_CCR1_PINC
// - SFDITEM_FIELD__DMA_CCR1_MINC
// - SFDITEM_FIELD__DMA_CCR1_PSIZE
// - SFDITEM_FIELD__DMA_CCR1_MSIZE
// - SFDITEM_FIELD__DMA_CCR1_PL
// - SFDITEM_FIELD__DMA_CCR1_MEM2MEM
//
//
// ---------------------------- Register Item Address: DMA_CNDTR1 -------------------------------
// SVD Line: 1633
unsigned int DMA_CNDTR1 __AT (0x4002000C);
// ------------------------------- Field Item: DMA_CNDTR1_NDT -----------------------------------
// SVD Line: 1639
// - SFDITEM_FIELD__DMA_CNDTR1_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x4002000C) Number of data to transfer
//
// ( (unsigned short)((DMA_CNDTR1 >> 0) & 0xFFFF), ((DMA_CNDTR1 = (DMA_CNDTR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR1 -----------------------------------
// SVD Line: 1633
// SFDITEM_REG__DMA_CNDTR1
// CNDTR1
//
// [Bits 31..0] RW (@ 0x4002000C) DMA channel 1 number of dataregister
// ( (unsigned int)((DMA_CNDTR1 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR1 = (DMA_CNDTR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR1_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR1 --------------------------------
// SVD Line: 1646
unsigned int DMA_CPAR1 __AT (0x40020010);
// -------------------------------- Field Item: DMA_CPAR1_PA ------------------------------------
// SVD Line: 1652
// - SFDITEM_FIELD__DMA_CPAR1_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020010) Peripheral address
//
// ( (unsigned int)((DMA_CPAR1 >> 0) & 0xFFFFFFFF), ((DMA_CPAR1 = (DMA_CPAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR1 -----------------------------------
// SVD Line: 1646
// SFDITEM_REG__DMA_CPAR1
// CPAR1
//
// [Bits 31..0] RW (@ 0x40020010) DMA channel 1 peripheral addressregister
// ( (unsigned int)((DMA_CPAR1 >> 0) & 0xFFFFFFFF), ((DMA_CPAR1 = (DMA_CPAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR1_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR1 --------------------------------
// SVD Line: 1659
unsigned int DMA_CMAR1 __AT (0x40020014);
// -------------------------------- Field Item: DMA_CMAR1_MA ------------------------------------
// SVD Line: 1665
// - SFDITEM_FIELD__DMA_CMAR1_MA
// MA
//
// [Bits 31..0] RW (@ 0x40020014) Memory address
//
// ( (unsigned int)((DMA_CMAR1 >> 0) & 0xFFFFFFFF), ((DMA_CMAR1 = (DMA_CMAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR1 -----------------------------------
// SVD Line: 1659
// SFDITEM_REG__DMA_CMAR1
// CMAR1
//
// [Bits 31..0] RW (@ 0x40020014) DMA channel 1 memory addressregister
// ( (unsigned int)((DMA_CMAR1 >> 0) & 0xFFFFFFFF), ((DMA_CMAR1 = (DMA_CMAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR1_MA
//
//
// ----------------------------- Register Item Address: DMA_CCR2 --------------------------------
// SVD Line: 1672
unsigned int DMA_CCR2 __AT (0x4002001C);
// --------------------------------- Field Item: DMA_CCR2_EN ------------------------------------
// SVD Line: 1678
// - SFDITEM_FIELD__DMA_CCR2_EN
// EN
//
// [Bit 0] RW (@ 0x4002001C) Channel enable
//
// ( (unsigned int) DMA_CCR2 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR2_TCIE -----------------------------------
// SVD Line: 1683
// - SFDITEM_FIELD__DMA_CCR2_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x4002001C) Transfer complete interrupt enable
//
// ( (unsigned int) DMA_CCR2 )
// TCIE
//
//
//
// -------------------------------- Field Item: DMA_CCR2_HTIE -----------------------------------
// SVD Line: 1688
// - SFDITEM_FIELD__DMA_CCR2_HTIE
// HTIE
//
// [Bit 2] RW (@ 0x4002001C) Half Transfer interrupt enable
//
// ( (unsigned int) DMA_CCR2 )
// HTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR2_TEIE -----------------------------------
// SVD Line: 1693
// - SFDITEM_FIELD__DMA_CCR2_TEIE
// TEIE
//
// [Bit 3] RW (@ 0x4002001C) Transfer error interrupt enable
//
// ( (unsigned int) DMA_CCR2 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR2_DIR ------------------------------------
// SVD Line: 1698
// - SFDITEM_FIELD__DMA_CCR2_DIR
// DIR
//
// [Bit 4] RW (@ 0x4002001C) Data transfer direction
//
// ( (unsigned int) DMA_CCR2 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR2_CIRC -----------------------------------
// SVD Line: 1703
// - SFDITEM_FIELD__DMA_CCR2_CIRC
// CIRC
//
// [Bit 5] RW (@ 0x4002001C) Circular mode
//
// ( (unsigned int) DMA_CCR2 )
// CIRC
//
//
//
// -------------------------------- Field Item: DMA_CCR2_PINC -----------------------------------
// SVD Line: 1708
// - SFDITEM_FIELD__DMA_CCR2_PINC
// PINC
//
// [Bit 6] RW (@ 0x4002001C) Peripheral increment mode
//
// ( (unsigned int) DMA_CCR2 )
// PINC
//
//
//
// -------------------------------- Field Item: DMA_CCR2_MINC -----------------------------------
// SVD Line: 1713
// - SFDITEM_FIELD__DMA_CCR2_MINC
// MINC
//
// [Bit 7] RW (@ 0x4002001C) Memory increment mode
//
// ( (unsigned int) DMA_CCR2 )
// MINC
//
//
//
// ------------------------------- Field Item: DMA_CCR2_PSIZE -----------------------------------
// SVD Line: 1718
// - SFDITEM_FIELD__DMA_CCR2_PSIZE
// PSIZE
//
// [Bits 9..8] RW (@ 0x4002001C) Peripheral size
//
// ( (unsigned char)((DMA_CCR2 >> 8) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR2_MSIZE -----------------------------------
// SVD Line: 1723
// - SFDITEM_FIELD__DMA_CCR2_MSIZE
// MSIZE
//
// [Bits 11..10] RW (@ 0x4002001C) Memory size
//
// ( (unsigned char)((DMA_CCR2 >> 10) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR2_PL ------------------------------------
// SVD Line: 1728
// - SFDITEM_FIELD__DMA_CCR2_PL
// PL
//
// [Bits 13..12] RW (@ 0x4002001C) Channel Priority level
//
// ( (unsigned char)((DMA_CCR2 >> 12) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR2_MEM2MEM ----------------------------------
// SVD Line: 1733
// - SFDITEM_FIELD__DMA_CCR2_MEM2MEM
// MEM2MEM
//
// [Bit 14] RW (@ 0x4002001C) Memory to memory mode
//
// ( (unsigned int) DMA_CCR2 )
// MEM2MEM
//
//
//
// -------------------------------- Register RTree: DMA_CCR2 ------------------------------------
// SVD Line: 1672
// SFDITEM_REG__DMA_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x4002001C) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR2 >> 0) & 0xFFFFFFFF), ((DMA_CCR2 = (DMA_CCR2 & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR2_EN
// - SFDITEM_FIELD__DMA_CCR2_TCIE
// - SFDITEM_FIELD__DMA_CCR2_HTIE
// - SFDITEM_FIELD__DMA_CCR2_TEIE
// - SFDITEM_FIELD__DMA_CCR2_DIR
// - SFDITEM_FIELD__DMA_CCR2_CIRC
// - SFDITEM_FIELD__DMA_CCR2_PINC
// - SFDITEM_FIELD__DMA_CCR2_MINC
// - SFDITEM_FIELD__DMA_CCR2_PSIZE
// - SFDITEM_FIELD__DMA_CCR2_MSIZE
// - SFDITEM_FIELD__DMA_CCR2_PL
// - SFDITEM_FIELD__DMA_CCR2_MEM2MEM
//
//
// ---------------------------- Register Item Address: DMA_CNDTR2 -------------------------------
// SVD Line: 1740
unsigned int DMA_CNDTR2 __AT (0x40020020);
// ------------------------------- Field Item: DMA_CNDTR2_NDT -----------------------------------
// SVD Line: 1746
// - SFDITEM_FIELD__DMA_CNDTR2_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x40020020) Number of data to transfer
//
// ( (unsigned short)((DMA_CNDTR2 >> 0) & 0xFFFF), ((DMA_CNDTR2 = (DMA_CNDTR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR2 -----------------------------------
// SVD Line: 1740
// SFDITEM_REG__DMA_CNDTR2
// CNDTR2
//
// [Bits 31..0] RW (@ 0x40020020) DMA channel 2 number of dataregister
// ( (unsigned int)((DMA_CNDTR2 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR2 = (DMA_CNDTR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR2_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR2 --------------------------------
// SVD Line: 1753
unsigned int DMA_CPAR2 __AT (0x40020024);
// -------------------------------- Field Item: DMA_CPAR2_PA ------------------------------------
// SVD Line: 1759
// - SFDITEM_FIELD__DMA_CPAR2_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020024) Peripheral address
//
// ( (unsigned int)((DMA_CPAR2 >> 0) & 0xFFFFFFFF), ((DMA_CPAR2 = (DMA_CPAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR2 -----------------------------------
// SVD Line: 1753
// SFDITEM_REG__DMA_CPAR2
// CPAR2
//
// [Bits 31..0] RW (@ 0x40020024) DMA channel 2 peripheral addressregister
// ( (unsigned int)((DMA_CPAR2 >> 0) & 0xFFFFFFFF), ((DMA_CPAR2 = (DMA_CPAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR2_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR2 --------------------------------
// SVD Line: 1766
unsigned int DMA_CMAR2 __AT (0x40020028);
// -------------------------------- Field Item: DMA_CMAR2_MA ------------------------------------
// SVD Line: 1772
// - SFDITEM_FIELD__DMA_CMAR2_MA
// MA
//
// [Bits 31..0] RW (@ 0x40020028) Memory address
//
// ( (unsigned int)((DMA_CMAR2 >> 0) & 0xFFFFFFFF), ((DMA_CMAR2 = (DMA_CMAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR2 -----------------------------------
// SVD Line: 1766
// SFDITEM_REG__DMA_CMAR2
// CMAR2
//
// [Bits 31..0] RW (@ 0x40020028) DMA channel 2 memory addressregister
// ( (unsigned int)((DMA_CMAR2 >> 0) & 0xFFFFFFFF), ((DMA_CMAR2 = (DMA_CMAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR2_MA
//
//
// ----------------------------- Register Item Address: DMA_CCR3 --------------------------------
// SVD Line: 1779
unsigned int DMA_CCR3 __AT (0x40020030);
// --------------------------------- Field Item: DMA_CCR3_EN ------------------------------------
// SVD Line: 1785
// - SFDITEM_FIELD__DMA_CCR3_EN
// EN
//
// [Bit 0] RW (@ 0x40020030) Channel enable
//
// ( (unsigned int) DMA_CCR3 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR3_TCIE -----------------------------------
// SVD Line: 1790
// - SFDITEM_FIELD__DMA_CCR3_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x40020030) Transfer complete interrupt enable
//
// ( (unsigned int) DMA_CCR3 )
// TCIE
//
//
//
// -------------------------------- Field Item: DMA_CCR3_HTIE -----------------------------------
// SVD Line: 1795
// - SFDITEM_FIELD__DMA_CCR3_HTIE
// HTIE
//
// [Bit 2] RW (@ 0x40020030) Half Transfer interrupt enable
//
// ( (unsigned int) DMA_CCR3 )
// HTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR3_TEIE -----------------------------------
// SVD Line: 1800
// - SFDITEM_FIELD__DMA_CCR3_TEIE
// TEIE
//
// [Bit 3] RW (@ 0x40020030) Transfer error interrupt enable
//
// ( (unsigned int) DMA_CCR3 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR3_DIR ------------------------------------
// SVD Line: 1805
// - SFDITEM_FIELD__DMA_CCR3_DIR
// DIR
//
// [Bit 4] RW (@ 0x40020030) Data transfer direction
//
// ( (unsigned int) DMA_CCR3 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR3_CIRC -----------------------------------
// SVD Line: 1810
// - SFDITEM_FIELD__DMA_CCR3_CIRC
// CIRC
//
// [Bit 5] RW (@ 0x40020030) Circular mode
//
// ( (unsigned int) DMA_CCR3 )
// CIRC
//
//
//
// -------------------------------- Field Item: DMA_CCR3_PINC -----------------------------------
// SVD Line: 1815
// - SFDITEM_FIELD__DMA_CCR3_PINC
// PINC
//
// [Bit 6] RW (@ 0x40020030) Peripheral increment mode
//
// ( (unsigned int) DMA_CCR3 )
// PINC
//
//
//
// -------------------------------- Field Item: DMA_CCR3_MINC -----------------------------------
// SVD Line: 1820
// - SFDITEM_FIELD__DMA_CCR3_MINC
// MINC
//
// [Bit 7] RW (@ 0x40020030) Memory increment mode
//
// ( (unsigned int) DMA_CCR3 )
// MINC
//
//
//
// ------------------------------- Field Item: DMA_CCR3_PSIZE -----------------------------------
// SVD Line: 1825
// - SFDITEM_FIELD__DMA_CCR3_PSIZE
// PSIZE
//
// [Bits 9..8] RW (@ 0x40020030) Peripheral size
//
// ( (unsigned char)((DMA_CCR3 >> 8) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR3_MSIZE -----------------------------------
// SVD Line: 1830
// - SFDITEM_FIELD__DMA_CCR3_MSIZE
// MSIZE
//
// [Bits 11..10] RW (@ 0x40020030) Memory size
//
// ( (unsigned char)((DMA_CCR3 >> 10) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR3_PL ------------------------------------
// SVD Line: 1835
// - SFDITEM_FIELD__DMA_CCR3_PL
// PL
//
// [Bits 13..12] RW (@ 0x40020030) Channel Priority level
//
// ( (unsigned char)((DMA_CCR3 >> 12) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR3_MEM2MEM ----------------------------------
// SVD Line: 1840
// - SFDITEM_FIELD__DMA_CCR3_MEM2MEM
// MEM2MEM
//
// [Bit 14] RW (@ 0x40020030) Memory to memory mode
//
// ( (unsigned int) DMA_CCR3 )
// MEM2MEM
//
//
//
// -------------------------------- Register RTree: DMA_CCR3 ------------------------------------
// SVD Line: 1779
// SFDITEM_REG__DMA_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40020030) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR3 >> 0) & 0xFFFFFFFF), ((DMA_CCR3 = (DMA_CCR3 & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR3_EN
// - SFDITEM_FIELD__DMA_CCR3_TCIE
// - SFDITEM_FIELD__DMA_CCR3_HTIE
// - SFDITEM_FIELD__DMA_CCR3_TEIE
// - SFDITEM_FIELD__DMA_CCR3_DIR
// - SFDITEM_FIELD__DMA_CCR3_CIRC
// - SFDITEM_FIELD__DMA_CCR3_PINC
// - SFDITEM_FIELD__DMA_CCR3_MINC
// - SFDITEM_FIELD__DMA_CCR3_PSIZE
// - SFDITEM_FIELD__DMA_CCR3_MSIZE
// - SFDITEM_FIELD__DMA_CCR3_PL
// - SFDITEM_FIELD__DMA_CCR3_MEM2MEM
//
//
// ---------------------------- Register Item Address: DMA_CNDTR3 -------------------------------
// SVD Line: 1847
unsigned int DMA_CNDTR3 __AT (0x40020034);
// ------------------------------- Field Item: DMA_CNDTR3_NDT -----------------------------------
// SVD Line: 1853
// - SFDITEM_FIELD__DMA_CNDTR3_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x40020034) Number of data to transfer
//
// ( (unsigned short)((DMA_CNDTR3 >> 0) & 0xFFFF), ((DMA_CNDTR3 = (DMA_CNDTR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR3 -----------------------------------
// SVD Line: 1847
// SFDITEM_REG__DMA_CNDTR3
// CNDTR3
//
// [Bits 31..0] RW (@ 0x40020034) DMA channel 3 number of dataregister
// ( (unsigned int)((DMA_CNDTR3 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR3 = (DMA_CNDTR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR3_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR3 --------------------------------
// SVD Line: 1860
unsigned int DMA_CPAR3 __AT (0x40020038);
// -------------------------------- Field Item: DMA_CPAR3_PA ------------------------------------
// SVD Line: 1866
// - SFDITEM_FIELD__DMA_CPAR3_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020038) Peripheral address
//
// ( (unsigned int)((DMA_CPAR3 >> 0) & 0xFFFFFFFF), ((DMA_CPAR3 = (DMA_CPAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR3 -----------------------------------
// SVD Line: 1860
// SFDITEM_REG__DMA_CPAR3
// CPAR3
//
// [Bits 31..0] RW (@ 0x40020038) DMA channel 3 peripheral addressregister
// ( (unsigned int)((DMA_CPAR3 >> 0) & 0xFFFFFFFF), ((DMA_CPAR3 = (DMA_CPAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR3_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR3 --------------------------------
// SVD Line: 1873
unsigned int DMA_CMAR3 __AT (0x4002003C);
// -------------------------------- Field Item: DMA_CMAR3_MA ------------------------------------
// SVD Line: 1879
// - SFDITEM_FIELD__DMA_CMAR3_MA
// MA
//
// [Bits 31..0] RW (@ 0x4002003C) Memory address
//
// ( (unsigned int)((DMA_CMAR3 >> 0) & 0xFFFFFFFF), ((DMA_CMAR3 = (DMA_CMAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR3 -----------------------------------
// SVD Line: 1873
// SFDITEM_REG__DMA_CMAR3
// CMAR3
//
// [Bits 31..0] RW (@ 0x4002003C) DMA channel 3 memory addressregister
// ( (unsigned int)((DMA_CMAR3 >> 0) & 0xFFFFFFFF), ((DMA_CMAR3 = (DMA_CMAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR3_MA
//
//
// ---------------------------------- Peripheral View: DMA --------------------------------------
// SVD Line: 1406
// DMA
// DMA
// - SFDITEM_REG__DMA_ISR
// - SFDITEM_REG__DMA_IFCR
// - SFDITEM_REG__DMA_CCR1
// - SFDITEM_REG__DMA_CNDTR1
// - SFDITEM_REG__DMA_CPAR1
// - SFDITEM_REG__DMA_CMAR1
// - SFDITEM_REG__DMA_CCR2
// - SFDITEM_REG__DMA_CNDTR2
// - SFDITEM_REG__DMA_CPAR2
// - SFDITEM_REG__DMA_CMAR2
// - SFDITEM_REG__DMA_CCR3
// - SFDITEM_REG__DMA_CNDTR3
// - SFDITEM_REG__DMA_CPAR3
// - SFDITEM_REG__DMA_CMAR3
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 1919
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 1925
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 1930
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 1935
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 1940
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 1945
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 1950
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 1955
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 1960
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT8 -----------------------------------
// SVD Line: 1965
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// RT8
//
// [Bit 8] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT8
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT9 -----------------------------------
// SVD Line: 1970
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// RT9
//
// [Bit 9] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT9
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT10 -----------------------------------
// SVD Line: 1975
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// RT10
//
// [Bit 10] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT10
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT11 -----------------------------------
// SVD Line: 1980
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// RT11
//
// [Bit 11] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT11
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT12 -----------------------------------
// SVD Line: 1985
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// RT12
//
// [Bit 12] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT12
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT13 -----------------------------------
// SVD Line: 1990
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// RT13
//
// [Bit 13] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT13
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT14 -----------------------------------
// SVD Line: 1995
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// RT14
//
// [Bit 14] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT14
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT15 -----------------------------------
// SVD Line: 2000
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// RT15
//
// [Bit 15] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT15
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT16 -----------------------------------
// SVD Line: 2005
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// RT16
//
// [Bit 16] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT16
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT17 -----------------------------------
// SVD Line: 2010
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// RT17
//
// [Bit 17] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT17
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT18 -----------------------------------
// SVD Line: 2015
// - SFDITEM_FIELD__EXTI_RTSR_RT18
// RT18
//
// [Bit 18] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT18
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 1919
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selectionregister
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// - SFDITEM_FIELD__EXTI_RTSR_RT18
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 2022
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 2028
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 2033
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 2038
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 2043
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 2048
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 2053
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 2058
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 2063
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT8 -----------------------------------
// SVD Line: 2068
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// FT8
//
// [Bit 8] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT8
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT9 -----------------------------------
// SVD Line: 2073
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// FT9
//
// [Bit 9] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT9
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT10 -----------------------------------
// SVD Line: 2078
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// FT10
//
// [Bit 10] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT10
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT11 -----------------------------------
// SVD Line: 2083
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// FT11
//
// [Bit 11] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT11
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT12 -----------------------------------
// SVD Line: 2088
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// FT12
//
// [Bit 12] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT12
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT13 -----------------------------------
// SVD Line: 2093
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// FT13
//
// [Bit 13] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT13
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT14 -----------------------------------
// SVD Line: 2098
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// FT14
//
// [Bit 14] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT14
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT15 -----------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// FT15
//
// [Bit 15] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT15
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT16 -----------------------------------
// SVD Line: 2108
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// FT16
//
// [Bit 16] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT16
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT17 -----------------------------------
// SVD Line: 2113
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// FT17
//
// [Bit 17] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT17
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT18 -----------------------------------
// SVD Line: 2118
// - SFDITEM_FIELD__EXTI_FTSR_FT18
// FT18
//
// [Bit 18] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT18
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 2022
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selectionregister
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// - SFDITEM_FIELD__EXTI_FTSR_FT18
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 2125
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------- Field Item: EXTI_SWIER_SWI0 ----------------------------------
// SVD Line: 2131
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// SWI0
//
// [Bit 0] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI0
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI1 ----------------------------------
// SVD Line: 2136
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// SWI1
//
// [Bit 1] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI1
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI2 ----------------------------------
// SVD Line: 2141
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// SWI2
//
// [Bit 2] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI2
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI3 ----------------------------------
// SVD Line: 2146
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// SWI3
//
// [Bit 3] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI3
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI4 ----------------------------------
// SVD Line: 2151
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// SWI4
//
// [Bit 4] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI4
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI5 ----------------------------------
// SVD Line: 2156
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// SWI5
//
// [Bit 5] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI5
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI6 ----------------------------------
// SVD Line: 2161
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// SWI6
//
// [Bit 6] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI6
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI7 ----------------------------------
// SVD Line: 2166
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// SWI7
//
// [Bit 7] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI7
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI8 ----------------------------------
// SVD Line: 2171
// - SFDITEM_FIELD__EXTI_SWIER_SWI8
// SWI8
//
// [Bit 8] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI8
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI9 ----------------------------------
// SVD Line: 2176
// - SFDITEM_FIELD__EXTI_SWIER_SWI9
// SWI9
//
// [Bit 9] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI9
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI10 ----------------------------------
// SVD Line: 2181
// - SFDITEM_FIELD__EXTI_SWIER_SWI10
// SWI10
//
// [Bit 10] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI10
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI11 ----------------------------------
// SVD Line: 2186
// - SFDITEM_FIELD__EXTI_SWIER_SWI11
// SWI11
//
// [Bit 11] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI11
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI12 ----------------------------------
// SVD Line: 2191
// - SFDITEM_FIELD__EXTI_SWIER_SWI12
// SWI12
//
// [Bit 12] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI12
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI13 ----------------------------------
// SVD Line: 2196
// - SFDITEM_FIELD__EXTI_SWIER_SWI13
// SWI13
//
// [Bit 13] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI13
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI14 ----------------------------------
// SVD Line: 2201
// - SFDITEM_FIELD__EXTI_SWIER_SWI14
// SWI14
//
// [Bit 14] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI14
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI15 ----------------------------------
// SVD Line: 2206
// - SFDITEM_FIELD__EXTI_SWIER_SWI15
// SWI15
//
// [Bit 15] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI15
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI16 ----------------------------------
// SVD Line: 2211
// - SFDITEM_FIELD__EXTI_SWIER_SWI16
// SWI16
//
// [Bit 16] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI16
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI17 ----------------------------------
// SVD Line: 2216
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// SWI17
//
// [Bit 17] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI17
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI18 ----------------------------------
// SVD Line: 2221
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
// SWI18
//
// [Bit 18] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI18
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 2125
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt eventregister
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// - SFDITEM_FIELD__EXTI_SWIER_SWI8
// - SFDITEM_FIELD__EXTI_SWIER_SWI9
// - SFDITEM_FIELD__EXTI_SWIER_SWI10
// - SFDITEM_FIELD__EXTI_SWIER_SWI11
// - SFDITEM_FIELD__EXTI_SWIER_SWI12
// - SFDITEM_FIELD__EXTI_SWIER_SWI13
// - SFDITEM_FIELD__EXTI_SWIER_SWI14
// - SFDITEM_FIELD__EXTI_SWIER_SWI15
// - SFDITEM_FIELD__EXTI_SWIER_SWI16
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 2228
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 2234
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 2239
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 2244
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 2249
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 2254
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 2259
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 2264
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 2269
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR8 ------------------------------------
// SVD Line: 2274
// - SFDITEM_FIELD__EXTI_PR_PR8
// PR8
//
// [Bit 8] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR8
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR9 ------------------------------------
// SVD Line: 2279
// - SFDITEM_FIELD__EXTI_PR_PR9
// PR9
//
// [Bit 9] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR9
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR10 ------------------------------------
// SVD Line: 2284
// - SFDITEM_FIELD__EXTI_PR_PR10
// PR10
//
// [Bit 10] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR10
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR11 ------------------------------------
// SVD Line: 2289
// - SFDITEM_FIELD__EXTI_PR_PR11
// PR11
//
// [Bit 11] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR11
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR12 ------------------------------------
// SVD Line: 2294
// - SFDITEM_FIELD__EXTI_PR_PR12
// PR12
//
// [Bit 12] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR12
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR13 ------------------------------------
// SVD Line: 2299
// - SFDITEM_FIELD__EXTI_PR_PR13
// PR13
//
// [Bit 13] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit
//
// ( (unsigned int) EXTI_PR )
// PR13
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR14 ------------------------------------
// SVD Line: 2304
// - SFDITEM_FIELD__EXTI_PR_PR14
// PR14
//
// [Bit 14] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR14
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR15 ------------------------------------
// SVD Line: 2309
// - SFDITEM_FIELD__EXTI_PR_PR15
// PR15
//
// [Bit 15] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR15
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR16 ------------------------------------
// SVD Line: 2314
// - SFDITEM_FIELD__EXTI_PR_PR16
// PR16
//
// [Bit 16] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR16
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR17 ------------------------------------
// SVD Line: 2319
// - SFDITEM_FIELD__EXTI_PR_PR17
// PR17
//
// [Bit 17] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR17
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR18 ------------------------------------
// SVD Line: 2324
// - SFDITEM_FIELD__EXTI_PR_PR18
// PR18
//
// [Bit 18] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR18
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 2228
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pendingregister
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
// - SFDITEM_FIELD__EXTI_PR_PR8
// - SFDITEM_FIELD__EXTI_PR_PR9
// - SFDITEM_FIELD__EXTI_PR_PR10
// - SFDITEM_FIELD__EXTI_PR_PR11
// - SFDITEM_FIELD__EXTI_PR_PR12
// - SFDITEM_FIELD__EXTI_PR_PR13
// - SFDITEM_FIELD__EXTI_PR_PR14
// - SFDITEM_FIELD__EXTI_PR_PR15
// - SFDITEM_FIELD__EXTI_PR_PR16
// - SFDITEM_FIELD__EXTI_PR_PR17
// - SFDITEM_FIELD__EXTI_PR_PR18
//
//
// --------------------------- Register Item Address: EXTI_EXTICR1 ------------------------------
// SVD Line: 2331
unsigned int EXTI_EXTICR1 __AT (0x40021860);
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI0 ---------------------------------
// SVD Line: 2337
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// EXTI0
//
// [Bits 1..0] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 0) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI1 ---------------------------------
// SVD Line: 2342
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// EXTI1
//
// [Bits 9..8] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 8) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI2 ---------------------------------
// SVD Line: 2347
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// EXTI2
//
// [Bits 17..16] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 16) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI3 ---------------------------------
// SVD Line: 2352
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
// EXTI3
//
// [Bits 25..24] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 24) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR1 ----------------------------------
// SVD Line: 2331
// SFDITEM_REG__EXTI_EXTICR1
// EXTICR1
//
// [Bits 31..0] RW (@ 0x40021860) EXTI external interrupt selectionregister
// ( (unsigned int)((EXTI_EXTICR1 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
//
//
// --------------------------- Register Item Address: EXTI_EXTICR2 ------------------------------
// SVD Line: 2359
unsigned int EXTI_EXTICR2 __AT (0x40021864);
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI4 ---------------------------------
// SVD Line: 2365
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// EXTI4
//
// [Bits 1..0] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 0) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI5 ---------------------------------
// SVD Line: 2370
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// EXTI5
//
// [Bits 9..8] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 8) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI6 ---------------------------------
// SVD Line: 2375
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// EXTI6
//
// [Bits 17..16] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 16) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI7 ---------------------------------
// SVD Line: 2380
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
// EXTI7
//
// [Bits 25..24] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 24) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR2 ----------------------------------
// SVD Line: 2359
// SFDITEM_REG__EXTI_EXTICR2
// EXTICR2
//
// [Bits 31..0] RW (@ 0x40021864) EXTI external interrupt selectionregister
// ( (unsigned int)((EXTI_EXTICR2 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
//
//
// --------------------------- Register Item Address: EXTI_EXTICR3 ------------------------------
// SVD Line: 2387
unsigned int EXTI_EXTICR3 __AT (0x40021868);
// ----------------------------- Field Item: EXTI_EXTICR3_EXTI8 ---------------------------------
// SVD Line: 2393
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI8
// EXTI8
//
// [Bits 1..0] RW (@ 0x40021868) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR3 >> 0) & 0x3), ((EXTI_EXTICR3 = (EXTI_EXTICR3 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR3_EXTI9 ---------------------------------
// SVD Line: 2398
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI9
// EXTI9
//
// [Bits 9..8] RW (@ 0x40021868) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR3 >> 8) & 0x3), ((EXTI_EXTICR3 = (EXTI_EXTICR3 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR3_EXTI10 --------------------------------
// SVD Line: 2403
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI10
// EXTI10
//
// [Bits 17..16] RW (@ 0x40021868) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR3 >> 16) & 0x3), ((EXTI_EXTICR3 = (EXTI_EXTICR3 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR3_EXTI11 --------------------------------
// SVD Line: 2408
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI11
// EXTI11
//
// [Bits 25..24] RW (@ 0x40021868) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR3 >> 24) & 0x3), ((EXTI_EXTICR3 = (EXTI_EXTICR3 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR3 ----------------------------------
// SVD Line: 2387
// SFDITEM_REG__EXTI_EXTICR3
// EXTICR3
//
// [Bits 31..0] RW (@ 0x40021868) EXTI external interrupt selectionregister
// ( (unsigned int)((EXTI_EXTICR3 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR3 = (EXTI_EXTICR3 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI8
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI9
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI10
// - SFDITEM_FIELD__EXTI_EXTICR3_EXTI11
//
//
// --------------------------- Register Item Address: EXTI_EXTICR4 ------------------------------
// SVD Line: 2415
unsigned int EXTI_EXTICR4 __AT (0x4002186C);
// ----------------------------- Field Item: EXTI_EXTICR4_EXTI12 --------------------------------
// SVD Line: 2421
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI12
// EXTI12
//
// [Bits 1..0] RW (@ 0x4002186C) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR4 >> 0) & 0x3), ((EXTI_EXTICR4 = (EXTI_EXTICR4 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR4_EXTI13 --------------------------------
// SVD Line: 2426
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI13
// EXTI13
//
// [Bits 9..8] RW (@ 0x4002186C) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR4 >> 8) & 0x3), ((EXTI_EXTICR4 = (EXTI_EXTICR4 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR4_EXTI14 --------------------------------
// SVD Line: 2431
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI14
// EXTI14
//
// [Bits 17..16] RW (@ 0x4002186C) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR4 >> 16) & 0x3), ((EXTI_EXTICR4 = (EXTI_EXTICR4 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR4_EXTI15 --------------------------------
// SVD Line: 2436
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI15
// EXTI15
//
// [Bits 25..24] RW (@ 0x4002186C) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR4 >> 24) & 0x3), ((EXTI_EXTICR4 = (EXTI_EXTICR4 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR4 ----------------------------------
// SVD Line: 2415
// SFDITEM_REG__EXTI_EXTICR4
// EXTICR4
//
// [Bits 31..0] RW (@ 0x4002186C) EXTI external interrupt selectionregister
// ( (unsigned int)((EXTI_EXTICR4 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR4 = (EXTI_EXTICR4 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI12
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI13
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI14
// - SFDITEM_FIELD__EXTI_EXTICR4_EXTI15
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 2443
unsigned int EXTI_IMR __AT (0x40021880);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 2450
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 2455
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 2460
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 2465
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 2470
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 2475
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 2480
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 2485
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM8 ------------------------------------
// SVD Line: 2490
// - SFDITEM_FIELD__EXTI_IMR_IM8
// IM8
//
// [Bit 8] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM8
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM9 ------------------------------------
// SVD Line: 2495
// - SFDITEM_FIELD__EXTI_IMR_IM9
// IM9
//
// [Bit 9] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM9
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM10 -----------------------------------
// SVD Line: 2500
// - SFDITEM_FIELD__EXTI_IMR_IM10
// IM10
//
// [Bit 10] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM10
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM11 -----------------------------------
// SVD Line: 2505
// - SFDITEM_FIELD__EXTI_IMR_IM11
// IM11
//
// [Bit 11] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM11
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM12 -----------------------------------
// SVD Line: 2510
// - SFDITEM_FIELD__EXTI_IMR_IM12
// IM12
//
// [Bit 12] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM12
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM13 -----------------------------------
// SVD Line: 2515
// - SFDITEM_FIELD__EXTI_IMR_IM13
// IM13
//
// [Bit 13] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM13
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM14 -----------------------------------
// SVD Line: 2520
// - SFDITEM_FIELD__EXTI_IMR_IM14
// IM14
//
// [Bit 14] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM14
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM15 -----------------------------------
// SVD Line: 2525
// - SFDITEM_FIELD__EXTI_IMR_IM15
// IM15
//
// [Bit 15] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM15
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM16 -----------------------------------
// SVD Line: 2530
// - SFDITEM_FIELD__EXTI_IMR_IM16
// IM16
//
// [Bit 16] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM16
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM17 -----------------------------------
// SVD Line: 2535
// - SFDITEM_FIELD__EXTI_IMR_IM17
// IM17
//
// [Bit 17] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM17
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM18 -----------------------------------
// SVD Line: 2540
// - SFDITEM_FIELD__EXTI_IMR_IM18
// IM18
//
// [Bit 18] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM18
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM19 -----------------------------------
// SVD Line: 2545
// - SFDITEM_FIELD__EXTI_IMR_IM19
// IM19
//
// [Bit 19] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM19
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM29 -----------------------------------
// SVD Line: 2550
// - SFDITEM_FIELD__EXTI_IMR_IM29
// IM29
//
// [Bit 29] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM29
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 2443
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021880) EXTI CPU wakeup with interrupt maskregister
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0x200FFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200FFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM8
// - SFDITEM_FIELD__EXTI_IMR_IM9
// - SFDITEM_FIELD__EXTI_IMR_IM10
// - SFDITEM_FIELD__EXTI_IMR_IM11
// - SFDITEM_FIELD__EXTI_IMR_IM12
// - SFDITEM_FIELD__EXTI_IMR_IM13
// - SFDITEM_FIELD__EXTI_IMR_IM14
// - SFDITEM_FIELD__EXTI_IMR_IM15
// - SFDITEM_FIELD__EXTI_IMR_IM16
// - SFDITEM_FIELD__EXTI_IMR_IM17
// - SFDITEM_FIELD__EXTI_IMR_IM18
// - SFDITEM_FIELD__EXTI_IMR_IM19
// - SFDITEM_FIELD__EXTI_IMR_IM29
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 2557
unsigned int EXTI_EMR __AT (0x40021884);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 2563
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 2568
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 2573
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 2578
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 2583
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 2588
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 2593
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 2598
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM8 ------------------------------------
// SVD Line: 2603
// - SFDITEM_FIELD__EXTI_EMR_EM8
// EM8
//
// [Bit 8] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM8
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM9 ------------------------------------
// SVD Line: 2608
// - SFDITEM_FIELD__EXTI_EMR_EM9
// EM9
//
// [Bit 9] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM9
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM10 -----------------------------------
// SVD Line: 2613
// - SFDITEM_FIELD__EXTI_EMR_EM10
// EM10
//
// [Bit 10] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM10
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM11 -----------------------------------
// SVD Line: 2618
// - SFDITEM_FIELD__EXTI_EMR_EM11
// EM11
//
// [Bit 11] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM11
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM12 -----------------------------------
// SVD Line: 2623
// - SFDITEM_FIELD__EXTI_EMR_EM12
// EM12
//
// [Bit 12] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM12
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM13 -----------------------------------
// SVD Line: 2628
// - SFDITEM_FIELD__EXTI_EMR_EM13
// EM13
//
// [Bit 13] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM13
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM14 -----------------------------------
// SVD Line: 2633
// - SFDITEM_FIELD__EXTI_EMR_EM14
// EM14
//
// [Bit 14] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM14
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM15 -----------------------------------
// SVD Line: 2638
// - SFDITEM_FIELD__EXTI_EMR_EM15
// EM15
//
// [Bit 15] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM15
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM16 -----------------------------------
// SVD Line: 2643
// - SFDITEM_FIELD__EXTI_EMR_EM16
// EM16
//
// [Bit 16] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM16
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM17 -----------------------------------
// SVD Line: 2648
// - SFDITEM_FIELD__EXTI_EMR_EM17
// EM17
//
// [Bit 17] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM17
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM18 -----------------------------------
// SVD Line: 2653
// - SFDITEM_FIELD__EXTI_EMR_EM18
// EM18
//
// [Bit 18] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM18
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM19 -----------------------------------
// SVD Line: 2658
// - SFDITEM_FIELD__EXTI_EMR_EM19
// EM19
//
// [Bit 19] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM19
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM29 -----------------------------------
// SVD Line: 2663
// - SFDITEM_FIELD__EXTI_EMR_EM29
// EM29
//
// [Bit 29] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM29
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 2557
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x40021884) EXTI CPU wakeup with event maskregister
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0x200FFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200FFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM8
// - SFDITEM_FIELD__EXTI_EMR_EM9
// - SFDITEM_FIELD__EXTI_EMR_EM10
// - SFDITEM_FIELD__EXTI_EMR_EM11
// - SFDITEM_FIELD__EXTI_EMR_EM12
// - SFDITEM_FIELD__EXTI_EMR_EM13
// - SFDITEM_FIELD__EXTI_EMR_EM14
// - SFDITEM_FIELD__EXTI_EMR_EM15
// - SFDITEM_FIELD__EXTI_EMR_EM16
// - SFDITEM_FIELD__EXTI_EMR_EM17
// - SFDITEM_FIELD__EXTI_EMR_EM18
// - SFDITEM_FIELD__EXTI_EMR_EM19
// - SFDITEM_FIELD__EXTI_EMR_EM29
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 1888
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_EXTICR1
// - SFDITEM_REG__EXTI_EXTICR2
// - SFDITEM_REG__EXTI_EXTICR3
// - SFDITEM_REG__EXTI_EXTICR4
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_ACR --------------------------------
// SVD Line: 2688
unsigned int FLASH_ACR __AT (0x40022000);
// ------------------------------ Field Item: FLASH_ACR_LATENCY ---------------------------------
// SVD Line: 2695
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
// LATENCY
//
// [Bits 1..0] RW (@ 0x40022000) Latency
//
// ( (unsigned char)((FLASH_ACR >> 0) & 0x3), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_ACR -----------------------------------
// SVD Line: 2688
// SFDITEM_REG__FLASH_ACR
// ACR
//
// [Bits 31..0] RW (@ 0x40022000) Access control register
// ( (unsigned int)((FLASH_ACR >> 0) & 0xFFFFFFFF), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
//
//
// ---------------------------- Register Item Address: FLASH_KEYR -------------------------------
// SVD Line: 2702
unsigned int FLASH_KEYR __AT (0x40022008);
// ------------------------------- Field Item: FLASH_KEYR_KEY -----------------------------------
// SVD Line: 2709
// - SFDITEM_FIELD__FLASH_KEYR_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash key
//
// ( (unsigned int)((FLASH_KEYR >> 0) & 0x0), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_KEYR -----------------------------------
// SVD Line: 2702
// SFDITEM_REG__FLASH_KEYR
// KEYR
//
// [Bits 31..0] WO (@ 0x40022008) Flash key register
// ( (unsigned int)((FLASH_KEYR >> 0) & 0xFFFFFFFF), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEYR_KEY
//
//
// -------------------------- Register Item Address: FLASH_OPTKEYR ------------------------------
// SVD Line: 2716
unsigned int FLASH_OPTKEYR __AT (0x4002200C);
// ---------------------------- Field Item: FLASH_OPTKEYR_OPTKEY --------------------------------
// SVD Line: 2723
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key
//
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0x0), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEYR ---------------------------------
// SVD Line: 2716
// SFDITEM_REG__FLASH_OPTKEYR
// OPTKEYR
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key register
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 2730
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 2736
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 2741
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protected error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_USRLOCK ----------------------------------
// SVD Line: 2746
// - SFDITEM_FIELD__FLASH_SR_USRLOCK
// USRLOCK
//
// [Bit 13] RW (@ 0x40022010) User data flash lock
//
// ( (unsigned int) FLASH_SR )
// USRLOCK
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 2751
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and Engineering bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 2756
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RW (@ 0x40022010) Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 2730
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) Status register
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x1A011UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1A011) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_USRLOCK
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 2763
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 2770
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Programming
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 2775
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 2780
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Mass erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 2785
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 2790
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option byte program start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------ Field Item: FLASH_CR_PGTSTRT ----------------------------------
// SVD Line: 2795
// - SFDITEM_FIELD__FLASH_CR_PGTSTRT
// PGTSTRT
//
// [Bit 19] RW (@ 0x40022014) Flash main memory program start
//
// ( (unsigned int) FLASH_CR )
// PGTSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 2800
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 2805
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 2810
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option byte loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 2815
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Options Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 2820
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) FLASH_CR Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 2763
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) Flash control register
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xCB0A0807UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCB0A0807) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_PGTSTRT
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 2827
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------- Field Item: FLASH_OPTR_RDP -----------------------------------
// SVD Line: 2834
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// RDP
//
// [Bits 7..0] RW (@ 0x40022020) Read Protection
//
// ( (unsigned char)((FLASH_OPTR >> 0) & 0xFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_IDWG_STOP --------------------------------
// SVD Line: 2839
// - SFDITEM_FIELD__FLASH_OPTR_IDWG_STOP
// IDWG_STOP
//
// [Bit 11] RW (@ 0x40022020) Stop mode IWDG counter
//
// ( (unsigned int) FLASH_OPTR )
// IDWG_STOP
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IDWG_SW ---------------------------------
// SVD Line: 2844
// - SFDITEM_FIELD__FLASH_OPTR_IDWG_SW
// IDWG_SW
//
// [Bit 12] RW (@ 0x40022020) Independent watchdog selection
//
// ( (unsigned int) FLASH_OPTR )
// IDWG_SW
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_WWDG_SW ---------------------------------
// SVD Line: 2849
// - SFDITEM_FIELD__FLASH_OPTR_WWDG_SW
// WWDG_SW
//
// [Bit 13] RW (@ 0x40022020) Window watchdog selection
//
// ( (unsigned int) FLASH_OPTR )
// WWDG_SW
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 2854
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 14] RW (@ 0x40022020) NRST_MODE
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_nBOOT1 ---------------------------------
// SVD Line: 2859
// - SFDITEM_FIELD__FLASH_OPTR_nBOOT1
// nBOOT1
//
// [Bit 15] RW (@ 0x40022020) Boot configuration
//
// ( (unsigned int) FLASH_OPTR )
// nBOOT1
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_BOREN ----------------------------------
// SVD Line: 2864
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// BOREN
//
// [Bit 16] RW (@ 0x40022020) BOR reset Level
//
// ( (unsigned int) FLASH_OPTR )
// BOREN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BORF_LEV --------------------------------
// SVD Line: 2869
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
// BORF_LEV
//
// [Bits 19..17] RW (@ 0x40022020) These bits contain the VDD supply level threshold that activates the reset
//
// ( (unsigned char)((FLASH_OPTR >> 17) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 17 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 17 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 2827
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) Flash option register
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFF8FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF8FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// - SFDITEM_FIELD__FLASH_OPTR_IDWG_STOP
// - SFDITEM_FIELD__FLASH_OPTR_IDWG_SW
// - SFDITEM_FIELD__FLASH_OPTR_WWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// - SFDITEM_FIELD__FLASH_OPTR_nBOOT1
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
//
//
// ---------------------------- Register Item Address: FLASH_SDKR -------------------------------
// SVD Line: 2876
unsigned int FLASH_SDKR __AT (0x40022024);
// ----------------------------- Field Item: FLASH_SDKR_SDK_STRT --------------------------------
// SVD Line: 2883
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// SDK_STRT
//
// [Bits 4..0] RW (@ 0x40022024) SDK area start address
//
// ( (unsigned char)((FLASH_SDKR >> 0) & 0x1F), ((FLASH_SDKR = (FLASH_SDKR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_SDKR_SDK_END ---------------------------------
// SVD Line: 2888
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
// SDK_END
//
// [Bits 12..8] RW (@ 0x40022024) SDK area end address
//
// ( (unsigned char)((FLASH_SDKR >> 8) & 0x1F), ((FLASH_SDKR = (FLASH_SDKR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SDKR -----------------------------------
// SVD Line: 2876
// SFDITEM_REG__FLASH_SDKR
// SDKR
//
// [Bits 31..0] RW (@ 0x40022024) Flash SDK address register
// ( (unsigned int)((FLASH_SDKR >> 0) & 0xFFFFFFFF), ((FLASH_SDKR = (FLASH_SDKR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 2895
unsigned int FLASH_WRPR __AT (0x4002202C);
// ------------------------------- Field Item: FLASH_WRPR_WRP -----------------------------------
// SVD Line: 2902
// - SFDITEM_FIELD__FLASH_WRPR_WRP
// WRP
//
// [Bits 15..0] RW (@ 0x4002202C) WRP address
//
// ( (unsigned short)((FLASH_WRPR >> 0) & 0xFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 2895
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x4002202C) Flash WRP addressregister
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_WRP
//
//
// ---------------------------- Register Item Address: FLASH_STCR -------------------------------
// SVD Line: 2909
unsigned int FLASH_STCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_STCR_SLEEP_EN --------------------------------
// SVD Line: 2916
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) FLash sleep enable
//
// ( (unsigned int) FLASH_STCR )
// SLEEP_EN
//
//
//
// ---------------------------- Field Item: FLASH_STCR_SLEEP_TIME -------------------------------
// SVD Line: 2921
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
// SLEEP_TIME
//
// [Bits 15..8] RW (@ 0x40022090) FLash sleep time configuration(counter based on HSI_10M)
//
// ( (unsigned char)((FLASH_STCR >> 8) & 0xFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_STCR -----------------------------------
// SVD Line: 2909
// SFDITEM_REG__FLASH_STCR
// STCR
//
// [Bits 31..0] RW (@ 0x40022090) Flash sleep time configregister
// ( (unsigned int)((FLASH_STCR >> 0) & 0xFFFFFFFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFF01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF01) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 2928
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 2935
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 7..0] RW (@ 0x40022100) FLash TS0 register
//
// ( (unsigned char)((FLASH_TS0 >> 0) & 0xFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 2928
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) Flash TS0 register
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 2942
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 2949
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 8..0] RW (@ 0x40022104) FLash TS1 register
//
// ( (unsigned short)((FLASH_TS1 >> 0) & 0x1FF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 2942
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) Flash TS1 register
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 2956
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 2963
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 7..0] RW (@ 0x40022108) FLash TS2P register
//
// ( (unsigned char)((FLASH_TS2P >> 0) & 0xFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 2956
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) Flash TS2P register
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 2970
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 2977
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 10..0] RW (@ 0x4002210C) FLash TPS3 register
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0x7FF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x7FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x7FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 2970
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) Flash TPS3 register
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x7FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 2984
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 2991
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 7..0] RW (@ 0x40022110) FLash TS3 register
//
// ( (unsigned char)((FLASH_TS3 >> 0) & 0xFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 2984
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) Flash TS3 register
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_PERTPE ------------------------------
// SVD Line: 2998
unsigned int FLASH_PERTPE __AT (0x40022114);
// ----------------------------- Field Item: FLASH_PERTPE_PERTPE --------------------------------
// SVD Line: 3005
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
// PERTPE
//
// [Bits 16..0] RW (@ 0x40022114) FLash PERTPE register
//
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0x1FFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PERTPE ----------------------------------
// SVD Line: 2998
// SFDITEM_REG__FLASH_PERTPE
// PERTPE
//
// [Bits 31..0] RW (@ 0x40022114) Flash PERTPE register
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0xFFFFFFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
//
//
// -------------------------- Register Item Address: FLASH_SMERTPE ------------------------------
// SVD Line: 3012
unsigned int FLASH_SMERTPE __AT (0x40022118);
// ---------------------------- Field Item: FLASH_SMERTPE_SMERTPE -------------------------------
// SVD Line: 3019
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
// SMERTPE
//
// [Bits 16..0] RW (@ 0x40022118) FLash SMERTPE register
//
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0x1FFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_SMERTPE ---------------------------------
// SVD Line: 3012
// SFDITEM_REG__FLASH_SMERTPE
// SMERTPE
//
// [Bits 31..0] RW (@ 0x40022118) Flash SMERTPE register
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0xFFFFFFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 3026
unsigned int FLASH_PRGTPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 3033
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 15..0] RW (@ 0x4002211C) FLash PRGTPE register
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0xFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 3026
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x4002211C) Flash PRGTPE register
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 3040
unsigned int FLASH_PRETPE __AT (0x40022120);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 3047
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 12..0] RW (@ 0x40022120) FLash PRETPE register
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0x1FFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 3040
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x40022120) Flash PRETPE register
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 2672
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_ACR
// - SFDITEM_REG__FLASH_KEYR
// - SFDITEM_REG__FLASH_OPTKEYR
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_SDKR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_STCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_PERTPE
// - SFDITEM_REG__FLASH_SMERTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 3067
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 3074
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 3079
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 3084
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 3089
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 3094
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 3099
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 3104
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 3109
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE8 ---------------------------------
// SVD Line: 3114
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 16) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE9 ---------------------------------
// SVD Line: 3119
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 18) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE10 ---------------------------------
// SVD Line: 3124
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 20) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE11 ---------------------------------
// SVD Line: 3129
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 22) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE12 ---------------------------------
// SVD Line: 3134
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 24) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE13 ---------------------------------
// SVD Line: 3139
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 26) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE14 ---------------------------------
// SVD Line: 3144
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 28) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE15 ---------------------------------
// SVD Line: 3149
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 30) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 3067
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 3156
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 3162
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 3167
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 3172
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 3177
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 3182
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 3187
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 3192
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 3197
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT8 ----------------------------------
// SVD Line: 3202
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT9 ----------------------------------
// SVD Line: 3207
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT10 ---------------------------------
// SVD Line: 3212
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT11 ---------------------------------
// SVD Line: 3217
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT12 ---------------------------------
// SVD Line: 3222
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT13 ---------------------------------
// SVD Line: 3227
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT14 ---------------------------------
// SVD Line: 3232
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT15 ---------------------------------
// SVD Line: 3237
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 3156
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 3244
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 3251
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 3256
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 3261
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 3266
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 3271
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 3276
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 3281
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 3286
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 3291
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 16) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 3296
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 18) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 3301
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 20) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 3306
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 22) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 3311
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 24) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 3316
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 26) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 3321
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 28) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 3326
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 30) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 3244
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 3333
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 3340
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 3345
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 3350
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 3355
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 3360
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 3365
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 3370
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 3375
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD8 ---------------------------------
// SVD Line: 3380
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 16) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD9 ---------------------------------
// SVD Line: 3385
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 18) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD10 ---------------------------------
// SVD Line: 3390
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 20) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD11 ---------------------------------
// SVD Line: 3395
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 22) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD12 ---------------------------------
// SVD Line: 3400
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 24) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD13 ---------------------------------
// SVD Line: 3405
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 26) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD14 ---------------------------------
// SVD Line: 3410
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 28) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD15 ---------------------------------
// SVD Line: 3415
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 30) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 3333
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 3422
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 3439
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 3444
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 3449
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 3454
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 3459
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 3464
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID8 -----------------------------------
// SVD Line: 3469
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID9 -----------------------------------
// SVD Line: 3474
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID10 -----------------------------------
// SVD Line: 3479
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID11 -----------------------------------
// SVD Line: 3484
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID12 -----------------------------------
// SVD Line: 3489
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID13 -----------------------------------
// SVD Line: 3494
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID14 -----------------------------------
// SVD Line: 3499
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID15 -----------------------------------
// SVD Line: 3504
// - SFDITEM_FIELD__GPIOA_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 3422
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// - SFDITEM_FIELD__GPIOA_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 3511
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 3517
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 3522
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 3527
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 3532
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 3537
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 3542
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 3547
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 3552
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD8 -----------------------------------
// SVD Line: 3557
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD9 -----------------------------------
// SVD Line: 3562
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD10 -----------------------------------
// SVD Line: 3567
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD11 -----------------------------------
// SVD Line: 3572
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD12 -----------------------------------
// SVD Line: 3577
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD13 -----------------------------------
// SVD Line: 3582
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD14 -----------------------------------
// SVD Line: 3587
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD15 -----------------------------------
// SVD Line: 3592
// - SFDITEM_FIELD__GPIOA_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 3511
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// - SFDITEM_FIELD__GPIOA_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 3599
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 3606
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 3611
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 3616
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 3621
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 3626
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 3631
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 3636
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 3641
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS8 -----------------------------------
// SVD Line: 3646
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS9 -----------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// BS9
//
// [Bit 9] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS10 ----------------------------------
// SVD Line: 3656
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// BS10
//
// [Bit 10] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS11 ----------------------------------
// SVD Line: 3661
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// BS11
//
// [Bit 11] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS12 ----------------------------------
// SVD Line: 3666
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// BS12
//
// [Bit 12] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS13 ----------------------------------
// SVD Line: 3671
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// BS13
//
// [Bit 13] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS14 ----------------------------------
// SVD Line: 3676
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// BS14
//
// [Bit 14] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS15 ----------------------------------
// SVD Line: 3681
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// BS15
//
// [Bit 15] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 3686
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 3691
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 3696
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 3701
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 3706
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 3711
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 3716
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 3721
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR8 -----------------------------------
// SVD Line: 3726
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR9 -----------------------------------
// SVD Line: 3731
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// BR9
//
// [Bit 25] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR10 ----------------------------------
// SVD Line: 3736
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// BR10
//
// [Bit 26] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR11 ----------------------------------
// SVD Line: 3741
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// BR11
//
// [Bit 27] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR12 ----------------------------------
// SVD Line: 3746
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// BR12
//
// [Bit 28] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR13 ----------------------------------
// SVD Line: 3751
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// BR13
//
// [Bit 29] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR14 ----------------------------------
// SVD Line: 3756
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// BR14
//
// [Bit 30] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR15 ----------------------------------
// SVD Line: 3761
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
// BR15
//
// [Bit 31] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 3599
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 3768
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 3774
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 3779
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 3784
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 3789
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 3794
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 3799
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 3804
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 3809
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK8 ----------------------------------
// SVD Line: 3814
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK9 ----------------------------------
// SVD Line: 3819
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK10 ----------------------------------
// SVD Line: 3824
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK11 ----------------------------------
// SVD Line: 3829
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK12 ----------------------------------
// SVD Line: 3834
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK13 ----------------------------------
// SVD Line: 3839
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK14 ----------------------------------
// SVD Line: 3844
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK15 ----------------------------------
// SVD Line: 3849
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 3854
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 3768
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 3861
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3867
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3872
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3877
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3882
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3887
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3892
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3897
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3902
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 3861
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_AFRH -------------------------------
// SVD Line: 3909
unsigned int GPIOA_AFRH __AT (0x50000024);
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3915
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 0) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3920
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 4) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3925
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 8) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3930
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 12) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3935
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 16) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3940
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 20) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3945
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 24) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3950
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 28) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRH -----------------------------------
// SVD Line: 3909
// SFDITEM_REG__GPIOA_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000024) GPIO alternate function highregister
// ( (unsigned int)((GPIOA_AFRH >> 0) & 0xFFFFFFFF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 3957
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 3964
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 3969
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 3974
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 3979
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 3984
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 3989
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 3994
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 3999
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR8 -----------------------------------
// SVD Line: 4004
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR9 -----------------------------------
// SVD Line: 4009
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// BR9
//
// [Bit 9] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR10 -----------------------------------
// SVD Line: 4014
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// BR10
//
// [Bit 10] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR11 -----------------------------------
// SVD Line: 4019
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// BR11
//
// [Bit 11] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR12 -----------------------------------
// SVD Line: 4024
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// BR12
//
// [Bit 12] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR13 -----------------------------------
// SVD Line: 4029
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// BR13
//
// [Bit 13] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR14 -----------------------------------
// SVD Line: 4034
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// BR14
//
// [Bit 14] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR15 -----------------------------------
// SVD Line: 4039
// - SFDITEM_FIELD__GPIOA_BRR_BR15
// BR15
//
// [Bit 15] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 3957
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// - SFDITEM_FIELD__GPIOA_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 3056
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_AFRH
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 3067
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 3074
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 3079
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 3084
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 3089
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE4 ---------------------------------
// SVD Line: 3094
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 8) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE5 ---------------------------------
// SVD Line: 3099
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 10) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE6 ---------------------------------
// SVD Line: 3104
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 12) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE7 ---------------------------------
// SVD Line: 3109
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 14) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE8 ---------------------------------
// SVD Line: 3114
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 16) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE9 ---------------------------------
// SVD Line: 3119
// - SFDITEM_FIELD__GPIOB_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 18) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE10 ---------------------------------
// SVD Line: 3124
// - SFDITEM_FIELD__GPIOB_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 20) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE11 ---------------------------------
// SVD Line: 3129
// - SFDITEM_FIELD__GPIOB_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 22) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE12 ---------------------------------
// SVD Line: 3134
// - SFDITEM_FIELD__GPIOB_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 24) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE13 ---------------------------------
// SVD Line: 3139
// - SFDITEM_FIELD__GPIOB_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 26) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE14 ---------------------------------
// SVD Line: 3144
// - SFDITEM_FIELD__GPIOB_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 28) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE15 ---------------------------------
// SVD Line: 3149
// - SFDITEM_FIELD__GPIOB_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 30) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 3067
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
// - SFDITEM_FIELD__GPIOB_MODER_MODE9
// - SFDITEM_FIELD__GPIOB_MODER_MODE10
// - SFDITEM_FIELD__GPIOB_MODER_MODE11
// - SFDITEM_FIELD__GPIOB_MODER_MODE12
// - SFDITEM_FIELD__GPIOB_MODER_MODE13
// - SFDITEM_FIELD__GPIOB_MODER_MODE14
// - SFDITEM_FIELD__GPIOB_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 3156
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 3162
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 3167
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 3172
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 3177
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT4 ----------------------------------
// SVD Line: 3182
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT5 ----------------------------------
// SVD Line: 3187
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT6 ----------------------------------
// SVD Line: 3192
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT7 ----------------------------------
// SVD Line: 3197
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT8 ----------------------------------
// SVD Line: 3202
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT9 ----------------------------------
// SVD Line: 3207
// - SFDITEM_FIELD__GPIOB_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT10 ---------------------------------
// SVD Line: 3212
// - SFDITEM_FIELD__GPIOB_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT11 ---------------------------------
// SVD Line: 3217
// - SFDITEM_FIELD__GPIOB_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT12 ---------------------------------
// SVD Line: 3222
// - SFDITEM_FIELD__GPIOB_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT13 ---------------------------------
// SVD Line: 3227
// - SFDITEM_FIELD__GPIOB_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT14 ---------------------------------
// SVD Line: 3232
// - SFDITEM_FIELD__GPIOB_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT15 ---------------------------------
// SVD Line: 3237
// - SFDITEM_FIELD__GPIOB_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 3156
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
// - SFDITEM_FIELD__GPIOB_OTYPER_OT9
// - SFDITEM_FIELD__GPIOB_OTYPER_OT10
// - SFDITEM_FIELD__GPIOB_OTYPER_OT11
// - SFDITEM_FIELD__GPIOB_OTYPER_OT12
// - SFDITEM_FIELD__GPIOB_OTYPER_OT13
// - SFDITEM_FIELD__GPIOB_OTYPER_OT14
// - SFDITEM_FIELD__GPIOB_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 3244
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 3251
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 3256
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 3261
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 3266
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 3271
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 8) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 3276
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 10) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 3281
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 12) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 3286
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 14) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 3291
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 16) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 3296
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 18) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 3301
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 20) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 3306
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 22) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 3311
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 24) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 3316
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 26) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 3321
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 28) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 3326
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 30) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 3244
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 3333
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 3340
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 3345
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 3350
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 3355
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD4 ---------------------------------
// SVD Line: 3360
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 8) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD5 ---------------------------------
// SVD Line: 3365
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 10) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD6 ---------------------------------
// SVD Line: 3370
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 12) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD7 ---------------------------------
// SVD Line: 3375
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 14) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD8 ---------------------------------
// SVD Line: 3380
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 16) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD9 ---------------------------------
// SVD Line: 3385
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 18) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD10 ---------------------------------
// SVD Line: 3390
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 20) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD11 ---------------------------------
// SVD Line: 3395
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 22) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD12 ---------------------------------
// SVD Line: 3400
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 24) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD13 ---------------------------------
// SVD Line: 3405
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 26) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD14 ---------------------------------
// SVD Line: 3410
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 28) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD15 ---------------------------------
// SVD Line: 3415
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 30) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 3333
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 3422
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 3439
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 3444
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID4 -----------------------------------
// SVD Line: 3449
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID5 -----------------------------------
// SVD Line: 3454
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID6 -----------------------------------
// SVD Line: 3459
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID7 -----------------------------------
// SVD Line: 3464
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID8 -----------------------------------
// SVD Line: 3469
// - SFDITEM_FIELD__GPIOB_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID9 -----------------------------------
// SVD Line: 3474
// - SFDITEM_FIELD__GPIOB_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID10 -----------------------------------
// SVD Line: 3479
// - SFDITEM_FIELD__GPIOB_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID11 -----------------------------------
// SVD Line: 3484
// - SFDITEM_FIELD__GPIOB_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID12 -----------------------------------
// SVD Line: 3489
// - SFDITEM_FIELD__GPIOB_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID13 -----------------------------------
// SVD Line: 3494
// - SFDITEM_FIELD__GPIOB_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID14 -----------------------------------
// SVD Line: 3499
// - SFDITEM_FIELD__GPIOB_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID15 -----------------------------------
// SVD Line: 3504
// - SFDITEM_FIELD__GPIOB_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 3422
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// - SFDITEM_FIELD__GPIOB_IDR_ID8
// - SFDITEM_FIELD__GPIOB_IDR_ID9
// - SFDITEM_FIELD__GPIOB_IDR_ID10
// - SFDITEM_FIELD__GPIOB_IDR_ID11
// - SFDITEM_FIELD__GPIOB_IDR_ID12
// - SFDITEM_FIELD__GPIOB_IDR_ID13
// - SFDITEM_FIELD__GPIOB_IDR_ID14
// - SFDITEM_FIELD__GPIOB_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 3511
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 3517
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 3522
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 3527
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 3532
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD4 -----------------------------------
// SVD Line: 3537
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD5 -----------------------------------
// SVD Line: 3542
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD6 -----------------------------------
// SVD Line: 3547
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD7 -----------------------------------
// SVD Line: 3552
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD8 -----------------------------------
// SVD Line: 3557
// - SFDITEM_FIELD__GPIOB_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD9 -----------------------------------
// SVD Line: 3562
// - SFDITEM_FIELD__GPIOB_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD10 -----------------------------------
// SVD Line: 3567
// - SFDITEM_FIELD__GPIOB_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD11 -----------------------------------
// SVD Line: 3572
// - SFDITEM_FIELD__GPIOB_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD12 -----------------------------------
// SVD Line: 3577
// - SFDITEM_FIELD__GPIOB_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD13 -----------------------------------
// SVD Line: 3582
// - SFDITEM_FIELD__GPIOB_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD14 -----------------------------------
// SVD Line: 3587
// - SFDITEM_FIELD__GPIOB_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD15 -----------------------------------
// SVD Line: 3592
// - SFDITEM_FIELD__GPIOB_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 3511
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// - SFDITEM_FIELD__GPIOB_ODR_OD8
// - SFDITEM_FIELD__GPIOB_ODR_OD9
// - SFDITEM_FIELD__GPIOB_ODR_OD10
// - SFDITEM_FIELD__GPIOB_ODR_OD11
// - SFDITEM_FIELD__GPIOB_ODR_OD12
// - SFDITEM_FIELD__GPIOB_ODR_OD13
// - SFDITEM_FIELD__GPIOB_ODR_OD14
// - SFDITEM_FIELD__GPIOB_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 3599
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 3606
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 3611
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 3616
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 3621
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS4 -----------------------------------
// SVD Line: 3626
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS5 -----------------------------------
// SVD Line: 3631
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS6 -----------------------------------
// SVD Line: 3636
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS7 -----------------------------------
// SVD Line: 3641
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS8 -----------------------------------
// SVD Line: 3646
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS9 -----------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__GPIOB_BSRR_BS9
// BS9
//
// [Bit 9] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS10 ----------------------------------
// SVD Line: 3656
// - SFDITEM_FIELD__GPIOB_BSRR_BS10
// BS10
//
// [Bit 10] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS11 ----------------------------------
// SVD Line: 3661
// - SFDITEM_FIELD__GPIOB_BSRR_BS11
// BS11
//
// [Bit 11] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS12 ----------------------------------
// SVD Line: 3666
// - SFDITEM_FIELD__GPIOB_BSRR_BS12
// BS12
//
// [Bit 12] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS13 ----------------------------------
// SVD Line: 3671
// - SFDITEM_FIELD__GPIOB_BSRR_BS13
// BS13
//
// [Bit 13] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS14 ----------------------------------
// SVD Line: 3676
// - SFDITEM_FIELD__GPIOB_BSRR_BS14
// BS14
//
// [Bit 14] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS15 ----------------------------------
// SVD Line: 3681
// - SFDITEM_FIELD__GPIOB_BSRR_BS15
// BS15
//
// [Bit 15] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 3686
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 3691
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 3696
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 3701
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR4 -----------------------------------
// SVD Line: 3706
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR5 -----------------------------------
// SVD Line: 3711
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR6 -----------------------------------
// SVD Line: 3716
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR7 -----------------------------------
// SVD Line: 3721
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR8 -----------------------------------
// SVD Line: 3726
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR9 -----------------------------------
// SVD Line: 3731
// - SFDITEM_FIELD__GPIOB_BSRR_BR9
// BR9
//
// [Bit 25] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR10 ----------------------------------
// SVD Line: 3736
// - SFDITEM_FIELD__GPIOB_BSRR_BR10
// BR10
//
// [Bit 26] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR11 ----------------------------------
// SVD Line: 3741
// - SFDITEM_FIELD__GPIOB_BSRR_BR11
// BR11
//
// [Bit 27] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR12 ----------------------------------
// SVD Line: 3746
// - SFDITEM_FIELD__GPIOB_BSRR_BR12
// BR12
//
// [Bit 28] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR13 ----------------------------------
// SVD Line: 3751
// - SFDITEM_FIELD__GPIOB_BSRR_BR13
// BR13
//
// [Bit 29] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR14 ----------------------------------
// SVD Line: 3756
// - SFDITEM_FIELD__GPIOB_BSRR_BR14
// BR14
//
// [Bit 30] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR15 ----------------------------------
// SVD Line: 3761
// - SFDITEM_FIELD__GPIOB_BSRR_BR15
// BR15
//
// [Bit 31] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 3599
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// - SFDITEM_FIELD__GPIOB_BSRR_BS9
// - SFDITEM_FIELD__GPIOB_BSRR_BS10
// - SFDITEM_FIELD__GPIOB_BSRR_BS11
// - SFDITEM_FIELD__GPIOB_BSRR_BS12
// - SFDITEM_FIELD__GPIOB_BSRR_BS13
// - SFDITEM_FIELD__GPIOB_BSRR_BS14
// - SFDITEM_FIELD__GPIOB_BSRR_BS15
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
// - SFDITEM_FIELD__GPIOB_BSRR_BR9
// - SFDITEM_FIELD__GPIOB_BSRR_BR10
// - SFDITEM_FIELD__GPIOB_BSRR_BR11
// - SFDITEM_FIELD__GPIOB_BSRR_BR12
// - SFDITEM_FIELD__GPIOB_BSRR_BR13
// - SFDITEM_FIELD__GPIOB_BSRR_BR14
// - SFDITEM_FIELD__GPIOB_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 3768
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 3774
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 3779
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 3784
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 3789
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK4 ----------------------------------
// SVD Line: 3794
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK5 ----------------------------------
// SVD Line: 3799
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK6 ----------------------------------
// SVD Line: 3804
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK7 ----------------------------------
// SVD Line: 3809
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK8 ----------------------------------
// SVD Line: 3814
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK9 ----------------------------------
// SVD Line: 3819
// - SFDITEM_FIELD__GPIOB_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK10 ----------------------------------
// SVD Line: 3824
// - SFDITEM_FIELD__GPIOB_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK11 ----------------------------------
// SVD Line: 3829
// - SFDITEM_FIELD__GPIOB_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK12 ----------------------------------
// SVD Line: 3834
// - SFDITEM_FIELD__GPIOB_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK13 ----------------------------------
// SVD Line: 3839
// - SFDITEM_FIELD__GPIOB_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK14 ----------------------------------
// SVD Line: 3844
// - SFDITEM_FIELD__GPIOB_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK15 ----------------------------------
// SVD Line: 3849
// - SFDITEM_FIELD__GPIOB_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 3854
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 3768
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// - SFDITEM_FIELD__GPIOB_LCKR_LCK9
// - SFDITEM_FIELD__GPIOB_LCKR_LCK10
// - SFDITEM_FIELD__GPIOB_LCKR_LCK11
// - SFDITEM_FIELD__GPIOB_LCKR_LCK12
// - SFDITEM_FIELD__GPIOB_LCKR_LCK13
// - SFDITEM_FIELD__GPIOB_LCKR_LCK14
// - SFDITEM_FIELD__GPIOB_LCKR_LCK15
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 3861
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3867
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3872
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3877
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3882
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3887
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 16) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3892
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 20) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3897
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 24) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3902
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 28) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 3861
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOB_AFRH -------------------------------
// SVD Line: 3909
unsigned int GPIOB_AFRH __AT (0x50000424);
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3915
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 0) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3920
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 4) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3925
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 8) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3930
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 12) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3935
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 16) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3940
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 20) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3945
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 24) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3950
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 28) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRH -----------------------------------
// SVD Line: 3909
// SFDITEM_REG__GPIOB_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000424) GPIO alternate function highregister
// ( (unsigned int)((GPIOB_AFRH >> 0) & 0xFFFFFFFF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 3957
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 3964
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 3969
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 3974
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 3979
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR4 -----------------------------------
// SVD Line: 3984
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR5 -----------------------------------
// SVD Line: 3989
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR6 -----------------------------------
// SVD Line: 3994
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR7 -----------------------------------
// SVD Line: 3999
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR8 -----------------------------------
// SVD Line: 4004
// - SFDITEM_FIELD__GPIOB_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR9 -----------------------------------
// SVD Line: 4009
// - SFDITEM_FIELD__GPIOB_BRR_BR9
// BR9
//
// [Bit 9] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR10 -----------------------------------
// SVD Line: 4014
// - SFDITEM_FIELD__GPIOB_BRR_BR10
// BR10
//
// [Bit 10] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR11 -----------------------------------
// SVD Line: 4019
// - SFDITEM_FIELD__GPIOB_BRR_BR11
// BR11
//
// [Bit 11] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR12 -----------------------------------
// SVD Line: 4024
// - SFDITEM_FIELD__GPIOB_BRR_BR12
// BR12
//
// [Bit 12] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR13 -----------------------------------
// SVD Line: 4029
// - SFDITEM_FIELD__GPIOB_BRR_BR13
// BR13
//
// [Bit 13] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR14 -----------------------------------
// SVD Line: 4034
// - SFDITEM_FIELD__GPIOB_BRR_BR14
// BR14
//
// [Bit 14] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR15 -----------------------------------
// SVD Line: 4039
// - SFDITEM_FIELD__GPIOB_BRR_BR15
// BR15
//
// [Bit 15] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 3957
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// - SFDITEM_FIELD__GPIOB_BRR_BR8
// - SFDITEM_FIELD__GPIOB_BRR_BR9
// - SFDITEM_FIELD__GPIOB_BRR_BR10
// - SFDITEM_FIELD__GPIOB_BRR_BR11
// - SFDITEM_FIELD__GPIOB_BRR_BR12
// - SFDITEM_FIELD__GPIOB_BRR_BR13
// - SFDITEM_FIELD__GPIOB_BRR_BR14
// - SFDITEM_FIELD__GPIOB_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 4048
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_AFRH
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOF_MODER -------------------------------
// SVD Line: 3067
unsigned int GPIOF_MODER __AT (0x50001400);
// ------------------------------ Field Item: GPIOF_MODER_MODE0 ---------------------------------
// SVD Line: 3074
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 0) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE1 ---------------------------------
// SVD Line: 3079
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 2) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE2 ---------------------------------
// SVD Line: 3084
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 4) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE3 ---------------------------------
// SVD Line: 3089
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 6) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE4 ---------------------------------
// SVD Line: 3094
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 8) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE5 ---------------------------------
// SVD Line: 3099
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 10) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE6 ---------------------------------
// SVD Line: 3104
// - SFDITEM_FIELD__GPIOF_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 12) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE7 ---------------------------------
// SVD Line: 3109
// - SFDITEM_FIELD__GPIOF_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 14) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE8 ---------------------------------
// SVD Line: 3114
// - SFDITEM_FIELD__GPIOF_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 16) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE9 ---------------------------------
// SVD Line: 3119
// - SFDITEM_FIELD__GPIOF_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 18) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE10 ---------------------------------
// SVD Line: 3124
// - SFDITEM_FIELD__GPIOF_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 20) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE11 ---------------------------------
// SVD Line: 3129
// - SFDITEM_FIELD__GPIOF_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 22) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE12 ---------------------------------
// SVD Line: 3134
// - SFDITEM_FIELD__GPIOF_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 24) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE13 ---------------------------------
// SVD Line: 3139
// - SFDITEM_FIELD__GPIOF_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 26) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE14 ---------------------------------
// SVD Line: 3144
// - SFDITEM_FIELD__GPIOF_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 28) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE15 ---------------------------------
// SVD Line: 3149
// - SFDITEM_FIELD__GPIOF_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 30) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_MODER ----------------------------------
// SVD Line: 3067
// SFDITEM_REG__GPIOF_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50001400) GPIO port mode register
// ( (unsigned int)((GPIOF_MODER >> 0) & 0xFFFFFFFF), ((GPIOF_MODER = (GPIOF_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
// - SFDITEM_FIELD__GPIOF_MODER_MODE6
// - SFDITEM_FIELD__GPIOF_MODER_MODE7
// - SFDITEM_FIELD__GPIOF_MODER_MODE8
// - SFDITEM_FIELD__GPIOF_MODER_MODE9
// - SFDITEM_FIELD__GPIOF_MODER_MODE10
// - SFDITEM_FIELD__GPIOF_MODER_MODE11
// - SFDITEM_FIELD__GPIOF_MODER_MODE12
// - SFDITEM_FIELD__GPIOF_MODER_MODE13
// - SFDITEM_FIELD__GPIOF_MODER_MODE14
// - SFDITEM_FIELD__GPIOF_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOF_OTYPER ------------------------------
// SVD Line: 3156
unsigned int GPIOF_OTYPER __AT (0x50001404);
// ------------------------------ Field Item: GPIOF_OTYPER_OT0 ----------------------------------
// SVD Line: 3162
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT1 ----------------------------------
// SVD Line: 3167
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT2 ----------------------------------
// SVD Line: 3172
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT3 ----------------------------------
// SVD Line: 3177
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT4 ----------------------------------
// SVD Line: 3182
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT5 ----------------------------------
// SVD Line: 3187
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT6 ----------------------------------
// SVD Line: 3192
// - SFDITEM_FIELD__GPIOF_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT7 ----------------------------------
// SVD Line: 3197
// - SFDITEM_FIELD__GPIOF_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT8 ----------------------------------
// SVD Line: 3202
// - SFDITEM_FIELD__GPIOF_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT9 ----------------------------------
// SVD Line: 3207
// - SFDITEM_FIELD__GPIOF_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT10 ---------------------------------
// SVD Line: 3212
// - SFDITEM_FIELD__GPIOF_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT11 ---------------------------------
// SVD Line: 3217
// - SFDITEM_FIELD__GPIOF_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT12 ---------------------------------
// SVD Line: 3222
// - SFDITEM_FIELD__GPIOF_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT13 ---------------------------------
// SVD Line: 3227
// - SFDITEM_FIELD__GPIOF_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT14 ---------------------------------
// SVD Line: 3232
// - SFDITEM_FIELD__GPIOF_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT15 ---------------------------------
// SVD Line: 3237
// - SFDITEM_FIELD__GPIOF_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOF_OTYPER ----------------------------------
// SVD Line: 3156
// SFDITEM_REG__GPIOF_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50001404) GPIO port output type register
// ( (unsigned int)((GPIOF_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOF_OTYPER = (GPIOF_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
// - SFDITEM_FIELD__GPIOF_OTYPER_OT6
// - SFDITEM_FIELD__GPIOF_OTYPER_OT7
// - SFDITEM_FIELD__GPIOF_OTYPER_OT8
// - SFDITEM_FIELD__GPIOF_OTYPER_OT9
// - SFDITEM_FIELD__GPIOF_OTYPER_OT10
// - SFDITEM_FIELD__GPIOF_OTYPER_OT11
// - SFDITEM_FIELD__GPIOF_OTYPER_OT12
// - SFDITEM_FIELD__GPIOF_OTYPER_OT13
// - SFDITEM_FIELD__GPIOF_OTYPER_OT14
// - SFDITEM_FIELD__GPIOF_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOF_OSPEEDR ------------------------------
// SVD Line: 3244
unsigned int GPIOF_OSPEEDR __AT (0x50001408);
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 3251
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 0) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 3256
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 2) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 3261
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 4) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 3266
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 6) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 3271
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 8) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 3276
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 10) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 3281
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 12) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 3286
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 14) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 3291
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 16) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 3296
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 18) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 3301
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 20) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 3306
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 22) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 3311
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 24) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 3316
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 26) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 3321
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 28) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 3326
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 30) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOF_OSPEEDR ---------------------------------
// SVD Line: 3244
// SFDITEM_REG__GPIOF_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50001408) GPIO port output speed register
// ( (unsigned int)((GPIOF_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOF_PUPDR -------------------------------
// SVD Line: 3333
unsigned int GPIOF_PUPDR __AT (0x5000140C);
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD0 ---------------------------------
// SVD Line: 3340
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 0) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD1 ---------------------------------
// SVD Line: 3345
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 2) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD2 ---------------------------------
// SVD Line: 3350
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 4) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD3 ---------------------------------
// SVD Line: 3355
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 6) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD4 ---------------------------------
// SVD Line: 3360
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 8) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD5 ---------------------------------
// SVD Line: 3365
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 10) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD6 ---------------------------------
// SVD Line: 3370
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 12) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD7 ---------------------------------
// SVD Line: 3375
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 14) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD8 ---------------------------------
// SVD Line: 3380
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 16) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD9 ---------------------------------
// SVD Line: 3385
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 18) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD10 ---------------------------------
// SVD Line: 3390
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 20) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD11 ---------------------------------
// SVD Line: 3395
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 22) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD12 ---------------------------------
// SVD Line: 3400
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 24) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD13 ---------------------------------
// SVD Line: 3405
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 26) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD14 ---------------------------------
// SVD Line: 3410
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 28) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD15 ---------------------------------
// SVD Line: 3415
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 30) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_PUPDR ----------------------------------
// SVD Line: 3333
// SFDITEM_REG__GPIOF_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000140C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOF_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOF_IDR --------------------------------
// SVD Line: 3422
unsigned int GPIOF_IDR __AT (0x50001410);
// -------------------------------- Field Item: GPIOF_IDR_ID0 -----------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID1 -----------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID2 -----------------------------------
// SVD Line: 3439
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID3 -----------------------------------
// SVD Line: 3444
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID4 -----------------------------------
// SVD Line: 3449
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID5 -----------------------------------
// SVD Line: 3454
// - SFDITEM_FIELD__GPIOF_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID6 -----------------------------------
// SVD Line: 3459
// - SFDITEM_FIELD__GPIOF_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID7 -----------------------------------
// SVD Line: 3464
// - SFDITEM_FIELD__GPIOF_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID8 -----------------------------------
// SVD Line: 3469
// - SFDITEM_FIELD__GPIOF_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID9 -----------------------------------
// SVD Line: 3474
// - SFDITEM_FIELD__GPIOF_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID10 -----------------------------------
// SVD Line: 3479
// - SFDITEM_FIELD__GPIOF_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID11 -----------------------------------
// SVD Line: 3484
// - SFDITEM_FIELD__GPIOF_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID12 -----------------------------------
// SVD Line: 3489
// - SFDITEM_FIELD__GPIOF_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID13 -----------------------------------
// SVD Line: 3494
// - SFDITEM_FIELD__GPIOF_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID14 -----------------------------------
// SVD Line: 3499
// - SFDITEM_FIELD__GPIOF_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID15 -----------------------------------
// SVD Line: 3504
// - SFDITEM_FIELD__GPIOF_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOF_IDR -----------------------------------
// SVD Line: 3422
// SFDITEM_REG__GPIOF_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50001410) GPIO port input data register
// ( (unsigned int)((GPIOF_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// - SFDITEM_FIELD__GPIOF_IDR_ID5
// - SFDITEM_FIELD__GPIOF_IDR_ID6
// - SFDITEM_FIELD__GPIOF_IDR_ID7
// - SFDITEM_FIELD__GPIOF_IDR_ID8
// - SFDITEM_FIELD__GPIOF_IDR_ID9
// - SFDITEM_FIELD__GPIOF_IDR_ID10
// - SFDITEM_FIELD__GPIOF_IDR_ID11
// - SFDITEM_FIELD__GPIOF_IDR_ID12
// - SFDITEM_FIELD__GPIOF_IDR_ID13
// - SFDITEM_FIELD__GPIOF_IDR_ID14
// - SFDITEM_FIELD__GPIOF_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOF_ODR --------------------------------
// SVD Line: 3511
unsigned int GPIOF_ODR __AT (0x50001414);
// -------------------------------- Field Item: GPIOF_ODR_OD0 -----------------------------------
// SVD Line: 3517
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD1 -----------------------------------
// SVD Line: 3522
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD2 -----------------------------------
// SVD Line: 3527
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD3 -----------------------------------
// SVD Line: 3532
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD4 -----------------------------------
// SVD Line: 3537
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD5 -----------------------------------
// SVD Line: 3542
// - SFDITEM_FIELD__GPIOF_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD6 -----------------------------------
// SVD Line: 3547
// - SFDITEM_FIELD__GPIOF_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD7 -----------------------------------
// SVD Line: 3552
// - SFDITEM_FIELD__GPIOF_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD8 -----------------------------------
// SVD Line: 3557
// - SFDITEM_FIELD__GPIOF_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD9 -----------------------------------
// SVD Line: 3562
// - SFDITEM_FIELD__GPIOF_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD10 -----------------------------------
// SVD Line: 3567
// - SFDITEM_FIELD__GPIOF_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD11 -----------------------------------
// SVD Line: 3572
// - SFDITEM_FIELD__GPIOF_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD12 -----------------------------------
// SVD Line: 3577
// - SFDITEM_FIELD__GPIOF_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD13 -----------------------------------
// SVD Line: 3582
// - SFDITEM_FIELD__GPIOF_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD14 -----------------------------------
// SVD Line: 3587
// - SFDITEM_FIELD__GPIOF_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD15 -----------------------------------
// SVD Line: 3592
// - SFDITEM_FIELD__GPIOF_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOF_ODR -----------------------------------
// SVD Line: 3511
// SFDITEM_REG__GPIOF_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50001414) GPIO port output data register
// ( (unsigned int)((GPIOF_ODR >> 0) & 0xFFFFFFFF), ((GPIOF_ODR = (GPIOF_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// - SFDITEM_FIELD__GPIOF_ODR_OD5
// - SFDITEM_FIELD__GPIOF_ODR_OD6
// - SFDITEM_FIELD__GPIOF_ODR_OD7
// - SFDITEM_FIELD__GPIOF_ODR_OD8
// - SFDITEM_FIELD__GPIOF_ODR_OD9
// - SFDITEM_FIELD__GPIOF_ODR_OD10
// - SFDITEM_FIELD__GPIOF_ODR_OD11
// - SFDITEM_FIELD__GPIOF_ODR_OD12
// - SFDITEM_FIELD__GPIOF_ODR_OD13
// - SFDITEM_FIELD__GPIOF_ODR_OD14
// - SFDITEM_FIELD__GPIOF_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOF_BSRR -------------------------------
// SVD Line: 3599
unsigned int GPIOF_BSRR __AT (0x50001418);
// ------------------------------- Field Item: GPIOF_BSRR_BS0 -----------------------------------
// SVD Line: 3606
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS1 -----------------------------------
// SVD Line: 3611
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS2 -----------------------------------
// SVD Line: 3616
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS3 -----------------------------------
// SVD Line: 3621
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS4 -----------------------------------
// SVD Line: 3626
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS5 -----------------------------------
// SVD Line: 3631
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS6 -----------------------------------
// SVD Line: 3636
// - SFDITEM_FIELD__GPIOF_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS7 -----------------------------------
// SVD Line: 3641
// - SFDITEM_FIELD__GPIOF_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS8 -----------------------------------
// SVD Line: 3646
// - SFDITEM_FIELD__GPIOF_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS9 -----------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__GPIOF_BSRR_BS9
// BS9
//
// [Bit 9] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS10 ----------------------------------
// SVD Line: 3656
// - SFDITEM_FIELD__GPIOF_BSRR_BS10
// BS10
//
// [Bit 10] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS11 ----------------------------------
// SVD Line: 3661
// - SFDITEM_FIELD__GPIOF_BSRR_BS11
// BS11
//
// [Bit 11] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS12 ----------------------------------
// SVD Line: 3666
// - SFDITEM_FIELD__GPIOF_BSRR_BS12
// BS12
//
// [Bit 12] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS13 ----------------------------------
// SVD Line: 3671
// - SFDITEM_FIELD__GPIOF_BSRR_BS13
// BS13
//
// [Bit 13] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS14 ----------------------------------
// SVD Line: 3676
// - SFDITEM_FIELD__GPIOF_BSRR_BS14
// BS14
//
// [Bit 14] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS15 ----------------------------------
// SVD Line: 3681
// - SFDITEM_FIELD__GPIOF_BSRR_BS15
// BS15
//
// [Bit 15] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR0 -----------------------------------
// SVD Line: 3686
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR1 -----------------------------------
// SVD Line: 3691
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR2 -----------------------------------
// SVD Line: 3696
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR3 -----------------------------------
// SVD Line: 3701
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR4 -----------------------------------
// SVD Line: 3706
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR5 -----------------------------------
// SVD Line: 3711
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR6 -----------------------------------
// SVD Line: 3716
// - SFDITEM_FIELD__GPIOF_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR7 -----------------------------------
// SVD Line: 3721
// - SFDITEM_FIELD__GPIOF_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR8 -----------------------------------
// SVD Line: 3726
// - SFDITEM_FIELD__GPIOF_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR9 -----------------------------------
// SVD Line: 3731
// - SFDITEM_FIELD__GPIOF_BSRR_BR9
// BR9
//
// [Bit 25] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR10 ----------------------------------
// SVD Line: 3736
// - SFDITEM_FIELD__GPIOF_BSRR_BR10
// BR10
//
// [Bit 26] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR11 ----------------------------------
// SVD Line: 3741
// - SFDITEM_FIELD__GPIOF_BSRR_BR11
// BR11
//
// [Bit 27] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR12 ----------------------------------
// SVD Line: 3746
// - SFDITEM_FIELD__GPIOF_BSRR_BR12
// BR12
//
// [Bit 28] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR13 ----------------------------------
// SVD Line: 3751
// - SFDITEM_FIELD__GPIOF_BSRR_BR13
// BR13
//
// [Bit 29] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR14 ----------------------------------
// SVD Line: 3756
// - SFDITEM_FIELD__GPIOF_BSRR_BR14
// BR14
//
// [Bit 30] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR15 ----------------------------------
// SVD Line: 3761
// - SFDITEM_FIELD__GPIOF_BSRR_BR15
// BR15
//
// [Bit 31] WO (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOF_BSRR -----------------------------------
// SVD Line: 3599
// SFDITEM_REG__GPIOF_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50001418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOF_BSRR >> 0) & 0xFFFFFFFF), ((GPIOF_BSRR = (GPIOF_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// - SFDITEM_FIELD__GPIOF_BSRR_BS6
// - SFDITEM_FIELD__GPIOF_BSRR_BS7
// - SFDITEM_FIELD__GPIOF_BSRR_BS8
// - SFDITEM_FIELD__GPIOF_BSRR_BS9
// - SFDITEM_FIELD__GPIOF_BSRR_BS10
// - SFDITEM_FIELD__GPIOF_BSRR_BS11
// - SFDITEM_FIELD__GPIOF_BSRR_BS12
// - SFDITEM_FIELD__GPIOF_BSRR_BS13
// - SFDITEM_FIELD__GPIOF_BSRR_BS14
// - SFDITEM_FIELD__GPIOF_BSRR_BS15
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
// - SFDITEM_FIELD__GPIOF_BSRR_BR6
// - SFDITEM_FIELD__GPIOF_BSRR_BR7
// - SFDITEM_FIELD__GPIOF_BSRR_BR8
// - SFDITEM_FIELD__GPIOF_BSRR_BR9
// - SFDITEM_FIELD__GPIOF_BSRR_BR10
// - SFDITEM_FIELD__GPIOF_BSRR_BR11
// - SFDITEM_FIELD__GPIOF_BSRR_BR12
// - SFDITEM_FIELD__GPIOF_BSRR_BR13
// - SFDITEM_FIELD__GPIOF_BSRR_BR14
// - SFDITEM_FIELD__GPIOF_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOF_LCKR -------------------------------
// SVD Line: 3768
unsigned int GPIOF_LCKR __AT (0x5000141C);
// ------------------------------- Field Item: GPIOF_LCKR_LCK0 ----------------------------------
// SVD Line: 3774
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK1 ----------------------------------
// SVD Line: 3779
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK2 ----------------------------------
// SVD Line: 3784
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK3 ----------------------------------
// SVD Line: 3789
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK4 ----------------------------------
// SVD Line: 3794
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK5 ----------------------------------
// SVD Line: 3799
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK6 ----------------------------------
// SVD Line: 3804
// - SFDITEM_FIELD__GPIOF_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK7 ----------------------------------
// SVD Line: 3809
// - SFDITEM_FIELD__GPIOF_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK8 ----------------------------------
// SVD Line: 3814
// - SFDITEM_FIELD__GPIOF_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK9 ----------------------------------
// SVD Line: 3819
// - SFDITEM_FIELD__GPIOF_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK10 ----------------------------------
// SVD Line: 3824
// - SFDITEM_FIELD__GPIOF_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK11 ----------------------------------
// SVD Line: 3829
// - SFDITEM_FIELD__GPIOF_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK12 ----------------------------------
// SVD Line: 3834
// - SFDITEM_FIELD__GPIOF_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK13 ----------------------------------
// SVD Line: 3839
// - SFDITEM_FIELD__GPIOF_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK14 ----------------------------------
// SVD Line: 3844
// - SFDITEM_FIELD__GPIOF_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK15 ----------------------------------
// SVD Line: 3849
// - SFDITEM_FIELD__GPIOF_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCKK ----------------------------------
// SVD Line: 3854
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOF_LCKR -----------------------------------
// SVD Line: 3768
// SFDITEM_REG__GPIOF_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000141C) GPIO port configuration lock register
// ( (unsigned int)((GPIOF_LCKR >> 0) & 0xFFFFFFFF), ((GPIOF_LCKR = (GPIOF_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// - SFDITEM_FIELD__GPIOF_LCKR_LCK6
// - SFDITEM_FIELD__GPIOF_LCKR_LCK7
// - SFDITEM_FIELD__GPIOF_LCKR_LCK8
// - SFDITEM_FIELD__GPIOF_LCKR_LCK9
// - SFDITEM_FIELD__GPIOF_LCKR_LCK10
// - SFDITEM_FIELD__GPIOF_LCKR_LCK11
// - SFDITEM_FIELD__GPIOF_LCKR_LCK12
// - SFDITEM_FIELD__GPIOF_LCKR_LCK13
// - SFDITEM_FIELD__GPIOF_LCKR_LCK14
// - SFDITEM_FIELD__GPIOF_LCKR_LCK15
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOF_AFRL -------------------------------
// SVD Line: 3861
unsigned int GPIOF_AFRL __AT (0x50001420);
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3867
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 0) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3872
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 4) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3877
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 8) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3882
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 12) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3887
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 16) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3892
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 20) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3897
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 24) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3902
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 28) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_AFRL -----------------------------------
// SVD Line: 3861
// SFDITEM_REG__GPIOF_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50001420) GPIO alternate function low register
// ( (unsigned int)((GPIOF_AFRL >> 0) & 0xFFFFFFFF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOF_AFRH -------------------------------
// SVD Line: 3909
unsigned int GPIOF_AFRH __AT (0x50001424);
// ------------------------------ Field Item: GPIOF_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3915
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 0) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3920
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 4) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3925
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 8) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3930
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 12) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3935
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 16) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3940
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 20) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3945
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 24) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3950
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 28) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_AFRH -----------------------------------
// SVD Line: 3909
// SFDITEM_REG__GPIOF_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50001424) GPIO alternate function highregister
// ( (unsigned int)((GPIOF_AFRH >> 0) & 0xFFFFFFFF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOF_BRR --------------------------------
// SVD Line: 3957
unsigned int GPIOF_BRR __AT (0x50001428);
// -------------------------------- Field Item: GPIOF_BRR_BR0 -----------------------------------
// SVD Line: 3964
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR1 -----------------------------------
// SVD Line: 3969
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR2 -----------------------------------
// SVD Line: 3974
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR3 -----------------------------------
// SVD Line: 3979
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR4 -----------------------------------
// SVD Line: 3984
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR5 -----------------------------------
// SVD Line: 3989
// - SFDITEM_FIELD__GPIOF_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR6 -----------------------------------
// SVD Line: 3994
// - SFDITEM_FIELD__GPIOF_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR7 -----------------------------------
// SVD Line: 3999
// - SFDITEM_FIELD__GPIOF_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR8 -----------------------------------
// SVD Line: 4004
// - SFDITEM_FIELD__GPIOF_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR9 -----------------------------------
// SVD Line: 4009
// - SFDITEM_FIELD__GPIOF_BRR_BR9
// BR9
//
// [Bit 9] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR10 -----------------------------------
// SVD Line: 4014
// - SFDITEM_FIELD__GPIOF_BRR_BR10
// BR10
//
// [Bit 10] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR11 -----------------------------------
// SVD Line: 4019
// - SFDITEM_FIELD__GPIOF_BRR_BR11
// BR11
//
// [Bit 11] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR12 -----------------------------------
// SVD Line: 4024
// - SFDITEM_FIELD__GPIOF_BRR_BR12
// BR12
//
// [Bit 12] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR13 -----------------------------------
// SVD Line: 4029
// - SFDITEM_FIELD__GPIOF_BRR_BR13
// BR13
//
// [Bit 13] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR14 -----------------------------------
// SVD Line: 4034
// - SFDITEM_FIELD__GPIOF_BRR_BR14
// BR14
//
// [Bit 14] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR15 -----------------------------------
// SVD Line: 4039
// - SFDITEM_FIELD__GPIOF_BRR_BR15
// BR15
//
// [Bit 15] WO (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOF_BRR -----------------------------------
// SVD Line: 3957
// SFDITEM_REG__GPIOF_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50001428) port bit reset register
// ( (unsigned int)((GPIOF_BRR >> 0) & 0xFFFFFFFF), ((GPIOF_BRR = (GPIOF_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// - SFDITEM_FIELD__GPIOF_BRR_BR5
// - SFDITEM_FIELD__GPIOF_BRR_BR6
// - SFDITEM_FIELD__GPIOF_BRR_BR7
// - SFDITEM_FIELD__GPIOF_BRR_BR8
// - SFDITEM_FIELD__GPIOF_BRR_BR9
// - SFDITEM_FIELD__GPIOF_BRR_BR10
// - SFDITEM_FIELD__GPIOF_BRR_BR11
// - SFDITEM_FIELD__GPIOF_BRR_BR12
// - SFDITEM_FIELD__GPIOF_BRR_BR13
// - SFDITEM_FIELD__GPIOF_BRR_BR14
// - SFDITEM_FIELD__GPIOF_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOF -------------------------------------
// SVD Line: 4052
// GPIOF
// GPIOF
// - SFDITEM_REG__GPIOF_MODER
// - SFDITEM_REG__GPIOF_OTYPER
// - SFDITEM_REG__GPIOF_OSPEEDR
// - SFDITEM_REG__GPIOF_PUPDR
// - SFDITEM_REG__GPIOF_IDR
// - SFDITEM_REG__GPIOF_ODR
// - SFDITEM_REG__GPIOF_BSRR
// - SFDITEM_REG__GPIOF_LCKR
// - SFDITEM_REG__GPIOF_AFRL
// - SFDITEM_REG__GPIOF_AFRH
// - SFDITEM_REG__GPIOF_BRR
//
//
// ----------------------------- Register Item Address: I2C1_CR1 --------------------------------
// SVD Line: 4072
unsigned int I2C1_CR1 __AT (0x40005400);
// --------------------------------- Field Item: I2C1_CR1_PE ------------------------------------
// SVD Line: 4078
// - SFDITEM_FIELD__I2C1_CR1_PE
// PE
//
// [Bit 0] RW (@ 0x40005400) Peripheral enable
//
// ( (unsigned int) I2C1_CR1 )
// PE
//
//
//
// -------------------------------- Field Item: I2C1_CR1_ENGC -----------------------------------
// SVD Line: 4083
// - SFDITEM_FIELD__I2C1_CR1_ENGC
// ENGC
//
// [Bit 6] RW (@ 0x40005400) General call enable
//
// ( (unsigned int) I2C1_CR1 )
// ENGC
//
//
//
// ----------------------------- Field Item: I2C1_CR1_NOSTRETCH ---------------------------------
// SVD Line: 4088
// - SFDITEM_FIELD__I2C1_CR1_NOSTRETCH
// NOSTRETCH
//
// [Bit 7] RW (@ 0x40005400) Clock stretching disable (Slave mode)
//
// ( (unsigned int) I2C1_CR1 )
// NOSTRETCH
//
//
//
// ------------------------------- Field Item: I2C1_CR1_START -----------------------------------
// SVD Line: 4093
// - SFDITEM_FIELD__I2C1_CR1_START
// START
//
// [Bit 8] RW (@ 0x40005400) Start generation
//
// ( (unsigned int) I2C1_CR1 )
// START
//
//
//
// -------------------------------- Field Item: I2C1_CR1_STOP -----------------------------------
// SVD Line: 4098
// - SFDITEM_FIELD__I2C1_CR1_STOP
// STOP
//
// [Bit 9] RW (@ 0x40005400) Stop generation
//
// ( (unsigned int) I2C1_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: I2C1_CR1_ACK ------------------------------------
// SVD Line: 4103
// - SFDITEM_FIELD__I2C1_CR1_ACK
// ACK
//
// [Bit 10] RW (@ 0x40005400) Acknowledge enable
//
// ( (unsigned int) I2C1_CR1 )
// ACK
//
//
//
// -------------------------------- Field Item: I2C1_CR1_POS ------------------------------------
// SVD Line: 4108
// - SFDITEM_FIELD__I2C1_CR1_POS
// POS
//
// [Bit 11] RW (@ 0x40005400) Acknowledge/PEC Position (for data reception)
//
// ( (unsigned int) I2C1_CR1 )
// POS
//
//
//
// ------------------------------- Field Item: I2C1_CR1_SWRST -----------------------------------
// SVD Line: 4113
// - SFDITEM_FIELD__I2C1_CR1_SWRST
// SWRST
//
// [Bit 15] RW (@ 0x40005400) Software reset
//
// ( (unsigned int) I2C1_CR1 )
// SWRST
//
//
//
// -------------------------------- Register RTree: I2C1_CR1 ------------------------------------
// SVD Line: 4072
// SFDITEM_REG__I2C1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40005400) Control register 1
// ( (unsigned int)((I2C1_CR1 >> 0) & 0xFFFFFFFF), ((I2C1_CR1 = (I2C1_CR1 & ~(0x8FC1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8FC1) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CR1_PE
// - SFDITEM_FIELD__I2C1_CR1_ENGC
// - SFDITEM_FIELD__I2C1_CR1_NOSTRETCH
// - SFDITEM_FIELD__I2C1_CR1_START
// - SFDITEM_FIELD__I2C1_CR1_STOP
// - SFDITEM_FIELD__I2C1_CR1_ACK
// - SFDITEM_FIELD__I2C1_CR1_POS
// - SFDITEM_FIELD__I2C1_CR1_SWRST
//
//
// ----------------------------- Register Item Address: I2C1_CR2 --------------------------------
// SVD Line: 4120
unsigned int I2C1_CR2 __AT (0x40005404);
// -------------------------------- Field Item: I2C1_CR2_FREQ -----------------------------------
// SVD Line: 4126
// - SFDITEM_FIELD__I2C1_CR2_FREQ
// FREQ
//
// [Bits 6..0] RW (@ 0x40005404) Peripheral clock frequency
//
// ( (unsigned char)((I2C1_CR2 >> 0) & 0x7F), ((I2C1_CR2 = (I2C1_CR2 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: I2C1_CR2_ITERREN ----------------------------------
// SVD Line: 4131
// - SFDITEM_FIELD__I2C1_CR2_ITERREN
// ITERREN
//
// [Bit 8] RW (@ 0x40005404) Error interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ITERREN
//
//
//
// ------------------------------ Field Item: I2C1_CR2_ITEVTEN ----------------------------------
// SVD Line: 4136
// - SFDITEM_FIELD__I2C1_CR2_ITEVTEN
// ITEVTEN
//
// [Bit 9] RW (@ 0x40005404) Event interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ITEVTEN
//
//
//
// ------------------------------ Field Item: I2C1_CR2_ITBUFEN ----------------------------------
// SVD Line: 4141
// - SFDITEM_FIELD__I2C1_CR2_ITBUFEN
// ITBUFEN
//
// [Bit 10] RW (@ 0x40005404) Buffer interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ITBUFEN
//
//
//
// ------------------------------- Field Item: I2C1_CR2_DMAEN -----------------------------------
// SVD Line: 4146
// - SFDITEM_FIELD__I2C1_CR2_DMAEN
// DMAEN
//
// [Bit 11] RW (@ 0x40005404) DMA requests enable
//
// ( (unsigned int) I2C1_CR2 )
// DMAEN
//
//
//
// -------------------------------- Field Item: I2C1_CR2_LAST -----------------------------------
// SVD Line: 4151
// - SFDITEM_FIELD__I2C1_CR2_LAST
// LAST
//
// [Bit 12] RW (@ 0x40005404) DMA last transfer
//
// ( (unsigned int) I2C1_CR2 )
// LAST
//
//
//
// -------------------------------- Register RTree: I2C1_CR2 ------------------------------------
// SVD Line: 4120
// SFDITEM_REG__I2C1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40005404) Control register 2
// ( (unsigned int)((I2C1_CR2 >> 0) & 0xFFFFFFFF), ((I2C1_CR2 = (I2C1_CR2 & ~(0x1F7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F7F) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CR2_FREQ
// - SFDITEM_FIELD__I2C1_CR2_ITERREN
// - SFDITEM_FIELD__I2C1_CR2_ITEVTEN
// - SFDITEM_FIELD__I2C1_CR2_ITBUFEN
// - SFDITEM_FIELD__I2C1_CR2_DMAEN
// - SFDITEM_FIELD__I2C1_CR2_LAST
//
//
// ---------------------------- Register Item Address: I2C1_OAR1 --------------------------------
// SVD Line: 4158
unsigned int I2C1_OAR1 __AT (0x40005408);
// -------------------------------- Field Item: I2C1_OAR1_ADD -----------------------------------
// SVD Line: 4164
// - SFDITEM_FIELD__I2C1_OAR1_ADD
// ADD
//
// [Bits 7..1] RW (@ 0x40005408) Interface address
//
// ( (unsigned char)((I2C1_OAR1 >> 1) & 0x7F), ((I2C1_OAR1 = (I2C1_OAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C1_OAR1 -----------------------------------
// SVD Line: 4158
// SFDITEM_REG__I2C1_OAR1
// OAR1
//
// [Bits 31..0] RW (@ 0x40005408) Own address register 1
// ( (unsigned int)((I2C1_OAR1 >> 0) & 0xFFFFFFFF), ((I2C1_OAR1 = (I2C1_OAR1 & ~(0xFEUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFE) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_OAR1_ADD
//
//
// ----------------------------- Register Item Address: I2C1_DR ---------------------------------
// SVD Line: 4171
unsigned int I2C1_DR __AT (0x40005410);
// --------------------------------- Field Item: I2C1_DR_DR -------------------------------------
// SVD Line: 4177
// - SFDITEM_FIELD__I2C1_DR_DR
// DR
//
// [Bits 7..0] RW (@ 0x40005410) 8-bit data register
//
// ( (unsigned char)((I2C1_DR >> 0) & 0xFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: I2C1_DR ------------------------------------
// SVD Line: 4171
// SFDITEM_REG__I2C1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40005410) Data register
// ( (unsigned int)((I2C1_DR >> 0) & 0xFFFFFFFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_DR_DR
//
//
// ----------------------------- Register Item Address: I2C1_SR1 --------------------------------
// SVD Line: 4184
unsigned int I2C1_SR1 __AT (0x40005414);
// --------------------------------- Field Item: I2C1_SR1_SB ------------------------------------
// SVD Line: 4190
// - SFDITEM_FIELD__I2C1_SR1_SB
// SB
//
// [Bit 0] RO (@ 0x40005414) Start bit (Master mode)
//
// ( (unsigned int) I2C1_SR1 )
// SB
//
//
//
// -------------------------------- Field Item: I2C1_SR1_ADDR -----------------------------------
// SVD Line: 4196
// - SFDITEM_FIELD__I2C1_SR1_ADDR
// ADDR
//
// [Bit 1] RO (@ 0x40005414) Address sent (master mode)/matched (slave mode)
//
// ( (unsigned int) I2C1_SR1 )
// ADDR
//
//
//
// -------------------------------- Field Item: I2C1_SR1_BTF ------------------------------------
// SVD Line: 4202
// - SFDITEM_FIELD__I2C1_SR1_BTF
// BTF
//
// [Bit 2] RO (@ 0x40005414) Byte transfer finished
//
// ( (unsigned int) I2C1_SR1 )
// BTF
//
//
//
// ------------------------------- Field Item: I2C1_SR1_STOPF -----------------------------------
// SVD Line: 4208
// - SFDITEM_FIELD__I2C1_SR1_STOPF
// STOPF
//
// [Bit 4] RO (@ 0x40005414) Stop detection (slave mode)
//
// ( (unsigned int) I2C1_SR1 )
// STOPF
//
//
//
// -------------------------------- Field Item: I2C1_SR1_RxNE -----------------------------------
// SVD Line: 4214
// - SFDITEM_FIELD__I2C1_SR1_RxNE
// RxNE
//
// [Bit 6] RO (@ 0x40005414) Data register not empty (receivers)
//
// ( (unsigned int) I2C1_SR1 )
// RxNE
//
//
//
// -------------------------------- Field Item: I2C1_SR1_TxE ------------------------------------
// SVD Line: 4220
// - SFDITEM_FIELD__I2C1_SR1_TxE
// TxE
//
// [Bit 7] RO (@ 0x40005414) Data register empty (transmitters)
//
// ( (unsigned int) I2C1_SR1 )
// TxE
//
//
//
// -------------------------------- Field Item: I2C1_SR1_BERR -----------------------------------
// SVD Line: 4226
// - SFDITEM_FIELD__I2C1_SR1_BERR
// BERR
//
// [Bit 8] RW (@ 0x40005414) Bus error
//
// ( (unsigned int) I2C1_SR1 )
// BERR
//
//
//
// -------------------------------- Field Item: I2C1_SR1_ARLO -----------------------------------
// SVD Line: 4231
// - SFDITEM_FIELD__I2C1_SR1_ARLO
// ARLO
//
// [Bit 9] RW (@ 0x40005414) Arbitration lost (master mode)
//
// ( (unsigned int) I2C1_SR1 )
// ARLO
//
//
//
// --------------------------------- Field Item: I2C1_SR1_AF ------------------------------------
// SVD Line: 4236
// - SFDITEM_FIELD__I2C1_SR1_AF
// AF
//
// [Bit 10] RW (@ 0x40005414) Acknowledge failure
//
// ( (unsigned int) I2C1_SR1 )
// AF
//
//
//
// -------------------------------- Field Item: I2C1_SR1_OVR ------------------------------------
// SVD Line: 4241
// - SFDITEM_FIELD__I2C1_SR1_OVR
// OVR
//
// [Bit 11] RW (@ 0x40005414) Overrun/Underrun
//
// ( (unsigned int) I2C1_SR1 )
// OVR
//
//
//
// -------------------------------- Register RTree: I2C1_SR1 ------------------------------------
// SVD Line: 4184
// SFDITEM_REG__I2C1_SR1
// SR1
//
// [Bits 31..0] RW (@ 0x40005414) Status register 1
// ( (unsigned int)((I2C1_SR1 >> 0) & 0xFFFFFFFF), ((I2C1_SR1 = (I2C1_SR1 & ~(0xF00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF00) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_SR1_SB
// - SFDITEM_FIELD__I2C1_SR1_ADDR
// - SFDITEM_FIELD__I2C1_SR1_BTF
// - SFDITEM_FIELD__I2C1_SR1_STOPF
// - SFDITEM_FIELD__I2C1_SR1_RxNE
// - SFDITEM_FIELD__I2C1_SR1_TxE
// - SFDITEM_FIELD__I2C1_SR1_BERR
// - SFDITEM_FIELD__I2C1_SR1_ARLO
// - SFDITEM_FIELD__I2C1_SR1_AF
// - SFDITEM_FIELD__I2C1_SR1_OVR
//
//
// ----------------------------- Register Item Address: I2C1_SR2 --------------------------------
// SVD Line: 4248
unsigned int I2C1_SR2 __AT (0x40005418);
// -------------------------------- Field Item: I2C1_SR2_MSL ------------------------------------
// SVD Line: 4255
// - SFDITEM_FIELD__I2C1_SR2_MSL
// MSL
//
// [Bit 0] RO (@ 0x40005418) Master/slave
//
// ( (unsigned int) I2C1_SR2 )
// MSL
//
//
//
// -------------------------------- Field Item: I2C1_SR2_BUSY -----------------------------------
// SVD Line: 4260
// - SFDITEM_FIELD__I2C1_SR2_BUSY
// BUSY
//
// [Bit 1] RO (@ 0x40005418) Bus busy
//
// ( (unsigned int) I2C1_SR2 )
// BUSY
//
//
//
// -------------------------------- Field Item: I2C1_SR2_TRA ------------------------------------
// SVD Line: 4265
// - SFDITEM_FIELD__I2C1_SR2_TRA
// TRA
//
// [Bit 2] RO (@ 0x40005418) Transmitter/receiver
//
// ( (unsigned int) I2C1_SR2 )
// TRA
//
//
//
// ------------------------------ Field Item: I2C1_SR2_GENCALL ----------------------------------
// SVD Line: 4270
// - SFDITEM_FIELD__I2C1_SR2_GENCALL
// GENCALL
//
// [Bit 4] RO (@ 0x40005418) General call address (Slave mode)
//
// ( (unsigned int) I2C1_SR2 )
// GENCALL
//
//
//
// -------------------------------- Register RTree: I2C1_SR2 ------------------------------------
// SVD Line: 4248
// SFDITEM_REG__I2C1_SR2
// SR2
//
// [Bits 31..0] RO (@ 0x40005418) Status register 2
// ( (unsigned int)((I2C1_SR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__I2C1_SR2_MSL
// - SFDITEM_FIELD__I2C1_SR2_BUSY
// - SFDITEM_FIELD__I2C1_SR2_TRA
// - SFDITEM_FIELD__I2C1_SR2_GENCALL
//
//
// ----------------------------- Register Item Address: I2C1_CCR --------------------------------
// SVD Line: 4277
unsigned int I2C1_CCR __AT (0x4000541C);
// -------------------------------- Field Item: I2C1_CCR_CCR ------------------------------------
// SVD Line: 4283
// - SFDITEM_FIELD__I2C1_CCR_CCR
// CCR
//
// [Bits 11..0] RW (@ 0x4000541C) Clock control register in Fast/Standard mode (Master mode)
//
// ( (unsigned short)((I2C1_CCR >> 0) & 0xFFF), ((I2C1_CCR = (I2C1_CCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: I2C1_CCR_FP ------------------------------------
// SVD Line: 4288
// - SFDITEM_FIELD__I2C1_CCR_FP
// FP
//
// [Bit 13] RW (@ 0x4000541C) I2C master FP mode selection
//
// ( (unsigned int) I2C1_CCR )
// FP
//
//
//
// -------------------------------- Field Item: I2C1_CCR_DUTY -----------------------------------
// SVD Line: 4293
// - SFDITEM_FIELD__I2C1_CCR_DUTY
// DUTY
//
// [Bit 14] RW (@ 0x4000541C) Fast mode duty cycle
//
// ( (unsigned int) I2C1_CCR )
// DUTY
//
//
//
// --------------------------------- Field Item: I2C1_CCR_FS ------------------------------------
// SVD Line: 4298
// - SFDITEM_FIELD__I2C1_CCR_FS
// FS
//
// [Bit 15] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C1_CCR )
// FS
//
//
//
// -------------------------------- Register RTree: I2C1_CCR ------------------------------------
// SVD Line: 4277
// SFDITEM_REG__I2C1_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x4000541C) Clock control register
// ( (unsigned int)((I2C1_CCR >> 0) & 0xFFFFFFFF), ((I2C1_CCR = (I2C1_CCR & ~(0xEFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xEFFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CCR_CCR
// - SFDITEM_FIELD__I2C1_CCR_FP
// - SFDITEM_FIELD__I2C1_CCR_DUTY
// - SFDITEM_FIELD__I2C1_CCR_FS
//
//
// ---------------------------- Register Item Address: I2C1_TRISE -------------------------------
// SVD Line: 4305
unsigned int I2C1_TRISE __AT (0x40005420);
// ------------------------------ Field Item: I2C1_TRISE_TRISE ----------------------------------
// SVD Line: 4312
// - SFDITEM_FIELD__I2C1_TRISE_TRISE
// TRISE
//
// [Bits 6..0] RW (@ 0x40005420) Maximum rise time in Fast/Standard mode (Master mode)
//
// ( (unsigned char)((I2C1_TRISE >> 0) & 0x7F), ((I2C1_TRISE = (I2C1_TRISE & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: I2C1_TRISE_THOLDDATA --------------------------------
// SVD Line: 4317
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA
// THOLDDATA
//
// [Bits 11..7] RW (@ 0x40005420) desc THOLDDATA
//
// ( (unsigned char)((I2C1_TRISE >> 7) & 0x1F), ((I2C1_TRISE = (I2C1_TRISE & ~(0x1FUL << 7 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 7 ) ) ))
//
//
//
// -------------------------- Field Item: I2C1_TRISE_THOLDDATA_SEL ------------------------------
// SVD Line: 4322
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA_SEL
// THOLDDATA_SEL
//
// [Bit 12] RW (@ 0x40005420) desc THOLDDATA_SEL
//
// ( (unsigned int) I2C1_TRISE )
// THOLDDATA_SEL
//
//
//
// ------------------------------- Register RTree: I2C1_TRISE -----------------------------------
// SVD Line: 4305
// SFDITEM_REG__I2C1_TRISE
// TRISE
//
// [Bits 31..0] RW (@ 0x40005420) TRISE register
// ( (unsigned int)((I2C1_TRISE >> 0) & 0xFFFFFFFF), ((I2C1_TRISE = (I2C1_TRISE & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_TRISE_TRISE
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA_SEL
//
//
// ---------------------------------- Peripheral View: I2C1 -------------------------------------
// SVD Line: 4056
// I2C1
// I2C1
// - SFDITEM_REG__I2C1_CR1
// - SFDITEM_REG__I2C1_CR2
// - SFDITEM_REG__I2C1_OAR1
// - SFDITEM_REG__I2C1_DR
// - SFDITEM_REG__I2C1_SR1
// - SFDITEM_REG__I2C1_SR2
// - SFDITEM_REG__I2C1_CCR
// - SFDITEM_REG__I2C1_TRISE
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 4342
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 4349
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] WO (@ 0x40003000) Key value
//
// ( (unsigned short)((IWDG_KR >> 0) & 0x0), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 4342
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] WO (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 4356
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 4362
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) Prescaler divider
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 4356
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 4369
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 4376
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) Watchdog counter reload value
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 4369
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 4383
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 4390
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 4395
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 4383
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RO (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 4331
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM_ISR --------------------------------
// SVD Line: 4420
unsigned int LPTIM_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM_ISR_ARRM -----------------------------------
// SVD Line: 4427
// - SFDITEM_FIELD__LPTIM_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM_ISR )
// ARRM
//
//
//
// ------------------------------- Field Item: LPTIM_ISR_ARROK ----------------------------------
// SVD Line: 4432
// - SFDITEM_FIELD__LPTIM_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload OK
//
// ( (unsigned int) LPTIM_ISR )
// ARROK
//
//
//
// -------------------------------- Register RTree: LPTIM_ISR -----------------------------------
// SVD Line: 4420
// SFDITEM_REG__LPTIM_ISR
// ISR
//
// [Bits 31..0] RO (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM_ISR_ARRM
// - SFDITEM_FIELD__LPTIM_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM_ICR --------------------------------
// SVD Line: 4439
unsigned int LPTIM_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM_ICR_ARRMCF ----------------------------------
// SVD Line: 4446
// - SFDITEM_FIELD__LPTIM_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] WO (@ 0x40007C04) Autoreload match Clear Flag
//
// ( (unsigned int) LPTIM_ICR )
// ARRMCF
//
//
//
// ------------------------------ Field Item: LPTIM_ICR_ARROKCF ---------------------------------
// SVD Line: 4451
// - SFDITEM_FIELD__LPTIM_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] WO (@ 0x40007C04) Autoreload OK Clear Flag
//
// ( (unsigned int) LPTIM_ICR )
// ARROKCF
//
//
//
// -------------------------------- Register RTree: LPTIM_ICR -----------------------------------
// SVD Line: 4439
// SFDITEM_REG__LPTIM_ICR
// ICR
//
// [Bits 31..0] WO (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM_ICR >> 0) & 0xFFFFFFFF), ((LPTIM_ICR = (LPTIM_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM_IER --------------------------------
// SVD Line: 4458
unsigned int LPTIM_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM_IER_ARRMIE ----------------------------------
// SVD Line: 4464
// - SFDITEM_FIELD__LPTIM_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload match Interrupt Enable
//
// ( (unsigned int) LPTIM_IER )
// ARRMIE
//
//
//
// ------------------------------ Field Item: LPTIM_IER_ARROKIE ---------------------------------
// SVD Line: 4469
// - SFDITEM_FIELD__LPTIM_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload OK Interrupt Enable
//
// ( (unsigned int) LPTIM_IER )
// ARROKIE
//
//
//
// -------------------------------- Register RTree: LPTIM_IER -----------------------------------
// SVD Line: 4458
// SFDITEM_REG__LPTIM_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM_IER >> 0) & 0xFFFFFFFF), ((LPTIM_IER = (LPTIM_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM_IER_ARROKIE
//
//
// ---------------------------- Register Item Address: LPTIM_CFGR -------------------------------
// SVD Line: 4476
unsigned int LPTIM_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM_CFGR_PRESC ----------------------------------
// SVD Line: 4482
// - SFDITEM_FIELD__LPTIM_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM_CFGR >> 9) & 0x7), ((LPTIM_CFGR = (LPTIM_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM_CFGR_PRELOAD ---------------------------------
// SVD Line: 4487
// - SFDITEM_FIELD__LPTIM_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM_CFGR -----------------------------------
// SVD Line: 4476
// SFDITEM_REG__LPTIM_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM_CFGR = (LPTIM_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM_CFGR_PRELOAD
//
//
// ----------------------------- Register Item Address: LPTIM_CR --------------------------------
// SVD Line: 4494
unsigned int LPTIM_CR __AT (0x40007C10);
// ------------------------------- Field Item: LPTIM_CR_ENABLE ----------------------------------
// SVD Line: 4500
// - SFDITEM_FIELD__LPTIM_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM Enable
//
// ( (unsigned int) LPTIM_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM_CR_SNGSTRT ----------------------------------
// SVD Line: 4505
// - SFDITEM_FIELD__LPTIM_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in single mode
//
// ( (unsigned int) LPTIM_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM_CR_CNTSTRT ----------------------------------
// SVD Line: 4510
// - SFDITEM_FIELD__LPTIM_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) LPTIM start in continue mode
//
// ( (unsigned int) LPTIM_CR )
// CNTSTRT
//
//
//
// ------------------------------ Field Item: LPTIM_CR_COUNTRST ---------------------------------
// SVD Line: 4515
// - SFDITEM_FIELD__LPTIM_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) LPTIM counter reset
//
// ( (unsigned int) LPTIM_CR )
// COUNTRST
//
//
//
// ------------------------------- Field Item: LPTIM_CR_RSTARE ----------------------------------
// SVD Line: 4520
// - SFDITEM_FIELD__LPTIM_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM_CR ------------------------------------
// SVD Line: 4494
// SFDITEM_REG__LPTIM_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM_CR >> 0) & 0xFFFFFFFF), ((LPTIM_CR = (LPTIM_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_CR_ENABLE
// - SFDITEM_FIELD__LPTIM_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM_ARR --------------------------------
// SVD Line: 4527
unsigned int LPTIM_ARR __AT (0x40007C18);
// -------------------------------- Field Item: LPTIM_ARR_ARR -----------------------------------
// SVD Line: 4534
// - SFDITEM_FIELD__LPTIM_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM_ARR >> 0) & 0xFFFF), ((LPTIM_ARR = (LPTIM_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: LPTIM_ARR -----------------------------------
// SVD Line: 4527
// SFDITEM_REG__LPTIM_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM_ARR >> 0) & 0xFFFFFFFF), ((LPTIM_ARR = (LPTIM_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM_CNT --------------------------------
// SVD Line: 4541
unsigned int LPTIM_CNT __AT (0x40007C1C);
// -------------------------------- Field Item: LPTIM_CNT_CNT -----------------------------------
// SVD Line: 4548
// - SFDITEM_FIELD__LPTIM_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM_CNT >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: LPTIM_CNT -----------------------------------
// SVD Line: 4541
// SFDITEM_REG__LPTIM_CNT
// CNT
//
// [Bits 31..0] RO (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM -------------------------------------
// SVD Line: 4404
// LPTIM
// LPTIM
// - SFDITEM_REG__LPTIM_ISR
// - SFDITEM_REG__LPTIM_ICR
// - SFDITEM_REG__LPTIM_IER
// - SFDITEM_REG__LPTIM_CFGR
// - SFDITEM_REG__LPTIM_CR
// - SFDITEM_REG__LPTIM_ARR
// - SFDITEM_REG__LPTIM_CNT
//
//
// ----------------------------- Register Item Address: OPA_OENR --------------------------------
// SVD Line: 4568
unsigned int OPA_OENR __AT (0x40010330);
// ------------------------------ Field Item: OPA_OENR_OPA1OEN ----------------------------------
// SVD Line: 4574
// - SFDITEM_FIELD__OPA_OENR_OPA1OEN
// OPA1OEN
//
// [Bit 1] RW (@ 0x40010330) OPA1 output enable
//
// ( (unsigned int) OPA_OENR )
// OPA1OEN
//
//
//
// ------------------------------ Field Item: OPA_OENR_OPA2OEN ----------------------------------
// SVD Line: 4579
// - SFDITEM_FIELD__OPA_OENR_OPA2OEN
// OPA2OEN
//
// [Bit 6] RW (@ 0x40010330) OPA2 output enable
//
// ( (unsigned int) OPA_OENR )
// OPA2OEN
//
//
//
// -------------------------------- Register RTree: OPA_OENR ------------------------------------
// SVD Line: 4568
// SFDITEM_REG__OPA_OENR
// OENR
//
// [Bits 31..0] RW (@ 0x40010330) OPA output enable register
// ( (unsigned int)((OPA_OENR >> 0) & 0xFFFFFFFF), ((OPA_OENR = (OPA_OENR & ~(0x42UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x42) << 0 ) ) ))
// - SFDITEM_FIELD__OPA_OENR_OPA1OEN
// - SFDITEM_FIELD__OPA_OENR_OPA2OEN
//
//
// ------------------------------ Register Item Address: OPA_CR ---------------------------------
// SVD Line: 4586
unsigned int OPA_CR __AT (0x40010334);
// -------------------------------- Field Item: OPA_CR_OPA1EN -----------------------------------
// SVD Line: 4592
// - SFDITEM_FIELD__OPA_CR_OPA1EN
// OPA1EN
//
// [Bit 5] RW (@ 0x40010334) OPA1 enable
//
// ( (unsigned int) OPA_CR )
// OPA1EN
//
//
//
// -------------------------------- Field Item: OPA_CR_OPA2EN -----------------------------------
// SVD Line: 4597
// - SFDITEM_FIELD__OPA_CR_OPA2EN
// OPA2EN
//
// [Bit 6] RW (@ 0x40010334) OPA2 enable
//
// ( (unsigned int) OPA_CR )
// OPA2EN
//
//
//
// --------------------------------- Register RTree: OPA_CR -------------------------------------
// SVD Line: 4586
// SFDITEM_REG__OPA_CR
// CR
//
// [Bits 31..0] RW (@ 0x40010334) OPA control register
// ( (unsigned int)((OPA_CR >> 0) & 0xFFFFFFFF), ((OPA_CR = (OPA_CR & ~(0x60UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x60) << 0 ) ) ))
// - SFDITEM_FIELD__OPA_CR_OPA1EN
// - SFDITEM_FIELD__OPA_CR_OPA2EN
//
//
// ---------------------------------- Peripheral View: OPA --------------------------------------
// SVD Line: 4557
// OPA
// OPA
// - SFDITEM_REG__OPA_OENR
// - SFDITEM_REG__OPA_CR
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 4617
unsigned int PWR_CR1 __AT (0x40007000);
// --------------------------------- Field Item: PWR_CR1_DBP ------------------------------------
// SVD Line: 4624
// - SFDITEM_FIELD__PWR_CR1_DBP
// DBP
//
// [Bit 8] RW (@ 0x40007000) Disable backup domain write protection
//
// ( (unsigned int) PWR_CR1 )
// DBP
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 4629
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) Flash wait time after wakeup from the stop mode
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------------- Field Item: PWR_CR1_LPR ------------------------------------
// SVD Line: 4634
// - SFDITEM_FIELD__PWR_CR1_LPR
// LPR
//
// [Bit 14] RW (@ 0x40007000) Low-power run
//
// ( (unsigned int) PWR_CR1 )
// LPR
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 4617
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0x7100UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7100) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_DBP
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_LPR
//
//
// ----------------------------- Register Item Address: PWR_CR2 ---------------------------------
// SVD Line: 4641
unsigned int PWR_CR2 __AT (0x40007004);
// -------------------------------- Field Item: PWR_CR2_PVDE ------------------------------------
// SVD Line: 4648
// - SFDITEM_FIELD__PWR_CR2_PVDE
// PVDE
//
// [Bit 0] RW (@ 0x40007004) Power voltage detector enable
//
// ( (unsigned int) PWR_CR2 )
// PVDE
//
//
//
// ------------------------------- Field Item: PWR_CR2_SRCSEL -----------------------------------
// SVD Line: 4653
// - SFDITEM_FIELD__PWR_CR2_SRCSEL
// SRCSEL
//
// [Bit 2] RW (@ 0x40007004) Power voltage detector volatage selection
//
// ( (unsigned int) PWR_CR2 )
// SRCSEL
//
//
//
// -------------------------------- Field Item: PWR_CR2_PVDT ------------------------------------
// SVD Line: 4658
// - SFDITEM_FIELD__PWR_CR2_PVDT
// PVDT
//
// [Bits 6..4] RW (@ 0x40007004) Power voltage detector threshold selection
//
// ( (unsigned char)((PWR_CR2 >> 4) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: PWR_CR2_FLTEN -----------------------------------
// SVD Line: 4663
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// FLTEN
//
// [Bit 8] RW (@ 0x40007004) Digital filter enable
//
// ( (unsigned int) PWR_CR2 )
// FLTEN
//
//
//
// ------------------------------ Field Item: PWR_CR2_FLT_TIME ----------------------------------
// SVD Line: 4668
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
// FLT_TIME
//
// [Bits 11..9] RW (@ 0x40007004) Digital filter time configuration
//
// ( (unsigned char)((PWR_CR2 >> 9) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWR_CR2 ------------------------------------
// SVD Line: 4641
// SFDITEM_REG__PWR_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40007004) Power control register 2
// ( (unsigned int)((PWR_CR2 >> 0) & 0xFFFFFFFF), ((PWR_CR2 = (PWR_CR2 & ~(0xF75UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF75) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR2_PVDE
// - SFDITEM_FIELD__PWR_CR2_SRCSEL
// - SFDITEM_FIELD__PWR_CR2_PVDT
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
//
//
// ------------------------------ Register Item Address: PWR_SR ---------------------------------
// SVD Line: 4675
unsigned int PWR_SR __AT (0x40007014);
// --------------------------------- Field Item: PWR_SR_PVDO ------------------------------------
// SVD Line: 4682
// - SFDITEM_FIELD__PWR_SR_PVDO
// PVDO
//
// [Bit 11] RO (@ 0x40007014) PVD output
//
// ( (unsigned int) PWR_SR )
// PVDO
//
//
//
// --------------------------------- Register RTree: PWR_SR -------------------------------------
// SVD Line: 4675
// SFDITEM_REG__PWR_SR
// SR
//
// [Bits 31..0] RO (@ 0x40007014) Power status register
// ( (unsigned int)((PWR_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__PWR_SR_PVDO
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 4606
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
// - SFDITEM_REG__PWR_CR2
// - SFDITEM_REG__PWR_SR
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 4707
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 4714
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI16 clock enable
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 4719
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RW (@ 0x40021000) HSI16 clock ready flag
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 4724
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI16 clock division factor
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEON ------------------------------------
// SVD Line: 4729
// - SFDITEM_FIELD__RCC_CR_HSEON
// HSEON
//
// [Bit 16] RW (@ 0x40021000) HSE clock enable
//
// ( (unsigned int) RCC_CR )
// HSEON
//
//
//
// -------------------------------- Field Item: RCC_CR_HSERDY -----------------------------------
// SVD Line: 4734
// - SFDITEM_FIELD__RCC_CR_HSERDY
// HSERDY
//
// [Bit 17] RW (@ 0x40021000) HSE clock ready flag
//
// ( (unsigned int) RCC_CR )
// HSERDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEBYP -----------------------------------
// SVD Line: 4739
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// HSEBYP
//
// [Bit 18] RW (@ 0x40021000) HSE crystal oscillator bypass
//
// ( (unsigned int) RCC_CR )
// HSEBYP
//
//
//
// ------------------------------ Field Item: RCC_CR_HSE_CSSON ----------------------------------
// SVD Line: 4744
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
// HSE_CSSON
//
// [Bit 19] RW (@ 0x40021000) Clock security system enable
//
// ( (unsigned int) RCC_CR )
// HSE_CSSON
//
//
//
// -------------------------------- Field Item: RCC_CR_PLLON ------------------------------------
// SVD Line: 4749
// - SFDITEM_FIELD__RCC_CR_PLLON
// PLLON
//
// [Bit 24] RW (@ 0x40021000) PLL enable
//
// ( (unsigned int) RCC_CR )
// PLLON
//
//
//
// -------------------------------- Field Item: RCC_CR_PLLRDY -----------------------------------
// SVD Line: 4754
// - SFDITEM_FIELD__RCC_CR_PLLRDY
// PLLRDY
//
// [Bit 25] RW (@ 0x40021000) PLL clock ready flag
//
// ( (unsigned int) RCC_CR )
// PLLRDY
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 4707
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0x30F3D00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30F3D00) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// - SFDITEM_FIELD__RCC_CR_HSEON
// - SFDITEM_FIELD__RCC_CR_HSERDY
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
// - SFDITEM_FIELD__RCC_CR_PLLON
// - SFDITEM_FIELD__RCC_CR_PLLRDY
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 4761
unsigned int RCC_ICSCR __AT (0x40021004);
// ----------------------------- Field Item: RCC_ICSCR_HSI_TRIM ---------------------------------
// SVD Line: 4768
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// HSI_TRIM
//
// [Bits 12..0] RW (@ 0x40021004) HSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0x1FFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 4773
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bits 15..13] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 13) & 0x7), ((RCC_ICSCR = (RCC_ICSCR & ~(0x7UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 13 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 4778
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 24..16] RW (@ 0x40021004) LSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 16) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 4761
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibrationregister
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 4785
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 4791
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock switch
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 4796
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RO (@ 0x40021008) System clock switch status
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7) )
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 4802
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) AHB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 4807
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 4812
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 27..24] RW (@ 0x40021008) Microcontroller clock output
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 4817
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 30..28] RW (@ 0x40021008) Microcontroller clock output prescaler
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 4785
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0x7F007F07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F007F07) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// --------------------------- Register Item Address: RCC_PLLCFGR -------------------------------
// SVD Line: 4824
unsigned int RCC_PLLCFGR __AT (0x4002100C);
// ----------------------------- Field Item: RCC_PLLCFGR_PLLSRC ---------------------------------
// SVD Line: 4830
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLSRC
// PLLSRC
//
// [Bit 0] RW (@ 0x4002100C) PLL clock source selection
//
// ( (unsigned int) RCC_PLLCFGR )
// PLLSRC
//
//
//
// ----------------------------- Field Item: RCC_PLLCFGR_PLLMUL ---------------------------------
// SVD Line: 4835
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLMUL
// PLLMUL
//
// [Bits 3..2] RW (@ 0x4002100C) PLL clock mul
//
// ( (unsigned char)((RCC_PLLCFGR >> 2) & 0x3), ((RCC_PLLCFGR = (RCC_PLLCFGR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------- Register RTree: RCC_PLLCFGR ----------------------------------
// SVD Line: 4824
// SFDITEM_REG__RCC_PLLCFGR
// PLLCFGR
//
// [Bits 31..0] RW (@ 0x4002100C) PLL configuration register
// ( (unsigned int)((RCC_PLLCFGR >> 0) & 0xFFFFFFFF), ((RCC_PLLCFGR = (RCC_PLLCFGR & ~(0xDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLSRC
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLMUL
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 4842
unsigned int RCC_ECSCR __AT (0x40021010);
// ---------------------------- Field Item: RCC_ECSCR_HSE_DRIVER --------------------------------
// SVD Line: 4849
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRIVER
// HSE_DRIVER
//
// [Bits 1..0] RW (@ 0x40021010) HSE clock driver selection
//
// ( (unsigned char)((RCC_ECSCR >> 0) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_HSE_STARTUP -------------------------------
// SVD Line: 4854
// - SFDITEM_FIELD__RCC_ECSCR_HSE_STARTUP
// HSE_STARTUP
//
// [Bits 4..3] RW (@ 0x40021010) HSE clock start up
//
// ( (unsigned char)((RCC_ECSCR >> 3) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 4842
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x1BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRIVER
// - SFDITEM_FIELD__RCC_ECSCR_HSE_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 4861
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 4867
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 4872
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSERDYIE ---------------------------------
// SVD Line: 4877
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
// HSERDYIE
//
// [Bit 4] RW (@ 0x40021018) HSE ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// HSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_PLLRDYIE ---------------------------------
// SVD Line: 4882
// - SFDITEM_FIELD__RCC_CIER_PLLRDYIE
// PLLRDYIE
//
// [Bit 5] RW (@ 0x40021018) PLL ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// PLLRDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 4861
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enableregister
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0x39UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x39) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
// - SFDITEM_FIELD__RCC_CIER_PLLRDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 4889
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 4896
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 4901
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSERDYF ----------------------------------
// SVD Line: 4906
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// HSERDYF
//
// [Bit 4] RO (@ 0x4002101C) HSE ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_PLLRDYF ----------------------------------
// SVD Line: 4911
// - SFDITEM_FIELD__RCC_CIFR_PLLRDYF
// PLLRDYF
//
// [Bit 5] RO (@ 0x4002101C) PLL ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// PLLRDYF
//
//
//
// -------------------------------- Field Item: RCC_CIFR_CSSF -----------------------------------
// SVD Line: 4916
// - SFDITEM_FIELD__RCC_CIFR_CSSF
// CSSF
//
// [Bit 8] RO (@ 0x4002101C) HSE clock secure system interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// CSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 4889
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RO (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// - SFDITEM_FIELD__RCC_CIFR_PLLRDYF
// - SFDITEM_FIELD__RCC_CIFR_CSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 4923
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 4930
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] WO (@ 0x40021020) LSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 4935
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] WO (@ 0x40021020) HSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSERDYC ----------------------------------
// SVD Line: 4940
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// HSERDYC
//
// [Bit 4] WO (@ 0x40021020) HSE ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// HSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_PLLRDYC ----------------------------------
// SVD Line: 4945
// - SFDITEM_FIELD__RCC_CICR_PLLRDYC
// PLLRDYC
//
// [Bit 5] WO (@ 0x40021020) PLL ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// PLLRDYC
//
//
//
// -------------------------------- Field Item: RCC_CICR_CSSC -----------------------------------
// SVD Line: 4950
// - SFDITEM_FIELD__RCC_CICR_CSSC
// CSSC
//
// [Bit 8] WO (@ 0x40021020) clock secure system interrupt flag clear
//
// ( (unsigned int) RCC_CICR )
// CSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 4923
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] WO (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x139UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x139) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// - SFDITEM_FIELD__RCC_CICR_PLLRDYC
// - SFDITEM_FIELD__RCC_CICR_CSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 4957
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 4963
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O port A reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 4968
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O port B reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOFRST --------------------------------
// SVD Line: 4973
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
// GPIOFRST
//
// [Bit 5] RW (@ 0x40021024) I/O port F reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOFRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 4957
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
//
//
// --------------------------- Register Item Address: RCC_AHBRSTR -------------------------------
// SVD Line: 4980
unsigned int RCC_AHBRSTR __AT (0x40021028);
// ----------------------------- Field Item: RCC_AHBRSTR_DMARST ---------------------------------
// SVD Line: 4986
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// DMARST
//
// [Bit 0] RW (@ 0x40021028) DMA reset
//
// ( (unsigned int) RCC_AHBRSTR )
// DMARST
//
//
//
// ----------------------------- Field Item: RCC_AHBRSTR_CRCRST ---------------------------------
// SVD Line: 4991
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// CRCRST
//
// [Bit 12] RW (@ 0x40021028) CRC reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CRCRST
//
//
//
// ----------------------------- Field Item: RCC_AHBRSTR_HDIVRST --------------------------------
// SVD Line: 4996
// - SFDITEM_FIELD__RCC_AHBRSTR_HDIVRST
// HDIVRST
//
// [Bit 24] RW (@ 0x40021028) DIV reset
//
// ( (unsigned int) RCC_AHBRSTR )
// HDIVRST
//
//
//
// ---------------------------- Field Item: RCC_AHBRSTR_CORDICRST -------------------------------
// SVD Line: 5001
// - SFDITEM_FIELD__RCC_AHBRSTR_CORDICRST
// CORDICRST
//
// [Bit 25] RW (@ 0x40021028) CORDIC reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CORDICRST
//
//
//
// ------------------------------- Register RTree: RCC_AHBRSTR ----------------------------------
// SVD Line: 4980
// SFDITEM_REG__RCC_AHBRSTR
// AHBRSTR
//
// [Bits 31..0] RW (@ 0x40021028) AHB peripheral reset register
// ( (unsigned int)((RCC_AHBRSTR >> 0) & 0xFFFFFFFF), ((RCC_AHBRSTR = (RCC_AHBRSTR & ~(0x3001001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3001001) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// - SFDITEM_FIELD__RCC_AHBRSTR_HDIVRST
// - SFDITEM_FIELD__RCC_AHBRSTR_CORDICRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 5008
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// ---------------------------- Field Item: RCC_APBRSTR1_TIM2RST --------------------------------
// SVD Line: 5014
// - SFDITEM_FIELD__RCC_APBRSTR1_TIM2RST
// TIM2RST
//
// [Bit 0] RW (@ 0x4002102C) TIM2 timer reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// TIM2RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR1_RTCAPBRST -------------------------------
// SVD Line: 5019
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// RTCAPBRST
//
// [Bit 10] RW (@ 0x4002102C) RTC APB reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// RTCAPBRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_WWDGRST --------------------------------
// SVD Line: 5024
// - SFDITEM_FIELD__RCC_APBRSTR1_WWDGRST
// WWDGRST
//
// [Bit 11] RW (@ 0x4002102C) WWDG reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// WWDGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_SPI2RST --------------------------------
// SVD Line: 5029
// - SFDITEM_FIELD__RCC_APBRSTR1_SPI2RST
// SPI2RST
//
// [Bit 14] RW (@ 0x4002102C) SPI2 reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// SPI2RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR1_USART2RST -------------------------------
// SVD Line: 5034
// - SFDITEM_FIELD__RCC_APBRSTR1_USART2RST
// USART2RST
//
// [Bit 17] RW (@ 0x4002102C) USART2 reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// USART2RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_I2C1RST --------------------------------
// SVD Line: 5039
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// I2C1RST
//
// [Bit 21] RW (@ 0x4002102C) I2C1 reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// I2C1RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 5044
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) Debug support reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 5049
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) Power interface reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_OPARST --------------------------------
// SVD Line: 5054
// - SFDITEM_FIELD__RCC_APBRSTR1_OPARST
// OPARST
//
// [Bit 30] RW (@ 0x4002102C) OPA reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// OPARST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_LPTIMRST -------------------------------
// SVD Line: 5059
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
// LPTIMRST
//
// [Bit 31] RW (@ 0x4002102C) Low Power Timer reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPTIMRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 5008
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APB peripheral reset register1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0xD8224C01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD8224C01) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_TIM2RST
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// - SFDITEM_FIELD__RCC_APBRSTR1_WWDGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_SPI2RST
// - SFDITEM_FIELD__RCC_APBRSTR1_USART2RST
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// - SFDITEM_FIELD__RCC_APBRSTR1_OPARST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 5066
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 5072
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) SYSCFG and COMP reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 5077
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) TIM1 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_SPI1RST --------------------------------
// SVD Line: 5082
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// SPI1RST
//
// [Bit 12] RW (@ 0x40021030) SPI1 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SPI1RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR2_USART1RST -------------------------------
// SVD Line: 5087
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// USART1RST
//
// [Bit 14] RW (@ 0x40021030) USART1 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// USART1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 5092
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) TIM14 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM16RST -------------------------------
// SVD Line: 5097
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM16RST
// TIM16RST
//
// [Bit 17] RW (@ 0x40021030) TIM16 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM16RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM17RST -------------------------------
// SVD Line: 5102
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM17RST
// TIM17RST
//
// [Bit 18] RW (@ 0x40021030) TIM17 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM17RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_ADCRST --------------------------------
// SVD Line: 5107
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// ADCRST
//
// [Bit 20] RW (@ 0x40021030) ADC reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// ADCRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP1RST -------------------------------
// SVD Line: 5112
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// COMP1RST
//
// [Bit 21] RW (@ 0x40021030) COMP1 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP2RST -------------------------------
// SVD Line: 5117
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// COMP2RST
//
// [Bit 22] RW (@ 0x40021030) COMP2 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP2RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_LCDRST --------------------------------
// SVD Line: 5122
// - SFDITEM_FIELD__RCC_APBRSTR2_LCDRST
// LCDRST
//
// [Bit 24] RW (@ 0x40021030) LCD reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// LCDRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 5066
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x176D801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x176D801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM16RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM17RST
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// - SFDITEM_FIELD__RCC_APBRSTR2_LCDRST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 5129
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 5135
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O port A clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 5140
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O port B clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOFEN ---------------------------------
// SVD Line: 5145
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
// GPIOFEN
//
// [Bit 5] RW (@ 0x40021034) I/O port F clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOFEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 5129
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 5152
unsigned int RCC_AHBENR __AT (0x40021038);
// ------------------------------ Field Item: RCC_AHBENR_DMAEN ----------------------------------
// SVD Line: 5158
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// DMAEN
//
// [Bit 0] RW (@ 0x40021038) DMA clock enable
//
// ( (unsigned int) RCC_AHBENR )
// DMAEN
//
//
//
// ----------------------------- Field Item: RCC_AHBENR_FLASHEN ---------------------------------
// SVD Line: 5163
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// FLASHEN
//
// [Bit 8] RW (@ 0x40021038) Flash memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// FLASHEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_SRAMEN ---------------------------------
// SVD Line: 5168
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// SRAMEN
//
// [Bit 9] RW (@ 0x40021038) SRAM memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// SRAMEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_CRCEN ----------------------------------
// SVD Line: 5173
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// CRCEN
//
// [Bit 12] RW (@ 0x40021038) CRC clock enable
//
// ( (unsigned int) RCC_AHBENR )
// CRCEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_HDIVEN ---------------------------------
// SVD Line: 5178
// - SFDITEM_FIELD__RCC_AHBENR_HDIVEN
// HDIVEN
//
// [Bit 24] RW (@ 0x40021038) DIV clockenable
//
// ( (unsigned int) RCC_AHBENR )
// HDIVEN
//
//
//
// ----------------------------- Field Item: RCC_AHBENR_CORDICEN --------------------------------
// SVD Line: 5183
// - SFDITEM_FIELD__RCC_AHBENR_CORDICEN
// CORDICEN
//
// [Bit 25] RW (@ 0x40021038) CORDIC clock enable
//
// ( (unsigned int) RCC_AHBENR )
// CORDICEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 5152
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enableregister
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x3001301UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3001301) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// - SFDITEM_FIELD__RCC_AHBENR_HDIVEN
// - SFDITEM_FIELD__RCC_AHBENR_CORDICEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 5190
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ----------------------------- Field Item: RCC_APBENR1_TIM2EN ---------------------------------
// SVD Line: 5196
// - SFDITEM_FIELD__RCC_APBENR1_TIM2EN
// TIM2EN
//
// [Bit 0] RW (@ 0x4002103C) TIM2 timer clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// TIM2EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR1_RTCAPBEN --------------------------------
// SVD Line: 5201
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// RTCAPBEN
//
// [Bit 10] RW (@ 0x4002103C) RTC APB clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// RTCAPBEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_WWDGEN ---------------------------------
// SVD Line: 5206
// - SFDITEM_FIELD__RCC_APBENR1_WWDGEN
// WWDGEN
//
// [Bit 11] RW (@ 0x4002103C) WWDG clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// WWDGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_SPI2EN ---------------------------------
// SVD Line: 5211
// - SFDITEM_FIELD__RCC_APBENR1_SPI2EN
// SPI2EN
//
// [Bit 14] RW (@ 0x4002103C) SPI2 clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// SPI2EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR1_USART2EN --------------------------------
// SVD Line: 5216
// - SFDITEM_FIELD__RCC_APBENR1_USART2EN
// USART2EN
//
// [Bit 17] RW (@ 0x4002103C) USART2 clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// USART2EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_I2C1EN ---------------------------------
// SVD Line: 5221
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// I2C1EN
//
// [Bit 21] RW (@ 0x4002103C) I2C1 clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// I2C1EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 5226
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) Debug support clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 5231
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) Power interface clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_OPAEN ---------------------------------
// SVD Line: 5236
// - SFDITEM_FIELD__RCC_APBENR1_OPAEN
// OPAEN
//
// [Bit 30] RW (@ 0x4002103C) OPA clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// OPAEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_LPTIMEN --------------------------------
// SVD Line: 5241
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
// LPTIMEN
//
// [Bit 31] RW (@ 0x4002103C) LPTIM clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// LPTIMEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 5190
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0xD8224C01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD8224C01) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_TIM2EN
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// - SFDITEM_FIELD__RCC_APBENR1_WWDGEN
// - SFDITEM_FIELD__RCC_APBENR1_SPI2EN
// - SFDITEM_FIELD__RCC_APBENR1_USART2EN
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// - SFDITEM_FIELD__RCC_APBENR1_OPAEN
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 5248
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 5254
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) SYSCFG, COMP and VREFBUF clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 5259
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) TIM1 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_SPI1EN ---------------------------------
// SVD Line: 5264
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// SPI1EN
//
// [Bit 12] RW (@ 0x40021040) SPI1 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// SPI1EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR2_USART1EN --------------------------------
// SVD Line: 5269
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// USART1EN
//
// [Bit 14] RW (@ 0x40021040) USART1 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// USART1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 5274
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM16EN --------------------------------
// SVD Line: 5279
// - SFDITEM_FIELD__RCC_APBENR2_TIM16EN
// TIM16EN
//
// [Bit 17] RW (@ 0x40021040) TIM16 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM16EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM17EN --------------------------------
// SVD Line: 5284
// - SFDITEM_FIELD__RCC_APBENR2_TIM17EN
// TIM17EN
//
// [Bit 18] RW (@ 0x40021040) TIM16 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM17EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_ADCEN ---------------------------------
// SVD Line: 5289
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// ADCEN
//
// [Bit 20] RW (@ 0x40021040) ADC clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// ADCEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP1EN --------------------------------
// SVD Line: 5294
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// COMP1EN
//
// [Bit 21] RW (@ 0x40021040) COMP1 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP2EN --------------------------------
// SVD Line: 5299
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// COMP2EN
//
// [Bit 22] RW (@ 0x40021040) COMP2 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP2EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_LCDEN ---------------------------------
// SVD Line: 5304
// - SFDITEM_FIELD__RCC_APBENR2_LCDEN
// LCDEN
//
// [Bit 24] RW (@ 0x40021040) LCD clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// LCDEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 5248
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x176D801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x176D801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM16EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM17EN
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// - SFDITEM_FIELD__RCC_APBENR2_LCDEN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 5311
unsigned int RCC_CCIPR __AT (0x40021054);
// ---------------------------- Field Item: RCC_CCIPR_TIMCLKCTRL --------------------------------
// SVD Line: 5317
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLKCTRL
// TIMCLKCTRL
//
// [Bit 0] RW (@ 0x40021054) TIMER PCLK frequency control
//
// ( (unsigned int) RCC_CCIPR )
// TIMCLKCTRL
//
//
//
// ------------------------------ Field Item: RCC_CCIPR_PVDSEL ----------------------------------
// SVD Line: 5322
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// PVDSEL
//
// [Bit 7] RW (@ 0x40021054) PVD detect clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// PVDSEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP1SEL ---------------------------------
// SVD Line: 5327
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// COMP1SEL
//
// [Bit 8] RW (@ 0x40021054) COMP1 clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP1SEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP2SEL ---------------------------------
// SVD Line: 5332
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// COMP2SEL
//
// [Bit 9] RW (@ 0x40021054) COMP2 clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP2SEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_LPTIM1SEL --------------------------------
// SVD Line: 5337
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// LPTIM1SEL
//
// [Bits 19..18] RW (@ 0x40021054) LPTIM1 clock source selection
//
// ( (unsigned char)((RCC_CCIPR >> 18) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 5311
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configurationregister
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xC0381UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC0381) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLKCTRL
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 5344
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_RTCSEL ----------------------------------
// SVD Line: 5350
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// RTCSEL
//
// [Bits 9..8] RW (@ 0x4002105C) RTC clock source selection
//
// ( (unsigned char)((RCC_BDCR >> 8) & 0x3), ((RCC_BDCR = (RCC_BDCR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_BDCR_RTCEN -----------------------------------
// SVD Line: 5355
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// RTCEN
//
// [Bit 15] RW (@ 0x4002105C) RTC clock source enable
//
// ( (unsigned int) RCC_BDCR )
// RTCEN
//
//
//
// ------------------------------- Field Item: RCC_BDCR_BDRST -----------------------------------
// SVD Line: 5360
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// BDRST
//
// [Bit 16] RW (@ 0x4002105C) RTC domain software reset
//
// ( (unsigned int) RCC_BDCR )
// BDRST
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCSEL ----------------------------------
// SVD Line: 5365
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
// LSCSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock selection
//
// ( (unsigned int) RCC_BDCR )
// LSCSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 5344
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x2018300UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2018300) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 5372
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 5378
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI oscillator enable
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 5383
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RW (@ 0x40021060) LSI oscillator ready
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 5388
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Remove reset flags
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 5393
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RW (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 5398
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RW (@ 0x40021060) Pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PWRRSTF ----------------------------------
// SVD Line: 5403
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// PWRRSTF
//
// [Bit 27] RW (@ 0x40021060) BOR or POR/PDR flag
//
// ( (unsigned int) RCC_CSR )
// PWRRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 5408
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RW (@ 0x40021060) Software reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 5413
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RW (@ 0x40021060) Independent window watchdog reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_WWDGRSTF ----------------------------------
// SVD Line: 5418
// - SFDITEM_FIELD__RCC_CSR_WWDGRSTF
// WWDGRSTF
//
// [Bit 30] RW (@ 0x40021060) Window watchdog reset flag
//
// ( (unsigned int) RCC_CSR )
// WWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 5372
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x7E800003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7E800003) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// - SFDITEM_FIELD__RCC_CSR_WWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 4691
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_PLLCFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_AHBRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// ----------------------------- Register Item Address: RTC_CRH ---------------------------------
// SVD Line: 5443
unsigned int RTC_CRH __AT (0x40002800);
// -------------------------------- Field Item: RTC_CRH_SECIE -----------------------------------
// SVD Line: 5449
// - SFDITEM_FIELD__RTC_CRH_SECIE
// SECIE
//
// [Bit 0] RW (@ 0x40002800) Second interrupt Enable
//
// ( (unsigned int) RTC_CRH )
// SECIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_ALRIE -----------------------------------
// SVD Line: 5454
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// ALRIE
//
// [Bit 1] RW (@ 0x40002800) Alarm interrupt Enable
//
// ( (unsigned int) RTC_CRH )
// ALRIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_OWIE ------------------------------------
// SVD Line: 5459
// - SFDITEM_FIELD__RTC_CRH_OWIE
// OWIE
//
// [Bit 2] RW (@ 0x40002800) Overflow interrupt Enable
//
// ( (unsigned int) RTC_CRH )
// OWIE
//
//
//
// --------------------------------- Register RTree: RTC_CRH ------------------------------------
// SVD Line: 5443
// SFDITEM_REG__RTC_CRH
// CRH
//
// [Bits 31..0] RW (@ 0x40002800) RTC Control Register High
// ( (unsigned int)((RTC_CRH >> 0) & 0xFFFFFFFF), ((RTC_CRH = (RTC_CRH & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRH_SECIE
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// - SFDITEM_FIELD__RTC_CRH_OWIE
//
//
// ----------------------------- Register Item Address: RTC_CRL ---------------------------------
// SVD Line: 5466
unsigned int RTC_CRL __AT (0x40002804);
// -------------------------------- Field Item: RTC_CRL_SECF ------------------------------------
// SVD Line: 5473
// - SFDITEM_FIELD__RTC_CRL_SECF
// SECF
//
// [Bit 0] RW (@ 0x40002804) Second Flag
//
// ( (unsigned int) RTC_CRL )
// SECF
//
//
//
// -------------------------------- Field Item: RTC_CRL_ALRF ------------------------------------
// SVD Line: 5478
// - SFDITEM_FIELD__RTC_CRL_ALRF
// ALRF
//
// [Bit 1] RW (@ 0x40002804) Alarm Flag
//
// ( (unsigned int) RTC_CRL )
// ALRF
//
//
//
// --------------------------------- Field Item: RTC_CRL_OWF ------------------------------------
// SVD Line: 5483
// - SFDITEM_FIELD__RTC_CRL_OWF
// OWF
//
// [Bit 2] RW (@ 0x40002804) Overflow Flag
//
// ( (unsigned int) RTC_CRL )
// OWF
//
//
//
// --------------------------------- Field Item: RTC_CRL_RSF ------------------------------------
// SVD Line: 5488
// - SFDITEM_FIELD__RTC_CRL_RSF
// RSF
//
// [Bit 3] RW (@ 0x40002804) Registers Synchronized Flag
//
// ( (unsigned int) RTC_CRL )
// RSF
//
//
//
// --------------------------------- Field Item: RTC_CRL_CNF ------------------------------------
// SVD Line: 5493
// - SFDITEM_FIELD__RTC_CRL_CNF
// CNF
//
// [Bit 4] RW (@ 0x40002804) Configuration Flag
//
// ( (unsigned int) RTC_CRL )
// CNF
//
//
//
// -------------------------------- Field Item: RTC_CRL_RTOFF -----------------------------------
// SVD Line: 5498
// - SFDITEM_FIELD__RTC_CRL_RTOFF
// RTOFF
//
// [Bit 5] RO (@ 0x40002804) RTC operation OFF
//
// ( (unsigned int) RTC_CRL )
// RTOFF
//
//
//
// --------------------------------- Register RTree: RTC_CRL ------------------------------------
// SVD Line: 5466
// SFDITEM_REG__RTC_CRL
// CRL
//
// [Bits 31..0] RW (@ 0x40002804) RTC Control Register Low
// ( (unsigned int)((RTC_CRL >> 0) & 0xFFFFFFFF), ((RTC_CRL = (RTC_CRL & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRL_SECF
// - SFDITEM_FIELD__RTC_CRL_ALRF
// - SFDITEM_FIELD__RTC_CRL_OWF
// - SFDITEM_FIELD__RTC_CRL_RSF
// - SFDITEM_FIELD__RTC_CRL_CNF
// - SFDITEM_FIELD__RTC_CRL_RTOFF
//
//
// ----------------------------- Register Item Address: RTC_PRLH --------------------------------
// SVD Line: 5506
unsigned int RTC_PRLH __AT (0x40002808);
// -------------------------------- Field Item: RTC_PRLH_PRLH -----------------------------------
// SVD Line: 5513
// - SFDITEM_FIELD__RTC_PRLH_PRLH
// PRLH
//
// [Bits 3..0] WO (@ 0x40002808) RTC Prescaler Load Register High
//
// ( (unsigned char)((RTC_PRLH >> 0) & 0x0), ((RTC_PRLH = (RTC_PRLH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLH ------------------------------------
// SVD Line: 5506
// SFDITEM_REG__RTC_PRLH
// PRLH
//
// [Bits 31..0] WO (@ 0x40002808) RTC Prescaler Load Register High
// ( (unsigned int)((RTC_PRLH >> 0) & 0xFFFFFFFF), ((RTC_PRLH = (RTC_PRLH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLH_PRLH
//
//
// ----------------------------- Register Item Address: RTC_PRLL --------------------------------
// SVD Line: 5520
unsigned int RTC_PRLL __AT (0x4000280C);
// -------------------------------- Field Item: RTC_PRLL_PRLL -----------------------------------
// SVD Line: 5528
// - SFDITEM_FIELD__RTC_PRLL_PRLL
// PRLL
//
// [Bits 15..0] WO (@ 0x4000280C) RTC Prescaler Divider Register Low
//
// ( (unsigned short)((RTC_PRLL >> 0) & 0x0), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLL ------------------------------------
// SVD Line: 5520
// SFDITEM_REG__RTC_PRLL
// PRLL
//
// [Bits 31..0] WO (@ 0x4000280C) RTC Prescaler Load Register Low
// ( (unsigned int)((RTC_PRLL >> 0) & 0xFFFFFFFF), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLL_PRLL
//
//
// ----------------------------- Register Item Address: RTC_DIVH --------------------------------
// SVD Line: 5535
unsigned int RTC_DIVH __AT (0x40002810);
// -------------------------------- Field Item: RTC_DIVH_DIVH -----------------------------------
// SVD Line: 5542
// - SFDITEM_FIELD__RTC_DIVH_DIVH
// DIVH
//
// [Bits 3..0] RO (@ 0x40002810) RTC prescaler divider register high
//
// ( (unsigned char)((RTC_DIVH >> 0) & 0xF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVH ------------------------------------
// SVD Line: 5535
// SFDITEM_REG__RTC_DIVH
// DIVH
//
// [Bits 31..0] RO (@ 0x40002810) RTC Prescaler Divider Register High
// ( (unsigned int)((RTC_DIVH >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVH_DIVH
//
//
// ----------------------------- Register Item Address: RTC_DIVL --------------------------------
// SVD Line: 5549
unsigned int RTC_DIVL __AT (0x40002814);
// -------------------------------- Field Item: RTC_DIVL_DIVL -----------------------------------
// SVD Line: 5557
// - SFDITEM_FIELD__RTC_DIVL_DIVL
// DIVL
//
// [Bits 15..0] RO (@ 0x40002814) RTC prescaler divider register Low
//
// ( (unsigned short)((RTC_DIVL >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVL ------------------------------------
// SVD Line: 5549
// SFDITEM_REG__RTC_DIVL
// DIVL
//
// [Bits 31..0] RO (@ 0x40002814) RTC Prescaler Divider Register Low
// ( (unsigned int)((RTC_DIVL >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVL_DIVL
//
//
// ----------------------------- Register Item Address: RTC_CNTH --------------------------------
// SVD Line: 5564
unsigned int RTC_CNTH __AT (0x40002818);
// -------------------------------- Field Item: RTC_CNTH_CNTH -----------------------------------
// SVD Line: 5570
// - SFDITEM_FIELD__RTC_CNTH_CNTH
// CNTH
//
// [Bits 15..0] RW (@ 0x40002818) RTC counter register high
//
// ( (unsigned short)((RTC_CNTH >> 0) & 0xFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTH ------------------------------------
// SVD Line: 5564
// SFDITEM_REG__RTC_CNTH
// CNTH
//
// [Bits 31..0] RW (@ 0x40002818) RTC Counter Register High
// ( (unsigned int)((RTC_CNTH >> 0) & 0xFFFFFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTH_CNTH
//
//
// ----------------------------- Register Item Address: RTC_CNTL --------------------------------
// SVD Line: 5577
unsigned int RTC_CNTL __AT (0x4000281C);
// -------------------------------- Field Item: RTC_CNTL_CNTL -----------------------------------
// SVD Line: 5583
// - SFDITEM_FIELD__RTC_CNTL_CNTL
// CNTL
//
// [Bits 15..0] RW (@ 0x4000281C) RTC counter register Low
//
// ( (unsigned short)((RTC_CNTL >> 0) & 0xFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTL ------------------------------------
// SVD Line: 5577
// SFDITEM_REG__RTC_CNTL
// CNTL
//
// [Bits 31..0] RW (@ 0x4000281C) RTC Counter Register Low
// ( (unsigned int)((RTC_CNTL >> 0) & 0xFFFFFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTL_CNTL
//
//
// ----------------------------- Register Item Address: RTC_ALRH --------------------------------
// SVD Line: 5590
unsigned int RTC_ALRH __AT (0x40002820);
// -------------------------------- Field Item: RTC_ALRH_ALRH -----------------------------------
// SVD Line: 5597
// - SFDITEM_FIELD__RTC_ALRH_ALRH
// ALRH
//
// [Bits 15..0] RW (@ 0x40002820) RTC alarm register high
//
// ( (unsigned short)((RTC_ALRH >> 0) & 0xFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRH ------------------------------------
// SVD Line: 5590
// SFDITEM_REG__RTC_ALRH
// ALRH
//
// [Bits 31..0] RW (@ 0x40002820) RTC Alarm Register High
// ( (unsigned int)((RTC_ALRH >> 0) & 0xFFFFFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRH_ALRH
//
//
// ----------------------------- Register Item Address: RTC_ALRL --------------------------------
// SVD Line: 5604
unsigned int RTC_ALRL __AT (0x40002824);
// -------------------------------- Field Item: RTC_ALRL_ALRL -----------------------------------
// SVD Line: 5611
// - SFDITEM_FIELD__RTC_ALRL_ALRL
// ALRL
//
// [Bits 15..0] RW (@ 0x40002824) RTC alarm register low
//
// ( (unsigned short)((RTC_ALRL >> 0) & 0xFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRL ------------------------------------
// SVD Line: 5604
// SFDITEM_REG__RTC_ALRL
// ALRL
//
// [Bits 31..0] RW (@ 0x40002824) RTC Alarm Register Low
// ( (unsigned int)((RTC_ALRL >> 0) & 0xFFFFFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRL_ALRL
//
//
// ---------------------------- Register Item Address: RTC_RTCCR --------------------------------
// SVD Line: 5618
unsigned int RTC_RTCCR __AT (0x4000282C);
// -------------------------------- Field Item: RTC_RTCCR_CAL -----------------------------------
// SVD Line: 5624
// - SFDITEM_FIELD__RTC_RTCCR_CAL
// CAL
//
// [Bits 6..0] RW (@ 0x4000282C) Calibration value
//
// ( (unsigned char)((RTC_RTCCR >> 0) & 0x7F), ((RTC_RTCCR = (RTC_RTCCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RTC_RTCCR_CCO -----------------------------------
// SVD Line: 5629
// - SFDITEM_FIELD__RTC_RTCCR_CCO
// CCO
//
// [Bit 7] RW (@ 0x4000282C) Calibration clock output
//
// ( (unsigned int) RTC_RTCCR )
// CCO
//
//
//
// ------------------------------- Field Item: RTC_RTCCR_ASOE -----------------------------------
// SVD Line: 5634
// - SFDITEM_FIELD__RTC_RTCCR_ASOE
// ASOE
//
// [Bit 8] RW (@ 0x4000282C) Alarm or second output enable
//
// ( (unsigned int) RTC_RTCCR )
// ASOE
//
//
//
// ------------------------------- Field Item: RTC_RTCCR_ASOS -----------------------------------
// SVD Line: 5639
// - SFDITEM_FIELD__RTC_RTCCR_ASOS
// ASOS
//
// [Bit 9] RW (@ 0x4000282C) Alarm or second output selection
//
// ( (unsigned int) RTC_RTCCR )
// ASOS
//
//
//
// -------------------------------- Register RTree: RTC_RTCCR -----------------------------------
// SVD Line: 5618
// SFDITEM_REG__RTC_RTCCR
// RTCCR
//
// [Bits 31..0] RW (@ 0x4000282C) RTC clock calibration
// ( (unsigned int)((RTC_RTCCR >> 0) & 0xFFFFFFFF), ((RTC_RTCCR = (RTC_RTCCR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_RTCCR_CAL
// - SFDITEM_FIELD__RTC_RTCCR_CCO
// - SFDITEM_FIELD__RTC_RTCCR_ASOE
// - SFDITEM_FIELD__RTC_RTCCR_ASOS
//
//
// ---------------------------------- Peripheral View: RTC --------------------------------------
// SVD Line: 5427
// RTC
// RTC
// - SFDITEM_REG__RTC_CRH
// - SFDITEM_REG__RTC_CRL
// - SFDITEM_REG__RTC_PRLH
// - SFDITEM_REG__RTC_PRLL
// - SFDITEM_REG__RTC_DIVH
// - SFDITEM_REG__RTC_DIVL
// - SFDITEM_REG__RTC_CNTH
// - SFDITEM_REG__RTC_CNTL
// - SFDITEM_REG__RTC_ALRH
// - SFDITEM_REG__RTC_ALRL
// - SFDITEM_REG__RTC_RTCCR
//
//
// ----------------------------- Register Item Address: SPI1_CR1 --------------------------------
// SVD Line: 5664
unsigned int SPI1_CR1 __AT (0x40013000);
// -------------------------------- Field Item: SPI1_CR1_CPHA -----------------------------------
// SVD Line: 5670
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// CPHA
//
// [Bit 0] RW (@ 0x40013000) Clock phase
//
// ( (unsigned int) SPI1_CR1 )
// CPHA
//
//
//
// -------------------------------- Field Item: SPI1_CR1_CPOL -----------------------------------
// SVD Line: 5675
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// CPOL
//
// [Bit 1] RW (@ 0x40013000) Clock polarity
//
// ( (unsigned int) SPI1_CR1 )
// CPOL
//
//
//
// -------------------------------- Field Item: SPI1_CR1_MSTR -----------------------------------
// SVD Line: 5680
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// MSTR
//
// [Bit 2] RW (@ 0x40013000) Master selection
//
// ( (unsigned int) SPI1_CR1 )
// MSTR
//
//
//
// --------------------------------- Field Item: SPI1_CR1_BR ------------------------------------
// SVD Line: 5685
// - SFDITEM_FIELD__SPI1_CR1_BR
// BR
//
// [Bits 5..3] RW (@ 0x40013000) Baud rate control
//
// ( (unsigned char)((SPI1_CR1 >> 3) & 0x7), ((SPI1_CR1 = (SPI1_CR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SPE ------------------------------------
// SVD Line: 5690
// - SFDITEM_FIELD__SPI1_CR1_SPE
// SPE
//
// [Bit 6] RW (@ 0x40013000) SPI enable
//
// ( (unsigned int) SPI1_CR1 )
// SPE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_LSBFIRST ---------------------------------
// SVD Line: 5695
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// LSBFIRST
//
// [Bit 7] RW (@ 0x40013000) Frame format
//
// ( (unsigned int) SPI1_CR1 )
// LSBFIRST
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSI ------------------------------------
// SVD Line: 5700
// - SFDITEM_FIELD__SPI1_CR1_SSI
// SSI
//
// [Bit 8] RW (@ 0x40013000) Internal slave selection
//
// ( (unsigned int) SPI1_CR1 )
// SSI
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSM ------------------------------------
// SVD Line: 5705
// - SFDITEM_FIELD__SPI1_CR1_SSM
// SSM
//
// [Bit 9] RW (@ 0x40013000) Software slave management
//
// ( (unsigned int) SPI1_CR1 )
// SSM
//
//
//
// ------------------------------- Field Item: SPI1_CR1_RXONLY ----------------------------------
// SVD Line: 5710
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// RXONLY
//
// [Bit 10] RW (@ 0x40013000) Receive only
//
// ( (unsigned int) SPI1_CR1 )
// RXONLY
//
//
//
// -------------------------------- Field Item: SPI1_CR1_DFF ------------------------------------
// SVD Line: 5715
// - SFDITEM_FIELD__SPI1_CR1_DFF
// DFF
//
// [Bit 11] RW (@ 0x40013000) Data frame format
//
// ( (unsigned int) SPI1_CR1 )
// DFF
//
//
//
// ------------------------------ Field Item: SPI1_CR1_CRCNEXT ----------------------------------
// SVD Line: 5720
// - SFDITEM_FIELD__SPI1_CR1_CRCNEXT
// CRCNEXT
//
// [Bit 12] RW (@ 0x40013000) Transmit CRC next
//
// ( (unsigned int) SPI1_CR1 )
// CRCNEXT
//
//
//
// ------------------------------- Field Item: SPI1_CR1_CRCEN -----------------------------------
// SVD Line: 5725
// - SFDITEM_FIELD__SPI1_CR1_CRCEN
// CRCEN
//
// [Bit 13] RW (@ 0x40013000) Hardware CRC calculation enable
//
// ( (unsigned int) SPI1_CR1 )
// CRCEN
//
//
//
// ------------------------------- Field Item: SPI1_CR1_BIDIOE ----------------------------------
// SVD Line: 5730
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// BIDIOE
//
// [Bit 14] RW (@ 0x40013000) Output enable in bidirectional mode
//
// ( (unsigned int) SPI1_CR1 )
// BIDIOE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_BIDIMODE ---------------------------------
// SVD Line: 5735
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
// BIDIMODE
//
// [Bit 15] RW (@ 0x40013000) Bidirectional data mode enable
//
// ( (unsigned int) SPI1_CR1 )
// BIDIMODE
//
//
//
// -------------------------------- Register RTree: SPI1_CR1 ------------------------------------
// SVD Line: 5664
// SFDITEM_REG__SPI1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40013000) control register 1
// ( (unsigned int)((SPI1_CR1 >> 0) & 0xFFFFFFFF), ((SPI1_CR1 = (SPI1_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// - SFDITEM_FIELD__SPI1_CR1_BR
// - SFDITEM_FIELD__SPI1_CR1_SPE
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// - SFDITEM_FIELD__SPI1_CR1_SSI
// - SFDITEM_FIELD__SPI1_CR1_SSM
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// - SFDITEM_FIELD__SPI1_CR1_DFF
// - SFDITEM_FIELD__SPI1_CR1_CRCNEXT
// - SFDITEM_FIELD__SPI1_CR1_CRCEN
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
//
//
// ----------------------------- Register Item Address: SPI1_CR2 --------------------------------
// SVD Line: 5742
unsigned int SPI1_CR2 __AT (0x40013004);
// ------------------------------ Field Item: SPI1_CR2_RXDMAEN ----------------------------------
// SVD Line: 5748
// - SFDITEM_FIELD__SPI1_CR2_RXDMAEN
// RXDMAEN
//
// [Bit 0] RW (@ 0x40013004) Rx buffer DMA enable
//
// ( (unsigned int) SPI1_CR2 )
// RXDMAEN
//
//
//
// ------------------------------ Field Item: SPI1_CR2_TXDMAEN ----------------------------------
// SVD Line: 5753
// - SFDITEM_FIELD__SPI1_CR2_TXDMAEN
// TXDMAEN
//
// [Bit 1] RW (@ 0x40013004) Tx buffer DMA enable
//
// ( (unsigned int) SPI1_CR2 )
// TXDMAEN
//
//
//
// -------------------------------- Field Item: SPI1_CR2_SSOE -----------------------------------
// SVD Line: 5758
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// SSOE
//
// [Bit 2] RW (@ 0x40013004) SS output enable
//
// ( (unsigned int) SPI1_CR2 )
// SSOE
//
//
//
// ----------------------------- Field Item: SPI1_CR2_CLRTXFIFO ---------------------------------
// SVD Line: 5763
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// CLRTXFIFO
//
// [Bit 4] RW (@ 0x40013004) Clear TXFIFO
//
// ( (unsigned int) SPI1_CR2 )
// CLRTXFIFO
//
//
//
// ------------------------------- Field Item: SPI1_CR2_ERRIE -----------------------------------
// SVD Line: 5768
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// ERRIE
//
// [Bit 5] RW (@ 0x40013004) Error interrupt enable
//
// ( (unsigned int) SPI1_CR2 )
// ERRIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_RXNEIE ----------------------------------
// SVD Line: 5773
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// RXNEIE
//
// [Bit 6] RW (@ 0x40013004) RX buffer not empty interrupt enable
//
// ( (unsigned int) SPI1_CR2 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_TXEIE -----------------------------------
// SVD Line: 5778
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40013004) Tx buffer empty interrupt enable
//
// ( (unsigned int) SPI1_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: SPI1_CR2 ------------------------------------
// SVD Line: 5742
// SFDITEM_REG__SPI1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013004) control register 2
// ( (unsigned int)((SPI1_CR2 >> 0) & 0xFFFFFFFF), ((SPI1_CR2 = (SPI1_CR2 & ~(0xF7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF7) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR2_RXDMAEN
// - SFDITEM_FIELD__SPI1_CR2_TXDMAEN
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
//
//
// ----------------------------- Register Item Address: SPI1_SR ---------------------------------
// SVD Line: 5785
unsigned int SPI1_SR __AT (0x40013008);
// -------------------------------- Field Item: SPI1_SR_RXNE ------------------------------------
// SVD Line: 5792
// - SFDITEM_FIELD__SPI1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40013008) Receive buffer not empty
//
// ( (unsigned int) SPI1_SR )
// RXNE
//
//
//
// --------------------------------- Field Item: SPI1_SR_TXE ------------------------------------
// SVD Line: 5798
// - SFDITEM_FIELD__SPI1_SR_TXE
// TXE
//
// [Bit 1] RO (@ 0x40013008) Transmit buffer empty
//
// ( (unsigned int) SPI1_SR )
// TXE
//
//
//
// ------------------------------- Field Item: SPI1_SR_CHSIDE -----------------------------------
// SVD Line: 5804
// - SFDITEM_FIELD__SPI1_SR_CHSIDE
// CHSIDE
//
// [Bit 2] RO (@ 0x40013008) Channel control
//
// ( (unsigned int) SPI1_SR )
// CHSIDE
//
//
//
// --------------------------------- Field Item: SPI1_SR_UDR ------------------------------------
// SVD Line: 5810
// - SFDITEM_FIELD__SPI1_SR_UDR
// UDR
//
// [Bit 3] RO (@ 0x40013008) Underflow flag
//
// ( (unsigned int) SPI1_SR )
// UDR
//
//
//
// ------------------------------- Field Item: SPI1_SR_CRCERR -----------------------------------
// SVD Line: 5816
// - SFDITEM_FIELD__SPI1_SR_CRCERR
// CRCERR
//
// [Bit 4] RO (@ 0x40013008) CRC error flag
//
// ( (unsigned int) SPI1_SR )
// CRCERR
//
//
//
// -------------------------------- Field Item: SPI1_SR_MODF ------------------------------------
// SVD Line: 5822
// - SFDITEM_FIELD__SPI1_SR_MODF
// MODF
//
// [Bit 5] RO (@ 0x40013008) Mode fault
//
// ( (unsigned int) SPI1_SR )
// MODF
//
//
//
// --------------------------------- Field Item: SPI1_SR_OVR ------------------------------------
// SVD Line: 5828
// - SFDITEM_FIELD__SPI1_SR_OVR
// OVR
//
// [Bit 6] RO (@ 0x40013008) Overrun flag
//
// ( (unsigned int) SPI1_SR )
// OVR
//
//
//
// --------------------------------- Field Item: SPI1_SR_BSY ------------------------------------
// SVD Line: 5834
// - SFDITEM_FIELD__SPI1_SR_BSY
// BSY
//
// [Bit 7] RO (@ 0x40013008) Busy flag
//
// ( (unsigned int) SPI1_SR )
// BSY
//
//
//
// -------------------------------- Field Item: SPI1_SR_FRLVL -----------------------------------
// SVD Line: 5840
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// FRLVL
//
// [Bits 10..9] RO (@ 0x40013008) FIFO reception level
//
// ( (unsigned char)((SPI1_SR >> 9) & 0x3) )
//
//
//
// -------------------------------- Field Item: SPI1_SR_FTLVL -----------------------------------
// SVD Line: 5846
// - SFDITEM_FIELD__SPI1_SR_FTLVL
// FTLVL
//
// [Bits 12..11] RO (@ 0x40013008) FIFO transmission level
//
// ( (unsigned char)((SPI1_SR >> 11) & 0x3) )
//
//
//
// --------------------------------- Register RTree: SPI1_SR ------------------------------------
// SVD Line: 5785
// SFDITEM_REG__SPI1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013008) status register
// ( (unsigned int)((SPI1_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__SPI1_SR_RXNE
// - SFDITEM_FIELD__SPI1_SR_TXE
// - SFDITEM_FIELD__SPI1_SR_CHSIDE
// - SFDITEM_FIELD__SPI1_SR_UDR
// - SFDITEM_FIELD__SPI1_SR_CRCERR
// - SFDITEM_FIELD__SPI1_SR_MODF
// - SFDITEM_FIELD__SPI1_SR_OVR
// - SFDITEM_FIELD__SPI1_SR_BSY
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// - SFDITEM_FIELD__SPI1_SR_FTLVL
//
//
// ----------------------------- Register Item Address: SPI1_DR ---------------------------------
// SVD Line: 5854
unsigned int SPI1_DR __AT (0x4001300C);
// --------------------------------- Field Item: SPI1_DR_DR -------------------------------------
// SVD Line: 5860
// - SFDITEM_FIELD__SPI1_DR_DR
// DR
//
// [Bits 15..0] RW (@ 0x4001300C) Data register
//
// ( (unsigned short)((SPI1_DR >> 0) & 0xFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: SPI1_DR ------------------------------------
// SVD Line: 5854
// SFDITEM_REG__SPI1_DR
// DR
//
// [Bits 31..0] RW (@ 0x4001300C) data register
// ( (unsigned int)((SPI1_DR >> 0) & 0xFFFFFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_DR_DR
//
//
// ---------------------------- Register Item Address: SPI1_CRCPR -------------------------------
// SVD Line: 5867
unsigned int SPI1_CRCPR __AT (0x40013010);
// ----------------------------- Field Item: SPI1_CRCPR_CRCPOLY ---------------------------------
// SVD Line: 5873
// - SFDITEM_FIELD__SPI1_CRCPR_CRCPOLY
// CRCPOLY
//
// [Bits 15..0] RW (@ 0x40013010) CRC polynomial register
//
// ( (unsigned short)((SPI1_CRCPR >> 0) & 0xFFFF), ((SPI1_CRCPR = (SPI1_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI1_CRCPR -----------------------------------
// SVD Line: 5867
// SFDITEM_REG__SPI1_CRCPR
// CRCPR
//
// [Bits 31..0] RW (@ 0x40013010) CRC polynomial register
// ( (unsigned int)((SPI1_CRCPR >> 0) & 0xFFFFFFFF), ((SPI1_CRCPR = (SPI1_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CRCPR_CRCPOLY
//
//
// ---------------------------- Register Item Address: SPI1_RXCRC -------------------------------
// SVD Line: 5880
unsigned int SPI1_RXCRC __AT (0x40013014);
// ------------------------------ Field Item: SPI1_RXCRC_RXCRC ----------------------------------
// SVD Line: 5886
// - SFDITEM_FIELD__SPI1_RXCRC_RXCRC
// RXCRC
//
// [Bits 15..0] RW (@ 0x40013014) RX CRC register
//
// ( (unsigned short)((SPI1_RXCRC >> 0) & 0xFFFF), ((SPI1_RXCRC = (SPI1_RXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI1_RXCRC -----------------------------------
// SVD Line: 5880
// SFDITEM_REG__SPI1_RXCRC
// RXCRC
//
// [Bits 31..0] RW (@ 0x40013014) RX CRC register
// ( (unsigned int)((SPI1_RXCRC >> 0) & 0xFFFFFFFF), ((SPI1_RXCRC = (SPI1_RXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_RXCRC_RXCRC
//
//
// ---------------------------- Register Item Address: SPI1_TXCRC -------------------------------
// SVD Line: 5893
unsigned int SPI1_TXCRC __AT (0x40013018);
// ------------------------------ Field Item: SPI1_TXCRC_TXCRC ----------------------------------
// SVD Line: 5899
// - SFDITEM_FIELD__SPI1_TXCRC_TXCRC
// TXCRC
//
// [Bits 15..0] RW (@ 0x40013018) TX CRC register
//
// ( (unsigned short)((SPI1_TXCRC >> 0) & 0xFFFF), ((SPI1_TXCRC = (SPI1_TXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI1_TXCRC -----------------------------------
// SVD Line: 5893
// SFDITEM_REG__SPI1_TXCRC
// TXCRC
//
// [Bits 31..0] RW (@ 0x40013018) TX CRC register
// ( (unsigned int)((SPI1_TXCRC >> 0) & 0xFFFFFFFF), ((SPI1_TXCRC = (SPI1_TXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_TXCRC_TXCRC
//
//
// --------------------------- Register Item Address: SPI1_I2SCFGR ------------------------------
// SVD Line: 5906
unsigned int SPI1_I2SCFGR __AT (0x4001301C);
// ----------------------------- Field Item: SPI1_I2SCFGR_CHLEN ---------------------------------
// SVD Line: 5912
// - SFDITEM_FIELD__SPI1_I2SCFGR_CHLEN
// CHLEN
//
// [Bit 0] RW (@ 0x4001301C) Channel length
//
// ( (unsigned int) SPI1_I2SCFGR )
// CHLEN
//
//
//
// ----------------------------- Field Item: SPI1_I2SCFGR_DATLEN --------------------------------
// SVD Line: 5917
// - SFDITEM_FIELD__SPI1_I2SCFGR_DATLEN
// DATLEN
//
// [Bits 2..1] RW (@ 0x4001301C) Data length to be transferred
//
// ( (unsigned char)((SPI1_I2SCFGR >> 1) & 0x3), ((SPI1_I2SCFGR = (SPI1_I2SCFGR & ~(0x3UL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 1 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI1_I2SCFGR_CKPOL ---------------------------------
// SVD Line: 5922
// - SFDITEM_FIELD__SPI1_I2SCFGR_CKPOL
// CKPOL
//
// [Bit 3] RW (@ 0x4001301C) Steady state clock polarity
//
// ( (unsigned int) SPI1_I2SCFGR )
// CKPOL
//
//
//
// ----------------------------- Field Item: SPI1_I2SCFGR_I2SSTD --------------------------------
// SVD Line: 5927
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SSTD
// I2SSTD
//
// [Bits 5..4] RW (@ 0x4001301C) I2S standard selection
//
// ( (unsigned char)((SPI1_I2SCFGR >> 4) & 0x3), ((SPI1_I2SCFGR = (SPI1_I2SCFGR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: SPI1_I2SCFGR_PCMSYNC --------------------------------
// SVD Line: 5932
// - SFDITEM_FIELD__SPI1_I2SCFGR_PCMSYNC
// PCMSYNC
//
// [Bit 7] RW (@ 0x4001301C) PCM frame synchronization
//
// ( (unsigned int) SPI1_I2SCFGR )
// PCMSYNC
//
//
//
// ----------------------------- Field Item: SPI1_I2SCFGR_I2SCFG --------------------------------
// SVD Line: 5937
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SCFG
// I2SCFG
//
// [Bits 9..8] RW (@ 0x4001301C) I2S configuration mode
//
// ( (unsigned char)((SPI1_I2SCFGR >> 8) & 0x3), ((SPI1_I2SCFGR = (SPI1_I2SCFGR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: SPI1_I2SCFGR_I2SE ---------------------------------
// SVD Line: 5942
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SE
// I2SE
//
// [Bit 10] RW (@ 0x4001301C) I2S enable
//
// ( (unsigned int) SPI1_I2SCFGR )
// I2SE
//
//
//
// ----------------------------- Field Item: SPI1_I2SCFGR_I2SMOD --------------------------------
// SVD Line: 5947
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SMOD
// I2SMOD
//
// [Bit 11] RW (@ 0x4001301C) I2S mode selection
//
// ( (unsigned int) SPI1_I2SCFGR )
// I2SMOD
//
//
//
// ------------------------------ Register RTree: SPI1_I2SCFGR ----------------------------------
// SVD Line: 5906
// SFDITEM_REG__SPI1_I2SCFGR
// I2SCFGR
//
// [Bits 31..0] RW (@ 0x4001301C) I2S Configuration register
// ( (unsigned int)((SPI1_I2SCFGR >> 0) & 0xFFFFFFFF), ((SPI1_I2SCFGR = (SPI1_I2SCFGR & ~(0xFBFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFBF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_I2SCFGR_CHLEN
// - SFDITEM_FIELD__SPI1_I2SCFGR_DATLEN
// - SFDITEM_FIELD__SPI1_I2SCFGR_CKPOL
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SSTD
// - SFDITEM_FIELD__SPI1_I2SCFGR_PCMSYNC
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SCFG
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SE
// - SFDITEM_FIELD__SPI1_I2SCFGR_I2SMOD
//
//
// ---------------------------- Register Item Address: SPI1_I2SPR -------------------------------
// SVD Line: 5954
unsigned int SPI1_I2SPR __AT (0x40013020);
// ------------------------------ Field Item: SPI1_I2SPR_I2SDIV ---------------------------------
// SVD Line: 5960
// - SFDITEM_FIELD__SPI1_I2SPR_I2SDIV
// I2SDIV
//
// [Bits 7..0] RW (@ 0x40013020) I2S linear prescaler
//
// ( (unsigned char)((SPI1_I2SPR >> 0) & 0xFF), ((SPI1_I2SPR = (SPI1_I2SPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: SPI1_I2SPR_ODD -----------------------------------
// SVD Line: 5965
// - SFDITEM_FIELD__SPI1_I2SPR_ODD
// ODD
//
// [Bit 8] RW (@ 0x40013020) Odd factor for the prescaler
//
// ( (unsigned int) SPI1_I2SPR )
// ODD
//
//
//
// ------------------------------ Field Item: SPI1_I2SPR_MCKOE ----------------------------------
// SVD Line: 5970
// - SFDITEM_FIELD__SPI1_I2SPR_MCKOE
// MCKOE
//
// [Bit 9] RW (@ 0x40013020) Master clock output enable
//
// ( (unsigned int) SPI1_I2SPR )
// MCKOE
//
//
//
// ------------------------------- Register RTree: SPI1_I2SPR -----------------------------------
// SVD Line: 5954
// SFDITEM_REG__SPI1_I2SPR
// I2SPR
//
// [Bits 31..0] RW (@ 0x40013020) I2S prescaler register
// ( (unsigned int)((SPI1_I2SPR >> 0) & 0xFFFFFFFF), ((SPI1_I2SPR = (SPI1_I2SPR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_I2SPR_I2SDIV
// - SFDITEM_FIELD__SPI1_I2SPR_ODD
// - SFDITEM_FIELD__SPI1_I2SPR_MCKOE
//
//
// ---------------------------------- Peripheral View: SPI1 -------------------------------------
// SVD Line: 5648
// SPI1
// SPI1
// - SFDITEM_REG__SPI1_CR1
// - SFDITEM_REG__SPI1_CR2
// - SFDITEM_REG__SPI1_SR
// - SFDITEM_REG__SPI1_DR
// - SFDITEM_REG__SPI1_CRCPR
// - SFDITEM_REG__SPI1_RXCRC
// - SFDITEM_REG__SPI1_TXCRC
// - SFDITEM_REG__SPI1_I2SCFGR
// - SFDITEM_REG__SPI1_I2SPR
//
//
// ----------------------------- Register Item Address: SPI2_CR1 --------------------------------
// SVD Line: 5664
unsigned int SPI2_CR1 __AT (0x40003800);
// -------------------------------- Field Item: SPI2_CR1_CPHA -----------------------------------
// SVD Line: 5670
// - SFDITEM_FIELD__SPI2_CR1_CPHA
// CPHA
//
// [Bit 0] RW (@ 0x40003800) Clock phase
//
// ( (unsigned int) SPI2_CR1 )
// CPHA
//
//
//
// -------------------------------- Field Item: SPI2_CR1_CPOL -----------------------------------
// SVD Line: 5675
// - SFDITEM_FIELD__SPI2_CR1_CPOL
// CPOL
//
// [Bit 1] RW (@ 0x40003800) Clock polarity
//
// ( (unsigned int) SPI2_CR1 )
// CPOL
//
//
//
// -------------------------------- Field Item: SPI2_CR1_MSTR -----------------------------------
// SVD Line: 5680
// - SFDITEM_FIELD__SPI2_CR1_MSTR
// MSTR
//
// [Bit 2] RW (@ 0x40003800) Master selection
//
// ( (unsigned int) SPI2_CR1 )
// MSTR
//
//
//
// --------------------------------- Field Item: SPI2_CR1_BR ------------------------------------
// SVD Line: 5685
// - SFDITEM_FIELD__SPI2_CR1_BR
// BR
//
// [Bits 5..3] RW (@ 0x40003800) Baud rate control
//
// ( (unsigned char)((SPI2_CR1 >> 3) & 0x7), ((SPI2_CR1 = (SPI2_CR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SPE ------------------------------------
// SVD Line: 5690
// - SFDITEM_FIELD__SPI2_CR1_SPE
// SPE
//
// [Bit 6] RW (@ 0x40003800) SPI enable
//
// ( (unsigned int) SPI2_CR1 )
// SPE
//
//
//
// ------------------------------ Field Item: SPI2_CR1_LSBFIRST ---------------------------------
// SVD Line: 5695
// - SFDITEM_FIELD__SPI2_CR1_LSBFIRST
// LSBFIRST
//
// [Bit 7] RW (@ 0x40003800) Frame format
//
// ( (unsigned int) SPI2_CR1 )
// LSBFIRST
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SSI ------------------------------------
// SVD Line: 5700
// - SFDITEM_FIELD__SPI2_CR1_SSI
// SSI
//
// [Bit 8] RW (@ 0x40003800) Internal slave selection
//
// ( (unsigned int) SPI2_CR1 )
// SSI
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SSM ------------------------------------
// SVD Line: 5705
// - SFDITEM_FIELD__SPI2_CR1_SSM
// SSM
//
// [Bit 9] RW (@ 0x40003800) Software slave management
//
// ( (unsigned int) SPI2_CR1 )
// SSM
//
//
//
// ------------------------------- Field Item: SPI2_CR1_RXONLY ----------------------------------
// SVD Line: 5710
// - SFDITEM_FIELD__SPI2_CR1_RXONLY
// RXONLY
//
// [Bit 10] RW (@ 0x40003800) Receive only
//
// ( (unsigned int) SPI2_CR1 )
// RXONLY
//
//
//
// -------------------------------- Field Item: SPI2_CR1_DFF ------------------------------------
// SVD Line: 5715
// - SFDITEM_FIELD__SPI2_CR1_DFF
// DFF
//
// [Bit 11] RW (@ 0x40003800) Data frame format
//
// ( (unsigned int) SPI2_CR1 )
// DFF
//
//
//
// ------------------------------ Field Item: SPI2_CR1_CRCNEXT ----------------------------------
// SVD Line: 5720
// - SFDITEM_FIELD__SPI2_CR1_CRCNEXT
// CRCNEXT
//
// [Bit 12] RW (@ 0x40003800) Transmit CRC next
//
// ( (unsigned int) SPI2_CR1 )
// CRCNEXT
//
//
//
// ------------------------------- Field Item: SPI2_CR1_CRCEN -----------------------------------
// SVD Line: 5725
// - SFDITEM_FIELD__SPI2_CR1_CRCEN
// CRCEN
//
// [Bit 13] RW (@ 0x40003800) Hardware CRC calculation enable
//
// ( (unsigned int) SPI2_CR1 )
// CRCEN
//
//
//
// ------------------------------- Field Item: SPI2_CR1_BIDIOE ----------------------------------
// SVD Line: 5730
// - SFDITEM_FIELD__SPI2_CR1_BIDIOE
// BIDIOE
//
// [Bit 14] RW (@ 0x40003800) Output enable in bidirectional mode
//
// ( (unsigned int) SPI2_CR1 )
// BIDIOE
//
//
//
// ------------------------------ Field Item: SPI2_CR1_BIDIMODE ---------------------------------
// SVD Line: 5735
// - SFDITEM_FIELD__SPI2_CR1_BIDIMODE
// BIDIMODE
//
// [Bit 15] RW (@ 0x40003800) Bidirectional data mode enable
//
// ( (unsigned int) SPI2_CR1 )
// BIDIMODE
//
//
//
// -------------------------------- Register RTree: SPI2_CR1 ------------------------------------
// SVD Line: 5664
// SFDITEM_REG__SPI2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40003800) control register 1
// ( (unsigned int)((SPI2_CR1 >> 0) & 0xFFFFFFFF), ((SPI2_CR1 = (SPI2_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CR1_CPHA
// - SFDITEM_FIELD__SPI2_CR1_CPOL
// - SFDITEM_FIELD__SPI2_CR1_MSTR
// - SFDITEM_FIELD__SPI2_CR1_BR
// - SFDITEM_FIELD__SPI2_CR1_SPE
// - SFDITEM_FIELD__SPI2_CR1_LSBFIRST
// - SFDITEM_FIELD__SPI2_CR1_SSI
// - SFDITEM_FIELD__SPI2_CR1_SSM
// - SFDITEM_FIELD__SPI2_CR1_RXONLY
// - SFDITEM_FIELD__SPI2_CR1_DFF
// - SFDITEM_FIELD__SPI2_CR1_CRCNEXT
// - SFDITEM_FIELD__SPI2_CR1_CRCEN
// - SFDITEM_FIELD__SPI2_CR1_BIDIOE
// - SFDITEM_FIELD__SPI2_CR1_BIDIMODE
//
//
// ----------------------------- Register Item Address: SPI2_CR2 --------------------------------
// SVD Line: 5742
unsigned int SPI2_CR2 __AT (0x40003804);
// ------------------------------ Field Item: SPI2_CR2_RXDMAEN ----------------------------------
// SVD Line: 5748
// - SFDITEM_FIELD__SPI2_CR2_RXDMAEN
// RXDMAEN
//
// [Bit 0] RW (@ 0x40003804) Rx buffer DMA enable
//
// ( (unsigned int) SPI2_CR2 )
// RXDMAEN
//
//
//
// ------------------------------ Field Item: SPI2_CR2_TXDMAEN ----------------------------------
// SVD Line: 5753
// - SFDITEM_FIELD__SPI2_CR2_TXDMAEN
// TXDMAEN
//
// [Bit 1] RW (@ 0x40003804) Tx buffer DMA enable
//
// ( (unsigned int) SPI2_CR2 )
// TXDMAEN
//
//
//
// -------------------------------- Field Item: SPI2_CR2_SSOE -----------------------------------
// SVD Line: 5758
// - SFDITEM_FIELD__SPI2_CR2_SSOE
// SSOE
//
// [Bit 2] RW (@ 0x40003804) SS output enable
//
// ( (unsigned int) SPI2_CR2 )
// SSOE
//
//
//
// ----------------------------- Field Item: SPI2_CR2_CLRTXFIFO ---------------------------------
// SVD Line: 5763
// - SFDITEM_FIELD__SPI2_CR2_CLRTXFIFO
// CLRTXFIFO
//
// [Bit 4] RW (@ 0x40003804) Clear TXFIFO
//
// ( (unsigned int) SPI2_CR2 )
// CLRTXFIFO
//
//
//
// ------------------------------- Field Item: SPI2_CR2_ERRIE -----------------------------------
// SVD Line: 5768
// - SFDITEM_FIELD__SPI2_CR2_ERRIE
// ERRIE
//
// [Bit 5] RW (@ 0x40003804) Error interrupt enable
//
// ( (unsigned int) SPI2_CR2 )
// ERRIE
//
//
//
// ------------------------------- Field Item: SPI2_CR2_RXNEIE ----------------------------------
// SVD Line: 5773
// - SFDITEM_FIELD__SPI2_CR2_RXNEIE
// RXNEIE
//
// [Bit 6] RW (@ 0x40003804) RX buffer not empty interrupt enable
//
// ( (unsigned int) SPI2_CR2 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: SPI2_CR2_TXEIE -----------------------------------
// SVD Line: 5778
// - SFDITEM_FIELD__SPI2_CR2_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40003804) Tx buffer empty interrupt enable
//
// ( (unsigned int) SPI2_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: SPI2_CR2 ------------------------------------
// SVD Line: 5742
// SFDITEM_REG__SPI2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40003804) control register 2
// ( (unsigned int)((SPI2_CR2 >> 0) & 0xFFFFFFFF), ((SPI2_CR2 = (SPI2_CR2 & ~(0xF7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF7) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CR2_RXDMAEN
// - SFDITEM_FIELD__SPI2_CR2_TXDMAEN
// - SFDITEM_FIELD__SPI2_CR2_SSOE
// - SFDITEM_FIELD__SPI2_CR2_CLRTXFIFO
// - SFDITEM_FIELD__SPI2_CR2_ERRIE
// - SFDITEM_FIELD__SPI2_CR2_RXNEIE
// - SFDITEM_FIELD__SPI2_CR2_TXEIE
//
//
// ----------------------------- Register Item Address: SPI2_SR ---------------------------------
// SVD Line: 5785
unsigned int SPI2_SR __AT (0x40003808);
// -------------------------------- Field Item: SPI2_SR_RXNE ------------------------------------
// SVD Line: 5792
// - SFDITEM_FIELD__SPI2_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40003808) Receive buffer not empty
//
// ( (unsigned int) SPI2_SR )
// RXNE
//
//
//
// --------------------------------- Field Item: SPI2_SR_TXE ------------------------------------
// SVD Line: 5798
// - SFDITEM_FIELD__SPI2_SR_TXE
// TXE
//
// [Bit 1] RO (@ 0x40003808) Transmit buffer empty
//
// ( (unsigned int) SPI2_SR )
// TXE
//
//
//
// ------------------------------- Field Item: SPI2_SR_CHSIDE -----------------------------------
// SVD Line: 5804
// - SFDITEM_FIELD__SPI2_SR_CHSIDE
// CHSIDE
//
// [Bit 2] RO (@ 0x40003808) Channel control
//
// ( (unsigned int) SPI2_SR )
// CHSIDE
//
//
//
// --------------------------------- Field Item: SPI2_SR_UDR ------------------------------------
// SVD Line: 5810
// - SFDITEM_FIELD__SPI2_SR_UDR
// UDR
//
// [Bit 3] RO (@ 0x40003808) Underflow flag
//
// ( (unsigned int) SPI2_SR )
// UDR
//
//
//
// ------------------------------- Field Item: SPI2_SR_CRCERR -----------------------------------
// SVD Line: 5816
// - SFDITEM_FIELD__SPI2_SR_CRCERR
// CRCERR
//
// [Bit 4] RO (@ 0x40003808) CRC error flag
//
// ( (unsigned int) SPI2_SR )
// CRCERR
//
//
//
// -------------------------------- Field Item: SPI2_SR_MODF ------------------------------------
// SVD Line: 5822
// - SFDITEM_FIELD__SPI2_SR_MODF
// MODF
//
// [Bit 5] RO (@ 0x40003808) Mode fault
//
// ( (unsigned int) SPI2_SR )
// MODF
//
//
//
// --------------------------------- Field Item: SPI2_SR_OVR ------------------------------------
// SVD Line: 5828
// - SFDITEM_FIELD__SPI2_SR_OVR
// OVR
//
// [Bit 6] RO (@ 0x40003808) Overrun flag
//
// ( (unsigned int) SPI2_SR )
// OVR
//
//
//
// --------------------------------- Field Item: SPI2_SR_BSY ------------------------------------
// SVD Line: 5834
// - SFDITEM_FIELD__SPI2_SR_BSY
// BSY
//
// [Bit 7] RO (@ 0x40003808) Busy flag
//
// ( (unsigned int) SPI2_SR )
// BSY
//
//
//
// -------------------------------- Field Item: SPI2_SR_FRLVL -----------------------------------
// SVD Line: 5840
// - SFDITEM_FIELD__SPI2_SR_FRLVL
// FRLVL
//
// [Bits 10..9] RO (@ 0x40003808) FIFO reception level
//
// ( (unsigned char)((SPI2_SR >> 9) & 0x3) )
//
//
//
// -------------------------------- Field Item: SPI2_SR_FTLVL -----------------------------------
// SVD Line: 5846
// - SFDITEM_FIELD__SPI2_SR_FTLVL
// FTLVL
//
// [Bits 12..11] RO (@ 0x40003808) FIFO transmission level
//
// ( (unsigned char)((SPI2_SR >> 11) & 0x3) )
//
//
//
// --------------------------------- Register RTree: SPI2_SR ------------------------------------
// SVD Line: 5785
// SFDITEM_REG__SPI2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40003808) status register
// ( (unsigned int)((SPI2_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__SPI2_SR_RXNE
// - SFDITEM_FIELD__SPI2_SR_TXE
// - SFDITEM_FIELD__SPI2_SR_CHSIDE
// - SFDITEM_FIELD__SPI2_SR_UDR
// - SFDITEM_FIELD__SPI2_SR_CRCERR
// - SFDITEM_FIELD__SPI2_SR_MODF
// - SFDITEM_FIELD__SPI2_SR_OVR
// - SFDITEM_FIELD__SPI2_SR_BSY
// - SFDITEM_FIELD__SPI2_SR_FRLVL
// - SFDITEM_FIELD__SPI2_SR_FTLVL
//
//
// ----------------------------- Register Item Address: SPI2_DR ---------------------------------
// SVD Line: 5854
unsigned int SPI2_DR __AT (0x4000380C);
// --------------------------------- Field Item: SPI2_DR_DR -------------------------------------
// SVD Line: 5860
// - SFDITEM_FIELD__SPI2_DR_DR
// DR
//
// [Bits 15..0] RW (@ 0x4000380C) Data register
//
// ( (unsigned short)((SPI2_DR >> 0) & 0xFFFF), ((SPI2_DR = (SPI2_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: SPI2_DR ------------------------------------
// SVD Line: 5854
// SFDITEM_REG__SPI2_DR
// DR
//
// [Bits 31..0] RW (@ 0x4000380C) data register
// ( (unsigned int)((SPI2_DR >> 0) & 0xFFFFFFFF), ((SPI2_DR = (SPI2_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_DR_DR
//
//
// ---------------------------- Register Item Address: SPI2_CRCPR -------------------------------
// SVD Line: 5867
unsigned int SPI2_CRCPR __AT (0x40003810);
// ----------------------------- Field Item: SPI2_CRCPR_CRCPOLY ---------------------------------
// SVD Line: 5873
// - SFDITEM_FIELD__SPI2_CRCPR_CRCPOLY
// CRCPOLY
//
// [Bits 15..0] RW (@ 0x40003810) CRC polynomial register
//
// ( (unsigned short)((SPI2_CRCPR >> 0) & 0xFFFF), ((SPI2_CRCPR = (SPI2_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI2_CRCPR -----------------------------------
// SVD Line: 5867
// SFDITEM_REG__SPI2_CRCPR
// CRCPR
//
// [Bits 31..0] RW (@ 0x40003810) CRC polynomial register
// ( (unsigned int)((SPI2_CRCPR >> 0) & 0xFFFFFFFF), ((SPI2_CRCPR = (SPI2_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CRCPR_CRCPOLY
//
//
// ---------------------------- Register Item Address: SPI2_RXCRC -------------------------------
// SVD Line: 5880
unsigned int SPI2_RXCRC __AT (0x40003814);
// ------------------------------ Field Item: SPI2_RXCRC_RXCRC ----------------------------------
// SVD Line: 5886
// - SFDITEM_FIELD__SPI2_RXCRC_RXCRC
// RXCRC
//
// [Bits 15..0] RW (@ 0x40003814) RX CRC register
//
// ( (unsigned short)((SPI2_RXCRC >> 0) & 0xFFFF), ((SPI2_RXCRC = (SPI2_RXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI2_RXCRC -----------------------------------
// SVD Line: 5880
// SFDITEM_REG__SPI2_RXCRC
// RXCRC
//
// [Bits 31..0] RW (@ 0x40003814) RX CRC register
// ( (unsigned int)((SPI2_RXCRC >> 0) & 0xFFFFFFFF), ((SPI2_RXCRC = (SPI2_RXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_RXCRC_RXCRC
//
//
// ---------------------------- Register Item Address: SPI2_TXCRC -------------------------------
// SVD Line: 5893
unsigned int SPI2_TXCRC __AT (0x40003818);
// ------------------------------ Field Item: SPI2_TXCRC_TXCRC ----------------------------------
// SVD Line: 5899
// - SFDITEM_FIELD__SPI2_TXCRC_TXCRC
// TXCRC
//
// [Bits 15..0] RW (@ 0x40003818) TX CRC register
//
// ( (unsigned short)((SPI2_TXCRC >> 0) & 0xFFFF), ((SPI2_TXCRC = (SPI2_TXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI2_TXCRC -----------------------------------
// SVD Line: 5893
// SFDITEM_REG__SPI2_TXCRC
// TXCRC
//
// [Bits 31..0] RW (@ 0x40003818) TX CRC register
// ( (unsigned int)((SPI2_TXCRC >> 0) & 0xFFFFFFFF), ((SPI2_TXCRC = (SPI2_TXCRC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_TXCRC_TXCRC
//
//
// --------------------------- Register Item Address: SPI2_I2SCFGR ------------------------------
// SVD Line: 5906
unsigned int SPI2_I2SCFGR __AT (0x4000381C);
// ----------------------------- Field Item: SPI2_I2SCFGR_CHLEN ---------------------------------
// SVD Line: 5912
// - SFDITEM_FIELD__SPI2_I2SCFGR_CHLEN
// CHLEN
//
// [Bit 0] RW (@ 0x4000381C) Channel length
//
// ( (unsigned int) SPI2_I2SCFGR )
// CHLEN
//
//
//
// ----------------------------- Field Item: SPI2_I2SCFGR_DATLEN --------------------------------
// SVD Line: 5917
// - SFDITEM_FIELD__SPI2_I2SCFGR_DATLEN
// DATLEN
//
// [Bits 2..1] RW (@ 0x4000381C) Data length to be transferred
//
// ( (unsigned char)((SPI2_I2SCFGR >> 1) & 0x3), ((SPI2_I2SCFGR = (SPI2_I2SCFGR & ~(0x3UL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 1 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI2_I2SCFGR_CKPOL ---------------------------------
// SVD Line: 5922
// - SFDITEM_FIELD__SPI2_I2SCFGR_CKPOL
// CKPOL
//
// [Bit 3] RW (@ 0x4000381C) Steady state clock polarity
//
// ( (unsigned int) SPI2_I2SCFGR )
// CKPOL
//
//
//
// ----------------------------- Field Item: SPI2_I2SCFGR_I2SSTD --------------------------------
// SVD Line: 5927
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SSTD
// I2SSTD
//
// [Bits 5..4] RW (@ 0x4000381C) I2S standard selection
//
// ( (unsigned char)((SPI2_I2SCFGR >> 4) & 0x3), ((SPI2_I2SCFGR = (SPI2_I2SCFGR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: SPI2_I2SCFGR_PCMSYNC --------------------------------
// SVD Line: 5932
// - SFDITEM_FIELD__SPI2_I2SCFGR_PCMSYNC
// PCMSYNC
//
// [Bit 7] RW (@ 0x4000381C) PCM frame synchronization
//
// ( (unsigned int) SPI2_I2SCFGR )
// PCMSYNC
//
//
//
// ----------------------------- Field Item: SPI2_I2SCFGR_I2SCFG --------------------------------
// SVD Line: 5937
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SCFG
// I2SCFG
//
// [Bits 9..8] RW (@ 0x4000381C) I2S configuration mode
//
// ( (unsigned char)((SPI2_I2SCFGR >> 8) & 0x3), ((SPI2_I2SCFGR = (SPI2_I2SCFGR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: SPI2_I2SCFGR_I2SE ---------------------------------
// SVD Line: 5942
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SE
// I2SE
//
// [Bit 10] RW (@ 0x4000381C) I2S enable
//
// ( (unsigned int) SPI2_I2SCFGR )
// I2SE
//
//
//
// ----------------------------- Field Item: SPI2_I2SCFGR_I2SMOD --------------------------------
// SVD Line: 5947
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SMOD
// I2SMOD
//
// [Bit 11] RW (@ 0x4000381C) I2S mode selection
//
// ( (unsigned int) SPI2_I2SCFGR )
// I2SMOD
//
//
//
// ------------------------------ Register RTree: SPI2_I2SCFGR ----------------------------------
// SVD Line: 5906
// SFDITEM_REG__SPI2_I2SCFGR
// I2SCFGR
//
// [Bits 31..0] RW (@ 0x4000381C) I2S Configuration register
// ( (unsigned int)((SPI2_I2SCFGR >> 0) & 0xFFFFFFFF), ((SPI2_I2SCFGR = (SPI2_I2SCFGR & ~(0xFBFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFBF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_I2SCFGR_CHLEN
// - SFDITEM_FIELD__SPI2_I2SCFGR_DATLEN
// - SFDITEM_FIELD__SPI2_I2SCFGR_CKPOL
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SSTD
// - SFDITEM_FIELD__SPI2_I2SCFGR_PCMSYNC
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SCFG
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SE
// - SFDITEM_FIELD__SPI2_I2SCFGR_I2SMOD
//
//
// ---------------------------- Register Item Address: SPI2_I2SPR -------------------------------
// SVD Line: 5954
unsigned int SPI2_I2SPR __AT (0x40003820);
// ------------------------------ Field Item: SPI2_I2SPR_I2SDIV ---------------------------------
// SVD Line: 5960
// - SFDITEM_FIELD__SPI2_I2SPR_I2SDIV
// I2SDIV
//
// [Bits 7..0] RW (@ 0x40003820) I2S linear prescaler
//
// ( (unsigned char)((SPI2_I2SPR >> 0) & 0xFF), ((SPI2_I2SPR = (SPI2_I2SPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: SPI2_I2SPR_ODD -----------------------------------
// SVD Line: 5965
// - SFDITEM_FIELD__SPI2_I2SPR_ODD
// ODD
//
// [Bit 8] RW (@ 0x40003820) Odd factor for the prescaler
//
// ( (unsigned int) SPI2_I2SPR )
// ODD
//
//
//
// ------------------------------ Field Item: SPI2_I2SPR_MCKOE ----------------------------------
// SVD Line: 5970
// - SFDITEM_FIELD__SPI2_I2SPR_MCKOE
// MCKOE
//
// [Bit 9] RW (@ 0x40003820) Master clock output enable
//
// ( (unsigned int) SPI2_I2SPR )
// MCKOE
//
//
//
// ------------------------------- Register RTree: SPI2_I2SPR -----------------------------------
// SVD Line: 5954
// SFDITEM_REG__SPI2_I2SPR
// I2SPR
//
// [Bits 31..0] RW (@ 0x40003820) I2S prescaler register
// ( (unsigned int)((SPI2_I2SPR >> 0) & 0xFFFFFFFF), ((SPI2_I2SPR = (SPI2_I2SPR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_I2SPR_I2SDIV
// - SFDITEM_FIELD__SPI2_I2SPR_ODD
// - SFDITEM_FIELD__SPI2_I2SPR_MCKOE
//
//
// ---------------------------------- Peripheral View: SPI2 -------------------------------------
// SVD Line: 5979
// SPI2
// SPI2
// - SFDITEM_REG__SPI2_CR1
// - SFDITEM_REG__SPI2_CR2
// - SFDITEM_REG__SPI2_SR
// - SFDITEM_REG__SPI2_DR
// - SFDITEM_REG__SPI2_CRCPR
// - SFDITEM_REG__SPI2_RXCRC
// - SFDITEM_REG__SPI2_TXCRC
// - SFDITEM_REG__SPI2_I2SCFGR
// - SFDITEM_REG__SPI2_I2SPR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR1 ------------------------------
// SVD Line: 5999
unsigned int SYSCFG_CFGR1 __AT (0x40010000);
// ---------------------------- Field Item: SYSCFG_CFGR1_MEM_MODE -------------------------------
// SVD Line: 6005
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// MEM_MODE
//
// [Bits 1..0] RW (@ 0x40010000) Memory mapping selection bits
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 0) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_TIM1_IC1_SRC -----------------------------
// SVD Line: 6010
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM1_IC1_SRC
// TIM1_IC1_SRC
//
// [Bits 3..2] RW (@ 0x40010000) TIM1_IC1_SRC
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 2) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_TIM2_IC4_SRC -----------------------------
// SVD Line: 6014
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM2_IC4_SRC
// TIM2_IC4_SRC
//
// [Bits 5..4] RW (@ 0x40010000) TIM2_IC4_SRC
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 4) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_ETR_SRC_TIM1 -----------------------------
// SVD Line: 6018
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM1
// ETR_SRC_TIM1
//
// [Bits 9..8] RW (@ 0x40010000) ETR_SRC_TIM1
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 8) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_ETR_SRC_TIM2 -----------------------------
// SVD Line: 6022
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM2
// ETR_SRC_TIM2
//
// [Bits 13..12] RW (@ 0x40010000) ETR_SRC_TIM2
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 12) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_GPIO_AHB_SEL -----------------------------
// SVD Line: 6026
// - SFDITEM_FIELD__SYSCFG_CFGR1_GPIO_AHB_SEL
// GPIO_AHB_SEL
//
// [Bit 24] RW (@ 0x40010000) GPIO_AHB_SEL
//
// ( (unsigned int) SYSCFG_CFGR1 )
// GPIO_AHB_SEL
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR1 ----------------------------------
// SVD Line: 5999
// SFDITEM_REG__SYSCFG_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x40010000) SYSCFG configuration register1
// ( (unsigned int)((SYSCFG_CFGR1 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x100333FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100333F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM1_IC1_SRC
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM2_IC4_SRC
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM2
// - SFDITEM_FIELD__SYSCFG_CFGR1_GPIO_AHB_SEL
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 6032
unsigned int SYSCFG_CFGR2 __AT (0x40010004);
// -------------------------- Field Item: SYSCFG_CFGR2_LOCKUP_LOCK ------------------------------
// SVD Line: 6038
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// LOCKUP_LOCK
//
// [Bit 0] RW (@ 0x40010004) Cortex-M0+ LOCKUP bit enable bit
//
// ( (unsigned int) SYSCFG_CFGR2 )
// LOCKUP_LOCK
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR2_PVD_LOCK -------------------------------
// SVD Line: 6043
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVD_LOCK
// PVD_LOCK
//
// [Bit 2] RW (@ 0x40010004) PVD lock enable bit
//
// ( (unsigned int) SYSCFG_CFGR2 )
// PVD_LOCK
//
//
//
// ------------------------- Field Item: SYSCFG_CFGR2_COMP1_BRK_TIM1 ----------------------------
// SVD Line: 6048
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM1
// COMP1_BRK_TIM1
//
// [Bit 3] RW (@ 0x40010004) COMP1 is enable to input of TIM1 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_BRK_TIM1
//
//
//
// ------------------------- Field Item: SYSCFG_CFGR2_COMP2_BRK_TIM1 ----------------------------
// SVD Line: 6053
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM1
// COMP2_BRK_TIM1
//
// [Bit 4] RW (@ 0x40010004) COMP2 is enable to input of TIM1 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_BRK_TIM1
//
//
//
// ------------------------ Field Item: SYSCFG_CFGR2_COMP1_BRK_TIM16 ----------------------------
// SVD Line: 6058
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM16
// COMP1_BRK_TIM16
//
// [Bit 5] RW (@ 0x40010004) COMP1 is enable to input of TIM16 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_BRK_TIM16
//
//
//
// ------------------------ Field Item: SYSCFG_CFGR2_COMP2_BRK_TIM16 ----------------------------
// SVD Line: 6063
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM16
// COMP2_BRK_TIM16
//
// [Bit 6] RW (@ 0x40010004) COMP2 is enable to input of TIM16 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_BRK_TIM16
//
//
//
// ------------------------ Field Item: SYSCFG_CFGR2_COMP1_BRK_TIM17 ----------------------------
// SVD Line: 6068
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM17
// COMP1_BRK_TIM17
//
// [Bit 7] RW (@ 0x40010004) COMP1 is enable to input of TIM17 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_BRK_TIM17
//
//
//
// ------------------------ Field Item: SYSCFG_CFGR2_COMP2_BRK_TIM17 ----------------------------
// SVD Line: 6073
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM17
// COMP2_BRK_TIM17
//
// [Bit 8] RW (@ 0x40010004) COMP2 is enable to input of TIM17 break
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_BRK_TIM17
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM1 -------------------------
// SVD Line: 6078
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM1
// COMP1_Ocref_CLR_TIM1
//
// [Bit 9] RW (@ 0x40010004) COMP1_Ocref_CLR_TIM1
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_Ocref_CLR_TIM1
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM2 -------------------------
// SVD Line: 6082
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM2
// COMP1_Ocref_CLR_TIM2
//
// [Bit 10] RW (@ 0x40010004) COMP1_Ocref_CLR_TIM2
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_Ocref_CLR_TIM2
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM1 -------------------------
// SVD Line: 6086
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM1
// COMP2_Ocref_CLR_TIM1
//
// [Bit 11] RW (@ 0x40010004) COMP2_Ocref_CLR_TIM1
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_Ocref_CLR_TIM1
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM2 -------------------------
// SVD Line: 6090
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM2
// COMP2_Ocref_CLR_TIM2
//
// [Bit 12] RW (@ 0x40010004) COMP2_Ocref_CLR_TIM2
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_Ocref_CLR_TIM2
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 6032
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010004) SYSCFG configuration register2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x1FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFD) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVD_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM16
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM16
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM17
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM17
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_Ocref_CLR_TIM2
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_Ocref_CLR_TIM2
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR3 ------------------------------
// SVD Line: 6096
unsigned int SYSCFG_CFGR3 __AT (0x40010008);
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA1_MAP -------------------------------
// SVD Line: 6102
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA1_MAP
// DMA1_MAP
//
// [Bits 5..0] RW (@ 0x40010008) DMA channel1 requeset selection
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 0) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA2_MAP -------------------------------
// SVD Line: 6107
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA2_MAP
// DMA2_MAP
//
// [Bits 13..8] RW (@ 0x40010008) DMA channel2 requeset selection
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 8) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA3_MAP -------------------------------
// SVD Line: 6112
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA3_MAP
// DMA3_MAP
//
// [Bits 21..16] RW (@ 0x40010008) DMA channel3 requeset selection
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 16) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR3 ----------------------------------
// SVD Line: 6096
// SFDITEM_REG__SYSCFG_CFGR3
// CFGR3
//
// [Bits 31..0] RW (@ 0x40010008) SYSCFG configuration register3
// ( (unsigned int)((SYSCFG_CFGR3 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA1_MAP
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA2_MAP
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA3_MAP
//
//
// -------------------------- Register Item Address: SYSCFG_PA_ENS ------------------------------
// SVD Line: 6119
unsigned int SYSCFG_PA_ENS __AT (0x40010010);
// ---------------------------- Field Item: SYSCFG_PA_ENS_PA_ENS --------------------------------
// SVD Line: 6125
// - SFDITEM_FIELD__SYSCFG_PA_ENS_PA_ENS
// PA_ENS
//
// [Bits 15..0] RW (@ 0x40010010) Noise filter enable, active high
//
// ( (unsigned short)((SYSCFG_PA_ENS >> 0) & 0xFFFF), ((SYSCFG_PA_ENS = (SYSCFG_PA_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PA_ENS ---------------------------------
// SVD Line: 6119
// SFDITEM_REG__SYSCFG_PA_ENS
// PA_ENS
//
// [Bits 31..0] RW (@ 0x40010010) GPIOA noise filter enable register
// ( (unsigned int)((SYSCFG_PA_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ENS = (SYSCFG_PA_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ENS_PA_ENS
//
//
// -------------------------- Register Item Address: SYSCFG_PB_ENS ------------------------------
// SVD Line: 6132
unsigned int SYSCFG_PB_ENS __AT (0x40010014);
// ---------------------------- Field Item: SYSCFG_PB_ENS_PB_ENS --------------------------------
// SVD Line: 6138
// - SFDITEM_FIELD__SYSCFG_PB_ENS_PB_ENS
// PB_ENS
//
// [Bits 15..0] RW (@ 0x40010014) Noise filter enable, active high
//
// ( (unsigned short)((SYSCFG_PB_ENS >> 0) & 0xFFFF), ((SYSCFG_PB_ENS = (SYSCFG_PB_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PB_ENS ---------------------------------
// SVD Line: 6132
// SFDITEM_REG__SYSCFG_PB_ENS
// PB_ENS
//
// [Bits 31..0] RW (@ 0x40010014) GPIOB noise filter enable register
// ( (unsigned int)((SYSCFG_PB_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_ENS = (SYSCFG_PB_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_ENS_PB_ENS
//
//
// -------------------------- Register Item Address: SYSCFG_PF_ENS ------------------------------
// SVD Line: 6145
unsigned int SYSCFG_PF_ENS __AT (0x40010018);
// ---------------------------- Field Item: SYSCFG_PF_ENS_PF_ENS --------------------------------
// SVD Line: 6151
// - SFDITEM_FIELD__SYSCFG_PF_ENS_PF_ENS
// PF_ENS
//
// [Bits 15..0] RW (@ 0x40010018) Noise filter enable, active high
//
// ( (unsigned short)((SYSCFG_PF_ENS >> 0) & 0xFFFF), ((SYSCFG_PF_ENS = (SYSCFG_PF_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PF_ENS ---------------------------------
// SVD Line: 6145
// SFDITEM_REG__SYSCFG_PF_ENS
// PF_ENS
//
// [Bits 31..0] RW (@ 0x40010018) GPIOF noise filter enable register
// ( (unsigned int)((SYSCFG_PF_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_ENS = (SYSCFG_PF_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_ENS_PF_ENS
//
//
// -------------------------- Register Item Address: SYSCFG_IO_CFG ------------------------------
// SVD Line: 6158
unsigned int SYSCFG_IO_CFG __AT (0x4001001C);
// ---------------------------- Field Item: SYSCFG_IO_CFG_PA_EI2C -------------------------------
// SVD Line: 6164
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PA_EI2C
// PA_EI2C
//
// [Bits 7..0] RW (@ 0x4001001C) desc PA_EI2C
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 0) & 0xFF), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IO_CFG_PB_EI2C -------------------------------
// SVD Line: 6169
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PB_EI2C
// PB_EI2C
//
// [Bits 12..8] RW (@ 0x4001001C) desc PB_EI2C
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 8) & 0x1F), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IO_CFG_PA_EHS --------------------------------
// SVD Line: 6174
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PA_EHS
// PA_EHS
//
// [Bits 14..13] RW (@ 0x4001001C) desc PA_EHS
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 13) & 0x3), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IO_CFG_PB_EHS --------------------------------
// SVD Line: 6179
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PB_EHS
// PB_EHS
//
// [Bits 21..16] RW (@ 0x4001001C) desc PB_EHS
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 16) & 0x3F), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IO_CFG_PF_EI2C -------------------------------
// SVD Line: 6184
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PF_EI2C
// PF_EI2C
//
// [Bits 27..24] RW (@ 0x4001001C) desc PF_EI2C
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 24) & 0xF), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_IO_CFG_PF_PU_I2C ------------------------------
// SVD Line: 6189
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PF_PU_I2C
// PF_PU_I2C
//
// [Bits 29..28] RW (@ 0x4001001C) desc PF_PU_I2C
//
// ( (unsigned char)((SYSCFG_IO_CFG >> 28) & 0x3), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_IO_CFG ---------------------------------
// SVD Line: 6158
// SFDITEM_REG__SYSCFG_IO_CFG
// IO_CFG
//
// [Bits 31..0] RW (@ 0x4001001C) I2C type IO configure register
// ( (unsigned int)((SYSCFG_IO_CFG >> 0) & 0xFFFFFFFF), ((SYSCFG_IO_CFG = (SYSCFG_IO_CFG & ~(0x3F3F7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PA_EI2C
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PB_EI2C
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PA_EHS
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PB_EHS
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PF_EI2C
// - SFDITEM_FIELD__SYSCFG_IO_CFG_PF_PU_I2C
//
//
// ------------------------- Register Item Address: SYSCFG_PA_ANA2EN ----------------------------
// SVD Line: 6196
unsigned int SYSCFG_PA_ANA2EN __AT (0x40010020);
// ------------------------- Field Item: SYSCFG_PA_ANA2EN_PA_ANA2EN -----------------------------
// SVD Line: 6202
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA_ANA2EN
// PA_ANA2EN
//
// [Bits 15..0] RW (@ 0x40010020) IO PORTA PAD_ANA2 enable
//
// ( (unsigned short)((SYSCFG_PA_ANA2EN >> 0) & 0xFFFF), ((SYSCFG_PA_ANA2EN = (SYSCFG_PA_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PA_ANA2EN --------------------------------
// SVD Line: 6196
// SFDITEM_REG__SYSCFG_PA_ANA2EN
// PA_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010020) GPIOA Analog2 enable register
// ( (unsigned int)((SYSCFG_PA_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ANA2EN = (SYSCFG_PA_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA_ANA2EN
//
//
// ------------------------- Register Item Address: SYSCFG_PB_ANA2EN ----------------------------
// SVD Line: 6209
unsigned int SYSCFG_PB_ANA2EN __AT (0x40010024);
// ------------------------- Field Item: SYSCFG_PB_ANA2EN_PB_ANA2EN -----------------------------
// SVD Line: 6215
// - SFDITEM_FIELD__SYSCFG_PB_ANA2EN_PB_ANA2EN
// PB_ANA2EN
//
// [Bits 15..0] RW (@ 0x40010024) IO PORTB PAD_ANA2 enable
//
// ( (unsigned short)((SYSCFG_PB_ANA2EN >> 0) & 0xFFFF), ((SYSCFG_PB_ANA2EN = (SYSCFG_PB_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PB_ANA2EN --------------------------------
// SVD Line: 6209
// SFDITEM_REG__SYSCFG_PB_ANA2EN
// PB_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010024) GPIOB Analog2 enable register
// ( (unsigned int)((SYSCFG_PB_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_ANA2EN = (SYSCFG_PB_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_ANA2EN_PB_ANA2EN
//
//
// ------------------------- Register Item Address: SYSCFG_PF_ANA2EN ----------------------------
// SVD Line: 6222
unsigned int SYSCFG_PF_ANA2EN __AT (0x40010028);
// ------------------------- Field Item: SYSCFG_PF_ANA2EN_PF_ANA2EN -----------------------------
// SVD Line: 6228
// - SFDITEM_FIELD__SYSCFG_PF_ANA2EN_PF_ANA2EN
// PF_ANA2EN
//
// [Bits 15..0] RW (@ 0x40010028) IO PORTF PAD_ANA2 enable
//
// ( (unsigned short)((SYSCFG_PF_ANA2EN >> 0) & 0xFFFF), ((SYSCFG_PF_ANA2EN = (SYSCFG_PF_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PF_ANA2EN --------------------------------
// SVD Line: 6222
// SFDITEM_REG__SYSCFG_PF_ANA2EN
// PF_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010028) GPIOF Analog2 enable register
// ( (unsigned int)((SYSCFG_PF_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_ANA2EN = (SYSCFG_PF_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_ANA2EN_PF_ANA2EN
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 5988
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR1
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_CFGR3
// - SFDITEM_REG__SYSCFG_PA_ENS
// - SFDITEM_REG__SYSCFG_PB_ENS
// - SFDITEM_REG__SYSCFG_PF_ENS
// - SFDITEM_REG__SYSCFG_IO_CFG
// - SFDITEM_REG__SYSCFG_PA_ANA2EN
// - SFDITEM_REG__SYSCFG_PB_ANA2EN
// - SFDITEM_REG__SYSCFG_PF_ANA2EN
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 6258
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 6264
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) Counter enable
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 6269
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) Update disable
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 6274
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) Update request source
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 6279
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) One-pulse mode
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 6284
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) Direction
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 6289
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) Center-aligned mode selection
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 6294
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) Auto-reload preload enable
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 6299
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) Clock division
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 6258
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) control register 1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 6306
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 6312
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) Capture/compare preloaded control
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 6317
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) Capture/compare control update selection
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCDS -----------------------------------
// SVD Line: 6322
// - SFDITEM_FIELD__TIM1_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40012C04) Capture/compare DMA selection
//
// ( (unsigned int) TIM1_CR2 )
// CCDS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_MMS ------------------------------------
// SVD Line: 6327
// - SFDITEM_FIELD__TIM1_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40012C04) Master mode selection
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 6332
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) TI1 selection
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 6337
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) Output Idle state 1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 6342
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) Output Idle state 1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 6347
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) Output Idle state 2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 6352
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) Output Idle state 2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 6357
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) Output Idle state 3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 6362
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) Output Idle state 3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 6367
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) Output Idle state 4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 6306
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) control register 2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFD) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_CCDS
// - SFDITEM_FIELD__TIM1_CR2_MMS
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 6374
unsigned int TIM1_SMCR __AT (0x40012C08);
// -------------------------------- Field Item: TIM1_SMCR_SMS -----------------------------------
// SVD Line: 6380
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40012C08) Slave mode selection
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 6385
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) OCREF clear selection bit
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_TS ------------------------------------
// SVD Line: 6390
// - SFDITEM_FIELD__TIM1_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40012C08) Trigger selection
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 6395
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) Master/Slave mode
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 6400
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) External trigger filter
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 6405
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) External trigger prescaler
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 6410
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) External clock enable
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 6415
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) External trigger polarity
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_SMS_3 ----------------------------------
// SVD Line: 6420
// - SFDITEM_FIELD__TIM1_SMCR_SMS_3
// SMS_3
//
// [Bit 16] RW (@ 0x40012C08) Slave mode selection
//
// ( (unsigned int) TIM1_SMCR )
// SMS_3
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 6374
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) slave mode control register
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// - SFDITEM_FIELD__TIM1_SMCR_SMS_3
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 6427
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 6433
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) Update interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 6438
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) Capture/Compare 1 interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 6443
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) Capture/Compare 2 interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 6448
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) Capture/Compare 3 interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 6453
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) Capture/Compare 4 interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 6458
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) COM interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 6463
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) Trigger interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 6468
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) Break interrupt enable
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_UDE -----------------------------------
// SVD Line: 6473
// - SFDITEM_FIELD__TIM1_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x40012C0C) Update DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// UDE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1DE ----------------------------------
// SVD Line: 6478
// - SFDITEM_FIELD__TIM1_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x40012C0C) Capture/Compare 1 DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// CC1DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2DE ----------------------------------
// SVD Line: 6483
// - SFDITEM_FIELD__TIM1_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x40012C0C) Capture/Compare 2 DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// CC2DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3DE ----------------------------------
// SVD Line: 6488
// - SFDITEM_FIELD__TIM1_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x40012C0C) Capture/Compare 3 DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// CC3DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4DE ----------------------------------
// SVD Line: 6493
// - SFDITEM_FIELD__TIM1_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x40012C0C) Capture/Compare 4 DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// CC4DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMDE ----------------------------------
// SVD Line: 6498
// - SFDITEM_FIELD__TIM1_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x40012C0C) COM DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// COMDE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TDE -----------------------------------
// SVD Line: 6503
// - SFDITEM_FIELD__TIM1_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x40012C0C) Trigger DMA request enable
//
// ( (unsigned int) TIM1_DIER )
// TDE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 6427
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) DMA/Interrupt enable register
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
// - SFDITEM_FIELD__TIM1_DIER_UDE
// - SFDITEM_FIELD__TIM1_DIER_CC1DE
// - SFDITEM_FIELD__TIM1_DIER_CC2DE
// - SFDITEM_FIELD__TIM1_DIER_CC3DE
// - SFDITEM_FIELD__TIM1_DIER_CC4DE
// - SFDITEM_FIELD__TIM1_DIER_COMDE
// - SFDITEM_FIELD__TIM1_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 6510
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 6516
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) Update interrupt flag
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 6521
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) Capture/compare 1 interrupt flag
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 6526
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) Capture/Compare 2 interrupt flag
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 6531
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) Capture/Compare 3 interrupt flag
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 6536
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) Capture/Compare 4 interrupt flag
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 6541
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) COM interrupt flag
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 6546
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) Trigger interrupt flag
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 6551
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) Break interrupt flag
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 6556
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) Capture/Compare 1 overcapture flag
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 6561
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) Capture/compare 2 overcapture flag
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 6566
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) Capture/Compare 3 overcapture flag
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 6571
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) Capture/Compare 4 overcapture flag
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 6576
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40012C10) Capture 1 Rise edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 6581
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 17] RW (@ 0x40012C10) Capture 2 Rise edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 6586
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 18] RW (@ 0x40012C10) Capture 3 Rise edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 6591
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 19] RW (@ 0x40012C10) Capture 4 Rise edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 6596
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40012C10) Capture 1 Fall edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 6601
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 21] RW (@ 0x40012C10) Capture 2 Fall edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 6606
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 22] RW (@ 0x40012C10) Capture 3 Fall edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 6611
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 23] RW (@ 0x40012C10) Capture 4 Fall edge capture flag
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 6510
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) status register
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0xFF1EFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1EFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 6618
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 6625
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40012C14) Update generation
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 6630
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40012C14) Capture/compare 1 generation
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 6635
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] WO (@ 0x40012C14) Capture/compare 2 generation
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 6640
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] WO (@ 0x40012C14) Capture/compare 3 generation
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 6645
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] WO (@ 0x40012C14) Capture/compare 4 generation
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 6650
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40012C14) Capture/Compare control update generation
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 6655
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] WO (@ 0x40012C14) Trigger generation
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 6660
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40012C14) Break generation
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 6618
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40012C14) event generation register
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_Output ----------------------------
// SVD Line: 6667
unsigned int TIM1_CCMR1_Output __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_Output_CC1S -------------------------------
// SVD Line: 6673
// - SFDITEM_FIELD__TIM1_CCMR1_Output_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM1_CCMR1_Output >> 0) & 0x3), ((TIM1_CCMR1_Output = (TIM1_CCMR1_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC1FE ------------------------------
// SVD Line: 6678
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) Output Compare 1 fast enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC1PE ------------------------------
// SVD Line: 6683
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) Output Compare 1 preload enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC1M -------------------------------
// SVD Line: 6688
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40012C18) Output Compare 1 mode
//
// ( (unsigned char)((TIM1_CCMR1_Output >> 4) & 0x7), ((TIM1_CCMR1_Output = (TIM1_CCMR1_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC1CE ------------------------------
// SVD Line: 6693
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) Output Compare 1 clear enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_CC2S -------------------------------
// SVD Line: 6698
// - SFDITEM_FIELD__TIM1_CCMR1_Output_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) Capture/Compare 2 selection
//
// ( (unsigned char)((TIM1_CCMR1_Output >> 8) & 0x3), ((TIM1_CCMR1_Output = (TIM1_CCMR1_Output & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC2FE ------------------------------
// SVD Line: 6703
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) Output Compare 2 fast enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC2PE ------------------------------
// SVD Line: 6708
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) Output Compare 2 preload enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC2M -------------------------------
// SVD Line: 6713
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40012C18) Output Compare 2 mode
//
// ( (unsigned char)((TIM1_CCMR1_Output >> 12) & 0x7), ((TIM1_CCMR1_Output = (TIM1_CCMR1_Output & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Output_OC2CE ------------------------------
// SVD Line: 6718
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) Output Compare 2 clear enable
//
// ( (unsigned int) TIM1_CCMR1_Output )
// OC2CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_Output -------------------------------
// SVD Line: 6667
// SFDITEM_REG__TIM1_CCMR1_Output
// CCMR1_Output
//
// [Bits 31..0] RW (@ 0x40012C18) capture/compare mode register (outputmode)
// ( (unsigned int)((TIM1_CCMR1_Output >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_Output = (TIM1_CCMR1_Output & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_Output_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1M
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_Output_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2M
// - SFDITEM_FIELD__TIM1_CCMR1_Output_OC2CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_Input ----------------------------
// SVD Line: 6725
unsigned int TIM1_CCMR1_Input __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_Input_CC1S -------------------------------
// SVD Line: 6732
// - SFDITEM_FIELD__TIM1_CCMR1_Input_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 0) & 0x3), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Input_ICPSC -------------------------------
// SVD Line: 6737
// - SFDITEM_FIELD__TIM1_CCMR1_Input_ICPSC
// ICPSC
//
// [Bits 3..2] RW (@ 0x40012C18) Input capture 1 prescaler
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 2) & 0x3), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_Input_IC1F -------------------------------
// SVD Line: 6742
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) Input capture 1 filter
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 4) & 0xF), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_Input_CC2S -------------------------------
// SVD Line: 6747
// - SFDITEM_FIELD__TIM1_CCMR1_Input_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) Capture/Compare 2 selection
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 8) & 0x3), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_Input_IC2PSC ------------------------------
// SVD Line: 6752
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) Input capture 2 prescaler
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 10) & 0x3), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_Input_IC2F -------------------------------
// SVD Line: 6757
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) Input capture 2 filter
//
// ( (unsigned char)((TIM1_CCMR1_Input >> 12) & 0xF), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_Input --------------------------------
// SVD Line: 6725
// SFDITEM_REG__TIM1_CCMR1_Input
// CCMR1_Input
//
// [Bits 31..0] RW (@ 0x40012C18) capture/compare mode register 1 (inputmode)
// ( (unsigned int)((TIM1_CCMR1_Input >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_Input = (TIM1_CCMR1_Input & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_Input_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_Input_ICPSC
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_Input_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_Input_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_Output ----------------------------
// SVD Line: 6764
unsigned int TIM1_CCMR2_Output __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_Output_CC3S -------------------------------
// SVD Line: 6770
// - SFDITEM_FIELD__TIM1_CCMR2_Output_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) Capture/Compare 3 selection
//
// ( (unsigned char)((TIM1_CCMR2_Output >> 0) & 0x3), ((TIM1_CCMR2_Output = (TIM1_CCMR2_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC3FE ------------------------------
// SVD Line: 6775
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) Output compare 3 fast enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC3PE ------------------------------
// SVD Line: 6780
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) Output compare 3 preload enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC3M -------------------------------
// SVD Line: 6785
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x40012C1C) Output compare 3 mode
//
// ( (unsigned char)((TIM1_CCMR2_Output >> 4) & 0x7), ((TIM1_CCMR2_Output = (TIM1_CCMR2_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC3CE ------------------------------
// SVD Line: 6790
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) Output compare 3 clear enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_CC4S -------------------------------
// SVD Line: 6795
// - SFDITEM_FIELD__TIM1_CCMR2_Output_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) Capture/Compare 4 selection
//
// ( (unsigned char)((TIM1_CCMR2_Output >> 8) & 0x3), ((TIM1_CCMR2_Output = (TIM1_CCMR2_Output & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC4FE ------------------------------
// SVD Line: 6800
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) Output compare 4 fast enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC4PE ------------------------------
// SVD Line: 6805
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) Output compare 4 preload enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC4M -------------------------------
// SVD Line: 6810
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x40012C1C) Output compare 4 mode
//
// ( (unsigned char)((TIM1_CCMR2_Output >> 12) & 0x7), ((TIM1_CCMR2_Output = (TIM1_CCMR2_Output & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Output_OC4CE ------------------------------
// SVD Line: 6815
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) Output compare 4 clear enable
//
// ( (unsigned int) TIM1_CCMR2_Output )
// OC4CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_Output -------------------------------
// SVD Line: 6764
// SFDITEM_REG__TIM1_CCMR2_Output
// CCMR2_Output
//
// [Bits 31..0] RW (@ 0x40012C1C) capture/compare mode register (outputmode)
// ( (unsigned int)((TIM1_CCMR2_Output >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_Output = (TIM1_CCMR2_Output & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_Output_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3M
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_Output_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4M
// - SFDITEM_FIELD__TIM1_CCMR2_Output_OC4CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_Input ----------------------------
// SVD Line: 6822
unsigned int TIM1_CCMR2_Input __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_Input_CC3S -------------------------------
// SVD Line: 6829
// - SFDITEM_FIELD__TIM1_CCMR2_Input_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) Capture/compare 3 selection
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 0) & 0x3), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Input_IC3PSC ------------------------------
// SVD Line: 6834
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) Input capture 3 prescaler
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 2) & 0x3), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_Input_IC3F -------------------------------
// SVD Line: 6839
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) Input capture 3 filter
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 4) & 0xF), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_Input_CC4S -------------------------------
// SVD Line: 6844
// - SFDITEM_FIELD__TIM1_CCMR2_Input_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) Capture/Compare 4 selection
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 8) & 0x3), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_Input_IC4PSC ------------------------------
// SVD Line: 6849
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) Input capture 4 prescaler
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 10) & 0x3), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_Input_IC4F -------------------------------
// SVD Line: 6854
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) Input capture 4 filter
//
// ( (unsigned char)((TIM1_CCMR2_Input >> 12) & 0xF), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_Input --------------------------------
// SVD Line: 6822
// SFDITEM_REG__TIM1_CCMR2_Input
// CCMR2_Input
//
// [Bits 31..0] RW (@ 0x40012C1C) capture/compare mode register 2 (inputmode)
// ( (unsigned int)((TIM1_CCMR2_Input >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_Input = (TIM1_CCMR2_Input & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_Input_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_Input_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_Input_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 6861
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 6867
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) Capture/Compare 1 output enable
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 6872
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 6877
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) Capture/Compare 1 complementary output enable
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 6882
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 6887
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) Capture/Compare 2 output enable
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 6892
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) Capture/Compare 2 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 6897
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) Capture/Compare 2 complementary output enable
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 6902
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) Capture/Compare 2 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 6907
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) Capture/Compare 3 output enable
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 6912
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) Capture/Compare 3 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 6917
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) Capture/Compare 3 complementary output enable
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 6922
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) Capture/Compare 3 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 6927
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) Capture/Compare 4 output enable
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 6932
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) Capture/Compare 3 output Polarity
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 6861
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) capture/compare enableregister
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 6939
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 6945
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) counter value
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 6939
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) counter
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 6952
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 6958
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) Prescaler value
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 6952
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) prescaler
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 6965
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 6971
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) Auto-reload value
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 6965
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) auto-reload register
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 6978
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 6984
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) Repetition counter value
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 6978
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) repetition counter register
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 6991
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 6997
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) Capture/Compare 1 value
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 6991
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) capture/compare register 1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 7004
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 7010
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) Capture/Compare 2 value
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 7004
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) capture/compare register 2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 7017
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 7023
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) Capture/Compare value
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 7017
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) capture/compare register 3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 7030
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 7036
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) Capture/Compare value
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 7030
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) capture/compare register 4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 7043
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 7049
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) Dead-time generator setup
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 7054
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) Lock configuration
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 7059
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) Off-state selection for Idle mode
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 7064
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) Off-state selection for Run mode
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 7069
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) Break enable
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 7074
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) Break polarity
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 7079
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) Automatic output enable
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 7084
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) Main output enable
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 7043
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) break and dead-time register
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ----------------------------- Register Item Address: TIM1_DCR --------------------------------
// SVD Line: 7091
unsigned int TIM1_DCR __AT (0x40012C48);
// -------------------------------- Field Item: TIM1_DCR_DBA ------------------------------------
// SVD Line: 7097
// - SFDITEM_FIELD__TIM1_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40012C48) DMA base address
//
// ( (unsigned char)((TIM1_DCR >> 0) & 0x1F), ((TIM1_DCR = (TIM1_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_DCR_DBL ------------------------------------
// SVD Line: 7102
// - SFDITEM_FIELD__TIM1_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40012C48) DMA burst length
//
// ( (unsigned char)((TIM1_DCR >> 8) & 0x1F), ((TIM1_DCR = (TIM1_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_DCR ------------------------------------
// SVD Line: 7091
// SFDITEM_REG__TIM1_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40012C48) DMA control register
// ( (unsigned int)((TIM1_DCR >> 0) & 0xFFFFFFFF), ((TIM1_DCR = (TIM1_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DCR_DBA
// - SFDITEM_FIELD__TIM1_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM1_DMAR --------------------------------
// SVD Line: 7109
unsigned int TIM1_DMAR __AT (0x40012C4C);
// ------------------------------- Field Item: TIM1_DMAR_DMAB -----------------------------------
// SVD Line: 7115
// - SFDITEM_FIELD__TIM1_DMAR_DMAB
// DMAB
//
// [Bits 15..0] RW (@ 0x40012C4C) DMA register for burst accesses
//
// ( (unsigned short)((TIM1_DMAR >> 0) & 0xFFFF), ((TIM1_DMAR = (TIM1_DMAR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_DMAR -----------------------------------
// SVD Line: 7109
// SFDITEM_REG__TIM1_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x40012C4C) DMA address for full transfer
// ( (unsigned int)((TIM1_DMAR >> 0) & 0xFFFFFFFF), ((TIM1_DMAR = (TIM1_DMAR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DMAR_DMAB
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 6237
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_Output
// - SFDITEM_REG__TIM1_CCMR1_Input
// - SFDITEM_REG__TIM1_CCMR2_Output
// - SFDITEM_REG__TIM1_CCMR2_Input
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
// - SFDITEM_REG__TIM1_DCR
// - SFDITEM_REG__TIM1_DMAR
//
//
// ----------------------------- Register Item Address: TIM2_CR1 --------------------------------
// SVD Line: 7140
unsigned int TIM2_CR1 __AT (0x40000000);
// -------------------------------- Field Item: TIM2_CR1_CEN ------------------------------------
// SVD Line: 7146
// - SFDITEM_FIELD__TIM2_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40000000) Counter enable
//
// ( (unsigned int) TIM2_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM2_CR1_UDIS -----------------------------------
// SVD Line: 7151
// - SFDITEM_FIELD__TIM2_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40000000) Update disable
//
// ( (unsigned int) TIM2_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM2_CR1_URS ------------------------------------
// SVD Line: 7156
// - SFDITEM_FIELD__TIM2_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40000000) Update request source
//
// ( (unsigned int) TIM2_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM2_CR1_OPM ------------------------------------
// SVD Line: 7161
// - SFDITEM_FIELD__TIM2_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40000000) One-pulse mode
//
// ( (unsigned int) TIM2_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM2_CR1_DIR ------------------------------------
// SVD Line: 7166
// - SFDITEM_FIELD__TIM2_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40000000) Direction
//
// ( (unsigned int) TIM2_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM2_CR1_CMS ------------------------------------
// SVD Line: 7171
// - SFDITEM_FIELD__TIM2_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40000000) Center-aligned mode selection
//
// ( (unsigned char)((TIM2_CR1 >> 5) & 0x3), ((TIM2_CR1 = (TIM2_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM2_CR1_ARPE -----------------------------------
// SVD Line: 7176
// - SFDITEM_FIELD__TIM2_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40000000) Auto-reload preload enable
//
// ( (unsigned int) TIM2_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM2_CR1_CKD ------------------------------------
// SVD Line: 7181
// - SFDITEM_FIELD__TIM2_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40000000) Clock division
//
// ( (unsigned char)((TIM2_CR1 >> 8) & 0x3), ((TIM2_CR1 = (TIM2_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CR1 ------------------------------------
// SVD Line: 7140
// SFDITEM_REG__TIM2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40000000) control register 1
// ( (unsigned int)((TIM2_CR1 >> 0) & 0xFFFFFFFF), ((TIM2_CR1 = (TIM2_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CR1_CEN
// - SFDITEM_FIELD__TIM2_CR1_UDIS
// - SFDITEM_FIELD__TIM2_CR1_URS
// - SFDITEM_FIELD__TIM2_CR1_OPM
// - SFDITEM_FIELD__TIM2_CR1_DIR
// - SFDITEM_FIELD__TIM2_CR1_CMS
// - SFDITEM_FIELD__TIM2_CR1_ARPE
// - SFDITEM_FIELD__TIM2_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM2_CR2 --------------------------------
// SVD Line: 7188
unsigned int TIM2_CR2 __AT (0x40000004);
// -------------------------------- Field Item: TIM2_CR2_CCDS -----------------------------------
// SVD Line: 7194
// - SFDITEM_FIELD__TIM2_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40000004) Capture/compare DMA selection
//
// ( (unsigned int) TIM2_CR2 )
// CCDS
//
//
//
// -------------------------------- Field Item: TIM2_CR2_MMS ------------------------------------
// SVD Line: 7199
// - SFDITEM_FIELD__TIM2_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40000004) Master mode selection
//
// ( (unsigned char)((TIM2_CR2 >> 4) & 0x7), ((TIM2_CR2 = (TIM2_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM2_CR2_TI1S -----------------------------------
// SVD Line: 7204
// - SFDITEM_FIELD__TIM2_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40000004) TI1 selection
//
// ( (unsigned int) TIM2_CR2 )
// TI1S
//
//
//
// -------------------------------- Register RTree: TIM2_CR2 ------------------------------------
// SVD Line: 7188
// SFDITEM_REG__TIM2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40000004) control register 2
// ( (unsigned int)((TIM2_CR2 >> 0) & 0xFFFFFFFF), ((TIM2_CR2 = (TIM2_CR2 & ~(0xF8UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF8) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CR2_CCDS
// - SFDITEM_FIELD__TIM2_CR2_MMS
// - SFDITEM_FIELD__TIM2_CR2_TI1S
//
//
// ---------------------------- Register Item Address: TIM2_SMCR --------------------------------
// SVD Line: 7211
unsigned int TIM2_SMCR __AT (0x40000008);
// -------------------------------- Field Item: TIM2_SMCR_SMS -----------------------------------
// SVD Line: 7217
// - SFDITEM_FIELD__TIM2_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40000008) Slave mode selection
//
// ( (unsigned char)((TIM2_SMCR >> 0) & 0x7), ((TIM2_SMCR = (TIM2_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM2_SMCR_OCCS -----------------------------------
// SVD Line: 7222
// - SFDITEM_FIELD__TIM2_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40000008) OCREF Clear Selection
//
// ( (unsigned int) TIM2_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM2_SMCR_TS ------------------------------------
// SVD Line: 7227
// - SFDITEM_FIELD__TIM2_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40000008) Trigger selection
//
// ( (unsigned char)((TIM2_SMCR >> 4) & 0x7), ((TIM2_SMCR = (TIM2_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM2_SMCR_MSM -----------------------------------
// SVD Line: 7232
// - SFDITEM_FIELD__TIM2_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40000008) Master/Slave mode
//
// ( (unsigned int) TIM2_SMCR )
// MSM
//
//
//
// -------------------------------- Register RTree: TIM2_SMCR -----------------------------------
// SVD Line: 7211
// SFDITEM_REG__TIM2_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40000008) slave mode control register
// ( (unsigned int)((TIM2_SMCR >> 0) & 0xFFFFFFFF), ((TIM2_SMCR = (TIM2_SMCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_SMCR_SMS
// - SFDITEM_FIELD__TIM2_SMCR_OCCS
// - SFDITEM_FIELD__TIM2_SMCR_TS
// - SFDITEM_FIELD__TIM2_SMCR_MSM
//
//
// ---------------------------- Register Item Address: TIM2_DIER --------------------------------
// SVD Line: 7239
unsigned int TIM2_DIER __AT (0x4000000C);
// -------------------------------- Field Item: TIM2_DIER_UIE -----------------------------------
// SVD Line: 7245
// - SFDITEM_FIELD__TIM2_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000000C) Update interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC1IE ----------------------------------
// SVD Line: 7250
// - SFDITEM_FIELD__TIM2_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000000C) Capture/Compare 1 interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC2IE ----------------------------------
// SVD Line: 7255
// - SFDITEM_FIELD__TIM2_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x4000000C) Capture/Compare 2 interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC3IE ----------------------------------
// SVD Line: 7260
// - SFDITEM_FIELD__TIM2_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x4000000C) Capture/Compare 3 interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC4IE ----------------------------------
// SVD Line: 7265
// - SFDITEM_FIELD__TIM2_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x4000000C) Capture/Compare 4 interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// CC4IE
//
//
//
// -------------------------------- Field Item: TIM2_DIER_TIE -----------------------------------
// SVD Line: 7270
// - SFDITEM_FIELD__TIM2_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x4000000C) Trigger interrupt enable
//
// ( (unsigned int) TIM2_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM2_DIER_UDE -----------------------------------
// SVD Line: 7275
// - SFDITEM_FIELD__TIM2_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4000000C) Update DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// UDE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC1DE ----------------------------------
// SVD Line: 7280
// - SFDITEM_FIELD__TIM2_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4000000C) Capture/Compare 1 DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// CC1DE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC2DE ----------------------------------
// SVD Line: 7285
// - SFDITEM_FIELD__TIM2_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x4000000C) Capture/Compare 2 DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// CC2DE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC3DE ----------------------------------
// SVD Line: 7290
// - SFDITEM_FIELD__TIM2_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x4000000C) Capture/Compare 3 DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// CC3DE
//
//
//
// ------------------------------- Field Item: TIM2_DIER_CC4DE ----------------------------------
// SVD Line: 7295
// - SFDITEM_FIELD__TIM2_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x4000000C) Capture/Compare 4 DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// CC4DE
//
//
//
// -------------------------------- Field Item: TIM2_DIER_TDE -----------------------------------
// SVD Line: 7300
// - SFDITEM_FIELD__TIM2_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x4000000C) Trigger DMA request enable
//
// ( (unsigned int) TIM2_DIER )
// TDE
//
//
//
// -------------------------------- Register RTree: TIM2_DIER -----------------------------------
// SVD Line: 7239
// SFDITEM_REG__TIM2_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000000C) DMA/Interrupt enable register
// ( (unsigned int)((TIM2_DIER >> 0) & 0xFFFFFFFF), ((TIM2_DIER = (TIM2_DIER & ~(0x5F5FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5F5F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_DIER_UIE
// - SFDITEM_FIELD__TIM2_DIER_CC1IE
// - SFDITEM_FIELD__TIM2_DIER_CC2IE
// - SFDITEM_FIELD__TIM2_DIER_CC3IE
// - SFDITEM_FIELD__TIM2_DIER_CC4IE
// - SFDITEM_FIELD__TIM2_DIER_TIE
// - SFDITEM_FIELD__TIM2_DIER_UDE
// - SFDITEM_FIELD__TIM2_DIER_CC1DE
// - SFDITEM_FIELD__TIM2_DIER_CC2DE
// - SFDITEM_FIELD__TIM2_DIER_CC3DE
// - SFDITEM_FIELD__TIM2_DIER_CC4DE
// - SFDITEM_FIELD__TIM2_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM2_SR ---------------------------------
// SVD Line: 7307
unsigned int TIM2_SR __AT (0x40000010);
// --------------------------------- Field Item: TIM2_SR_UIF ------------------------------------
// SVD Line: 7313
// - SFDITEM_FIELD__TIM2_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40000010) Update interrupt flag
//
// ( (unsigned int) TIM2_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC1IF -----------------------------------
// SVD Line: 7318
// - SFDITEM_FIELD__TIM2_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40000010) Capture/compare 1 interrupt flag
//
// ( (unsigned int) TIM2_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC2IF -----------------------------------
// SVD Line: 7323
// - SFDITEM_FIELD__TIM2_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40000010) Capture/Compare 2 interrupt flag
//
// ( (unsigned int) TIM2_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC3IF -----------------------------------
// SVD Line: 7328
// - SFDITEM_FIELD__TIM2_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40000010) Capture/Compare 3 interrupt flag
//
// ( (unsigned int) TIM2_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC4IF -----------------------------------
// SVD Line: 7333
// - SFDITEM_FIELD__TIM2_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40000010) Capture/Compare 4 interrupt flag
//
// ( (unsigned int) TIM2_SR )
// CC4IF
//
//
//
// --------------------------------- Field Item: TIM2_SR_TIF ------------------------------------
// SVD Line: 7338
// - SFDITEM_FIELD__TIM2_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40000010) Trigger interrupt flag
//
// ( (unsigned int) TIM2_SR )
// TIF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC1OF -----------------------------------
// SVD Line: 7343
// - SFDITEM_FIELD__TIM2_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40000010) Capture/Compare 1 overcapture flag
//
// ( (unsigned int) TIM2_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC2OF -----------------------------------
// SVD Line: 7348
// - SFDITEM_FIELD__TIM2_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40000010) Capture/compare 2 overcapture flag
//
// ( (unsigned int) TIM2_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC3OF -----------------------------------
// SVD Line: 7353
// - SFDITEM_FIELD__TIM2_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40000010) Capture/Compare 3 overcapture flag
//
// ( (unsigned int) TIM2_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM2_SR_CC4OF -----------------------------------
// SVD Line: 7358
// - SFDITEM_FIELD__TIM2_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40000010) Capture/Compare 4 overcapture flag
//
// ( (unsigned int) TIM2_SR )
// CC4OF
//
//
//
// --------------------------------- Register RTree: TIM2_SR ------------------------------------
// SVD Line: 7307
// SFDITEM_REG__TIM2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40000010) status register
// ( (unsigned int)((TIM2_SR >> 0) & 0xFFFFFFFF), ((TIM2_SR = (TIM2_SR & ~(0x1E5FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1E5F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_SR_UIF
// - SFDITEM_FIELD__TIM2_SR_CC1IF
// - SFDITEM_FIELD__TIM2_SR_CC2IF
// - SFDITEM_FIELD__TIM2_SR_CC3IF
// - SFDITEM_FIELD__TIM2_SR_CC4IF
// - SFDITEM_FIELD__TIM2_SR_TIF
// - SFDITEM_FIELD__TIM2_SR_CC1OF
// - SFDITEM_FIELD__TIM2_SR_CC2OF
// - SFDITEM_FIELD__TIM2_SR_CC3OF
// - SFDITEM_FIELD__TIM2_SR_CC4OF
//
//
// ----------------------------- Register Item Address: TIM2_EGR --------------------------------
// SVD Line: 7365
unsigned int TIM2_EGR __AT (0x40000014);
// --------------------------------- Field Item: TIM2_EGR_UG ------------------------------------
// SVD Line: 7372
// - SFDITEM_FIELD__TIM2_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40000014) Update generation
//
// ( (unsigned int) TIM2_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM2_EGR_CC1G -----------------------------------
// SVD Line: 7377
// - SFDITEM_FIELD__TIM2_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40000014) Capture/compare 1 generation
//
// ( (unsigned int) TIM2_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM2_EGR_CC2G -----------------------------------
// SVD Line: 7382
// - SFDITEM_FIELD__TIM2_EGR_CC2G
// CC2G
//
// [Bit 2] WO (@ 0x40000014) Capture/compare 2 generation
//
// ( (unsigned int) TIM2_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM2_EGR_CC3G -----------------------------------
// SVD Line: 7387
// - SFDITEM_FIELD__TIM2_EGR_CC3G
// CC3G
//
// [Bit 3] WO (@ 0x40000014) Capture/compare 3 generation
//
// ( (unsigned int) TIM2_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM2_EGR_CC4G -----------------------------------
// SVD Line: 7392
// - SFDITEM_FIELD__TIM2_EGR_CC4G
// CC4G
//
// [Bit 4] WO (@ 0x40000014) Capture/compare 4 generation
//
// ( (unsigned int) TIM2_EGR )
// CC4G
//
//
//
// --------------------------------- Field Item: TIM2_EGR_TG ------------------------------------
// SVD Line: 7397
// - SFDITEM_FIELD__TIM2_EGR_TG
// TG
//
// [Bit 6] WO (@ 0x40000014) Trigger generation
//
// ( (unsigned int) TIM2_EGR )
// TG
//
//
//
// -------------------------------- Register RTree: TIM2_EGR ------------------------------------
// SVD Line: 7365
// SFDITEM_REG__TIM2_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40000014) event generation register
// ( (unsigned int)((TIM2_EGR >> 0) & 0xFFFFFFFF), ((TIM2_EGR = (TIM2_EGR & ~(0x5FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_EGR_UG
// - SFDITEM_FIELD__TIM2_EGR_CC1G
// - SFDITEM_FIELD__TIM2_EGR_CC2G
// - SFDITEM_FIELD__TIM2_EGR_CC3G
// - SFDITEM_FIELD__TIM2_EGR_CC4G
// - SFDITEM_FIELD__TIM2_EGR_TG
//
//
// ------------------------ Register Item Address: TIM2_CCMR1_Output ----------------------------
// SVD Line: 7404
unsigned int TIM2_CCMR1_Output __AT (0x40000018);
// --------------------------- Field Item: TIM2_CCMR1_Output_CC1S -------------------------------
// SVD Line: 7410
// - SFDITEM_FIELD__TIM2_CCMR1_Output_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40000018) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM2_CCMR1_Output >> 0) & 0x3), ((TIM2_CCMR1_Output = (TIM2_CCMR1_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC1FE ------------------------------
// SVD Line: 7415
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40000018) Output compare 1 fast enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC1PE ------------------------------
// SVD Line: 7420
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40000018) Output compare 1 preload enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC1M -------------------------------
// SVD Line: 7425
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40000018) Output compare 1 mode
//
// ( (unsigned char)((TIM2_CCMR1_Output >> 4) & 0x7), ((TIM2_CCMR1_Output = (TIM2_CCMR1_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC1CE ------------------------------
// SVD Line: 7430
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40000018) Output compare 1 clear enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_CC2S -------------------------------
// SVD Line: 7435
// - SFDITEM_FIELD__TIM2_CCMR1_Output_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40000018) Capture/Compare 2 selection
//
// ( (unsigned char)((TIM2_CCMR1_Output >> 8) & 0x3), ((TIM2_CCMR1_Output = (TIM2_CCMR1_Output & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC2FE ------------------------------
// SVD Line: 7440
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40000018) Output compare 2 fast enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC2PE ------------------------------
// SVD Line: 7445
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40000018) Output compare 2 preload enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC2M -------------------------------
// SVD Line: 7450
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40000018) Output compare 2 mode
//
// ( (unsigned char)((TIM2_CCMR1_Output >> 12) & 0x7), ((TIM2_CCMR1_Output = (TIM2_CCMR1_Output & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Output_OC2CE ------------------------------
// SVD Line: 7455
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40000018) Output compare 2 clear enable
//
// ( (unsigned int) TIM2_CCMR1_Output )
// OC2CE
//
//
//
// ---------------------------- Register RTree: TIM2_CCMR1_Output -------------------------------
// SVD Line: 7404
// SFDITEM_REG__TIM2_CCMR1_Output
// CCMR1_Output
//
// [Bits 31..0] RW (@ 0x40000018) capture/compare mode register 1 (outputmode)
// ( (unsigned int)((TIM2_CCMR1_Output >> 0) & 0xFFFFFFFF), ((TIM2_CCMR1_Output = (TIM2_CCMR1_Output & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCMR1_Output_CC1S
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1FE
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1PE
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1M
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC1CE
// - SFDITEM_FIELD__TIM2_CCMR1_Output_CC2S
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2FE
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2PE
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2M
// - SFDITEM_FIELD__TIM2_CCMR1_Output_OC2CE
//
//
// ------------------------- Register Item Address: TIM2_CCMR1_Input ----------------------------
// SVD Line: 7462
unsigned int TIM2_CCMR1_Input __AT (0x40000018);
// ---------------------------- Field Item: TIM2_CCMR1_Input_CC1S -------------------------------
// SVD Line: 7469
// - SFDITEM_FIELD__TIM2_CCMR1_Input_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40000018) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 0) & 0x3), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Input_IC1PSC ------------------------------
// SVD Line: 7474
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40000018) Input capture 1 prescaler
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 2) & 0x3), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR1_Input_IC1F -------------------------------
// SVD Line: 7479
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40000018) Input capture 1 filter
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 4) & 0xF), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR1_Input_CC2S -------------------------------
// SVD Line: 7484
// - SFDITEM_FIELD__TIM2_CCMR1_Input_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40000018) Capture/compare 2 selection
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 8) & 0x3), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR1_Input_IC2PSC ------------------------------
// SVD Line: 7489
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40000018) Input capture 2 prescaler
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 10) & 0x3), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR1_Input_IC2F -------------------------------
// SVD Line: 7494
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40000018) Input capture 2 filter
//
// ( (unsigned char)((TIM2_CCMR1_Input >> 12) & 0xF), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM2_CCMR1_Input --------------------------------
// SVD Line: 7462
// SFDITEM_REG__TIM2_CCMR1_Input
// CCMR1_Input
//
// [Bits 31..0] RW (@ 0x40000018) capture/compare mode register 1 (inputmode)
// ( (unsigned int)((TIM2_CCMR1_Input >> 0) & 0xFFFFFFFF), ((TIM2_CCMR1_Input = (TIM2_CCMR1_Input & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCMR1_Input_CC1S
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC1PSC
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC1F
// - SFDITEM_FIELD__TIM2_CCMR1_Input_CC2S
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC2PSC
// - SFDITEM_FIELD__TIM2_CCMR1_Input_IC2F
//
//
// ------------------------ Register Item Address: TIM2_CCMR2_Output ----------------------------
// SVD Line: 7501
unsigned int TIM2_CCMR2_Output __AT (0x4000001C);
// --------------------------- Field Item: TIM2_CCMR2_Output_CC3S -------------------------------
// SVD Line: 7507
// - SFDITEM_FIELD__TIM2_CCMR2_Output_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x4000001C) Capture/Compare 3 selection
//
// ( (unsigned char)((TIM2_CCMR2_Output >> 0) & 0x3), ((TIM2_CCMR2_Output = (TIM2_CCMR2_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC3FE ------------------------------
// SVD Line: 7512
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x4000001C) Output compare 3 fast enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC3PE ------------------------------
// SVD Line: 7517
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x4000001C) Output compare 3 preload enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC3M -------------------------------
// SVD Line: 7522
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x4000001C) Output compare 3 mode
//
// ( (unsigned char)((TIM2_CCMR2_Output >> 4) & 0x7), ((TIM2_CCMR2_Output = (TIM2_CCMR2_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC3CE ------------------------------
// SVD Line: 7527
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x4000001C) Output compare 3 clear enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_CC4S -------------------------------
// SVD Line: 7532
// - SFDITEM_FIELD__TIM2_CCMR2_Output_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x4000001C) Capture/Compare 4 selection
//
// ( (unsigned char)((TIM2_CCMR2_Output >> 8) & 0x3), ((TIM2_CCMR2_Output = (TIM2_CCMR2_Output & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC4FE ------------------------------
// SVD Line: 7537
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x4000001C) Output compare 4 fast enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC4PE ------------------------------
// SVD Line: 7542
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x4000001C) Output compare 4 preload enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC4M -------------------------------
// SVD Line: 7547
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x4000001C) Output compare 4 mode
//
// ( (unsigned char)((TIM2_CCMR2_Output >> 12) & 0x7), ((TIM2_CCMR2_Output = (TIM2_CCMR2_Output & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Output_OC4CE ------------------------------
// SVD Line: 7552
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x4000001C) Output compare 4 clear enable
//
// ( (unsigned int) TIM2_CCMR2_Output )
// OC4CE
//
//
//
// ---------------------------- Register RTree: TIM2_CCMR2_Output -------------------------------
// SVD Line: 7501
// SFDITEM_REG__TIM2_CCMR2_Output
// CCMR2_Output
//
// [Bits 31..0] RW (@ 0x4000001C) capture/compare mode register 2 (outputmode)
// ( (unsigned int)((TIM2_CCMR2_Output >> 0) & 0xFFFFFFFF), ((TIM2_CCMR2_Output = (TIM2_CCMR2_Output & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCMR2_Output_CC3S
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3FE
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3PE
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3M
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC3CE
// - SFDITEM_FIELD__TIM2_CCMR2_Output_CC4S
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4FE
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4PE
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4M
// - SFDITEM_FIELD__TIM2_CCMR2_Output_OC4CE
//
//
// ------------------------- Register Item Address: TIM2_CCMR2_Input ----------------------------
// SVD Line: 7559
unsigned int TIM2_CCMR2_Input __AT (0x4000001C);
// ---------------------------- Field Item: TIM2_CCMR2_Input_CC3S -------------------------------
// SVD Line: 7566
// - SFDITEM_FIELD__TIM2_CCMR2_Input_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x4000001C) Capture/Compare 3 selection
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 0) & 0x3), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Input_IC3PSC ------------------------------
// SVD Line: 7571
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x4000001C) Input capture 3 prescaler
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 2) & 0x3), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR2_Input_IC3F -------------------------------
// SVD Line: 7576
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x4000001C) Input capture 3 filter
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 4) & 0xF), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR2_Input_CC4S -------------------------------
// SVD Line: 7581
// - SFDITEM_FIELD__TIM2_CCMR2_Input_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x4000001C) Capture/Compare 4 selection
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 8) & 0x3), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM2_CCMR2_Input_IC4PSC ------------------------------
// SVD Line: 7586
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x4000001C) Input capture 4 prescaler
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 10) & 0x3), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM2_CCMR2_Input_IC4F -------------------------------
// SVD Line: 7591
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x4000001C) Input capture 4 filter
//
// ( (unsigned char)((TIM2_CCMR2_Input >> 12) & 0xF), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM2_CCMR2_Input --------------------------------
// SVD Line: 7559
// SFDITEM_REG__TIM2_CCMR2_Input
// CCMR2_Input
//
// [Bits 31..0] RW (@ 0x4000001C) capture/compare mode register 2 (inputmode)
// ( (unsigned int)((TIM2_CCMR2_Input >> 0) & 0xFFFFFFFF), ((TIM2_CCMR2_Input = (TIM2_CCMR2_Input & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCMR2_Input_CC3S
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC3PSC
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC3F
// - SFDITEM_FIELD__TIM2_CCMR2_Input_CC4S
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC4PSC
// - SFDITEM_FIELD__TIM2_CCMR2_Input_IC4F
//
//
// ---------------------------- Register Item Address: TIM2_CCER --------------------------------
// SVD Line: 7598
unsigned int TIM2_CCER __AT (0x40000020);
// ------------------------------- Field Item: TIM2_CCER_CC1E -----------------------------------
// SVD Line: 7604
// - SFDITEM_FIELD__TIM2_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40000020) Capture/Compare 1 output enable
//
// ( (unsigned int) TIM2_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC1P -----------------------------------
// SVD Line: 7609
// - SFDITEM_FIELD__TIM2_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40000020) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC1NP ----------------------------------
// SVD Line: 7614
// - SFDITEM_FIELD__TIM2_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40000020) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC2E -----------------------------------
// SVD Line: 7619
// - SFDITEM_FIELD__TIM2_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40000020) Capture/Compare 2 output enable
//
// ( (unsigned int) TIM2_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC2P -----------------------------------
// SVD Line: 7624
// - SFDITEM_FIELD__TIM2_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40000020) Capture/Compare 2 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC2NP ----------------------------------
// SVD Line: 7629
// - SFDITEM_FIELD__TIM2_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40000020) Capture/Compare 2 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC3E -----------------------------------
// SVD Line: 7634
// - SFDITEM_FIELD__TIM2_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40000020) Capture/Compare 3 output enable
//
// ( (unsigned int) TIM2_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC3P -----------------------------------
// SVD Line: 7639
// - SFDITEM_FIELD__TIM2_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40000020) Capture/Compare 3 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC3NP ----------------------------------
// SVD Line: 7644
// - SFDITEM_FIELD__TIM2_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40000020) Capture/Compare 3 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC4E -----------------------------------
// SVD Line: 7649
// - SFDITEM_FIELD__TIM2_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40000020) Capture/Compare 4 output enable
//
// ( (unsigned int) TIM2_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM2_CCER_CC4P -----------------------------------
// SVD Line: 7654
// - SFDITEM_FIELD__TIM2_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40000020) Capture/Compare 4 output Polarity
//
// ( (unsigned int) TIM2_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM2_CCER -----------------------------------
// SVD Line: 7598
// SFDITEM_REG__TIM2_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40000020) capture/compare enableregister
// ( (unsigned int)((TIM2_CCER >> 0) & 0xFFFFFFFF), ((TIM2_CCER = (TIM2_CCER & ~(0x3BBBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3BBB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCER_CC1E
// - SFDITEM_FIELD__TIM2_CCER_CC1P
// - SFDITEM_FIELD__TIM2_CCER_CC1NP
// - SFDITEM_FIELD__TIM2_CCER_CC2E
// - SFDITEM_FIELD__TIM2_CCER_CC2P
// - SFDITEM_FIELD__TIM2_CCER_CC2NP
// - SFDITEM_FIELD__TIM2_CCER_CC3E
// - SFDITEM_FIELD__TIM2_CCER_CC3P
// - SFDITEM_FIELD__TIM2_CCER_CC3NP
// - SFDITEM_FIELD__TIM2_CCER_CC4E
// - SFDITEM_FIELD__TIM2_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM2_CNT --------------------------------
// SVD Line: 7661
unsigned int TIM2_CNT __AT (0x40000024);
// -------------------------------- Field Item: TIM2_CNT_CNT ------------------------------------
// SVD Line: 7667
// - SFDITEM_FIELD__TIM2_CNT_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40000024) counter value
//
// ( (unsigned int)((TIM2_CNT >> 0) & 0xFFFFFFFF), ((TIM2_CNT = (TIM2_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CNT ------------------------------------
// SVD Line: 7661
// SFDITEM_REG__TIM2_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40000024) counter
// ( (unsigned int)((TIM2_CNT >> 0) & 0xFFFFFFFF), ((TIM2_CNT = (TIM2_CNT & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM2_PSC --------------------------------
// SVD Line: 7674
unsigned int TIM2_PSC __AT (0x40000028);
// -------------------------------- Field Item: TIM2_PSC_PSC ------------------------------------
// SVD Line: 7680
// - SFDITEM_FIELD__TIM2_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40000028) Prescaler value
//
// ( (unsigned short)((TIM2_PSC >> 0) & 0xFFFF), ((TIM2_PSC = (TIM2_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_PSC ------------------------------------
// SVD Line: 7674
// SFDITEM_REG__TIM2_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40000028) prescaler
// ( (unsigned int)((TIM2_PSC >> 0) & 0xFFFFFFFF), ((TIM2_PSC = (TIM2_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM2_ARR --------------------------------
// SVD Line: 7687
unsigned int TIM2_ARR __AT (0x4000002C);
// -------------------------------- Field Item: TIM2_ARR_ARR ------------------------------------
// SVD Line: 7693
// - SFDITEM_FIELD__TIM2_ARR_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000002C) Auto-reload value
//
// ( (unsigned int)((TIM2_ARR >> 0) & 0xFFFFFFFF), ((TIM2_ARR = (TIM2_ARR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_ARR ------------------------------------
// SVD Line: 7687
// SFDITEM_REG__TIM2_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000002C) auto-reload register
// ( (unsigned int)((TIM2_ARR >> 0) & 0xFFFFFFFF), ((TIM2_ARR = (TIM2_ARR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM2_CCR1 --------------------------------
// SVD Line: 7700
unsigned int TIM2_CCR1 __AT (0x40000034);
// ------------------------------- Field Item: TIM2_CCR1_CCR1 -----------------------------------
// SVD Line: 7706
// - SFDITEM_FIELD__TIM2_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40000034) Capture/Compare 1 value
//
// ( (unsigned short)((TIM2_CCR1 >> 0) & 0xFFFF), ((TIM2_CCR1 = (TIM2_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CCR1 -----------------------------------
// SVD Line: 7700
// SFDITEM_REG__TIM2_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40000034) capture/compare register 1
// ( (unsigned int)((TIM2_CCR1 >> 0) & 0xFFFFFFFF), ((TIM2_CCR1 = (TIM2_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM2_CCR2 --------------------------------
// SVD Line: 7713
unsigned int TIM2_CCR2 __AT (0x40000038);
// ------------------------------- Field Item: TIM2_CCR2_CCR2 -----------------------------------
// SVD Line: 7719
// - SFDITEM_FIELD__TIM2_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40000038) Capture/Compare 2 value
//
// ( (unsigned short)((TIM2_CCR2 >> 0) & 0xFFFF), ((TIM2_CCR2 = (TIM2_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CCR2 -----------------------------------
// SVD Line: 7713
// SFDITEM_REG__TIM2_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40000038) capture/compare register 2
// ( (unsigned int)((TIM2_CCR2 >> 0) & 0xFFFFFFFF), ((TIM2_CCR2 = (TIM2_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM2_CCR3 --------------------------------
// SVD Line: 7726
unsigned int TIM2_CCR3 __AT (0x4000003C);
// ------------------------------- Field Item: TIM2_CCR3_CCR3 -----------------------------------
// SVD Line: 7732
// - SFDITEM_FIELD__TIM2_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x4000003C) Capture/Compare value
//
// ( (unsigned short)((TIM2_CCR3 >> 0) & 0xFFFF), ((TIM2_CCR3 = (TIM2_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CCR3 -----------------------------------
// SVD Line: 7726
// SFDITEM_REG__TIM2_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x4000003C) capture/compare register 3
// ( (unsigned int)((TIM2_CCR3 >> 0) & 0xFFFFFFFF), ((TIM2_CCR3 = (TIM2_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM2_CCR4 --------------------------------
// SVD Line: 7739
unsigned int TIM2_CCR4 __AT (0x40000040);
// ------------------------------- Field Item: TIM2_CCR4_CCR4 -----------------------------------
// SVD Line: 7745
// - SFDITEM_FIELD__TIM2_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40000040) Capture/Compare value
//
// ( (unsigned short)((TIM2_CCR4 >> 0) & 0xFFFF), ((TIM2_CCR4 = (TIM2_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_CCR4 -----------------------------------
// SVD Line: 7739
// SFDITEM_REG__TIM2_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40000040) capture/compare register 4
// ( (unsigned int)((TIM2_CCR4 >> 0) & 0xFFFFFFFF), ((TIM2_CCR4 = (TIM2_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_CCR4_CCR4
//
//
// ----------------------------- Register Item Address: TIM2_DCR --------------------------------
// SVD Line: 7752
unsigned int TIM2_DCR __AT (0x40000048);
// -------------------------------- Field Item: TIM2_DCR_DBA ------------------------------------
// SVD Line: 7758
// - SFDITEM_FIELD__TIM2_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40000048) DMA base address
//
// ( (unsigned char)((TIM2_DCR >> 0) & 0x1F), ((TIM2_DCR = (TIM2_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM2_DCR_DBL ------------------------------------
// SVD Line: 7763
// - SFDITEM_FIELD__TIM2_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40000048) DMA burst length
//
// ( (unsigned char)((TIM2_DCR >> 8) & 0x1F), ((TIM2_DCR = (TIM2_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_DCR ------------------------------------
// SVD Line: 7752
// SFDITEM_REG__TIM2_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40000048) DMA control register
// ( (unsigned int)((TIM2_DCR >> 0) & 0xFFFFFFFF), ((TIM2_DCR = (TIM2_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_DCR_DBA
// - SFDITEM_FIELD__TIM2_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM2_DMAR --------------------------------
// SVD Line: 7770
unsigned int TIM2_DMAR __AT (0x4000004C);
// ------------------------------- Field Item: TIM2_DMAR_DMAB -----------------------------------
// SVD Line: 7776
// - SFDITEM_FIELD__TIM2_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x4000004C) DMA register for burst accesses
//
// ( (unsigned int)((TIM2_DMAR >> 0) & 0xFFFFFFFF), ((TIM2_DMAR = (TIM2_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM2_DMAR -----------------------------------
// SVD Line: 7770
// SFDITEM_REG__TIM2_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x4000004C) DMA address for full transfer
// ( (unsigned int)((TIM2_DMAR >> 0) & 0xFFFFFFFF), ((TIM2_DMAR = (TIM2_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM2_DMAR_DMAB
//
//
// ---------------------------------- Peripheral View: TIM2 -------------------------------------
// SVD Line: 7124
// TIM2
// TIM2
// - SFDITEM_REG__TIM2_CR1
// - SFDITEM_REG__TIM2_CR2
// - SFDITEM_REG__TIM2_SMCR
// - SFDITEM_REG__TIM2_DIER
// - SFDITEM_REG__TIM2_SR
// - SFDITEM_REG__TIM2_EGR
// - SFDITEM_REG__TIM2_CCMR1_Output
// - SFDITEM_REG__TIM2_CCMR1_Input
// - SFDITEM_REG__TIM2_CCMR2_Output
// - SFDITEM_REG__TIM2_CCMR2_Input
// - SFDITEM_REG__TIM2_CCER
// - SFDITEM_REG__TIM2_CNT
// - SFDITEM_REG__TIM2_PSC
// - SFDITEM_REG__TIM2_ARR
// - SFDITEM_REG__TIM2_CCR1
// - SFDITEM_REG__TIM2_CCR2
// - SFDITEM_REG__TIM2_CCR3
// - SFDITEM_REG__TIM2_CCR4
// - SFDITEM_REG__TIM2_DCR
// - SFDITEM_REG__TIM2_DMAR
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 7801
unsigned int TIM14_CR1 __AT (0x40002000);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 7807
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002000) Counter enable
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 7812
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002000) Update disable
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 7817
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002000) Update request source
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 7822
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002000) Auto-reload preload enable
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 7827
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002000) Prescaler factor
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 7801
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002000) TIM14 control register1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x387UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x387) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 7834
unsigned int TIM14_DIER __AT (0x4000200C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 7840
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000200C) Update interrupt enable
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 7845
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000200C) Compare/
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 7834
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000200C) DMA/Interrupt enable register
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 7852
unsigned int TIM14_SR __AT (0x40002010);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 7858
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002010) Update interrupt flag
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 7863
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002010) Compare/capture 1 interrupt flag
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 7868
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002010) Compare/capture 1 flag
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 7852
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002010) status register
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x203UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x203) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 7875
unsigned int TIM14_EGR __AT (0x40002014);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 7882
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40002014) Update generation
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 7887
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40002014) Compare/capture1 event
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 7875
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40002014) event generation register
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_Output ---------------------------
// SVD Line: 7894
unsigned int TIM14_CCMR1_Output __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_Output_CC1S ------------------------------
// SVD Line: 7900
// - SFDITEM_FIELD__TIM14_CCMR1_Output_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM14_CCMR1_Output >> 0) & 0x3), ((TIM14_CCMR1_Output = (TIM14_CCMR1_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_Output_OC1FE ------------------------------
// SVD Line: 7905
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40002018) Output Compare 1 fast enable
//
// ( (unsigned int) TIM14_CCMR1_Output )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_Output_OC1PE ------------------------------
// SVD Line: 7910
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002018) Output Compare 1 preload enable
//
// ( (unsigned int) TIM14_CCMR1_Output )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_Output_OC1M ------------------------------
// SVD Line: 7915
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40002018) Output Compare 1 mode
//
// ( (unsigned char)((TIM14_CCMR1_Output >> 4) & 0x7), ((TIM14_CCMR1_Output = (TIM14_CCMR1_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_Output -------------------------------
// SVD Line: 7894
// SFDITEM_REG__TIM14_CCMR1_Output
// CCMR1_Output
//
// [Bits 31..0] RW (@ 0x40002018) capture/compare mode register (outputmode)
// ( (unsigned int)((TIM14_CCMR1_Output >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_Output = (TIM14_CCMR1_Output & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_Output_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1FE
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_Output_OC1M
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_Input ----------------------------
// SVD Line: 7922
unsigned int TIM14_CCMR1_Input __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_Input_CC1S -------------------------------
// SVD Line: 7929
// - SFDITEM_FIELD__TIM14_CCMR1_Input_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM14_CCMR1_Input >> 0) & 0x3), ((TIM14_CCMR1_Input = (TIM14_CCMR1_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_Input_IC1PSC ------------------------------
// SVD Line: 7934
// - SFDITEM_FIELD__TIM14_CCMR1_Input_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002018) Input capture 1 prescaler
//
// ( (unsigned char)((TIM14_CCMR1_Input >> 2) & 0x3), ((TIM14_CCMR1_Input = (TIM14_CCMR1_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_Input_IC1F -------------------------------
// SVD Line: 7939
// - SFDITEM_FIELD__TIM14_CCMR1_Input_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002018) Input capture 1 filter
//
// ( (unsigned char)((TIM14_CCMR1_Input >> 4) & 0xF), ((TIM14_CCMR1_Input = (TIM14_CCMR1_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_Input -------------------------------
// SVD Line: 7922
// SFDITEM_REG__TIM14_CCMR1_Input
// CCMR1_Input
//
// [Bits 31..0] RW (@ 0x40002018) capture/compare mode register 1 (inputmode)
// ( (unsigned int)((TIM14_CCMR1_Input >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_Input = (TIM14_CCMR1_Input & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_Input_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_Input_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_Input_IC1F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 7946
unsigned int TIM14_CCER __AT (0x40002020);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 7952
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002020) Capture/Compare 1 output enable
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 7957
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002020) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 7962
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002020) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 7946
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002020) capture/compare enableregister
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 7969
unsigned int TIM14_CNT __AT (0x40002024);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 7975
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002024) counter value
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 7969
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002024) counter
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 7982
unsigned int TIM14_PSC __AT (0x40002028);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 7988
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002028) Prescaler value
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 7982
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002028) prescaler
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 7995
unsigned int TIM14_ARR __AT (0x4000202C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 8001
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000202C) Auto-reload value
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 7995
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000202C) auto-reload register
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 8008
unsigned int TIM14_CCR1 __AT (0x40002034);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 8014
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002034) Capture/Compare 1 value
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 8008
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002034) capture/compare register 1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// ----------------------------- Register Item Address: TIM14_OR --------------------------------
// SVD Line: 8021
unsigned int TIM14_OR __AT (0x40002050);
// ------------------------------ Field Item: TIM14_OR_TI1_RMP ----------------------------------
// SVD Line: 8027
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
// TI1_RMP
//
// [Bits 1..0] RW (@ 0x40002050) TIM14 channel1 input remap
//
// ( (unsigned char)((TIM14_OR >> 0) & 0x3), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_OR ------------------------------------
// SVD Line: 8021
// SFDITEM_REG__TIM14_OR
// OR
//
// [Bits 31..0] RW (@ 0x40002050) Option register
// ( (unsigned int)((TIM14_OR >> 0) & 0xFFFFFFFF), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 7785
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_Output
// - SFDITEM_REG__TIM14_CCMR1_Input
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_OR
//
//
// ---------------------------- Register Item Address: TIM16_CR1 --------------------------------
// SVD Line: 8052
unsigned int TIM16_CR1 __AT (0x40014400);
// -------------------------------- Field Item: TIM16_CR1_CEN -----------------------------------
// SVD Line: 8058
// - SFDITEM_FIELD__TIM16_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40014400) Counter enable
//
// ( (unsigned int) TIM16_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM16_CR1_UDIS -----------------------------------
// SVD Line: 8063
// - SFDITEM_FIELD__TIM16_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40014400) Update disable
//
// ( (unsigned int) TIM16_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM16_CR1_URS -----------------------------------
// SVD Line: 8068
// - SFDITEM_FIELD__TIM16_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40014400) Update request source
//
// ( (unsigned int) TIM16_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM16_CR1_OPM -----------------------------------
// SVD Line: 8073
// - SFDITEM_FIELD__TIM16_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40014400) One pulse mode
//
// ( (unsigned int) TIM16_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM16_CR1_ARPE -----------------------------------
// SVD Line: 8078
// - SFDITEM_FIELD__TIM16_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40014400) Auto-reload preload enable
//
// ( (unsigned int) TIM16_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM16_CR1_CKD -----------------------------------
// SVD Line: 8083
// - SFDITEM_FIELD__TIM16_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40014400) Prescaler factor
//
// ( (unsigned char)((TIM16_CR1 >> 8) & 0x3), ((TIM16_CR1 = (TIM16_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_CR1 -----------------------------------
// SVD Line: 8052
// SFDITEM_REG__TIM16_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40014400) TIM16 control register1
// ( (unsigned int)((TIM16_CR1 >> 0) & 0xFFFFFFFF), ((TIM16_CR1 = (TIM16_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CR1_CEN
// - SFDITEM_FIELD__TIM16_CR1_UDIS
// - SFDITEM_FIELD__TIM16_CR1_URS
// - SFDITEM_FIELD__TIM16_CR1_OPM
// - SFDITEM_FIELD__TIM16_CR1_ARPE
// - SFDITEM_FIELD__TIM16_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM16_CR2 --------------------------------
// SVD Line: 8090
unsigned int TIM16_CR2 __AT (0x40014404);
// ------------------------------- Field Item: TIM16_CR2_CCPC -----------------------------------
// SVD Line: 8096
// - SFDITEM_FIELD__TIM16_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40014404) Capture/compare preloaded control
//
// ( (unsigned int) TIM16_CR2 )
// CCPC
//
//
//
// ------------------------------- Field Item: TIM16_CR2_CCDS -----------------------------------
// SVD Line: 8101
// - SFDITEM_FIELD__TIM16_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40014404) Capture/compare DMA selection
//
// ( (unsigned int) TIM16_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS1 -----------------------------------
// SVD Line: 8106
// - SFDITEM_FIELD__TIM16_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40014404) Output Idle state 1
//
// ( (unsigned int) TIM16_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS1N ----------------------------------
// SVD Line: 8111
// - SFDITEM_FIELD__TIM16_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40014404) Output Idle state 1
//
// ( (unsigned int) TIM16_CR2 )
// OIS1N
//
//
//
// -------------------------------- Register RTree: TIM16_CR2 -----------------------------------
// SVD Line: 8090
// SFDITEM_REG__TIM16_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40014404) control register 2
// ( (unsigned int)((TIM16_CR2 >> 0) & 0xFFFFFFFF), ((TIM16_CR2 = (TIM16_CR2 & ~(0x309UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x309) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CR2_CCPC
// - SFDITEM_FIELD__TIM16_CR2_CCDS
// - SFDITEM_FIELD__TIM16_CR2_OIS1
// - SFDITEM_FIELD__TIM16_CR2_OIS1N
//
//
// ---------------------------- Register Item Address: TIM16_DIER -------------------------------
// SVD Line: 8118
unsigned int TIM16_DIER __AT (0x4001440C);
// ------------------------------- Field Item: TIM16_DIER_UIE -----------------------------------
// SVD Line: 8124
// - SFDITEM_FIELD__TIM16_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4001440C) Update interrupt enable
//
// ( (unsigned int) TIM16_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC1IE ----------------------------------
// SVD Line: 8129
// - SFDITEM_FIELD__TIM16_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4001440C) Capture/Compare 1 interrupt enable
//
// ( (unsigned int) TIM16_DIER )
// CC1IE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_COMIE ----------------------------------
// SVD Line: 8134
// - SFDITEM_FIELD__TIM16_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4001440C) Com interrupt enable
//
// ( (unsigned int) TIM16_DIER )
// COMIE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_BIE -----------------------------------
// SVD Line: 8139
// - SFDITEM_FIELD__TIM16_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4001440C) Break interrupt enable
//
// ( (unsigned int) TIM16_DIER )
// BIE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_UDE -----------------------------------
// SVD Line: 8144
// - SFDITEM_FIELD__TIM16_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4001440C) Update DMA request enable
//
// ( (unsigned int) TIM16_DIER )
// UDE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC1DE ----------------------------------
// SVD Line: 8149
// - SFDITEM_FIELD__TIM16_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4001440C) Compare/capture DMA requeset enable
//
// ( (unsigned int) TIM16_DIER )
// CC1DE
//
//
//
// ------------------------------- Register RTree: TIM16_DIER -----------------------------------
// SVD Line: 8118
// SFDITEM_REG__TIM16_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4001440C) DMA/Interrupt enable register
// ( (unsigned int)((TIM16_DIER >> 0) & 0xFFFFFFFF), ((TIM16_DIER = (TIM16_DIER & ~(0x3A3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3A3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DIER_UIE
// - SFDITEM_FIELD__TIM16_DIER_CC1IE
// - SFDITEM_FIELD__TIM16_DIER_COMIE
// - SFDITEM_FIELD__TIM16_DIER_BIE
// - SFDITEM_FIELD__TIM16_DIER_UDE
// - SFDITEM_FIELD__TIM16_DIER_CC1DE
//
//
// ----------------------------- Register Item Address: TIM16_SR --------------------------------
// SVD Line: 8156
unsigned int TIM16_SR __AT (0x40014410);
// -------------------------------- Field Item: TIM16_SR_UIF ------------------------------------
// SVD Line: 8162
// - SFDITEM_FIELD__TIM16_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40014410) Update interrupt flag
//
// ( (unsigned int) TIM16_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC1IF -----------------------------------
// SVD Line: 8167
// - SFDITEM_FIELD__TIM16_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40014410) Capture/Compare 1 interrupt flag
//
// ( (unsigned int) TIM16_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_COMIF -----------------------------------
// SVD Line: 8172
// - SFDITEM_FIELD__TIM16_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40014410) Com interrupt flag
//
// ( (unsigned int) TIM16_SR )
// COMIF
//
//
//
// -------------------------------- Field Item: TIM16_SR_BIF ------------------------------------
// SVD Line: 8177
// - SFDITEM_FIELD__TIM16_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40014410) Break interrupt flag
//
// ( (unsigned int) TIM16_SR )
// BIF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC1OF -----------------------------------
// SVD Line: 8182
// - SFDITEM_FIELD__TIM16_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40014410) Update interrupt flag
//
// ( (unsigned int) TIM16_SR )
// CC1OF
//
//
//
// -------------------------------- Register RTree: TIM16_SR ------------------------------------
// SVD Line: 8156
// SFDITEM_REG__TIM16_SR
// SR
//
// [Bits 31..0] RW (@ 0x40014410) status register
// ( (unsigned int)((TIM16_SR >> 0) & 0xFFFFFFFF), ((TIM16_SR = (TIM16_SR & ~(0x2A3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2A3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_SR_UIF
// - SFDITEM_FIELD__TIM16_SR_CC1IF
// - SFDITEM_FIELD__TIM16_SR_COMIF
// - SFDITEM_FIELD__TIM16_SR_BIF
// - SFDITEM_FIELD__TIM16_SR_CC1OF
//
//
// ---------------------------- Register Item Address: TIM16_EGR --------------------------------
// SVD Line: 8189
unsigned int TIM16_EGR __AT (0x40014414);
// -------------------------------- Field Item: TIM16_EGR_UG ------------------------------------
// SVD Line: 8196
// - SFDITEM_FIELD__TIM16_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40014414) Update generation
//
// ( (unsigned int) TIM16_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM16_EGR_CC1G -----------------------------------
// SVD Line: 8201
// - SFDITEM_FIELD__TIM16_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40014414) Capture/Compare 1 generation
//
// ( (unsigned int) TIM16_EGR )
// CC1G
//
//
//
// ------------------------------- Field Item: TIM16_EGR_COMG -----------------------------------
// SVD Line: 8206
// - SFDITEM_FIELD__TIM16_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40014414) COM evnet generation
//
// ( (unsigned int) TIM16_EGR )
// COMG
//
//
//
// -------------------------------- Field Item: TIM16_EGR_BG ------------------------------------
// SVD Line: 8211
// - SFDITEM_FIELD__TIM16_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40014414) Break event generation
//
// ( (unsigned int) TIM16_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM16_EGR -----------------------------------
// SVD Line: 8189
// SFDITEM_REG__TIM16_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40014414) event generation register
// ( (unsigned int)((TIM16_EGR >> 0) & 0xFFFFFFFF), ((TIM16_EGR = (TIM16_EGR & ~(0xA3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_EGR_UG
// - SFDITEM_FIELD__TIM16_EGR_CC1G
// - SFDITEM_FIELD__TIM16_EGR_COMG
// - SFDITEM_FIELD__TIM16_EGR_BG
//
//
// ------------------------ Register Item Address: TIM16_CCMR1_Output ---------------------------
// SVD Line: 8218
unsigned int TIM16_CCMR1_Output __AT (0x40014418);
// --------------------------- Field Item: TIM16_CCMR1_Output_CC1S ------------------------------
// SVD Line: 8224
// - SFDITEM_FIELD__TIM16_CCMR1_Output_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014418) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM16_CCMR1_Output >> 0) & 0x3), ((TIM16_CCMR1_Output = (TIM16_CCMR1_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_Output_OC1FE ------------------------------
// SVD Line: 8229
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40014418) Output Compare 1 fast enable
//
// ( (unsigned int) TIM16_CCMR1_Output )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_Output_OC1PE ------------------------------
// SVD Line: 8234
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40014418) Output Compare 1 preload enable
//
// ( (unsigned int) TIM16_CCMR1_Output )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_Output_OC1M ------------------------------
// SVD Line: 8239
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40014418) Output Compare 1 mode
//
// ( (unsigned char)((TIM16_CCMR1_Output >> 4) & 0x7), ((TIM16_CCMR1_Output = (TIM16_CCMR1_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM16_CCMR1_Output -------------------------------
// SVD Line: 8218
// SFDITEM_REG__TIM16_CCMR1_Output
// CCMR1_Output
//
// [Bits 31..0] RW (@ 0x40014418) capture/compare mode register (outputmode)
// ( (unsigned int)((TIM16_CCMR1_Output >> 0) & 0xFFFFFFFF), ((TIM16_CCMR1_Output = (TIM16_CCMR1_Output & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCMR1_Output_CC1S
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1FE
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1PE
// - SFDITEM_FIELD__TIM16_CCMR1_Output_OC1M
//
//
// ------------------------ Register Item Address: TIM16_CCMR1_Input ----------------------------
// SVD Line: 8246
unsigned int TIM16_CCMR1_Input __AT (0x40014418);
// --------------------------- Field Item: TIM16_CCMR1_Input_CC1S -------------------------------
// SVD Line: 8253
// - SFDITEM_FIELD__TIM16_CCMR1_Input_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014418) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM16_CCMR1_Input >> 0) & 0x3), ((TIM16_CCMR1_Input = (TIM16_CCMR1_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_Input_IC1PSC ------------------------------
// SVD Line: 8258
// - SFDITEM_FIELD__TIM16_CCMR1_Input_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40014418) Input capture 1 prescaler
//
// ( (unsigned char)((TIM16_CCMR1_Input >> 2) & 0x3), ((TIM16_CCMR1_Input = (TIM16_CCMR1_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_Input_IC1F -------------------------------
// SVD Line: 8263
// - SFDITEM_FIELD__TIM16_CCMR1_Input_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40014418) Input capture 1 filter
//
// ( (unsigned char)((TIM16_CCMR1_Input >> 4) & 0xF), ((TIM16_CCMR1_Input = (TIM16_CCMR1_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM16_CCMR1_Input -------------------------------
// SVD Line: 8246
// SFDITEM_REG__TIM16_CCMR1_Input
// CCMR1_Input
//
// [Bits 31..0] RW (@ 0x40014418) capture/compare mode register 1 (inputmode)
// ( (unsigned int)((TIM16_CCMR1_Input >> 0) & 0xFFFFFFFF), ((TIM16_CCMR1_Input = (TIM16_CCMR1_Input & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCMR1_Input_CC1S
// - SFDITEM_FIELD__TIM16_CCMR1_Input_IC1PSC
// - SFDITEM_FIELD__TIM16_CCMR1_Input_IC1F
//
//
// ---------------------------- Register Item Address: TIM16_CCER -------------------------------
// SVD Line: 8270
unsigned int TIM16_CCER __AT (0x40014420);
// ------------------------------- Field Item: TIM16_CCER_CC1E ----------------------------------
// SVD Line: 8276
// - SFDITEM_FIELD__TIM16_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40014420) Capture/Compare 1 output enable
//
// ( (unsigned int) TIM16_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC1P ----------------------------------
// SVD Line: 8281
// - SFDITEM_FIELD__TIM16_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40014420) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM16_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC1NE ----------------------------------
// SVD Line: 8286
// - SFDITEM_FIELD__TIM16_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40014420) Capture/Compare 1 complementary output enable
//
// ( (unsigned int) TIM16_CCER )
// CC1NE
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC1NP ----------------------------------
// SVD Line: 8291
// - SFDITEM_FIELD__TIM16_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40014420) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM16_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM16_CCER -----------------------------------
// SVD Line: 8270
// SFDITEM_REG__TIM16_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40014420) capture/compare enableregister
// ( (unsigned int)((TIM16_CCER >> 0) & 0xFFFFFFFF), ((TIM16_CCER = (TIM16_CCER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCER_CC1E
// - SFDITEM_FIELD__TIM16_CCER_CC1P
// - SFDITEM_FIELD__TIM16_CCER_CC1NE
// - SFDITEM_FIELD__TIM16_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM16_CNT --------------------------------
// SVD Line: 8298
unsigned int TIM16_CNT __AT (0x40014424);
// -------------------------------- Field Item: TIM16_CNT_CNT -----------------------------------
// SVD Line: 8304
// - SFDITEM_FIELD__TIM16_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40014424) counter value
//
// ( (unsigned short)((TIM16_CNT >> 0) & 0xFFFF), ((TIM16_CNT = (TIM16_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_CNT -----------------------------------
// SVD Line: 8298
// SFDITEM_REG__TIM16_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40014424) counter
// ( (unsigned int)((TIM16_CNT >> 0) & 0xFFFFFFFF), ((TIM16_CNT = (TIM16_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM16_PSC --------------------------------
// SVD Line: 8311
unsigned int TIM16_PSC __AT (0x40014428);
// -------------------------------- Field Item: TIM16_PSC_PSC -----------------------------------
// SVD Line: 8317
// - SFDITEM_FIELD__TIM16_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40014428) Prescaler value
//
// ( (unsigned short)((TIM16_PSC >> 0) & 0xFFFF), ((TIM16_PSC = (TIM16_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_PSC -----------------------------------
// SVD Line: 8311
// SFDITEM_REG__TIM16_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40014428) prescaler
// ( (unsigned int)((TIM16_PSC >> 0) & 0xFFFFFFFF), ((TIM16_PSC = (TIM16_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM16_ARR --------------------------------
// SVD Line: 8324
unsigned int TIM16_ARR __AT (0x4001442C);
// -------------------------------- Field Item: TIM16_ARR_ARR -----------------------------------
// SVD Line: 8330
// - SFDITEM_FIELD__TIM16_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4001442C) Auto-reload value
//
// ( (unsigned short)((TIM16_ARR >> 0) & 0xFFFF), ((TIM16_ARR = (TIM16_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_ARR -----------------------------------
// SVD Line: 8324
// SFDITEM_REG__TIM16_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4001442C) auto-reload register
// ( (unsigned int)((TIM16_ARR >> 0) & 0xFFFFFFFF), ((TIM16_ARR = (TIM16_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM16_RCR --------------------------------
// SVD Line: 8337
unsigned int TIM16_RCR __AT (0x40014430);
// -------------------------------- Field Item: TIM16_RCR_REP -----------------------------------
// SVD Line: 8343
// - SFDITEM_FIELD__TIM16_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40014430) Repetition counter value
//
// ( (unsigned char)((TIM16_RCR >> 0) & 0xFF), ((TIM16_RCR = (TIM16_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_RCR -----------------------------------
// SVD Line: 8337
// SFDITEM_REG__TIM16_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40014430) repetition counter register
// ( (unsigned int)((TIM16_RCR >> 0) & 0xFFFFFFFF), ((TIM16_RCR = (TIM16_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM16_CCR1 -------------------------------
// SVD Line: 8350
unsigned int TIM16_CCR1 __AT (0x40014434);
// ------------------------------- Field Item: TIM16_CCR1_CCR1 ----------------------------------
// SVD Line: 8356
// - SFDITEM_FIELD__TIM16_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40014434) Capture/Compare 1 value
//
// ( (unsigned short)((TIM16_CCR1 >> 0) & 0xFFFF), ((TIM16_CCR1 = (TIM16_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM16_CCR1 -----------------------------------
// SVD Line: 8350
// SFDITEM_REG__TIM16_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40014434) capture/compare register 1
// ( (unsigned int)((TIM16_CCR1 >> 0) & 0xFFFFFFFF), ((TIM16_CCR1 = (TIM16_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM16_BDTR -------------------------------
// SVD Line: 8363
unsigned int TIM16_BDTR __AT (0x40014444);
// ------------------------------- Field Item: TIM16_BDTR_DTG -----------------------------------
// SVD Line: 8369
// - SFDITEM_FIELD__TIM16_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40014444) Dead-time generator setup
//
// ( (unsigned char)((TIM16_BDTR >> 0) & 0xFF), ((TIM16_BDTR = (TIM16_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_LOCK ----------------------------------
// SVD Line: 8374
// - SFDITEM_FIELD__TIM16_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40014444) Lock configuration
//
// ( (unsigned char)((TIM16_BDTR >> 8) & 0x3), ((TIM16_BDTR = (TIM16_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_OSSI ----------------------------------
// SVD Line: 8379
// - SFDITEM_FIELD__TIM16_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40014444) Off-state selection for Idle mode
//
// ( (unsigned int) TIM16_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_OSSR ----------------------------------
// SVD Line: 8384
// - SFDITEM_FIELD__TIM16_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40014444) Off-state selection for Run mode
//
// ( (unsigned int) TIM16_BDTR )
// OSSR
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_BKE -----------------------------------
// SVD Line: 8389
// - SFDITEM_FIELD__TIM16_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40014444) Break enable
//
// ( (unsigned int) TIM16_BDTR )
// BKE
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_BKP -----------------------------------
// SVD Line: 8394
// - SFDITEM_FIELD__TIM16_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40014444) Break polarity
//
// ( (unsigned int) TIM16_BDTR )
// BKP
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_AOE -----------------------------------
// SVD Line: 8399
// - SFDITEM_FIELD__TIM16_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40014444) Automatic output enable
//
// ( (unsigned int) TIM16_BDTR )
// AOE
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_MOE -----------------------------------
// SVD Line: 8404
// - SFDITEM_FIELD__TIM16_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40014444) Main output enable
//
// ( (unsigned int) TIM16_BDTR )
// MOE
//
//
//
// ------------------------------- Register RTree: TIM16_BDTR -----------------------------------
// SVD Line: 8363
// SFDITEM_REG__TIM16_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40014444) break and dead-time register
// ( (unsigned int)((TIM16_BDTR >> 0) & 0xFFFFFFFF), ((TIM16_BDTR = (TIM16_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_BDTR_DTG
// - SFDITEM_FIELD__TIM16_BDTR_LOCK
// - SFDITEM_FIELD__TIM16_BDTR_OSSI
// - SFDITEM_FIELD__TIM16_BDTR_OSSR
// - SFDITEM_FIELD__TIM16_BDTR_BKE
// - SFDITEM_FIELD__TIM16_BDTR_BKP
// - SFDITEM_FIELD__TIM16_BDTR_AOE
// - SFDITEM_FIELD__TIM16_BDTR_MOE
//
//
// ---------------------------- Register Item Address: TIM16_DCR --------------------------------
// SVD Line: 8411
unsigned int TIM16_DCR __AT (0x40014448);
// -------------------------------- Field Item: TIM16_DCR_DBA -----------------------------------
// SVD Line: 8417
// - SFDITEM_FIELD__TIM16_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40014448) DMA base address
//
// ( (unsigned char)((TIM16_DCR >> 0) & 0x1F), ((TIM16_DCR = (TIM16_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM16_DCR_DBL -----------------------------------
// SVD Line: 8422
// - SFDITEM_FIELD__TIM16_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40014448) DMA burst length
//
// ( (unsigned char)((TIM16_DCR >> 8) & 0x1F), ((TIM16_DCR = (TIM16_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_DCR -----------------------------------
// SVD Line: 8411
// SFDITEM_REG__TIM16_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40014448) DMA control register
// ( (unsigned int)((TIM16_DCR >> 0) & 0xFFFFFFFF), ((TIM16_DCR = (TIM16_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DCR_DBA
// - SFDITEM_FIELD__TIM16_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM16_DMAR -------------------------------
// SVD Line: 8429
unsigned int TIM16_DMAR __AT (0x4001444C);
// ------------------------------- Field Item: TIM16_DMAR_DMAB ----------------------------------
// SVD Line: 8435
// - SFDITEM_FIELD__TIM16_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x4001444C) DMA register for burst accesses
//
// ( (unsigned int)((TIM16_DMAR >> 0) & 0xFFFFFFFF), ((TIM16_DMAR = (TIM16_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM16_DMAR -----------------------------------
// SVD Line: 8429
// SFDITEM_REG__TIM16_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x4001444C) DMA address for full transfer
// ( (unsigned int)((TIM16_DMAR >> 0) & 0xFFFFFFFF), ((TIM16_DMAR = (TIM16_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DMAR_DMAB
//
//
// --------------------------------- Peripheral View: TIM16 -------------------------------------
// SVD Line: 8036
// TIM16
// TIM16
// - SFDITEM_REG__TIM16_CR1
// - SFDITEM_REG__TIM16_CR2
// - SFDITEM_REG__TIM16_DIER
// - SFDITEM_REG__TIM16_SR
// - SFDITEM_REG__TIM16_EGR
// - SFDITEM_REG__TIM16_CCMR1_Output
// - SFDITEM_REG__TIM16_CCMR1_Input
// - SFDITEM_REG__TIM16_CCER
// - SFDITEM_REG__TIM16_CNT
// - SFDITEM_REG__TIM16_PSC
// - SFDITEM_REG__TIM16_ARR
// - SFDITEM_REG__TIM16_RCR
// - SFDITEM_REG__TIM16_CCR1
// - SFDITEM_REG__TIM16_BDTR
// - SFDITEM_REG__TIM16_DCR
// - SFDITEM_REG__TIM16_DMAR
//
//
// ---------------------------- Register Item Address: TIM17_CR1 --------------------------------
// SVD Line: 8052
unsigned int TIM17_CR1 __AT (0x40014800);
// -------------------------------- Field Item: TIM17_CR1_CEN -----------------------------------
// SVD Line: 8058
// - SFDITEM_FIELD__TIM17_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40014800) Counter enable
//
// ( (unsigned int) TIM17_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM17_CR1_UDIS -----------------------------------
// SVD Line: 8063
// - SFDITEM_FIELD__TIM17_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40014800) Update disable
//
// ( (unsigned int) TIM17_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM17_CR1_URS -----------------------------------
// SVD Line: 8068
// - SFDITEM_FIELD__TIM17_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40014800) Update request source
//
// ( (unsigned int) TIM17_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM17_CR1_OPM -----------------------------------
// SVD Line: 8073
// - SFDITEM_FIELD__TIM17_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40014800) One pulse mode
//
// ( (unsigned int) TIM17_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM17_CR1_ARPE -----------------------------------
// SVD Line: 8078
// - SFDITEM_FIELD__TIM17_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40014800) Auto-reload preload enable
//
// ( (unsigned int) TIM17_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM17_CR1_CKD -----------------------------------
// SVD Line: 8083
// - SFDITEM_FIELD__TIM17_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40014800) Prescaler factor
//
// ( (unsigned char)((TIM17_CR1 >> 8) & 0x3), ((TIM17_CR1 = (TIM17_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_CR1 -----------------------------------
// SVD Line: 8052
// SFDITEM_REG__TIM17_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40014800) TIM16 control register1
// ( (unsigned int)((TIM17_CR1 >> 0) & 0xFFFFFFFF), ((TIM17_CR1 = (TIM17_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CR1_CEN
// - SFDITEM_FIELD__TIM17_CR1_UDIS
// - SFDITEM_FIELD__TIM17_CR1_URS
// - SFDITEM_FIELD__TIM17_CR1_OPM
// - SFDITEM_FIELD__TIM17_CR1_ARPE
// - SFDITEM_FIELD__TIM17_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM17_CR2 --------------------------------
// SVD Line: 8090
unsigned int TIM17_CR2 __AT (0x40014804);
// ------------------------------- Field Item: TIM17_CR2_CCPC -----------------------------------
// SVD Line: 8096
// - SFDITEM_FIELD__TIM17_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40014804) Capture/compare preloaded control
//
// ( (unsigned int) TIM17_CR2 )
// CCPC
//
//
//
// ------------------------------- Field Item: TIM17_CR2_CCDS -----------------------------------
// SVD Line: 8101
// - SFDITEM_FIELD__TIM17_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40014804) Capture/compare DMA selection
//
// ( (unsigned int) TIM17_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS1 -----------------------------------
// SVD Line: 8106
// - SFDITEM_FIELD__TIM17_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40014804) Output Idle state 1
//
// ( (unsigned int) TIM17_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS1N ----------------------------------
// SVD Line: 8111
// - SFDITEM_FIELD__TIM17_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40014804) Output Idle state 1
//
// ( (unsigned int) TIM17_CR2 )
// OIS1N
//
//
//
// -------------------------------- Register RTree: TIM17_CR2 -----------------------------------
// SVD Line: 8090
// SFDITEM_REG__TIM17_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40014804) control register 2
// ( (unsigned int)((TIM17_CR2 >> 0) & 0xFFFFFFFF), ((TIM17_CR2 = (TIM17_CR2 & ~(0x309UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x309) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CR2_CCPC
// - SFDITEM_FIELD__TIM17_CR2_CCDS
// - SFDITEM_FIELD__TIM17_CR2_OIS1
// - SFDITEM_FIELD__TIM17_CR2_OIS1N
//
//
// ---------------------------- Register Item Address: TIM17_DIER -------------------------------
// SVD Line: 8118
unsigned int TIM17_DIER __AT (0x4001480C);
// ------------------------------- Field Item: TIM17_DIER_UIE -----------------------------------
// SVD Line: 8124
// - SFDITEM_FIELD__TIM17_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4001480C) Update interrupt enable
//
// ( (unsigned int) TIM17_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC1IE ----------------------------------
// SVD Line: 8129
// - SFDITEM_FIELD__TIM17_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4001480C) Capture/Compare 1 interrupt enable
//
// ( (unsigned int) TIM17_DIER )
// CC1IE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_COMIE ----------------------------------
// SVD Line: 8134
// - SFDITEM_FIELD__TIM17_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4001480C) Com interrupt enable
//
// ( (unsigned int) TIM17_DIER )
// COMIE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_BIE -----------------------------------
// SVD Line: 8139
// - SFDITEM_FIELD__TIM17_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4001480C) Break interrupt enable
//
// ( (unsigned int) TIM17_DIER )
// BIE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_UDE -----------------------------------
// SVD Line: 8144
// - SFDITEM_FIELD__TIM17_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4001480C) Update DMA request enable
//
// ( (unsigned int) TIM17_DIER )
// UDE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC1DE ----------------------------------
// SVD Line: 8149
// - SFDITEM_FIELD__TIM17_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4001480C) Compare/capture DMA requeset enable
//
// ( (unsigned int) TIM17_DIER )
// CC1DE
//
//
//
// ------------------------------- Register RTree: TIM17_DIER -----------------------------------
// SVD Line: 8118
// SFDITEM_REG__TIM17_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4001480C) DMA/Interrupt enable register
// ( (unsigned int)((TIM17_DIER >> 0) & 0xFFFFFFFF), ((TIM17_DIER = (TIM17_DIER & ~(0x3A3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3A3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DIER_UIE
// - SFDITEM_FIELD__TIM17_DIER_CC1IE
// - SFDITEM_FIELD__TIM17_DIER_COMIE
// - SFDITEM_FIELD__TIM17_DIER_BIE
// - SFDITEM_FIELD__TIM17_DIER_UDE
// - SFDITEM_FIELD__TIM17_DIER_CC1DE
//
//
// ----------------------------- Register Item Address: TIM17_SR --------------------------------
// SVD Line: 8156
unsigned int TIM17_SR __AT (0x40014810);
// -------------------------------- Field Item: TIM17_SR_UIF ------------------------------------
// SVD Line: 8162
// - SFDITEM_FIELD__TIM17_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40014810) Update interrupt flag
//
// ( (unsigned int) TIM17_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC1IF -----------------------------------
// SVD Line: 8167
// - SFDITEM_FIELD__TIM17_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40014810) Capture/Compare 1 interrupt flag
//
// ( (unsigned int) TIM17_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_COMIF -----------------------------------
// SVD Line: 8172
// - SFDITEM_FIELD__TIM17_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40014810) Com interrupt flag
//
// ( (unsigned int) TIM17_SR )
// COMIF
//
//
//
// -------------------------------- Field Item: TIM17_SR_BIF ------------------------------------
// SVD Line: 8177
// - SFDITEM_FIELD__TIM17_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40014810) Break interrupt flag
//
// ( (unsigned int) TIM17_SR )
// BIF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC1OF -----------------------------------
// SVD Line: 8182
// - SFDITEM_FIELD__TIM17_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40014810) Update interrupt flag
//
// ( (unsigned int) TIM17_SR )
// CC1OF
//
//
//
// -------------------------------- Register RTree: TIM17_SR ------------------------------------
// SVD Line: 8156
// SFDITEM_REG__TIM17_SR
// SR
//
// [Bits 31..0] RW (@ 0x40014810) status register
// ( (unsigned int)((TIM17_SR >> 0) & 0xFFFFFFFF), ((TIM17_SR = (TIM17_SR & ~(0x2A3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2A3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_SR_UIF
// - SFDITEM_FIELD__TIM17_SR_CC1IF
// - SFDITEM_FIELD__TIM17_SR_COMIF
// - SFDITEM_FIELD__TIM17_SR_BIF
// - SFDITEM_FIELD__TIM17_SR_CC1OF
//
//
// ---------------------------- Register Item Address: TIM17_EGR --------------------------------
// SVD Line: 8189
unsigned int TIM17_EGR __AT (0x40014814);
// -------------------------------- Field Item: TIM17_EGR_UG ------------------------------------
// SVD Line: 8196
// - SFDITEM_FIELD__TIM17_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40014814) Update generation
//
// ( (unsigned int) TIM17_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM17_EGR_CC1G -----------------------------------
// SVD Line: 8201
// - SFDITEM_FIELD__TIM17_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40014814) Capture/Compare 1 generation
//
// ( (unsigned int) TIM17_EGR )
// CC1G
//
//
//
// ------------------------------- Field Item: TIM17_EGR_COMG -----------------------------------
// SVD Line: 8206
// - SFDITEM_FIELD__TIM17_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40014814) COM evnet generation
//
// ( (unsigned int) TIM17_EGR )
// COMG
//
//
//
// -------------------------------- Field Item: TIM17_EGR_BG ------------------------------------
// SVD Line: 8211
// - SFDITEM_FIELD__TIM17_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40014814) Break event generation
//
// ( (unsigned int) TIM17_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM17_EGR -----------------------------------
// SVD Line: 8189
// SFDITEM_REG__TIM17_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40014814) event generation register
// ( (unsigned int)((TIM17_EGR >> 0) & 0xFFFFFFFF), ((TIM17_EGR = (TIM17_EGR & ~(0xA3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_EGR_UG
// - SFDITEM_FIELD__TIM17_EGR_CC1G
// - SFDITEM_FIELD__TIM17_EGR_COMG
// - SFDITEM_FIELD__TIM17_EGR_BG
//
//
// ------------------------ Register Item Address: TIM17_CCMR1_Output ---------------------------
// SVD Line: 8218
unsigned int TIM17_CCMR1_Output __AT (0x40014818);
// --------------------------- Field Item: TIM17_CCMR1_Output_CC1S ------------------------------
// SVD Line: 8224
// - SFDITEM_FIELD__TIM17_CCMR1_Output_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014818) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM17_CCMR1_Output >> 0) & 0x3), ((TIM17_CCMR1_Output = (TIM17_CCMR1_Output & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_Output_OC1FE ------------------------------
// SVD Line: 8229
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40014818) Output Compare 1 fast enable
//
// ( (unsigned int) TIM17_CCMR1_Output )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_Output_OC1PE ------------------------------
// SVD Line: 8234
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40014818) Output Compare 1 preload enable
//
// ( (unsigned int) TIM17_CCMR1_Output )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_Output_OC1M ------------------------------
// SVD Line: 8239
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40014818) Output Compare 1 mode
//
// ( (unsigned char)((TIM17_CCMR1_Output >> 4) & 0x7), ((TIM17_CCMR1_Output = (TIM17_CCMR1_Output & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM17_CCMR1_Output -------------------------------
// SVD Line: 8218
// SFDITEM_REG__TIM17_CCMR1_Output
// CCMR1_Output
//
// [Bits 31..0] RW (@ 0x40014818) capture/compare mode register (outputmode)
// ( (unsigned int)((TIM17_CCMR1_Output >> 0) & 0xFFFFFFFF), ((TIM17_CCMR1_Output = (TIM17_CCMR1_Output & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCMR1_Output_CC1S
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1FE
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1PE
// - SFDITEM_FIELD__TIM17_CCMR1_Output_OC1M
//
//
// ------------------------ Register Item Address: TIM17_CCMR1_Input ----------------------------
// SVD Line: 8246
unsigned int TIM17_CCMR1_Input __AT (0x40014818);
// --------------------------- Field Item: TIM17_CCMR1_Input_CC1S -------------------------------
// SVD Line: 8253
// - SFDITEM_FIELD__TIM17_CCMR1_Input_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014818) Capture/Compare 1 selection
//
// ( (unsigned char)((TIM17_CCMR1_Input >> 0) & 0x3), ((TIM17_CCMR1_Input = (TIM17_CCMR1_Input & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_Input_IC1PSC ------------------------------
// SVD Line: 8258
// - SFDITEM_FIELD__TIM17_CCMR1_Input_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40014818) Input capture 1 prescaler
//
// ( (unsigned char)((TIM17_CCMR1_Input >> 2) & 0x3), ((TIM17_CCMR1_Input = (TIM17_CCMR1_Input & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_Input_IC1F -------------------------------
// SVD Line: 8263
// - SFDITEM_FIELD__TIM17_CCMR1_Input_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40014818) Input capture 1 filter
//
// ( (unsigned char)((TIM17_CCMR1_Input >> 4) & 0xF), ((TIM17_CCMR1_Input = (TIM17_CCMR1_Input & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM17_CCMR1_Input -------------------------------
// SVD Line: 8246
// SFDITEM_REG__TIM17_CCMR1_Input
// CCMR1_Input
//
// [Bits 31..0] RW (@ 0x40014818) capture/compare mode register 1 (inputmode)
// ( (unsigned int)((TIM17_CCMR1_Input >> 0) & 0xFFFFFFFF), ((TIM17_CCMR1_Input = (TIM17_CCMR1_Input & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCMR1_Input_CC1S
// - SFDITEM_FIELD__TIM17_CCMR1_Input_IC1PSC
// - SFDITEM_FIELD__TIM17_CCMR1_Input_IC1F
//
//
// ---------------------------- Register Item Address: TIM17_CCER -------------------------------
// SVD Line: 8270
unsigned int TIM17_CCER __AT (0x40014820);
// ------------------------------- Field Item: TIM17_CCER_CC1E ----------------------------------
// SVD Line: 8276
// - SFDITEM_FIELD__TIM17_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40014820) Capture/Compare 1 output enable
//
// ( (unsigned int) TIM17_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC1P ----------------------------------
// SVD Line: 8281
// - SFDITEM_FIELD__TIM17_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40014820) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM17_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC1NE ----------------------------------
// SVD Line: 8286
// - SFDITEM_FIELD__TIM17_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40014820) Capture/Compare 1 complementary output enable
//
// ( (unsigned int) TIM17_CCER )
// CC1NE
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC1NP ----------------------------------
// SVD Line: 8291
// - SFDITEM_FIELD__TIM17_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40014820) Capture/Compare 1 output Polarity
//
// ( (unsigned int) TIM17_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM17_CCER -----------------------------------
// SVD Line: 8270
// SFDITEM_REG__TIM17_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40014820) capture/compare enableregister
// ( (unsigned int)((TIM17_CCER >> 0) & 0xFFFFFFFF), ((TIM17_CCER = (TIM17_CCER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCER_CC1E
// - SFDITEM_FIELD__TIM17_CCER_CC1P
// - SFDITEM_FIELD__TIM17_CCER_CC1NE
// - SFDITEM_FIELD__TIM17_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM17_CNT --------------------------------
// SVD Line: 8298
unsigned int TIM17_CNT __AT (0x40014824);
// -------------------------------- Field Item: TIM17_CNT_CNT -----------------------------------
// SVD Line: 8304
// - SFDITEM_FIELD__TIM17_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40014824) counter value
//
// ( (unsigned short)((TIM17_CNT >> 0) & 0xFFFF), ((TIM17_CNT = (TIM17_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_CNT -----------------------------------
// SVD Line: 8298
// SFDITEM_REG__TIM17_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40014824) counter
// ( (unsigned int)((TIM17_CNT >> 0) & 0xFFFFFFFF), ((TIM17_CNT = (TIM17_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM17_PSC --------------------------------
// SVD Line: 8311
unsigned int TIM17_PSC __AT (0x40014828);
// -------------------------------- Field Item: TIM17_PSC_PSC -----------------------------------
// SVD Line: 8317
// - SFDITEM_FIELD__TIM17_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40014828) Prescaler value
//
// ( (unsigned short)((TIM17_PSC >> 0) & 0xFFFF), ((TIM17_PSC = (TIM17_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_PSC -----------------------------------
// SVD Line: 8311
// SFDITEM_REG__TIM17_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40014828) prescaler
// ( (unsigned int)((TIM17_PSC >> 0) & 0xFFFFFFFF), ((TIM17_PSC = (TIM17_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM17_ARR --------------------------------
// SVD Line: 8324
unsigned int TIM17_ARR __AT (0x4001482C);
// -------------------------------- Field Item: TIM17_ARR_ARR -----------------------------------
// SVD Line: 8330
// - SFDITEM_FIELD__TIM17_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4001482C) Auto-reload value
//
// ( (unsigned short)((TIM17_ARR >> 0) & 0xFFFF), ((TIM17_ARR = (TIM17_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_ARR -----------------------------------
// SVD Line: 8324
// SFDITEM_REG__TIM17_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4001482C) auto-reload register
// ( (unsigned int)((TIM17_ARR >> 0) & 0xFFFFFFFF), ((TIM17_ARR = (TIM17_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM17_RCR --------------------------------
// SVD Line: 8337
unsigned int TIM17_RCR __AT (0x40014830);
// -------------------------------- Field Item: TIM17_RCR_REP -----------------------------------
// SVD Line: 8343
// - SFDITEM_FIELD__TIM17_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40014830) Repetition counter value
//
// ( (unsigned char)((TIM17_RCR >> 0) & 0xFF), ((TIM17_RCR = (TIM17_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_RCR -----------------------------------
// SVD Line: 8337
// SFDITEM_REG__TIM17_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40014830) repetition counter register
// ( (unsigned int)((TIM17_RCR >> 0) & 0xFFFFFFFF), ((TIM17_RCR = (TIM17_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM17_CCR1 -------------------------------
// SVD Line: 8350
unsigned int TIM17_CCR1 __AT (0x40014834);
// ------------------------------- Field Item: TIM17_CCR1_CCR1 ----------------------------------
// SVD Line: 8356
// - SFDITEM_FIELD__TIM17_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40014834) Capture/Compare 1 value
//
// ( (unsigned short)((TIM17_CCR1 >> 0) & 0xFFFF), ((TIM17_CCR1 = (TIM17_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM17_CCR1 -----------------------------------
// SVD Line: 8350
// SFDITEM_REG__TIM17_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40014834) capture/compare register 1
// ( (unsigned int)((TIM17_CCR1 >> 0) & 0xFFFFFFFF), ((TIM17_CCR1 = (TIM17_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM17_BDTR -------------------------------
// SVD Line: 8363
unsigned int TIM17_BDTR __AT (0x40014844);
// ------------------------------- Field Item: TIM17_BDTR_DTG -----------------------------------
// SVD Line: 8369
// - SFDITEM_FIELD__TIM17_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40014844) Dead-time generator setup
//
// ( (unsigned char)((TIM17_BDTR >> 0) & 0xFF), ((TIM17_BDTR = (TIM17_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_LOCK ----------------------------------
// SVD Line: 8374
// - SFDITEM_FIELD__TIM17_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40014844) Lock configuration
//
// ( (unsigned char)((TIM17_BDTR >> 8) & 0x3), ((TIM17_BDTR = (TIM17_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_OSSI ----------------------------------
// SVD Line: 8379
// - SFDITEM_FIELD__TIM17_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40014844) Off-state selection for Idle mode
//
// ( (unsigned int) TIM17_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_OSSR ----------------------------------
// SVD Line: 8384
// - SFDITEM_FIELD__TIM17_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40014844) Off-state selection for Run mode
//
// ( (unsigned int) TIM17_BDTR )
// OSSR
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_BKE -----------------------------------
// SVD Line: 8389
// - SFDITEM_FIELD__TIM17_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40014844) Break enable
//
// ( (unsigned int) TIM17_BDTR )
// BKE
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_BKP -----------------------------------
// SVD Line: 8394
// - SFDITEM_FIELD__TIM17_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40014844) Break polarity
//
// ( (unsigned int) TIM17_BDTR )
// BKP
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_AOE -----------------------------------
// SVD Line: 8399
// - SFDITEM_FIELD__TIM17_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40014844) Automatic output enable
//
// ( (unsigned int) TIM17_BDTR )
// AOE
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_MOE -----------------------------------
// SVD Line: 8404
// - SFDITEM_FIELD__TIM17_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40014844) Main output enable
//
// ( (unsigned int) TIM17_BDTR )
// MOE
//
//
//
// ------------------------------- Register RTree: TIM17_BDTR -----------------------------------
// SVD Line: 8363
// SFDITEM_REG__TIM17_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40014844) break and dead-time register
// ( (unsigned int)((TIM17_BDTR >> 0) & 0xFFFFFFFF), ((TIM17_BDTR = (TIM17_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_BDTR_DTG
// - SFDITEM_FIELD__TIM17_BDTR_LOCK
// - SFDITEM_FIELD__TIM17_BDTR_OSSI
// - SFDITEM_FIELD__TIM17_BDTR_OSSR
// - SFDITEM_FIELD__TIM17_BDTR_BKE
// - SFDITEM_FIELD__TIM17_BDTR_BKP
// - SFDITEM_FIELD__TIM17_BDTR_AOE
// - SFDITEM_FIELD__TIM17_BDTR_MOE
//
//
// ---------------------------- Register Item Address: TIM17_DCR --------------------------------
// SVD Line: 8411
unsigned int TIM17_DCR __AT (0x40014848);
// -------------------------------- Field Item: TIM17_DCR_DBA -----------------------------------
// SVD Line: 8417
// - SFDITEM_FIELD__TIM17_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40014848) DMA base address
//
// ( (unsigned char)((TIM17_DCR >> 0) & 0x1F), ((TIM17_DCR = (TIM17_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM17_DCR_DBL -----------------------------------
// SVD Line: 8422
// - SFDITEM_FIELD__TIM17_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40014848) DMA burst length
//
// ( (unsigned char)((TIM17_DCR >> 8) & 0x1F), ((TIM17_DCR = (TIM17_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_DCR -----------------------------------
// SVD Line: 8411
// SFDITEM_REG__TIM17_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40014848) DMA control register
// ( (unsigned int)((TIM17_DCR >> 0) & 0xFFFFFFFF), ((TIM17_DCR = (TIM17_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DCR_DBA
// - SFDITEM_FIELD__TIM17_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM17_DMAR -------------------------------
// SVD Line: 8429
unsigned int TIM17_DMAR __AT (0x4001484C);
// ------------------------------- Field Item: TIM17_DMAR_DMAB ----------------------------------
// SVD Line: 8435
// - SFDITEM_FIELD__TIM17_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x4001484C) DMA register for burst accesses
//
// ( (unsigned int)((TIM17_DMAR >> 0) & 0xFFFFFFFF), ((TIM17_DMAR = (TIM17_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM17_DMAR -----------------------------------
// SVD Line: 8429
// SFDITEM_REG__TIM17_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x4001484C) DMA address for full transfer
// ( (unsigned int)((TIM17_DMAR >> 0) & 0xFFFFFFFF), ((TIM17_DMAR = (TIM17_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DMAR_DMAB
//
//
// --------------------------------- Peripheral View: TIM17 -------------------------------------
// SVD Line: 8444
// TIM17
// TIM17
// - SFDITEM_REG__TIM17_CR1
// - SFDITEM_REG__TIM17_CR2
// - SFDITEM_REG__TIM17_DIER
// - SFDITEM_REG__TIM17_SR
// - SFDITEM_REG__TIM17_EGR
// - SFDITEM_REG__TIM17_CCMR1_Output
// - SFDITEM_REG__TIM17_CCMR1_Input
// - SFDITEM_REG__TIM17_CCER
// - SFDITEM_REG__TIM17_CNT
// - SFDITEM_REG__TIM17_PSC
// - SFDITEM_REG__TIM17_ARR
// - SFDITEM_REG__TIM17_RCR
// - SFDITEM_REG__TIM17_CCR1
// - SFDITEM_REG__TIM17_BDTR
// - SFDITEM_REG__TIM17_DCR
// - SFDITEM_REG__TIM17_DMAR
//
//
// ---------------------------- Register Item Address: USART1_SR --------------------------------
// SVD Line: 8469
unsigned int USART1_SR __AT (0x40013800);
// -------------------------------- Field Item: USART1_SR_PE ------------------------------------
// SVD Line: 8476
// - SFDITEM_FIELD__USART1_SR_PE
// PE
//
// [Bit 0] RO (@ 0x40013800) Parity error
//
// ( (unsigned int) USART1_SR )
// PE
//
//
//
// -------------------------------- Field Item: USART1_SR_FE ------------------------------------
// SVD Line: 8482
// - SFDITEM_FIELD__USART1_SR_FE
// FE
//
// [Bit 1] RO (@ 0x40013800) Framing error
//
// ( (unsigned int) USART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: USART1_SR_NE ------------------------------------
// SVD Line: 8488
// - SFDITEM_FIELD__USART1_SR_NE
// NE
//
// [Bit 2] RO (@ 0x40013800) Noise error flag
//
// ( (unsigned int) USART1_SR )
// NE
//
//
//
// -------------------------------- Field Item: USART1_SR_ORE -----------------------------------
// SVD Line: 8494
// - SFDITEM_FIELD__USART1_SR_ORE
// ORE
//
// [Bit 3] RO (@ 0x40013800) Overrun error
//
// ( (unsigned int) USART1_SR )
// ORE
//
//
//
// ------------------------------- Field Item: USART1_SR_IDLE -----------------------------------
// SVD Line: 8500
// - SFDITEM_FIELD__USART1_SR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x40013800) IDLE line detected
//
// ( (unsigned int) USART1_SR )
// IDLE
//
//
//
// ------------------------------- Field Item: USART1_SR_RXNE -----------------------------------
// SVD Line: 8506
// - SFDITEM_FIELD__USART1_SR_RXNE
// RXNE
//
// [Bit 5] RW (@ 0x40013800) Read data register not empty
//
// ( (unsigned int) USART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: USART1_SR_TC ------------------------------------
// SVD Line: 8511
// - SFDITEM_FIELD__USART1_SR_TC
// TC
//
// [Bit 6] RW (@ 0x40013800) Transmission complete
//
// ( (unsigned int) USART1_SR )
// TC
//
//
//
// -------------------------------- Field Item: USART1_SR_TXE -----------------------------------
// SVD Line: 8516
// - SFDITEM_FIELD__USART1_SR_TXE
// TXE
//
// [Bit 7] RO (@ 0x40013800) Transmit data register empty
//
// ( (unsigned int) USART1_SR )
// TXE
//
//
//
// -------------------------------- Field Item: USART1_SR_LBD -----------------------------------
// SVD Line: 8522
// - SFDITEM_FIELD__USART1_SR_LBD
// LBD
//
// [Bit 8] RW (@ 0x40013800) desc LBD
//
// ( (unsigned int) USART1_SR )
// LBD
//
//
//
// -------------------------------- Field Item: USART1_SR_CTS -----------------------------------
// SVD Line: 8527
// - SFDITEM_FIELD__USART1_SR_CTS
// CTS
//
// [Bit 9] RW (@ 0x40013800) CTS flag
//
// ( (unsigned int) USART1_SR )
// CTS
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRF -----------------------------------
// SVD Line: 8532
// - SFDITEM_FIELD__USART1_SR_ABRF
// ABRF
//
// [Bit 10] RO (@ 0x40013800) Automate baudrate detection flag
//
// ( (unsigned int) USART1_SR )
// ABRF
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRE -----------------------------------
// SVD Line: 8538
// - SFDITEM_FIELD__USART1_SR_ABRE
// ABRE
//
// [Bit 11] RO (@ 0x40013800) Automate baudrate detection error flag
//
// ( (unsigned int) USART1_SR )
// ABRE
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRRQ ----------------------------------
// SVD Line: 8544
// - SFDITEM_FIELD__USART1_SR_ABRRQ
// ABRRQ
//
// [Bit 12] WO (@ 0x40013800) Automate baudrate detection requeset
//
// ( (unsigned int) USART1_SR )
// ABRRQ
//
//
//
// -------------------------------- Register RTree: USART1_SR -----------------------------------
// SVD Line: 8469
// SFDITEM_REG__USART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013800) Status register
// ( (unsigned int)((USART1_SR >> 0) & 0xFFFFFFFF), ((USART1_SR = (USART1_SR & ~(0x1360UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1360) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_SR_PE
// - SFDITEM_FIELD__USART1_SR_FE
// - SFDITEM_FIELD__USART1_SR_NE
// - SFDITEM_FIELD__USART1_SR_ORE
// - SFDITEM_FIELD__USART1_SR_IDLE
// - SFDITEM_FIELD__USART1_SR_RXNE
// - SFDITEM_FIELD__USART1_SR_TC
// - SFDITEM_FIELD__USART1_SR_TXE
// - SFDITEM_FIELD__USART1_SR_LBD
// - SFDITEM_FIELD__USART1_SR_CTS
// - SFDITEM_FIELD__USART1_SR_ABRF
// - SFDITEM_FIELD__USART1_SR_ABRE
// - SFDITEM_FIELD__USART1_SR_ABRRQ
//
//
// ---------------------------- Register Item Address: USART1_DR --------------------------------
// SVD Line: 8552
unsigned int USART1_DR __AT (0x40013804);
// -------------------------------- Field Item: USART1_DR_DR ------------------------------------
// SVD Line: 8558
// - SFDITEM_FIELD__USART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40013804) Data value
//
// ( (unsigned short)((USART1_DR >> 0) & 0x1FF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: USART1_DR -----------------------------------
// SVD Line: 8552
// SFDITEM_REG__USART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40013804) Data register
// ( (unsigned int)((USART1_DR >> 0) & 0xFFFFFFFF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_DR_DR
//
//
// ---------------------------- Register Item Address: USART1_BRR -------------------------------
// SVD Line: 8565
unsigned int USART1_BRR __AT (0x40013808);
// --------------------------- Field Item: USART1_BRR_DIV_Fraction ------------------------------
// SVD Line: 8571
// - SFDITEM_FIELD__USART1_BRR_DIV_Fraction
// DIV_Fraction
//
// [Bits 3..0] RW (@ 0x40013808) fraction of USARTDIV
//
// ( (unsigned char)((USART1_BRR >> 0) & 0xF), ((USART1_BRR = (USART1_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: USART1_BRR_DIV_Mantissa ------------------------------
// SVD Line: 8576
// - SFDITEM_FIELD__USART1_BRR_DIV_Mantissa
// DIV_Mantissa
//
// [Bits 15..4] RW (@ 0x40013808) mantissa of USARTDIV
//
// ( (unsigned short)((USART1_BRR >> 4) & 0xFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFUL << 4 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_BRR -----------------------------------
// SVD Line: 8565
// SFDITEM_REG__USART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40013808) Baud rate register
// ( (unsigned int)((USART1_BRR >> 0) & 0xFFFFFFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_BRR_DIV_Fraction
// - SFDITEM_FIELD__USART1_BRR_DIV_Mantissa
//
//
// ---------------------------- Register Item Address: USART1_CR1 -------------------------------
// SVD Line: 8583
unsigned int USART1_CR1 __AT (0x4001380C);
// ------------------------------- Field Item: USART1_CR1_SBK -----------------------------------
// SVD Line: 8589
// - SFDITEM_FIELD__USART1_CR1_SBK
// SBK
//
// [Bit 0] RW (@ 0x4001380C) Send break
//
// ( (unsigned int) USART1_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: USART1_CR1_RWU -----------------------------------
// SVD Line: 8594
// - SFDITEM_FIELD__USART1_CR1_RWU
// RWU
//
// [Bit 1] RW (@ 0x4001380C) Receiver wakeup
//
// ( (unsigned int) USART1_CR1 )
// RWU
//
//
//
// -------------------------------- Field Item: USART1_CR1_RE -----------------------------------
// SVD Line: 8599
// - SFDITEM_FIELD__USART1_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x4001380C) Receiver enable
//
// ( (unsigned int) USART1_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: USART1_CR1_TE -----------------------------------
// SVD Line: 8604
// - SFDITEM_FIELD__USART1_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x4001380C) Transmitter enable
//
// ( (unsigned int) USART1_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: USART1_CR1_IDLEIE ---------------------------------
// SVD Line: 8609
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x4001380C) IDLE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_RXNEIE ---------------------------------
// SVD Line: 8614
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x4001380C) RXNE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_TCIE ----------------------------------
// SVD Line: 8619
// - SFDITEM_FIELD__USART1_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x4001380C) Transmission complete interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_TXEIE ----------------------------------
// SVD Line: 8624
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x4001380C) TXE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_PEIE ----------------------------------
// SVD Line: 8629
// - SFDITEM_FIELD__USART1_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x4001380C) PE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: USART1_CR1_PS -----------------------------------
// SVD Line: 8634
// - SFDITEM_FIELD__USART1_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x4001380C) Parity selection
//
// ( (unsigned int) USART1_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: USART1_CR1_PCE -----------------------------------
// SVD Line: 8639
// - SFDITEM_FIELD__USART1_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x4001380C) Parity control enable
//
// ( (unsigned int) USART1_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: USART1_CR1_WAKE ----------------------------------
// SVD Line: 8644
// - SFDITEM_FIELD__USART1_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x4001380C) Wakeup method
//
// ( (unsigned int) USART1_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: USART1_CR1_M ------------------------------------
// SVD Line: 8649
// - SFDITEM_FIELD__USART1_CR1_M
// M
//
// [Bit 12] RW (@ 0x4001380C) Word length
//
// ( (unsigned int) USART1_CR1 )
// M
//
//
//
// -------------------------------- Field Item: USART1_CR1_UE -----------------------------------
// SVD Line: 8654
// - SFDITEM_FIELD__USART1_CR1_UE
// UE
//
// [Bit 13] RW (@ 0x4001380C) USART enable
//
// ( (unsigned int) USART1_CR1 )
// UE
//
//
//
// ------------------------------- Register RTree: USART1_CR1 -----------------------------------
// SVD Line: 8583
// SFDITEM_REG__USART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x4001380C) Control register 1
// ( (unsigned int)((USART1_CR1 >> 0) & 0xFFFFFFFF), ((USART1_CR1 = (USART1_CR1 & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR1_SBK
// - SFDITEM_FIELD__USART1_CR1_RWU
// - SFDITEM_FIELD__USART1_CR1_RE
// - SFDITEM_FIELD__USART1_CR1_TE
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// - SFDITEM_FIELD__USART1_CR1_TCIE
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// - SFDITEM_FIELD__USART1_CR1_PEIE
// - SFDITEM_FIELD__USART1_CR1_PS
// - SFDITEM_FIELD__USART1_CR1_PCE
// - SFDITEM_FIELD__USART1_CR1_WAKE
// - SFDITEM_FIELD__USART1_CR1_M
// - SFDITEM_FIELD__USART1_CR1_UE
//
//
// ---------------------------- Register Item Address: USART1_CR2 -------------------------------
// SVD Line: 8661
unsigned int USART1_CR2 __AT (0x40013810);
// ------------------------------- Field Item: USART1_CR2_ADD -----------------------------------
// SVD Line: 8667
// - SFDITEM_FIELD__USART1_CR2_ADD
// ADD
//
// [Bits 3..0] RW (@ 0x40013810) Address of the USART node
//
// ( (unsigned char)((USART1_CR2 >> 0) & 0xF), ((USART1_CR2 = (USART1_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART1_CR2_LBDL ----------------------------------
// SVD Line: 8672
// - SFDITEM_FIELD__USART1_CR2_LBDL
// LBDL
//
// [Bit 5] RW (@ 0x40013810) desc LBDL
//
// ( (unsigned int) USART1_CR2 )
// LBDL
//
//
//
// ------------------------------ Field Item: USART1_CR2_LBDIE ----------------------------------
// SVD Line: 8677
// - SFDITEM_FIELD__USART1_CR2_LBDIE
// LBDIE
//
// [Bit 6] RW (@ 0x40013810) desc LBDIE
//
// ( (unsigned int) USART1_CR2 )
// LBDIE
//
//
//
// ------------------------------- Field Item: USART1_CR2_LBCL ----------------------------------
// SVD Line: 8682
// - SFDITEM_FIELD__USART1_CR2_LBCL
// LBCL
//
// [Bit 8] RW (@ 0x40013810) Last bit clock pulse
//
// ( (unsigned int) USART1_CR2 )
// LBCL
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPHA ----------------------------------
// SVD Line: 8687
// - SFDITEM_FIELD__USART1_CR2_CPHA
// CPHA
//
// [Bit 9] RW (@ 0x40013810) Clock phase
//
// ( (unsigned int) USART1_CR2 )
// CPHA
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPOL ----------------------------------
// SVD Line: 8692
// - SFDITEM_FIELD__USART1_CR2_CPOL
// CPOL
//
// [Bit 10] RW (@ 0x40013810) Clock polarity
//
// ( (unsigned int) USART1_CR2 )
// CPOL
//
//
//
// ------------------------------ Field Item: USART1_CR2_CLKEN ----------------------------------
// SVD Line: 8697
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// CLKEN
//
// [Bit 11] RW (@ 0x40013810) Clock enable
//
// ( (unsigned int) USART1_CR2 )
// CLKEN
//
//
//
// ------------------------------- Field Item: USART1_CR2_STOP ----------------------------------
// SVD Line: 8702
// - SFDITEM_FIELD__USART1_CR2_STOP
// STOP
//
// [Bit 13] RW (@ 0x40013810) STOP bits
//
// ( (unsigned int) USART1_CR2 )
// STOP
//
//
//
// ------------------------------- Register RTree: USART1_CR2 -----------------------------------
// SVD Line: 8661
// SFDITEM_REG__USART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013810) Control register 2
// ( (unsigned int)((USART1_CR2 >> 0) & 0xFFFFFFFF), ((USART1_CR2 = (USART1_CR2 & ~(0x2F6FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2F6F) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR2_ADD
// - SFDITEM_FIELD__USART1_CR2_LBDL
// - SFDITEM_FIELD__USART1_CR2_LBDIE
// - SFDITEM_FIELD__USART1_CR2_LBCL
// - SFDITEM_FIELD__USART1_CR2_CPHA
// - SFDITEM_FIELD__USART1_CR2_CPOL
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// - SFDITEM_FIELD__USART1_CR2_STOP
//
//
// ---------------------------- Register Item Address: USART1_CR3 -------------------------------
// SVD Line: 8709
unsigned int USART1_CR3 __AT (0x40013814);
// ------------------------------- Field Item: USART1_CR3_EIE -----------------------------------
// SVD Line: 8715
// - SFDITEM_FIELD__USART1_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40013814) Error interrupt enable
//
// ( (unsigned int) USART1_CR3 )
// EIE
//
//
//
// ------------------------------- Field Item: USART1_CR3_IRLP ----------------------------------
// SVD Line: 8720
// - SFDITEM_FIELD__USART1_CR3_IRLP
// IRLP
//
// [Bit 2] RW (@ 0x40013814) IrDA low-power
//
// ( (unsigned int) USART1_CR3 )
// IRLP
//
//
//
// ------------------------------ Field Item: USART1_CR3_HDSEL ----------------------------------
// SVD Line: 8725
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40013814) Half-duplex selection
//
// ( (unsigned int) USART1_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: USART1_CR3_SCEN ----------------------------------
// SVD Line: 8730
// - SFDITEM_FIELD__USART1_CR3_SCEN
// SCEN
//
// [Bit 5] RW (@ 0x40013814) desc SCEN
//
// ( (unsigned int) USART1_CR3 )
// SCEN
//
//
//
// ------------------------------- Field Item: USART1_CR3_DMAR ----------------------------------
// SVD Line: 8735
// - SFDITEM_FIELD__USART1_CR3_DMAR
// DMAR
//
// [Bit 6] RW (@ 0x40013814) DMA enable receiver
//
// ( (unsigned int) USART1_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: USART1_CR3_DMAT ----------------------------------
// SVD Line: 8740
// - SFDITEM_FIELD__USART1_CR3_DMAT
// DMAT
//
// [Bit 7] RW (@ 0x40013814) DMA enable transmitter
//
// ( (unsigned int) USART1_CR3 )
// DMAT
//
//
//
// ------------------------------- Field Item: USART1_CR3_RTSE ----------------------------------
// SVD Line: 8745
// - SFDITEM_FIELD__USART1_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40013814) RTS enable
//
// ( (unsigned int) USART1_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: USART1_CR3_CTSE ----------------------------------
// SVD Line: 8750
// - SFDITEM_FIELD__USART1_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40013814) CTS enable
//
// ( (unsigned int) USART1_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: USART1_CR3_CTSIE ----------------------------------
// SVD Line: 8755
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40013814) CTS interrupt enable
//
// ( (unsigned int) USART1_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: USART1_CR3_OVER8 ----------------------------------
// SVD Line: 8760
// - SFDITEM_FIELD__USART1_CR3_OVER8
// OVER8
//
// [Bit 11] RW (@ 0x40013814) Oversampling mode
//
// ( (unsigned int) USART1_CR3 )
// OVER8
//
//
//
// ------------------------------ Field Item: USART1_CR3_ABREN ----------------------------------
// SVD Line: 8765
// - SFDITEM_FIELD__USART1_CR3_ABREN
// ABREN
//
// [Bit 12] RW (@ 0x40013814) Auto baudrate enable
//
// ( (unsigned int) USART1_CR3 )
// ABREN
//
//
//
// ----------------------------- Field Item: USART1_CR3_ABRMODE ---------------------------------
// SVD Line: 8770
// - SFDITEM_FIELD__USART1_CR3_ABRMODE
// ABRMODE
//
// [Bits 14..13] RW (@ 0x40013814) Auto baudrate mode
//
// ( (unsigned char)((USART1_CR3 >> 13) & 0x3), ((USART1_CR3 = (USART1_CR3 & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_CR3 -----------------------------------
// SVD Line: 8709
// SFDITEM_REG__USART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40013814) Control register 3
// ( (unsigned int)((USART1_CR3 >> 0) & 0xFFFFFFFF), ((USART1_CR3 = (USART1_CR3 & ~(0x7FEDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FED) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR3_EIE
// - SFDITEM_FIELD__USART1_CR3_IRLP
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// - SFDITEM_FIELD__USART1_CR3_SCEN
// - SFDITEM_FIELD__USART1_CR3_DMAR
// - SFDITEM_FIELD__USART1_CR3_DMAT
// - SFDITEM_FIELD__USART1_CR3_RTSE
// - SFDITEM_FIELD__USART1_CR3_CTSE
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// - SFDITEM_FIELD__USART1_CR3_OVER8
// - SFDITEM_FIELD__USART1_CR3_ABREN
// - SFDITEM_FIELD__USART1_CR3_ABRMODE
//
//
// --------------------------- Register Item Address: USART1_GTPR -------------------------------
// SVD Line: 8777
unsigned int USART1_GTPR __AT (0x40013818);
// ------------------------------- Field Item: USART1_GTPR_PSC ----------------------------------
// SVD Line: 8782
// - SFDITEM_FIELD__USART1_GTPR_PSC
// PSC
//
// [Bits 7..0] RW (@ 0x40013818) desc PSC
//
// ( (unsigned char)((USART1_GTPR >> 0) & 0xFF), ((USART1_GTPR = (USART1_GTPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART1_GTPR_GT -----------------------------------
// SVD Line: 8787
// - SFDITEM_FIELD__USART1_GTPR_GT
// GT
//
// [Bits 15..8] RW (@ 0x40013818) desc GT
//
// ( (unsigned char)((USART1_GTPR >> 8) & 0xFF), ((USART1_GTPR = (USART1_GTPR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_GTPR ----------------------------------
// SVD Line: 8777
// SFDITEM_REG__USART1_GTPR
// GTPR
//
// [Bits 31..0] RW (@ 0x40013818) desc GTPR
// ( (unsigned int)((USART1_GTPR >> 0) & 0xFFFFFFFF), ((USART1_GTPR = (USART1_GTPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_GTPR_PSC
// - SFDITEM_FIELD__USART1_GTPR_GT
//
//
// --------------------------------- Peripheral View: USART1 ------------------------------------
// SVD Line: 8453
// USART1
// USART1
// - SFDITEM_REG__USART1_SR
// - SFDITEM_REG__USART1_DR
// - SFDITEM_REG__USART1_BRR
// - SFDITEM_REG__USART1_CR1
// - SFDITEM_REG__USART1_CR2
// - SFDITEM_REG__USART1_CR3
// - SFDITEM_REG__USART1_GTPR
//
//
// ---------------------------- Register Item Address: USART2_SR --------------------------------
// SVD Line: 8469
unsigned int USART2_SR __AT (0x40004400);
// -------------------------------- Field Item: USART2_SR_PE ------------------------------------
// SVD Line: 8476
// - SFDITEM_FIELD__USART2_SR_PE
// PE
//
// [Bit 0] RO (@ 0x40004400) Parity error
//
// ( (unsigned int) USART2_SR )
// PE
//
//
//
// -------------------------------- Field Item: USART2_SR_FE ------------------------------------
// SVD Line: 8482
// - SFDITEM_FIELD__USART2_SR_FE
// FE
//
// [Bit 1] RO (@ 0x40004400) Framing error
//
// ( (unsigned int) USART2_SR )
// FE
//
//
//
// -------------------------------- Field Item: USART2_SR_NE ------------------------------------
// SVD Line: 8488
// - SFDITEM_FIELD__USART2_SR_NE
// NE
//
// [Bit 2] RO (@ 0x40004400) Noise error flag
//
// ( (unsigned int) USART2_SR )
// NE
//
//
//
// -------------------------------- Field Item: USART2_SR_ORE -----------------------------------
// SVD Line: 8494
// - SFDITEM_FIELD__USART2_SR_ORE
// ORE
//
// [Bit 3] RO (@ 0x40004400) Overrun error
//
// ( (unsigned int) USART2_SR )
// ORE
//
//
//
// ------------------------------- Field Item: USART2_SR_IDLE -----------------------------------
// SVD Line: 8500
// - SFDITEM_FIELD__USART2_SR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x40004400) IDLE line detected
//
// ( (unsigned int) USART2_SR )
// IDLE
//
//
//
// ------------------------------- Field Item: USART2_SR_RXNE -----------------------------------
// SVD Line: 8506
// - SFDITEM_FIELD__USART2_SR_RXNE
// RXNE
//
// [Bit 5] RW (@ 0x40004400) Read data register not empty
//
// ( (unsigned int) USART2_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: USART2_SR_TC ------------------------------------
// SVD Line: 8511
// - SFDITEM_FIELD__USART2_SR_TC
// TC
//
// [Bit 6] RW (@ 0x40004400) Transmission complete
//
// ( (unsigned int) USART2_SR )
// TC
//
//
//
// -------------------------------- Field Item: USART2_SR_TXE -----------------------------------
// SVD Line: 8516
// - SFDITEM_FIELD__USART2_SR_TXE
// TXE
//
// [Bit 7] RO (@ 0x40004400) Transmit data register empty
//
// ( (unsigned int) USART2_SR )
// TXE
//
//
//
// -------------------------------- Field Item: USART2_SR_LBD -----------------------------------
// SVD Line: 8522
// - SFDITEM_FIELD__USART2_SR_LBD
// LBD
//
// [Bit 8] RW (@ 0x40004400) desc LBD
//
// ( (unsigned int) USART2_SR )
// LBD
//
//
//
// -------------------------------- Field Item: USART2_SR_CTS -----------------------------------
// SVD Line: 8527
// - SFDITEM_FIELD__USART2_SR_CTS
// CTS
//
// [Bit 9] RW (@ 0x40004400) CTS flag
//
// ( (unsigned int) USART2_SR )
// CTS
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRF -----------------------------------
// SVD Line: 8532
// - SFDITEM_FIELD__USART2_SR_ABRF
// ABRF
//
// [Bit 10] RO (@ 0x40004400) Automate baudrate detection flag
//
// ( (unsigned int) USART2_SR )
// ABRF
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRE -----------------------------------
// SVD Line: 8538
// - SFDITEM_FIELD__USART2_SR_ABRE
// ABRE
//
// [Bit 11] RO (@ 0x40004400) Automate baudrate detection error flag
//
// ( (unsigned int) USART2_SR )
// ABRE
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRRQ ----------------------------------
// SVD Line: 8544
// - SFDITEM_FIELD__USART2_SR_ABRRQ
// ABRRQ
//
// [Bit 12] WO (@ 0x40004400) Automate baudrate detection requeset
//
// ( (unsigned int) USART2_SR )
// ABRRQ
//
//
//
// -------------------------------- Register RTree: USART2_SR -----------------------------------
// SVD Line: 8469
// SFDITEM_REG__USART2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004400) Status register
// ( (unsigned int)((USART2_SR >> 0) & 0xFFFFFFFF), ((USART2_SR = (USART2_SR & ~(0x1360UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1360) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_SR_PE
// - SFDITEM_FIELD__USART2_SR_FE
// - SFDITEM_FIELD__USART2_SR_NE
// - SFDITEM_FIELD__USART2_SR_ORE
// - SFDITEM_FIELD__USART2_SR_IDLE
// - SFDITEM_FIELD__USART2_SR_RXNE
// - SFDITEM_FIELD__USART2_SR_TC
// - SFDITEM_FIELD__USART2_SR_TXE
// - SFDITEM_FIELD__USART2_SR_LBD
// - SFDITEM_FIELD__USART2_SR_CTS
// - SFDITEM_FIELD__USART2_SR_ABRF
// - SFDITEM_FIELD__USART2_SR_ABRE
// - SFDITEM_FIELD__USART2_SR_ABRRQ
//
//
// ---------------------------- Register Item Address: USART2_DR --------------------------------
// SVD Line: 8552
unsigned int USART2_DR __AT (0x40004404);
// -------------------------------- Field Item: USART2_DR_DR ------------------------------------
// SVD Line: 8558
// - SFDITEM_FIELD__USART2_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004404) Data value
//
// ( (unsigned short)((USART2_DR >> 0) & 0x1FF), ((USART2_DR = (USART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: USART2_DR -----------------------------------
// SVD Line: 8552
// SFDITEM_REG__USART2_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004404) Data register
// ( (unsigned int)((USART2_DR >> 0) & 0xFFFFFFFF), ((USART2_DR = (USART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_DR_DR
//
//
// ---------------------------- Register Item Address: USART2_BRR -------------------------------
// SVD Line: 8565
unsigned int USART2_BRR __AT (0x40004408);
// --------------------------- Field Item: USART2_BRR_DIV_Fraction ------------------------------
// SVD Line: 8571
// - SFDITEM_FIELD__USART2_BRR_DIV_Fraction
// DIV_Fraction
//
// [Bits 3..0] RW (@ 0x40004408) fraction of USARTDIV
//
// ( (unsigned char)((USART2_BRR >> 0) & 0xF), ((USART2_BRR = (USART2_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: USART2_BRR_DIV_Mantissa ------------------------------
// SVD Line: 8576
// - SFDITEM_FIELD__USART2_BRR_DIV_Mantissa
// DIV_Mantissa
//
// [Bits 15..4] RW (@ 0x40004408) mantissa of USARTDIV
//
// ( (unsigned short)((USART2_BRR >> 4) & 0xFFF), ((USART2_BRR = (USART2_BRR & ~(0xFFFUL << 4 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART2_BRR -----------------------------------
// SVD Line: 8565
// SFDITEM_REG__USART2_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004408) Baud rate register
// ( (unsigned int)((USART2_BRR >> 0) & 0xFFFFFFFF), ((USART2_BRR = (USART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_BRR_DIV_Fraction
// - SFDITEM_FIELD__USART2_BRR_DIV_Mantissa
//
//
// ---------------------------- Register Item Address: USART2_CR1 -------------------------------
// SVD Line: 8583
unsigned int USART2_CR1 __AT (0x4000440C);
// ------------------------------- Field Item: USART2_CR1_SBK -----------------------------------
// SVD Line: 8589
// - SFDITEM_FIELD__USART2_CR1_SBK
// SBK
//
// [Bit 0] RW (@ 0x4000440C) Send break
//
// ( (unsigned int) USART2_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: USART2_CR1_RWU -----------------------------------
// SVD Line: 8594
// - SFDITEM_FIELD__USART2_CR1_RWU
// RWU
//
// [Bit 1] RW (@ 0x4000440C) Receiver wakeup
//
// ( (unsigned int) USART2_CR1 )
// RWU
//
//
//
// -------------------------------- Field Item: USART2_CR1_RE -----------------------------------
// SVD Line: 8599
// - SFDITEM_FIELD__USART2_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x4000440C) Receiver enable
//
// ( (unsigned int) USART2_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: USART2_CR1_TE -----------------------------------
// SVD Line: 8604
// - SFDITEM_FIELD__USART2_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x4000440C) Transmitter enable
//
// ( (unsigned int) USART2_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: USART2_CR1_IDLEIE ---------------------------------
// SVD Line: 8609
// - SFDITEM_FIELD__USART2_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x4000440C) IDLE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: USART2_CR1_RXNEIE ---------------------------------
// SVD Line: 8614
// - SFDITEM_FIELD__USART2_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x4000440C) RXNE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: USART2_CR1_TCIE ----------------------------------
// SVD Line: 8619
// - SFDITEM_FIELD__USART2_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x4000440C) Transmission complete interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: USART2_CR1_TXEIE ----------------------------------
// SVD Line: 8624
// - SFDITEM_FIELD__USART2_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x4000440C) TXE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: USART2_CR1_PEIE ----------------------------------
// SVD Line: 8629
// - SFDITEM_FIELD__USART2_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x4000440C) PE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: USART2_CR1_PS -----------------------------------
// SVD Line: 8634
// - SFDITEM_FIELD__USART2_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x4000440C) Parity selection
//
// ( (unsigned int) USART2_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: USART2_CR1_PCE -----------------------------------
// SVD Line: 8639
// - SFDITEM_FIELD__USART2_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x4000440C) Parity control enable
//
// ( (unsigned int) USART2_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: USART2_CR1_WAKE ----------------------------------
// SVD Line: 8644
// - SFDITEM_FIELD__USART2_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x4000440C) Wakeup method
//
// ( (unsigned int) USART2_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: USART2_CR1_M ------------------------------------
// SVD Line: 8649
// - SFDITEM_FIELD__USART2_CR1_M
// M
//
// [Bit 12] RW (@ 0x4000440C) Word length
//
// ( (unsigned int) USART2_CR1 )
// M
//
//
//
// -------------------------------- Field Item: USART2_CR1_UE -----------------------------------
// SVD Line: 8654
// - SFDITEM_FIELD__USART2_CR1_UE
// UE
//
// [Bit 13] RW (@ 0x4000440C) USART enable
//
// ( (unsigned int) USART2_CR1 )
// UE
//
//
//
// ------------------------------- Register RTree: USART2_CR1 -----------------------------------
// SVD Line: 8583
// SFDITEM_REG__USART2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x4000440C) Control register 1
// ( (unsigned int)((USART2_CR1 >> 0) & 0xFFFFFFFF), ((USART2_CR1 = (USART2_CR1 & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR1_SBK
// - SFDITEM_FIELD__USART2_CR1_RWU
// - SFDITEM_FIELD__USART2_CR1_RE
// - SFDITEM_FIELD__USART2_CR1_TE
// - SFDITEM_FIELD__USART2_CR1_IDLEIE
// - SFDITEM_FIELD__USART2_CR1_RXNEIE
// - SFDITEM_FIELD__USART2_CR1_TCIE
// - SFDITEM_FIELD__USART2_CR1_TXEIE
// - SFDITEM_FIELD__USART2_CR1_PEIE
// - SFDITEM_FIELD__USART2_CR1_PS
// - SFDITEM_FIELD__USART2_CR1_PCE
// - SFDITEM_FIELD__USART2_CR1_WAKE
// - SFDITEM_FIELD__USART2_CR1_M
// - SFDITEM_FIELD__USART2_CR1_UE
//
//
// ---------------------------- Register Item Address: USART2_CR2 -------------------------------
// SVD Line: 8661
unsigned int USART2_CR2 __AT (0x40004410);
// ------------------------------- Field Item: USART2_CR2_ADD -----------------------------------
// SVD Line: 8667
// - SFDITEM_FIELD__USART2_CR2_ADD
// ADD
//
// [Bits 3..0] RW (@ 0x40004410) Address of the USART node
//
// ( (unsigned char)((USART2_CR2 >> 0) & 0xF), ((USART2_CR2 = (USART2_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART2_CR2_LBDL ----------------------------------
// SVD Line: 8672
// - SFDITEM_FIELD__USART2_CR2_LBDL
// LBDL
//
// [Bit 5] RW (@ 0x40004410) desc LBDL
//
// ( (unsigned int) USART2_CR2 )
// LBDL
//
//
//
// ------------------------------ Field Item: USART2_CR2_LBDIE ----------------------------------
// SVD Line: 8677
// - SFDITEM_FIELD__USART2_CR2_LBDIE
// LBDIE
//
// [Bit 6] RW (@ 0x40004410) desc LBDIE
//
// ( (unsigned int) USART2_CR2 )
// LBDIE
//
//
//
// ------------------------------- Field Item: USART2_CR2_LBCL ----------------------------------
// SVD Line: 8682
// - SFDITEM_FIELD__USART2_CR2_LBCL
// LBCL
//
// [Bit 8] RW (@ 0x40004410) Last bit clock pulse
//
// ( (unsigned int) USART2_CR2 )
// LBCL
//
//
//
// ------------------------------- Field Item: USART2_CR2_CPHA ----------------------------------
// SVD Line: 8687
// - SFDITEM_FIELD__USART2_CR2_CPHA
// CPHA
//
// [Bit 9] RW (@ 0x40004410) Clock phase
//
// ( (unsigned int) USART2_CR2 )
// CPHA
//
//
//
// ------------------------------- Field Item: USART2_CR2_CPOL ----------------------------------
// SVD Line: 8692
// - SFDITEM_FIELD__USART2_CR2_CPOL
// CPOL
//
// [Bit 10] RW (@ 0x40004410) Clock polarity
//
// ( (unsigned int) USART2_CR2 )
// CPOL
//
//
//
// ------------------------------ Field Item: USART2_CR2_CLKEN ----------------------------------
// SVD Line: 8697
// - SFDITEM_FIELD__USART2_CR2_CLKEN
// CLKEN
//
// [Bit 11] RW (@ 0x40004410) Clock enable
//
// ( (unsigned int) USART2_CR2 )
// CLKEN
//
//
//
// ------------------------------- Field Item: USART2_CR2_STOP ----------------------------------
// SVD Line: 8702
// - SFDITEM_FIELD__USART2_CR2_STOP
// STOP
//
// [Bit 13] RW (@ 0x40004410) STOP bits
//
// ( (unsigned int) USART2_CR2 )
// STOP
//
//
//
// ------------------------------- Register RTree: USART2_CR2 -----------------------------------
// SVD Line: 8661
// SFDITEM_REG__USART2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004410) Control register 2
// ( (unsigned int)((USART2_CR2 >> 0) & 0xFFFFFFFF), ((USART2_CR2 = (USART2_CR2 & ~(0x2F6FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2F6F) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR2_ADD
// - SFDITEM_FIELD__USART2_CR2_LBDL
// - SFDITEM_FIELD__USART2_CR2_LBDIE
// - SFDITEM_FIELD__USART2_CR2_LBCL
// - SFDITEM_FIELD__USART2_CR2_CPHA
// - SFDITEM_FIELD__USART2_CR2_CPOL
// - SFDITEM_FIELD__USART2_CR2_CLKEN
// - SFDITEM_FIELD__USART2_CR2_STOP
//
//
// ---------------------------- Register Item Address: USART2_CR3 -------------------------------
// SVD Line: 8709
unsigned int USART2_CR3 __AT (0x40004414);
// ------------------------------- Field Item: USART2_CR3_EIE -----------------------------------
// SVD Line: 8715
// - SFDITEM_FIELD__USART2_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40004414) Error interrupt enable
//
// ( (unsigned int) USART2_CR3 )
// EIE
//
//
//
// ------------------------------- Field Item: USART2_CR3_IRLP ----------------------------------
// SVD Line: 8720
// - SFDITEM_FIELD__USART2_CR3_IRLP
// IRLP
//
// [Bit 2] RW (@ 0x40004414) IrDA low-power
//
// ( (unsigned int) USART2_CR3 )
// IRLP
//
//
//
// ------------------------------ Field Item: USART2_CR3_HDSEL ----------------------------------
// SVD Line: 8725
// - SFDITEM_FIELD__USART2_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40004414) Half-duplex selection
//
// ( (unsigned int) USART2_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: USART2_CR3_SCEN ----------------------------------
// SVD Line: 8730
// - SFDITEM_FIELD__USART2_CR3_SCEN
// SCEN
//
// [Bit 5] RW (@ 0x40004414) desc SCEN
//
// ( (unsigned int) USART2_CR3 )
// SCEN
//
//
//
// ------------------------------- Field Item: USART2_CR3_DMAR ----------------------------------
// SVD Line: 8735
// - SFDITEM_FIELD__USART2_CR3_DMAR
// DMAR
//
// [Bit 6] RW (@ 0x40004414) DMA enable receiver
//
// ( (unsigned int) USART2_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: USART2_CR3_DMAT ----------------------------------
// SVD Line: 8740
// - SFDITEM_FIELD__USART2_CR3_DMAT
// DMAT
//
// [Bit 7] RW (@ 0x40004414) DMA enable transmitter
//
// ( (unsigned int) USART2_CR3 )
// DMAT
//
//
//
// ------------------------------- Field Item: USART2_CR3_RTSE ----------------------------------
// SVD Line: 8745
// - SFDITEM_FIELD__USART2_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40004414) RTS enable
//
// ( (unsigned int) USART2_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: USART2_CR3_CTSE ----------------------------------
// SVD Line: 8750
// - SFDITEM_FIELD__USART2_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40004414) CTS enable
//
// ( (unsigned int) USART2_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: USART2_CR3_CTSIE ----------------------------------
// SVD Line: 8755
// - SFDITEM_FIELD__USART2_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40004414) CTS interrupt enable
//
// ( (unsigned int) USART2_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: USART2_CR3_OVER8 ----------------------------------
// SVD Line: 8760
// - SFDITEM_FIELD__USART2_CR3_OVER8
// OVER8
//
// [Bit 11] RW (@ 0x40004414) Oversampling mode
//
// ( (unsigned int) USART2_CR3 )
// OVER8
//
//
//
// ------------------------------ Field Item: USART2_CR3_ABREN ----------------------------------
// SVD Line: 8765
// - SFDITEM_FIELD__USART2_CR3_ABREN
// ABREN
//
// [Bit 12] RW (@ 0x40004414) Auto baudrate enable
//
// ( (unsigned int) USART2_CR3 )
// ABREN
//
//
//
// ----------------------------- Field Item: USART2_CR3_ABRMODE ---------------------------------
// SVD Line: 8770
// - SFDITEM_FIELD__USART2_CR3_ABRMODE
// ABRMODE
//
// [Bits 14..13] RW (@ 0x40004414) Auto baudrate mode
//
// ( (unsigned char)((USART2_CR3 >> 13) & 0x3), ((USART2_CR3 = (USART2_CR3 & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART2_CR3 -----------------------------------
// SVD Line: 8709
// SFDITEM_REG__USART2_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40004414) Control register 3
// ( (unsigned int)((USART2_CR3 >> 0) & 0xFFFFFFFF), ((USART2_CR3 = (USART2_CR3 & ~(0x7FEDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FED) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR3_EIE
// - SFDITEM_FIELD__USART2_CR3_IRLP
// - SFDITEM_FIELD__USART2_CR3_HDSEL
// - SFDITEM_FIELD__USART2_CR3_SCEN
// - SFDITEM_FIELD__USART2_CR3_DMAR
// - SFDITEM_FIELD__USART2_CR3_DMAT
// - SFDITEM_FIELD__USART2_CR3_RTSE
// - SFDITEM_FIELD__USART2_CR3_CTSE
// - SFDITEM_FIELD__USART2_CR3_CTSIE
// - SFDITEM_FIELD__USART2_CR3_OVER8
// - SFDITEM_FIELD__USART2_CR3_ABREN
// - SFDITEM_FIELD__USART2_CR3_ABRMODE
//
//
// --------------------------- Register Item Address: USART2_GTPR -------------------------------
// SVD Line: 8777
unsigned int USART2_GTPR __AT (0x40004418);
// ------------------------------- Field Item: USART2_GTPR_PSC ----------------------------------
// SVD Line: 8782
// - SFDITEM_FIELD__USART2_GTPR_PSC
// PSC
//
// [Bits 7..0] RW (@ 0x40004418) desc PSC
//
// ( (unsigned char)((USART2_GTPR >> 0) & 0xFF), ((USART2_GTPR = (USART2_GTPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART2_GTPR_GT -----------------------------------
// SVD Line: 8787
// - SFDITEM_FIELD__USART2_GTPR_GT
// GT
//
// [Bits 15..8] RW (@ 0x40004418) desc GT
//
// ( (unsigned char)((USART2_GTPR >> 8) & 0xFF), ((USART2_GTPR = (USART2_GTPR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART2_GTPR ----------------------------------
// SVD Line: 8777
// SFDITEM_REG__USART2_GTPR
// GTPR
//
// [Bits 31..0] RW (@ 0x40004418) desc GTPR
// ( (unsigned int)((USART2_GTPR >> 0) & 0xFFFFFFFF), ((USART2_GTPR = (USART2_GTPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_GTPR_PSC
// - SFDITEM_FIELD__USART2_GTPR_GT
//
//
// --------------------------------- Peripheral View: USART2 ------------------------------------
// SVD Line: 8796
// USART2
// USART2
// - SFDITEM_REG__USART2_SR
// - SFDITEM_REG__USART2_DR
// - SFDITEM_REG__USART2_BRR
// - SFDITEM_REG__USART2_CR1
// - SFDITEM_REG__USART2_CR2
// - SFDITEM_REG__USART2_CR3
// - SFDITEM_REG__USART2_GTPR
//
//
// ----------------------------- Register Item Address: WWDG_CR ---------------------------------
// SVD Line: 8821
unsigned int WWDG_CR __AT (0x40002C00);
// ---------------------------------- Field Item: WWDG_CR_T -------------------------------------
// SVD Line: 8828
// - SFDITEM_FIELD__WWDG_CR_T
// T
//
// [Bits 6..0] RW (@ 0x40002C00) 7-bit counter (MSB to LSB)
//
// ( (unsigned char)((WWDG_CR >> 0) & 0x7F), ((WWDG_CR = (WWDG_CR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: WWDG_CR_WDGA ------------------------------------
// SVD Line: 8833
// - SFDITEM_FIELD__WWDG_CR_WDGA
// WDGA
//
// [Bit 7] RW (@ 0x40002C00) Activation bit
//
// ( (unsigned int) WWDG_CR )
// WDGA
//
//
//
// --------------------------------- Register RTree: WWDG_CR ------------------------------------
// SVD Line: 8821
// SFDITEM_REG__WWDG_CR
// CR
//
// [Bits 31..0] RW (@ 0x40002C00) Control register (WWDG_CR)
// ( (unsigned int)((WWDG_CR >> 0) & 0xFFFFFFFF), ((WWDG_CR = (WWDG_CR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_CR_T
// - SFDITEM_FIELD__WWDG_CR_WDGA
//
//
// ----------------------------- Register Item Address: WWDG_CFR --------------------------------
// SVD Line: 8840
unsigned int WWDG_CFR __AT (0x40002C04);
// --------------------------------- Field Item: WWDG_CFR_W -------------------------------------
// SVD Line: 8847
// - SFDITEM_FIELD__WWDG_CFR_W
// W
//
// [Bits 6..0] RW (@ 0x40002C04) 7-bit window value
//
// ( (unsigned char)((WWDG_CFR >> 0) & 0x7F), ((WWDG_CFR = (WWDG_CFR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: WWDG_CFR_WDGTB -----------------------------------
// SVD Line: 8852
// - SFDITEM_FIELD__WWDG_CFR_WDGTB
// WDGTB
//
// [Bits 8..7] RW (@ 0x40002C04) Timer Base
//
// ( (unsigned char)((WWDG_CFR >> 7) & 0x3), ((WWDG_CFR = (WWDG_CFR & ~(0x3UL << 7 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 7 ) ) ))
//
//
//
// -------------------------------- Field Item: WWDG_CFR_EWI ------------------------------------
// SVD Line: 8857
// - SFDITEM_FIELD__WWDG_CFR_EWI
// EWI
//
// [Bit 9] RW (@ 0x40002C04) Early Wakeup Interrupt
//
// ( (unsigned int) WWDG_CFR )
// EWI
//
//
//
// -------------------------------- Register RTree: WWDG_CFR ------------------------------------
// SVD Line: 8840
// SFDITEM_REG__WWDG_CFR
// CFR
//
// [Bits 31..0] RW (@ 0x40002C04) Configuration register(WWDG_CFR)
// ( (unsigned int)((WWDG_CFR >> 0) & 0xFFFFFFFF), ((WWDG_CFR = (WWDG_CFR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_CFR_W
// - SFDITEM_FIELD__WWDG_CFR_WDGTB
// - SFDITEM_FIELD__WWDG_CFR_EWI
//
//
// ----------------------------- Register Item Address: WWDG_SR ---------------------------------
// SVD Line: 8864
unsigned int WWDG_SR __AT (0x40002C08);
// -------------------------------- Field Item: WWDG_SR_EWIF ------------------------------------
// SVD Line: 8870
// - SFDITEM_FIELD__WWDG_SR_EWIF
// EWIF
//
// [Bit 0] RW (@ 0x40002C08) Early Wakeup Interrupt flag
//
// ( (unsigned int) WWDG_SR )
// EWIF
//
//
//
// --------------------------------- Register RTree: WWDG_SR ------------------------------------
// SVD Line: 8864
// SFDITEM_REG__WWDG_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002C08) Status register (WWDG_SR)
// ( (unsigned int)((WWDG_SR >> 0) & 0xFFFFFFFF), ((WWDG_SR = (WWDG_SR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_SR_EWIF
//
//
// ---------------------------------- Peripheral View: WWDG -------------------------------------
// SVD Line: 8805
// WWDG
// WWDG
// - SFDITEM_REG__WWDG_CR
// - SFDITEM_REG__WWDG_CFR
// - SFDITEM_REG__WWDG_SR
//
//
// ----------------------------- IRQ Num definition: PY32F021xx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// -------------------------- PY32F021xx Specific Interrupt Numbers -----------------------------
// WWDG_IRQ
// WWDG
// Window WatchDog Interrupt
// 16
//
//
// PVD_IRQ
// PVD
// PVD Interrupt through EXTI Lines 16
// 17
//
//
// RTC_IRQ
// RTC
// RTC Interrupt through EXTI Lines 19
// 18
//
//
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 19
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 20
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 21
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 22
//
//
// EXTI4_15_IRQ
// EXTI4_15
// EXTI Line 4 to 15 Interrupt
// 23
//
//
// DMA_Channel1_IRQ
// DMA_Channel1
// DMA Channel 1 Interrupt
// 25
//
//
// DMA_Channel2_3_IRQ
// DMA_Channel2_3
// DMA Channel 2 and Channel 3 Interrupt
// 26
//
//
// ADC_COMP_IRQ
// ADC_COMP
// ADC and COMP Interrupt through EXTI Lines 17 and 18
// 28
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 29
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 30
//
//
// TIM2_IRQ
// TIM2
// TIM2 global Interrupt
// 31
//
//
// LPTIM_IRQ
// LPTIM
// LPTIM global Interrupt
// 33
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupt
// 35
//
//
// TIM16_IRQ
// TIM16
// TIM16 global Interrupt
// 37
//
//
// TIM17_IRQ
// TIM17
// TIM17 global Interrupt
// 38
//
//
// I2C1_IRQ
// I2C1
// I2C1 global Interrupt
// 39
//
//
// SPI1_IRQ
// SPI1
// SPI1 global Interrupt
// 41
//
//
// SPI2_IRQ
// SPI2
// SPI2 global Interrupt
// 42
//
//
// USART1_IRQ
// USART1
// USART1 global Interrupt
// 43
//
//
// USART2_IRQ
// USART2
// USART2 global Interrupt
// 44
//
//
// SQRT_IRQ
// SQRT
// SQRT global Interrupt
// 46
//
//
// CORDIC_IRQ
// CORDIC
// CORDIC global Interrupt
// 47
//
//
// PY32F021xx_IRQTable
// PY32F021xx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// WWDG_IRQ
// PVD_IRQ
// RTC_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_15_IRQ
// DMA_Channel1_IRQ
// DMA_Channel2_3_IRQ
// ADC_COMP_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// TIM2_IRQ
// LPTIM_IRQ
// TIM14_IRQ
// TIM16_IRQ
// TIM17_IRQ
// I2C1_IRQ
// SPI1_IRQ
// SPI2_IRQ
// USART1_IRQ
// USART2_IRQ
// SQRT_IRQ
// CORDIC_IRQ
//
// ------------------------------------ Menu: PY32F021xx ---------------------------------------
// SVD Line: 2
// ------------------------------ Peripheral Menu: 'PY32F021xx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// ADC
// ADC
//
//
// COMP
// COMP1
// COMP2
//
//
// CORDIC
// CORDIC
//
//
// CRC
// CRC
//
//
// DBGMCU
// DBGMCU
//
//
// DIV
// DIV
//
//
// DMA
// DMA
//
//
// EXTI
// EXTI
//
//
// Flash
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOF
//
//
// I2C
// I2C1
//
//
// IWDG
// IWDG
//
//
// LPTIM
// LPTIM
//
//
// OPA
// OPA
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// RTC
// RTC
//
//
// SPI
// SPI1
// SPI2
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM2
// TIM14
// TIM16
// TIM17
//
//
// USART
// USART1
// USART2
//
//
// WWDG
// WWDG
//
//