/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F020Bxx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:14:59 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F020Bxx.svd',
* last modified on Wed May 6 11:14:11 2026
*/
// ----------------------------- Register Item Address: ADC_ISR ---------------------------------
// SVD Line: 40
unsigned int ADC_ISR __AT (0x40012400);
// -------------------------------- Field Item: ADC_ISR_EOSMP -----------------------------------
// SVD Line: 45
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// EOSMP
//
// [Bit 1] RW (@ 0x40012400) ADC group regular end of sampling flag
//
// ( (unsigned int) ADC_ISR )
// EOSMP
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOC ------------------------------------
// SVD Line: 50
// - SFDITEM_FIELD__ADC_ISR_EOC
// EOC
//
// [Bit 2] RW (@ 0x40012400) ADC group regular end of unitary conversion flag
//
// ( (unsigned int) ADC_ISR )
// EOC
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOSEQ -----------------------------------
// SVD Line: 55
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// EOSEQ
//
// [Bit 3] RW (@ 0x40012400) ADC group regular end of sequence conversions flag
//
// ( (unsigned int) ADC_ISR )
// EOSEQ
//
//
//
// --------------------------------- Field Item: ADC_ISR_OVR ------------------------------------
// SVD Line: 60
// - SFDITEM_FIELD__ADC_ISR_OVR
// OVR
//
// [Bit 4] RW (@ 0x40012400) ADC group regular overrun flag
//
// ( (unsigned int) ADC_ISR )
// OVR
//
//
//
// --------------------------------- Field Item: ADC_ISR_AWD ------------------------------------
// SVD Line: 65
// - SFDITEM_FIELD__ADC_ISR_AWD
// AWD
//
// [Bit 7] RW (@ 0x40012400) ADC analog watchdog flag
//
// ( (unsigned int) ADC_ISR )
// AWD
//
//
//
// --------------------------------- Register RTree: ADC_ISR ------------------------------------
// SVD Line: 40
// SFDITEM_REG__ADC_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40012400) ADC interrupt and status register
// ( (unsigned int)((ADC_ISR >> 0) & 0xFFFFFFFF), ((ADC_ISR = (ADC_ISR & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// - SFDITEM_FIELD__ADC_ISR_EOC
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// - SFDITEM_FIELD__ADC_ISR_OVR
// - SFDITEM_FIELD__ADC_ISR_AWD
//
//
// ----------------------------- Register Item Address: ADC_IER ---------------------------------
// SVD Line: 72
unsigned int ADC_IER __AT (0x40012404);
// ------------------------------- Field Item: ADC_IER_EOSMPIE ----------------------------------
// SVD Line: 77
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// EOSMPIE
//
// [Bit 1] RW (@ 0x40012404) ADC group regular end of sampling interrupt
//
// ( (unsigned int) ADC_IER )
// EOSMPIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOCIE -----------------------------------
// SVD Line: 82
// - SFDITEM_FIELD__ADC_IER_EOCIE
// EOCIE
//
// [Bit 2] RW (@ 0x40012404) ADC group regular end of unitary conversion interrupt
//
// ( (unsigned int) ADC_IER )
// EOCIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOSEQIE ----------------------------------
// SVD Line: 87
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// EOSEQIE
//
// [Bit 3] RW (@ 0x40012404) ADC group regular end of sequence conversions interrupt
//
// ( (unsigned int) ADC_IER )
// EOSEQIE
//
//
//
// -------------------------------- Field Item: ADC_IER_OVRIE -----------------------------------
// SVD Line: 92
// - SFDITEM_FIELD__ADC_IER_OVRIE
// OVRIE
//
// [Bit 4] RW (@ 0x40012404) ADC group regular overrun interrupt
//
// ( (unsigned int) ADC_IER )
// OVRIE
//
//
//
// -------------------------------- Field Item: ADC_IER_AWDIE -----------------------------------
// SVD Line: 97
// - SFDITEM_FIELD__ADC_IER_AWDIE
// AWDIE
//
// [Bit 7] RW (@ 0x40012404) ADC analog watchdog interrupt
//
// ( (unsigned int) ADC_IER )
// AWDIE
//
//
//
// --------------------------------- Register RTree: ADC_IER ------------------------------------
// SVD Line: 72
// SFDITEM_REG__ADC_IER
// IER
//
// [Bits 31..0] RW (@ 0x40012404) ADC interrupt enable register
// ( (unsigned int)((ADC_IER >> 0) & 0xFFFFFFFF), ((ADC_IER = (ADC_IER & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// - SFDITEM_FIELD__ADC_IER_EOCIE
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// - SFDITEM_FIELD__ADC_IER_OVRIE
// - SFDITEM_FIELD__ADC_IER_AWDIE
//
//
// ------------------------------ Register Item Address: ADC_CR ---------------------------------
// SVD Line: 104
unsigned int ADC_CR __AT (0x40012408);
// --------------------------------- Field Item: ADC_CR_ADEN ------------------------------------
// SVD Line: 109
// - SFDITEM_FIELD__ADC_CR_ADEN
// ADEN
//
// [Bit 0] RW (@ 0x40012408) enabl adc
//
// ( (unsigned int) ADC_CR )
// ADEN
//
//
//
// -------------------------------- Field Item: ADC_CR_ADDIS ------------------------------------
// SVD Line: 114
// - SFDITEM_FIELD__ADC_CR_ADDIS
// ADDIS
//
// [Bit 1] RW (@ 0x40012408) addis conversion
//
// ( (unsigned int) ADC_CR )
// ADDIS
//
//
//
// ------------------------------- Field Item: ADC_CR_ADSTART -----------------------------------
// SVD Line: 119
// - SFDITEM_FIELD__ADC_CR_ADSTART
// ADSTART
//
// [Bit 2] RW (@ 0x40012408) start conversion
//
// ( (unsigned int) ADC_CR )
// ADSTART
//
//
//
// -------------------------------- Field Item: ADC_CR_ADSTP ------------------------------------
// SVD Line: 124
// - SFDITEM_FIELD__ADC_CR_ADSTP
// ADSTP
//
// [Bit 4] RW (@ 0x40012408) stop conversion
//
// ( (unsigned int) ADC_CR )
// ADSTP
//
//
//
// -------------------------------- Field Item: ADC_CR_ADCAL ------------------------------------
// SVD Line: 129
// - SFDITEM_FIELD__ADC_CR_ADCAL
// ADCAL
//
// [Bit 31] RW (@ 0x40012408) calibration enable
//
// ( (unsigned int) ADC_CR )
// ADCAL
//
//
//
// --------------------------------- Register RTree: ADC_CR -------------------------------------
// SVD Line: 104
// SFDITEM_REG__ADC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40012408) ADC control register
// ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0x80000017UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80000017) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CR_ADEN
// - SFDITEM_FIELD__ADC_CR_ADDIS
// - SFDITEM_FIELD__ADC_CR_ADSTART
// - SFDITEM_FIELD__ADC_CR_ADSTP
// - SFDITEM_FIELD__ADC_CR_ADCAL
//
//
// ---------------------------- Register Item Address: ADC_CFGR1 --------------------------------
// SVD Line: 136
unsigned int ADC_CFGR1 __AT (0x4001240C);
// ------------------------------ Field Item: ADC_CFGR1_SCANDIR ---------------------------------
// SVD Line: 141
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// SCANDIR
//
// [Bit 2] RW (@ 0x4001240C) sequence direction
//
// ( (unsigned int) ADC_CFGR1 )
// SCANDIR
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_RESSEL ----------------------------------
// SVD Line: 146
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// RESSEL
//
// [Bits 4..3] RO (@ 0x4001240C) conversion ressel select
//
// ( (unsigned char)((ADC_CFGR1 >> 3) & 0x3) )
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_ALIGN ----------------------------------
// SVD Line: 152
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// ALIGN
//
// [Bit 5] RW (@ 0x4001240C) align mode
//
// ( (unsigned int) ADC_CFGR1 )
// ALIGN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_EXTSEL ----------------------------------
// SVD Line: 157
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// EXTSEL
//
// [Bits 8..6] RW (@ 0x4001240C) tigle select
//
// ( (unsigned char)((ADC_CFGR1 >> 6) & 0x7), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_EXTEN ----------------------------------
// SVD Line: 162
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// EXTEN
//
// [Bits 11..10] RW (@ 0x4001240C) trigle mode select
//
// ( (unsigned char)((ADC_CFGR1 >> 10) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_OVRMOD ----------------------------------
// SVD Line: 167
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// OVRMOD
//
// [Bit 12] RW (@ 0x4001240C) over mode
//
// ( (unsigned int) ADC_CFGR1 )
// OVRMOD
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_CONT -----------------------------------
// SVD Line: 172
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// CONT
//
// [Bit 13] RW (@ 0x4001240C) continul mode
//
// ( (unsigned int) ADC_CFGR1 )
// CONT
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_WAIT -----------------------------------
// SVD Line: 177
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// WAIT
//
// [Bit 14] RW (@ 0x4001240C) wait mode
//
// ( (unsigned int) ADC_CFGR1 )
// WAIT
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_DISCEN ----------------------------------
// SVD Line: 182
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// DISCEN
//
// [Bit 16] RW (@ 0x4001240C) discent mode
//
// ( (unsigned int) ADC_CFGR1 )
// DISCEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_AWDSGL ----------------------------------
// SVD Line: 187
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// AWDSGL
//
// [Bit 22] RW (@ 0x4001240C) awd single mode
//
// ( (unsigned int) ADC_CFGR1 )
// AWDSGL
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDEN ----------------------------------
// SVD Line: 192
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// AWDEN
//
// [Bit 23] RW (@ 0x4001240C) awd enable
//
// ( (unsigned int) ADC_CFGR1 )
// AWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDCH ----------------------------------
// SVD Line: 197
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
// AWDCH
//
// [Bits 29..26] RW (@ 0x4001240C) awd channels
//
// ( (unsigned char)((ADC_CFGR1 >> 26) & 0xF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR1 -----------------------------------
// SVD Line: 136
// SFDITEM_REG__ADC_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x4001240C) ADC configuration register 1
// ( (unsigned int)((ADC_CFGR1 >> 0) & 0xFFFFFFFF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3CC17DE4UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CC17DE4) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
//
//
// ----------------------------- Register Item Address: ADC_SMP ---------------------------------
// SVD Line: 204
unsigned int ADC_SMP __AT (0x40012414);
// --------------------------------- Field Item: ADC_SMP_SMP ------------------------------------
// SVD Line: 208
// - SFDITEM_FIELD__ADC_SMP_SMP
// SMP
//
// [Bits 2..0] RW (@ 0x40012414) sample time
//
// ( (unsigned char)((ADC_SMP >> 0) & 0x7), ((ADC_SMP = (ADC_SMP & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_SMP ------------------------------------
// SVD Line: 204
// SFDITEM_REG__ADC_SMP
// SMP
//
// [Bits 31..0] RW (@ 0x40012414) SMP
// ( (unsigned int)((ADC_SMP >> 0) & 0xFFFFFFFF), ((ADC_SMP = (ADC_SMP & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMP_SMP
//
//
// ------------------------------ Register Item Address: ADC_TR ---------------------------------
// SVD Line: 215
unsigned int ADC_TR __AT (0x40012420);
// ---------------------------------- Field Item: ADC_TR_LT -------------------------------------
// SVD Line: 220
// - SFDITEM_FIELD__ADC_TR_LT
// LT
//
// [Bits 11..0] RW (@ 0x40012420) watch dog values of low
//
// ( (unsigned short)((ADC_TR >> 0) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ---------------------------------- Field Item: ADC_TR_HT -------------------------------------
// SVD Line: 225
// - SFDITEM_FIELD__ADC_TR_HT
// HT
//
// [Bits 27..16] RW (@ 0x40012420) watch dog values of high
//
// ( (unsigned short)((ADC_TR >> 16) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_TR -------------------------------------
// SVD Line: 215
// SFDITEM_REG__ADC_TR
// TR
//
// [Bits 31..0] RW (@ 0x40012420) ADC analog watchdog 1 threshold register
// ( (unsigned int)((ADC_TR >> 0) & 0xFFFFFFFF), ((ADC_TR = (ADC_TR & ~(0xFFF0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF0FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_TR_LT
// - SFDITEM_FIELD__ADC_TR_HT
//
//
// ---------------------------- Register Item Address: ADC_CHSEL --------------------------------
// SVD Line: 232
unsigned int ADC_CHSEL __AT (0x40012428);
// ------------------------------ Field Item: ADC_CHSEL_CHSEL0 ----------------------------------
// SVD Line: 236
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL0
// CHSEL0
//
// [Bit 0] RW (@ 0x40012428) Channel-0 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL0
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL1 ----------------------------------
// SVD Line: 241
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL1
// CHSEL1
//
// [Bit 1] RW (@ 0x40012428) Channel-1 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL1
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL2 ----------------------------------
// SVD Line: 246
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL2
// CHSEL2
//
// [Bit 2] RW (@ 0x40012428) Channel-2 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL2
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL3 ----------------------------------
// SVD Line: 251
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL3
// CHSEL3
//
// [Bit 3] RW (@ 0x40012428) Channel-3 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL3
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL4 ----------------------------------
// SVD Line: 256
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL4
// CHSEL4
//
// [Bit 4] RW (@ 0x40012428) Channel-4 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL4
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL5 ----------------------------------
// SVD Line: 261
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL5
// CHSEL5
//
// [Bit 5] RW (@ 0x40012428) Channel-5 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL5
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL6 ----------------------------------
// SVD Line: 266
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL6
// CHSEL6
//
// [Bit 6] RW (@ 0x40012428) Channel-6 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL6
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL7 ----------------------------------
// SVD Line: 271
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL7
// CHSEL7
//
// [Bit 7] RW (@ 0x40012428) Channel-7 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL7
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL8 ----------------------------------
// SVD Line: 276
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL8
// CHSEL8
//
// [Bit 8] RW (@ 0x40012428) Channel-8 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL8
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL9 ----------------------------------
// SVD Line: 281
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL9
// CHSEL9
//
// [Bit 9] RW (@ 0x40012428) Channel-9 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL9
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL10 ---------------------------------
// SVD Line: 286
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL10
// CHSEL10
//
// [Bit 10] RW (@ 0x40012428) Channel-10 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL10
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL11 ---------------------------------
// SVD Line: 291
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL11
// CHSEL11
//
// [Bit 11] RW (@ 0x40012428) Channel-11 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL11
//
//
//
// ------------------------------ Field Item: ADC_CHSEL_CHSEL12 ---------------------------------
// SVD Line: 296
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL12
// CHSEL12
//
// [Bit 12] RW (@ 0x40012428) Channel-12 selection
//
// ( (unsigned int) ADC_CHSEL )
// CHSEL12
//
//
//
// -------------------------------- Register RTree: ADC_CHSEL -----------------------------------
// SVD Line: 232
// SFDITEM_REG__ADC_CHSEL
// CHSEL
//
// [Bits 31..0] RW (@ 0x40012428) CHSEL
// ( (unsigned int)((ADC_CHSEL >> 0) & 0xFFFFFFFF), ((ADC_CHSEL = (ADC_CHSEL & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL0
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL1
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL2
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL3
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL4
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL5
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL6
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL7
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL8
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL9
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL10
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL11
// - SFDITEM_FIELD__ADC_CHSEL_CHSEL12
//
//
// ------------------------------ Register Item Address: ADC_DR ---------------------------------
// SVD Line: 303
unsigned int ADC_DR __AT (0x40012440);
// --------------------------------- Field Item: ADC_DR_DATA ------------------------------------
// SVD Line: 308
// - SFDITEM_FIELD__ADC_DR_DATA
// DATA
//
// [Bits 15..0] RO (@ 0x40012440) conversion data
//
// ( (unsigned short)((ADC_DR >> 0) & 0xFFFF) )
//
//
//
// --------------------------------- Register RTree: ADC_DR -------------------------------------
// SVD Line: 303
// SFDITEM_REG__ADC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40012440) ADC group regular data register
// ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_DR_DATA
//
//
// ----------------------------- Register Item Address: ADC_CCSR --------------------------------
// SVD Line: 316
unsigned int ADC_CCSR __AT (0x40012444);
// ------------------------------- Field Item: ADC_CCSR_CALSEL ----------------------------------
// SVD Line: 321
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// CALSEL
//
// [Bit 11] RW (@ 0x40012444) calibration mode select
//
// ( (unsigned int) ADC_CCSR )
// CALSEL
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSMP ----------------------------------
// SVD Line: 326
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// CALSMP
//
// [Bits 13..12] RW (@ 0x40012444) calibration sample time
//
// ( (unsigned char)((ADC_CCSR >> 12) & 0x3), ((ADC_CCSR = (ADC_CCSR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSET ----------------------------------
// SVD Line: 331
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// CALSET
//
// [Bit 15] RW (@ 0x40012444) calibration value of set
//
// ( (unsigned int) ADC_CCSR )
// CALSET
//
//
//
// ------------------------------- Field Item: ADC_CCSR_OFFSUC ----------------------------------
// SVD Line: 336
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// OFFSUC
//
// [Bit 29] RW (@ 0x40012444) offset line calibration success
//
// ( (unsigned int) ADC_CCSR )
// OFFSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CAPSUC ----------------------------------
// SVD Line: 341
// - SFDITEM_FIELD__ADC_CCSR_CAPSUC
// CAPSUC
//
// [Bit 30] RW (@ 0x40012444) capu calibration success
//
// ( (unsigned int) ADC_CCSR )
// CAPSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALON -----------------------------------
// SVD Line: 346
// - SFDITEM_FIELD__ADC_CCSR_CALON
// CALON
//
// [Bit 31] RO (@ 0x40012444) calibration status
//
// ( (unsigned int) ADC_CCSR )
// CALON
//
//
//
// -------------------------------- Register RTree: ADC_CCSR ------------------------------------
// SVD Line: 316
// SFDITEM_REG__ADC_CCSR
// CCSR
//
// [Bits 31..0] RW (@ 0x40012444) ADC calibration configuration and status register
// ( (unsigned int)((ADC_CCSR >> 0) & 0xFFFFFFFF), ((ADC_CCSR = (ADC_CCSR & ~(0x6000B800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6000B800) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// - SFDITEM_FIELD__ADC_CCSR_CAPSUC
// - SFDITEM_FIELD__ADC_CCSR_CALON
//
//
// ---------------------------- Register Item Address: ADC_CALRR1 -------------------------------
// SVD Line: 354
unsigned int ADC_CALRR1 __AT (0x40012448);
// ----------------------------- Field Item: ADC_CALRR1_CALC8OUT --------------------------------
// SVD Line: 359
// - SFDITEM_FIELD__ADC_CALRR1_CALC8OUT
// CALC8OUT
//
// [Bits 7..0] RO (@ 0x40012448) CALC8OUT
//
// ( (unsigned char)((ADC_CALRR1 >> 0) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR1_CALC9OUT --------------------------------
// SVD Line: 365
// - SFDITEM_FIELD__ADC_CALRR1_CALC9OUT
// CALC9OUT
//
// [Bits 15..8] RO (@ 0x40012448) CALC9OUT
//
// ( (unsigned char)((ADC_CALRR1 >> 8) & 0xFF) )
//
//
//
// ---------------------------- Field Item: ADC_CALRR1_CALC10OUT --------------------------------
// SVD Line: 371
// - SFDITEM_FIELD__ADC_CALRR1_CALC10OUT
// CALC10OUT
//
// [Bits 23..16] RO (@ 0x40012448) CALC10OUT
//
// ( (unsigned char)((ADC_CALRR1 >> 16) & 0xFF) )
//
//
//
// ---------------------------- Field Item: ADC_CALRR1_CALC11OUT --------------------------------
// SVD Line: 377
// - SFDITEM_FIELD__ADC_CALRR1_CALC11OUT
// CALC11OUT
//
// [Bits 31..24] RO (@ 0x40012448) CALC11OUT
//
// ( (unsigned char)((ADC_CALRR1 >> 24) & 0xFF) )
//
//
//
// ------------------------------- Register RTree: ADC_CALRR1 -----------------------------------
// SVD Line: 354
// SFDITEM_REG__ADC_CALRR1
// CALRR1
//
// [Bits 31..0] RW (@ 0x40012448) ADC calibration result register 1
// ( (unsigned int)((ADC_CALRR1 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_CALRR1_CALC8OUT
// - SFDITEM_FIELD__ADC_CALRR1_CALC9OUT
// - SFDITEM_FIELD__ADC_CALRR1_CALC10OUT
// - SFDITEM_FIELD__ADC_CALRR1_CALC11OUT
//
//
// ---------------------------- Register Item Address: ADC_CALRR2 -------------------------------
// SVD Line: 385
unsigned int ADC_CALRR2 __AT (0x4001244C);
// ----------------------------- Field Item: ADC_CALRR2_CALC4OUT --------------------------------
// SVD Line: 390
// - SFDITEM_FIELD__ADC_CALRR2_CALC4OUT
// CALC4OUT
//
// [Bits 7..0] RO (@ 0x4001244C) CALC4OUT
//
// ( (unsigned char)((ADC_CALRR2 >> 0) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC5OUT --------------------------------
// SVD Line: 396
// - SFDITEM_FIELD__ADC_CALRR2_CALC5OUT
// CALC5OUT
//
// [Bits 15..8] RO (@ 0x4001244C) CALC5OUT
//
// ( (unsigned char)((ADC_CALRR2 >> 8) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC6OUT --------------------------------
// SVD Line: 402
// - SFDITEM_FIELD__ADC_CALRR2_CALC6OUT
// CALC6OUT
//
// [Bits 23..16] RO (@ 0x4001244C) CALC6OUT
//
// ( (unsigned char)((ADC_CALRR2 >> 16) & 0xFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR2_CALC7OUT --------------------------------
// SVD Line: 408
// - SFDITEM_FIELD__ADC_CALRR2_CALC7OUT
// CALC7OUT
//
// [Bits 31..24] RO (@ 0x4001244C) CALC7OUT
//
// ( (unsigned char)((ADC_CALRR2 >> 24) & 0xFF) )
//
//
//
// ------------------------------- Register RTree: ADC_CALRR2 -----------------------------------
// SVD Line: 385
// SFDITEM_REG__ADC_CALRR2
// CALRR2
//
// [Bits 31..0] RW (@ 0x4001244C) ADC calibration result register 2
// ( (unsigned int)((ADC_CALRR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_CALRR2_CALC4OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC5OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC6OUT
// - SFDITEM_FIELD__ADC_CALRR2_CALC7OUT
//
//
// ---------------------------- Register Item Address: ADC_CALRR3 -------------------------------
// SVD Line: 416
unsigned int ADC_CALRR3 __AT (0x40012450);
// ----------------------------- Field Item: ADC_CALRR3_CALBOUT ---------------------------------
// SVD Line: 421
// - SFDITEM_FIELD__ADC_CALRR3_CALBOUT
// CALBOUT
//
// [Bits 11..0] RO (@ 0x40012450) CALBOUT
//
// ( (unsigned short)((ADC_CALRR3 >> 0) & 0xFFF) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR3_CALC2OUT --------------------------------
// SVD Line: 427
// - SFDITEM_FIELD__ADC_CALRR3_CALC2OUT
// CALC2OUT
//
// [Bits 20..16] RO (@ 0x40012450) CALC2OUT
//
// ( (unsigned char)((ADC_CALRR3 >> 16) & 0x1F) )
//
//
//
// ----------------------------- Field Item: ADC_CALRR3_CALC3OUT --------------------------------
// SVD Line: 433
// - SFDITEM_FIELD__ADC_CALRR3_CALC3OUT
// CALC3OUT
//
// [Bits 28..24] RO (@ 0x40012450) CALC3OUT
//
// ( (unsigned char)((ADC_CALRR3 >> 24) & 0x1F) )
//
//
//
// ------------------------------- Register RTree: ADC_CALRR3 -----------------------------------
// SVD Line: 416
// SFDITEM_REG__ADC_CALRR3
// CALRR3
//
// [Bits 31..0] RW (@ 0x40012450) ADC calibration result register 3
// ( (unsigned int)((ADC_CALRR3 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_CALRR3_CALBOUT
// - SFDITEM_FIELD__ADC_CALRR3_CALC2OUT
// - SFDITEM_FIELD__ADC_CALRR3_CALC3OUT
//
//
// --------------------------- Register Item Address: ADC_CALFIR1 -------------------------------
// SVD Line: 441
unsigned int ADC_CALFIR1 __AT (0x40012454);
// ----------------------------- Field Item: ADC_CALFIR1_CALC8IO --------------------------------
// SVD Line: 446
// - SFDITEM_FIELD__ADC_CALFIR1_CALC8IO
// CALC8IO
//
// [Bits 7..0] RW (@ 0x40012454) CALC8IO
//
// ( (unsigned char)((ADC_CALFIR1 >> 0) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR1_CALC9IO --------------------------------
// SVD Line: 451
// - SFDITEM_FIELD__ADC_CALFIR1_CALC9IO
// CALC9IO
//
// [Bits 15..8] RW (@ 0x40012454) CALC9IO
//
// ( (unsigned char)((ADC_CALFIR1 >> 8) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: ADC_CALFIR1_CALC10IO --------------------------------
// SVD Line: 456
// - SFDITEM_FIELD__ADC_CALFIR1_CALC10IO
// CALC10IO
//
// [Bits 23..16] RW (@ 0x40012454) CALC10IO
//
// ( (unsigned char)((ADC_CALFIR1 >> 16) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: ADC_CALFIR1_CALC11IO --------------------------------
// SVD Line: 461
// - SFDITEM_FIELD__ADC_CALFIR1_CALC11IO
// CALC11IO
//
// [Bits 31..24] RW (@ 0x40012454) CALC11IO
//
// ( (unsigned char)((ADC_CALFIR1 >> 24) & 0xFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: ADC_CALFIR1 ----------------------------------
// SVD Line: 441
// SFDITEM_REG__ADC_CALFIR1
// CALFIR1
//
// [Bits 31..0] RW (@ 0x40012454) ADC calibration factor input register 1
// ( (unsigned int)((ADC_CALFIR1 >> 0) & 0xFFFFFFFF), ((ADC_CALFIR1 = (ADC_CALFIR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFIR1_CALC8IO
// - SFDITEM_FIELD__ADC_CALFIR1_CALC9IO
// - SFDITEM_FIELD__ADC_CALFIR1_CALC10IO
// - SFDITEM_FIELD__ADC_CALFIR1_CALC11IO
//
//
// --------------------------- Register Item Address: ADC_CALFIR2 -------------------------------
// SVD Line: 468
unsigned int ADC_CALFIR2 __AT (0x40012458);
// ----------------------------- Field Item: ADC_CALFIR2_CALC4IO --------------------------------
// SVD Line: 473
// - SFDITEM_FIELD__ADC_CALFIR2_CALC4IO
// CALC4IO
//
// [Bits 7..0] RW (@ 0x40012458) CALC4IO
//
// ( (unsigned char)((ADC_CALFIR2 >> 0) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC5IO --------------------------------
// SVD Line: 478
// - SFDITEM_FIELD__ADC_CALFIR2_CALC5IO
// CALC5IO
//
// [Bits 15..8] RW (@ 0x40012458) CALC5IO
//
// ( (unsigned char)((ADC_CALFIR2 >> 8) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC6IO --------------------------------
// SVD Line: 483
// - SFDITEM_FIELD__ADC_CALFIR2_CALC6IO
// CALC6IO
//
// [Bits 23..16] RW (@ 0x40012458) CALC6IO
//
// ( (unsigned char)((ADC_CALFIR2 >> 16) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR2_CALC7IO --------------------------------
// SVD Line: 488
// - SFDITEM_FIELD__ADC_CALFIR2_CALC7IO
// CALC7IO
//
// [Bits 31..24] RW (@ 0x40012458) CALC7IO
//
// ( (unsigned char)((ADC_CALFIR2 >> 24) & 0xFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: ADC_CALFIR2 ----------------------------------
// SVD Line: 468
// SFDITEM_REG__ADC_CALFIR2
// CALFIR2
//
// [Bits 31..0] RW (@ 0x40012458) ADC calibration factor input register 2
// ( (unsigned int)((ADC_CALFIR2 >> 0) & 0xFFFFFFFF), ((ADC_CALFIR2 = (ADC_CALFIR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFIR2_CALC4IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC5IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC6IO
// - SFDITEM_FIELD__ADC_CALFIR2_CALC7IO
//
//
// --------------------------- Register Item Address: ADC_CALFIR3 -------------------------------
// SVD Line: 495
unsigned int ADC_CALFIR3 __AT (0x4001245C);
// ----------------------------- Field Item: ADC_CALFIR3_CALBIO ---------------------------------
// SVD Line: 500
// - SFDITEM_FIELD__ADC_CALFIR3_CALBIO
// CALBIO
//
// [Bits 11..0] RW (@ 0x4001245C) CALBIO
//
// ( (unsigned short)((ADC_CALFIR3 >> 0) & 0xFFF), ((ADC_CALFIR3 = (ADC_CALFIR3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR3_CALC2IO --------------------------------
// SVD Line: 505
// - SFDITEM_FIELD__ADC_CALFIR3_CALC2IO
// CALC2IO
//
// [Bits 20..16] RW (@ 0x4001245C) CALC2IO
//
// ( (unsigned char)((ADC_CALFIR3 >> 16) & 0x1F), ((ADC_CALFIR3 = (ADC_CALFIR3 & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFIR3_CALC3IO --------------------------------
// SVD Line: 510
// - SFDITEM_FIELD__ADC_CALFIR3_CALC3IO
// CALC3IO
//
// [Bits 28..24] RW (@ 0x4001245C) CALC3IO
//
// ( (unsigned char)((ADC_CALFIR3 >> 24) & 0x1F), ((ADC_CALFIR3 = (ADC_CALFIR3 & ~(0x1FUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: ADC_CALFIR3 ----------------------------------
// SVD Line: 495
// SFDITEM_REG__ADC_CALFIR3
// CALFIR3
//
// [Bits 31..0] RW (@ 0x4001245C) ADC calibration factor input register 2
// ( (unsigned int)((ADC_CALFIR3 >> 0) & 0xFFFFFFFF), ((ADC_CALFIR3 = (ADC_CALFIR3 & ~(0x1F1F0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F0FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFIR3_CALBIO
// - SFDITEM_FIELD__ADC_CALFIR3_CALC2IO
// - SFDITEM_FIELD__ADC_CALFIR3_CALC3IO
//
//
// --------------------------- Register Item Address: ADC_CAL_TEST ------------------------------
// SVD Line: 517
unsigned int ADC_CAL_TEST __AT (0x40012460);
// ---------------------------- Field Item: ADC_CAL_TEST_CAL_TEST -------------------------------
// SVD Line: 521
// - SFDITEM_FIELD__ADC_CAL_TEST_CAL_TEST
// CAL_TEST
//
// [Bits 2..0] RW (@ 0x40012460) calibration test values
//
// ( (unsigned char)((ADC_CAL_TEST >> 0) & 0x7), ((ADC_CAL_TEST = (ADC_CAL_TEST & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: ADC_CAL_TEST_DEBUG_SEL -------------------------------
// SVD Line: 526
// - SFDITEM_FIELD__ADC_CAL_TEST_DEBUG_SEL
// DEBUG_SEL
//
// [Bits 5..3] RW (@ 0x40012460) debug mode select output of sigs
//
// ( (unsigned char)((ADC_CAL_TEST >> 3) & 0x7), ((ADC_CAL_TEST = (ADC_CAL_TEST & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// ------------------------------ Register RTree: ADC_CAL_TEST ----------------------------------
// SVD Line: 517
// SFDITEM_REG__ADC_CAL_TEST
// CAL_TEST
//
// [Bits 31..0] RW (@ 0x40012460) CAL_TEST
// ( (unsigned int)((ADC_CAL_TEST >> 0) & 0xFFFFFFFF), ((ADC_CAL_TEST = (ADC_CAL_TEST & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CAL_TEST_CAL_TEST
// - SFDITEM_FIELD__ADC_CAL_TEST_DEBUG_SEL
//
//
// ----------------------------- Register Item Address: ADC_CCR ---------------------------------
// SVD Line: 533
unsigned int ADC_CCR __AT (0x40012708);
// ---------------------------- Field Item: ADC_CCR_VREF_BUFFERE --------------------------------
// SVD Line: 538
// - SFDITEM_FIELD__ADC_CCR_VREF_BUFFERE
// VREF_BUFFERE
//
// [Bit 5] RW (@ 0x40012708) VerfBuffer enable
//
// ( (unsigned int) ADC_CCR )
// VREF_BUFFERE
//
//
//
// ---------------------------- Field Item: ADC_CCR_VERFBUFF_SEL --------------------------------
// SVD Line: 543
// - SFDITEM_FIELD__ADC_CCR_VERFBUFF_SEL
// VERFBUFF_SEL
//
// [Bits 7..6] RW (@ 0x40012708) VREFBUF output voltage select
//
// ( (unsigned char)((ADC_CCR >> 6) & 0x3), ((ADC_CCR = (ADC_CCR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CCR_VREFEN -----------------------------------
// SVD Line: 548
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// VREFEN
//
// [Bit 22] RW (@ 0x40012708) reference voltage enable
//
// ( (unsigned int) ADC_CCR )
// VREFEN
//
//
//
// -------------------------------- Field Item: ADC_CCR_TSEN ------------------------------------
// SVD Line: 553
// - SFDITEM_FIELD__ADC_CCR_TSEN
// TSEN
//
// [Bit 23] RW (@ 0x40012708) ts line enable
//
// ( (unsigned int) ADC_CCR )
// TSEN
//
//
//
// --------------------------------- Register RTree: ADC_CCR ------------------------------------
// SVD Line: 533
// SFDITEM_REG__ADC_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x40012708) ADC common configuration register
// ( (unsigned int)((ADC_CCR >> 0) & 0xFFFFFFFF), ((ADC_CCR = (ADC_CCR & ~(0xC000E0UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC000E0) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCR_VREF_BUFFERE
// - SFDITEM_FIELD__ADC_CCR_VERFBUFF_SEL
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// - SFDITEM_FIELD__ADC_CCR_TSEN
//
//
// ---------------------------------- Peripheral View: ADC --------------------------------------
// SVD Line: 25
// ADC
// ADC
// - SFDITEM_REG__ADC_ISR
// - SFDITEM_REG__ADC_IER
// - SFDITEM_REG__ADC_CR
// - SFDITEM_REG__ADC_CFGR1
// - SFDITEM_REG__ADC_SMP
// - SFDITEM_REG__ADC_TR
// - SFDITEM_REG__ADC_CHSEL
// - SFDITEM_REG__ADC_DR
// - SFDITEM_REG__ADC_CCSR
// - SFDITEM_REG__ADC_CALRR1
// - SFDITEM_REG__ADC_CALRR2
// - SFDITEM_REG__ADC_CALRR3
// - SFDITEM_REG__ADC_CALFIR1
// - SFDITEM_REG__ADC_CALFIR2
// - SFDITEM_REG__ADC_CALFIR3
// - SFDITEM_REG__ADC_CAL_TEST
// - SFDITEM_REG__ADC_CCR
//
//
// ---------------------------- Register Item Address: COMP1_CSR --------------------------------
// SVD Line: 578
unsigned int COMP1_CSR __AT (0x40010200);
// ----------------------------- Field Item: COMP1_CSR_COMP1_EN ---------------------------------
// SVD Line: 583
// - SFDITEM_FIELD__COMP1_CSR_COMP1_EN
// COMP1_EN
//
// [Bit 0] RW (@ 0x40010200) COMP1 enable bit
//
// ( (unsigned int) COMP1_CSR )
// COMP1_EN
//
//
//
// ------------------------------ Field Item: COMP1_CSR_INMSEL ----------------------------------
// SVD Line: 588
// - SFDITEM_FIELD__COMP1_CSR_INMSEL
// INMSEL
//
// [Bits 7..6] RW (@ 0x40010200) COMP1 negative input select
//
// ( (unsigned char)((COMP1_CSR >> 6) & 0x3), ((COMP1_CSR = (COMP1_CSR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP1_CSR_INPSEL ----------------------------------
// SVD Line: 593
// - SFDITEM_FIELD__COMP1_CSR_INPSEL
// INPSEL
//
// [Bits 9..8] RW (@ 0x40010200) COMP1 positive input select
//
// ( (unsigned char)((COMP1_CSR >> 8) & 0x3), ((COMP1_CSR = (COMP1_CSR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP1_CSR_WINMODE ---------------------------------
// SVD Line: 598
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010200) COMP1 window mode enable
//
// ( (unsigned int) COMP1_CSR )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP1_CSR_POLARITY ---------------------------------
// SVD Line: 603
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010200) COMP1 output polarity selection
//
// ( (unsigned int) COMP1_CSR )
// POLARITY
//
//
//
// ------------------------------ Field Item: COMP1_CSR_PWRMODE ---------------------------------
// SVD Line: 608
// - SFDITEM_FIELD__COMP1_CSR_PWRMODE
// PWRMODE
//
// [Bit 18] RW (@ 0x40010200) COMP1 power mode selection
//
// ( (unsigned int) COMP1_CSR )
// PWRMODE
//
//
//
// ---------------------------- Field Item: COMP1_CSR_COMP_VCDIV --------------------------------
// SVD Line: 613
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCDIV
// COMP_VCDIV
//
// [Bits 25..20] RW (@ 0x40010200) COMP1, COMP2 partial voltage selection
//
// ( (unsigned char)((COMP1_CSR >> 20) & 0x3F), ((COMP1_CSR = (COMP1_CSR & ~(0x3FUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: COMP1_CSR_COMP_VCDIV_EN ------------------------------
// SVD Line: 618
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCDIV_EN
// COMP_VCDIV_EN
//
// [Bit 26] RW (@ 0x40010200) VREFCMP voltage divider enable signal
//
// ( (unsigned int) COMP1_CSR )
// COMP_VCDIV_EN
//
//
//
// ---------------------------- Field Item: COMP1_CSR_COMP_VCSEL --------------------------------
// SVD Line: 623
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCSEL
// COMP_VCSEL
//
// [Bit 27] RW (@ 0x40010200) VREFCMP reference source selection
//
// ( (unsigned int) COMP1_CSR )
// COMP_VCSEL
//
//
//
// ------------------------- Field Item: COMP1_CSR_TIM_EXTI_OUT_SEL -----------------------------
// SVD Line: 628
// - SFDITEM_FIELD__COMP1_CSR_TIM_EXTI_OUT_SEL
// TIM_EXTI_OUT_SEL
//
// [Bit 29] RW (@ 0x40010200) COMP1 output to TIM/EXTI selection
//
// ( (unsigned int) COMP1_CSR )
// TIM_EXTI_OUT_SEL
//
//
//
// ----------------------------- Field Item: COMP1_CSR_COMP_OUT ---------------------------------
// SVD Line: 633
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RO (@ 0x40010200) COMP1 output status
//
// ( (unsigned int) COMP1_CSR )
// COMP_OUT
//
//
//
// -------------------------------- Register RTree: COMP1_CSR -----------------------------------
// SVD Line: 578
// SFDITEM_REG__COMP1_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010200) COMP control and status register
// ( (unsigned int)((COMP1_CSR >> 0) & 0xFFFFFFFF), ((COMP1_CSR = (COMP1_CSR & ~(0x2FF48BC1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2FF48BC1) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_CSR_COMP1_EN
// - SFDITEM_FIELD__COMP1_CSR_INMSEL
// - SFDITEM_FIELD__COMP1_CSR_INPSEL
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// - SFDITEM_FIELD__COMP1_CSR_PWRMODE
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCDIV
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCDIV_EN
// - SFDITEM_FIELD__COMP1_CSR_COMP_VCSEL
// - SFDITEM_FIELD__COMP1_CSR_TIM_EXTI_OUT_SEL
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
//
//
// ----------------------------- Register Item Address: COMP1_FR --------------------------------
// SVD Line: 641
unsigned int COMP1_FR __AT (0x40010204);
// ------------------------------- Field Item: COMP1_FR_FLTEN1 ----------------------------------
// SVD Line: 646
// - SFDITEM_FIELD__COMP1_FR_FLTEN1
// FLTEN1
//
// [Bit 0] RW (@ 0x40010204) Comparator 1 digital filter configuration
//
// ( (unsigned int) COMP1_FR )
// FLTEN1
//
//
//
// ------------------------------ Field Item: COMP1_FR_FLTCNT1 ----------------------------------
// SVD Line: 651
// - SFDITEM_FIELD__COMP1_FR_FLTCNT1
// FLTCNT1
//
// [Bits 31..16] RW (@ 0x40010204) Comparator 1 sampling filter counter
//
// ( (unsigned short)((COMP1_FR >> 16) & 0xFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP1_FR ------------------------------------
// SVD Line: 641
// SFDITEM_REG__COMP1_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010204) Comparator Filter register
// ( (unsigned int)((COMP1_FR >> 0) & 0xFFFFFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_FR_FLTEN1
// - SFDITEM_FIELD__COMP1_FR_FLTCNT1
//
//
// --------------------------------- Peripheral View: COMP1 -------------------------------------
// SVD Line: 562
// COMP1
// COMP1
// - SFDITEM_REG__COMP1_CSR
// - SFDITEM_REG__COMP1_FR
//
//
// ---------------------------- Register Item Address: COMP2_CSR --------------------------------
// SVD Line: 676
unsigned int COMP2_CSR __AT (0x40010210);
// ----------------------------- Field Item: COMP2_CSR_COMP2_EN ---------------------------------
// SVD Line: 681
// - SFDITEM_FIELD__COMP2_CSR_COMP2_EN
// COMP2_EN
//
// [Bit 0] RW (@ 0x40010210) COMP2 enable bit
//
// ( (unsigned int) COMP2_CSR )
// COMP2_EN
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INMSEL ----------------------------------
// SVD Line: 686
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// INMSEL
//
// [Bits 7..6] RW (@ 0x40010210) COMP2 negative input select
//
// ( (unsigned char)((COMP2_CSR >> 6) & 0x3), ((COMP2_CSR = (COMP2_CSR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INPSEL ----------------------------------
// SVD Line: 691
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// INPSEL
//
// [Bits 9..8] RW (@ 0x40010210) COMP2 positive input select
//
// ( (unsigned char)((COMP2_CSR >> 8) & 0x3), ((COMP2_CSR = (COMP2_CSR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: COMP2_CSR_POLARITY ---------------------------------
// SVD Line: 696
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010210) COMP2 output polarity selection
//
// ( (unsigned int) COMP2_CSR )
// POLARITY
//
//
//
// ------------------------------ Field Item: COMP2_CSR_PWRMODE ---------------------------------
// SVD Line: 701
// - SFDITEM_FIELD__COMP2_CSR_PWRMODE
// PWRMODE
//
// [Bit 18] RW (@ 0x40010210) COMP2 power mode selection
//
// ( (unsigned int) COMP2_CSR )
// PWRMODE
//
//
//
// ------------------------- Field Item: COMP2_CSR_TIM_EXTI_OUT_SEL -----------------------------
// SVD Line: 706
// - SFDITEM_FIELD__COMP2_CSR_TIM_EXTI_OUT_SEL
// TIM_EXTI_OUT_SEL
//
// [Bit 29] RW (@ 0x40010210) COMP2 output to TIM/EXTI selection
//
// ( (unsigned int) COMP2_CSR )
// TIM_EXTI_OUT_SEL
//
//
//
// ----------------------------- Field Item: COMP2_CSR_COMP_OUT ---------------------------------
// SVD Line: 711
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RO (@ 0x40010210) COMP2 output status
//
// ( (unsigned int) COMP2_CSR )
// COMP_OUT
//
//
//
// -------------------------------- Register RTree: COMP2_CSR -----------------------------------
// SVD Line: 676
// SFDITEM_REG__COMP2_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010210) COMP control and status register
// ( (unsigned int)((COMP2_CSR >> 0) & 0xFFFFFFFF), ((COMP2_CSR = (COMP2_CSR & ~(0x200483C1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200483C1) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_CSR_COMP2_EN
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// - SFDITEM_FIELD__COMP2_CSR_PWRMODE
// - SFDITEM_FIELD__COMP2_CSR_TIM_EXTI_OUT_SEL
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
//
//
// ----------------------------- Register Item Address: COMP2_FR --------------------------------
// SVD Line: 719
unsigned int COMP2_FR __AT (0x40010214);
// ------------------------------- Field Item: COMP2_FR_FLTEN2 ----------------------------------
// SVD Line: 724
// - SFDITEM_FIELD__COMP2_FR_FLTEN2
// FLTEN2
//
// [Bit 0] RW (@ 0x40010214) Comparator 2 digital filtering configuration
//
// ( (unsigned int) COMP2_FR )
// FLTEN2
//
//
//
// ------------------------------ Field Item: COMP2_FR_FLTCNT2 ----------------------------------
// SVD Line: 729
// - SFDITEM_FIELD__COMP2_FR_FLTCNT2
// FLTCNT2
//
// [Bits 31..16] RW (@ 0x40010214) Comparator 2 sampling filter counter
//
// ( (unsigned short)((COMP2_FR >> 16) & 0xFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP2_FR ------------------------------------
// SVD Line: 719
// SFDITEM_REG__COMP2_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010214) Comparator Filter register
// ( (unsigned int)((COMP2_FR >> 0) & 0xFFFFFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_FR_FLTEN2
// - SFDITEM_FIELD__COMP2_FR_FLTCNT2
//
//
// --------------------------------- Peripheral View: COMP2 -------------------------------------
// SVD Line: 660
// COMP2
// COMP2
// - SFDITEM_REG__COMP2_CSR
// - SFDITEM_REG__COMP2_FR
//
//
// ------------------------------ Register Item Address: CRC_DR ---------------------------------
// SVD Line: 748
unsigned int CRC_DR __AT (0x40023000);
// ---------------------------------- Field Item: CRC_DR_DR -------------------------------------
// SVD Line: 753
// - SFDITEM_FIELD__CRC_DR_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register bits
//
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_DR -------------------------------------
// SVD Line: 748
// SFDITEM_REG__CRC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_DR_DR
//
//
// ----------------------------- Register Item Address: CRC_IDR ---------------------------------
// SVD Line: 760
unsigned int CRC_IDR __AT (0x40023004);
// --------------------------------- Field Item: CRC_IDR_IDR ------------------------------------
// SVD Line: 765
// - SFDITEM_FIELD__CRC_IDR_IDR
// IDR
//
// [Bits 7..0] RW (@ 0x40023004) General-purpose 8-bit data register bits
//
// ( (unsigned char)((CRC_IDR >> 0) & 0xFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_IDR ------------------------------------
// SVD Line: 760
// SFDITEM_REG__CRC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x40023004) Independent Data register
// ( (unsigned int)((CRC_IDR >> 0) & 0xFFFFFFFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_IDR_IDR
//
//
// ------------------------------ Register Item Address: CRC_CR ---------------------------------
// SVD Line: 772
unsigned int CRC_CR __AT (0x40023008);
// -------------------------------- Field Item: CRC_CR_RESET ------------------------------------
// SVD Line: 777
// - SFDITEM_FIELD__CRC_CR_RESET
// RESET
//
// [Bit 0] WO (@ 0x40023008) Reset the CRC module
//
// ( (unsigned int) CRC_CR )
// RESET
//
//
//
// --------------------------------- Register RTree: CRC_CR -------------------------------------
// SVD Line: 772
// SFDITEM_REG__CRC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40023008) Control register
// ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_CR_RESET
//
//
// ---------------------------------- Peripheral View: CRC --------------------------------------
// SVD Line: 738
// CRC
// CRC
// - SFDITEM_REG__CRC_DR
// - SFDITEM_REG__CRC_IDR
// - SFDITEM_REG__CRC_CR
//
//
// -------------------------- Register Item Address: DBGMCU_IDCODE ------------------------------
// SVD Line: 798
unsigned int DBGMCU_IDCODE __AT (0x40015800);
// ---------------------------- Field Item: DBGMCU_IDCODE_REV_ID --------------------------------
// SVD Line: 805
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
// REV_ID
//
// [Bits 31..0] RO (@ 0x40015800) REV_ID
//
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
//
//
//
// ------------------------------ Register RTree: DBGMCU_IDCODE ---------------------------------
// SVD Line: 798
// SFDITEM_REG__DBGMCU_IDCODE
// IDCODE
//
// [Bits 31..0] RO (@ 0x40015800) MCU Device ID Code Register
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 812
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_SLEEP --------------------------------
// SVD Line: 818
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// DBG_SLEEP
//
// [Bit 0] RW (@ 0x40015804) Debug Sleep Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_SLEEP
//
//
//
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 823
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) Debug Stop Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 812
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ1 -----------------------------
// SVD Line: 830
unsigned int DBGMCU_APB_FZ1 __AT (0x40015808);
// ------------------------- Field Item: DBGMCU_APB_FZ1_DBG_RTC_STOP ----------------------------
// SVD Line: 836
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_RTC_STOP
// DBG_RTC_STOP
//
// [Bit 10] RW (@ 0x40015808) Debug RTC stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_RTC_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_IWDG_STOP ----------------------------
// SVD Line: 841
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
// DBG_IWDG_STOP
//
// [Bit 12] RW (@ 0x40015808) Debug Independent Wachdog stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_IWDG_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ1 ---------------------------------
// SVD Line: 830
// SFDITEM_REG__DBGMCU_APB_FZ1
// APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) APB Freeze Register1
// ( (unsigned int)((DBGMCU_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ1 = (DBGMCU_APB_FZ1 & ~(0x1400UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1400) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_RTC_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ2 -----------------------------
// SVD Line: 848
unsigned int DBGMCU_APB_FZ2 __AT (0x4001580C);
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER1_STOP ---------------------------
// SVD Line: 854
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// DBG_TIMER1_STOP
//
// [Bit 11] RW (@ 0x4001580C) Debug Timer 1 stopped when Core ishalted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER1_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ2_DBG_TIM14_STOP ---------------------------
// SVD Line: 859
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
// DBG_TIM14_STOP
//
// [Bit 15] RW (@ 0x4001580C) Debug TIM 14 stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIM14_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ2 ---------------------------------
// SVD Line: 848
// SFDITEM_REG__DBGMCU_APB_FZ2
// APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) APB Freeze Register2
// ( (unsigned int)((DBGMCU_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ2 = (DBGMCU_APB_FZ2 & ~(0x8800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8800) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 787
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_APB_FZ1
// - SFDITEM_REG__DBGMCU_APB_FZ2
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 893
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 898
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 903
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 908
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 913
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 918
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 923
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 928
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 933
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT8 -----------------------------------
// SVD Line: 938
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// RT8
//
// [Bit 8] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT8
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT9 -----------------------------------
// SVD Line: 943
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// RT9
//
// [Bit 9] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT9
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT10 -----------------------------------
// SVD Line: 948
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// RT10
//
// [Bit 10] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT10
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT11 -----------------------------------
// SVD Line: 953
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// RT11
//
// [Bit 11] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT11
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT12 -----------------------------------
// SVD Line: 958
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// RT12
//
// [Bit 12] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT12
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT13 -----------------------------------
// SVD Line: 963
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// RT13
//
// [Bit 13] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT13
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT14 -----------------------------------
// SVD Line: 968
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// RT14
//
// [Bit 14] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT14
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT15 -----------------------------------
// SVD Line: 973
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// RT15
//
// [Bit 15] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT15
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT17 -----------------------------------
// SVD Line: 978
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// RT17
//
// [Bit 17] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT17
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT18 -----------------------------------
// SVD Line: 983
// - SFDITEM_FIELD__EXTI_RTSR_RT18
// RT18
//
// [Bit 18] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT18
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 893
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selection register
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0x6FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// - SFDITEM_FIELD__EXTI_RTSR_RT18
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 990
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 995
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 1000
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 1005
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 1010
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 1015
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 1020
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 1025
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 1030
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT8 -----------------------------------
// SVD Line: 1035
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// FT8
//
// [Bit 8] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT8
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT9 -----------------------------------
// SVD Line: 1040
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// FT9
//
// [Bit 9] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT9
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT10 -----------------------------------
// SVD Line: 1045
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// FT10
//
// [Bit 10] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT10
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT11 -----------------------------------
// SVD Line: 1050
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// FT11
//
// [Bit 11] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT11
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT12 -----------------------------------
// SVD Line: 1055
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// FT12
//
// [Bit 12] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT12
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT13 -----------------------------------
// SVD Line: 1060
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// FT13
//
// [Bit 13] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT13
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT14 -----------------------------------
// SVD Line: 1065
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// FT14
//
// [Bit 14] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT14
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT15 -----------------------------------
// SVD Line: 1070
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// FT15
//
// [Bit 15] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT15
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT17 -----------------------------------
// SVD Line: 1075
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// FT17
//
// [Bit 17] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT17
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT18 -----------------------------------
// SVD Line: 1080
// - SFDITEM_FIELD__EXTI_FTSR_FT18
// FT18
//
// [Bit 18] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT18
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 990
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selection register
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0x6FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// - SFDITEM_FIELD__EXTI_FTSR_FT18
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 1087
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------- Field Item: EXTI_SWIER_SWI0 ----------------------------------
// SVD Line: 1092
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// SWI0
//
// [Bit 0] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI0
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI1 ----------------------------------
// SVD Line: 1097
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// SWI1
//
// [Bit 1] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI1
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI2 ----------------------------------
// SVD Line: 1102
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// SWI2
//
// [Bit 2] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI2
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI3 ----------------------------------
// SVD Line: 1107
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// SWI3
//
// [Bit 3] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI3
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI4 ----------------------------------
// SVD Line: 1112
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// SWI4
//
// [Bit 4] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI4
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI5 ----------------------------------
// SVD Line: 1117
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// SWI5
//
// [Bit 5] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI5
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI6 ----------------------------------
// SVD Line: 1122
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// SWI6
//
// [Bit 6] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI6
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI7 ----------------------------------
// SVD Line: 1127
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// SWI7
//
// [Bit 7] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI7
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI8 ----------------------------------
// SVD Line: 1132
// - SFDITEM_FIELD__EXTI_SWIER_SWI8
// SWI8
//
// [Bit 8] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI8
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI9 ----------------------------------
// SVD Line: 1137
// - SFDITEM_FIELD__EXTI_SWIER_SWI9
// SWI9
//
// [Bit 9] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI9
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI10 ----------------------------------
// SVD Line: 1142
// - SFDITEM_FIELD__EXTI_SWIER_SWI10
// SWI10
//
// [Bit 10] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI10
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI11 ----------------------------------
// SVD Line: 1147
// - SFDITEM_FIELD__EXTI_SWIER_SWI11
// SWI11
//
// [Bit 11] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI11
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI12 ----------------------------------
// SVD Line: 1152
// - SFDITEM_FIELD__EXTI_SWIER_SWI12
// SWI12
//
// [Bit 12] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI12
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI13 ----------------------------------
// SVD Line: 1157
// - SFDITEM_FIELD__EXTI_SWIER_SWI13
// SWI13
//
// [Bit 13] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI13
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI14 ----------------------------------
// SVD Line: 1162
// - SFDITEM_FIELD__EXTI_SWIER_SWI14
// SWI14
//
// [Bit 14] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI14
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI15 ----------------------------------
// SVD Line: 1167
// - SFDITEM_FIELD__EXTI_SWIER_SWI15
// SWI15
//
// [Bit 15] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI15
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI17 ----------------------------------
// SVD Line: 1172
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// SWI17
//
// [Bit 17] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI17
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI18 ----------------------------------
// SVD Line: 1177
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
// SWI18
//
// [Bit 18] RW (@ 0x40021808) Configurable exti linex enable of soft trigle
//
// ( (unsigned int) EXTI_SWIER )
// SWI18
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 1087
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt event register
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0x6FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// - SFDITEM_FIELD__EXTI_SWIER_SWI8
// - SFDITEM_FIELD__EXTI_SWIER_SWI9
// - SFDITEM_FIELD__EXTI_SWIER_SWI10
// - SFDITEM_FIELD__EXTI_SWIER_SWI11
// - SFDITEM_FIELD__EXTI_SWIER_SWI12
// - SFDITEM_FIELD__EXTI_SWIER_SWI13
// - SFDITEM_FIELD__EXTI_SWIER_SWI14
// - SFDITEM_FIELD__EXTI_SWIER_SWI15
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 1184
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 1189
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 1194
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 1199
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 1204
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 1209
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 1214
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 1219
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 1224
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR8 ------------------------------------
// SVD Line: 1229
// - SFDITEM_FIELD__EXTI_PR_PR8
// PR8
//
// [Bit 8] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR8
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR9 ------------------------------------
// SVD Line: 1234
// - SFDITEM_FIELD__EXTI_PR_PR9
// PR9
//
// [Bit 9] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR9
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR10 ------------------------------------
// SVD Line: 1239
// - SFDITEM_FIELD__EXTI_PR_PR10
// PR10
//
// [Bit 10] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR10
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR11 ------------------------------------
// SVD Line: 1244
// - SFDITEM_FIELD__EXTI_PR_PR11
// PR11
//
// [Bit 11] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR11
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR12 ------------------------------------
// SVD Line: 1249
// - SFDITEM_FIELD__EXTI_PR_PR12
// PR12
//
// [Bit 12] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR12
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR13 ------------------------------------
// SVD Line: 1254
// - SFDITEM_FIELD__EXTI_PR_PR13
// PR13
//
// [Bit 13] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR13
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR14 ------------------------------------
// SVD Line: 1259
// - SFDITEM_FIELD__EXTI_PR_PR14
// PR14
//
// [Bit 14] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR14
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR15 ------------------------------------
// SVD Line: 1264
// - SFDITEM_FIELD__EXTI_PR_PR15
// PR15
//
// [Bit 15] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR15
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR17 ------------------------------------
// SVD Line: 1269
// - SFDITEM_FIELD__EXTI_PR_PR17
// PR17
//
// [Bit 17] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR17
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR18 ------------------------------------
// SVD Line: 1274
// - SFDITEM_FIELD__EXTI_PR_PR18
// PR18
//
// [Bit 18] RW (@ 0x4002180C) Pending line of exti
//
// ( (unsigned int) EXTI_PR )
// PR18
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 1184
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pending register
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0x6FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
// - SFDITEM_FIELD__EXTI_PR_PR8
// - SFDITEM_FIELD__EXTI_PR_PR9
// - SFDITEM_FIELD__EXTI_PR_PR10
// - SFDITEM_FIELD__EXTI_PR_PR11
// - SFDITEM_FIELD__EXTI_PR_PR12
// - SFDITEM_FIELD__EXTI_PR_PR13
// - SFDITEM_FIELD__EXTI_PR_PR14
// - SFDITEM_FIELD__EXTI_PR_PR15
// - SFDITEM_FIELD__EXTI_PR_PR17
// - SFDITEM_FIELD__EXTI_PR_PR18
//
//
// --------------------------- Register Item Address: EXTI_EXTICR1 ------------------------------
// SVD Line: 1281
unsigned int EXTI_EXTICR1 __AT (0x40021860);
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI0 ---------------------------------
// SVD Line: 1285
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// EXTI0
//
// [Bits 1..0] RW (@ 0x40021860) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR1 >> 0) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI1 ---------------------------------
// SVD Line: 1290
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// EXTI1
//
// [Bits 9..8] RW (@ 0x40021860) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR1 >> 8) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI2 ---------------------------------
// SVD Line: 1295
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// EXTI2
//
// [Bits 17..16] RW (@ 0x40021860) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR1 >> 16) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI3 ---------------------------------
// SVD Line: 1300
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
// EXTI3
//
// [Bits 25..24] RW (@ 0x40021860) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR1 >> 24) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR1 ----------------------------------
// SVD Line: 1281
// SFDITEM_REG__EXTI_EXTICR1
// EXTICR1
//
// [Bits 31..0] RW (@ 0x40021860) EXTICR1
// ( (unsigned int)((EXTI_EXTICR1 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
//
//
// --------------------------- Register Item Address: EXTI_EXTICR2 ------------------------------
// SVD Line: 1307
unsigned int EXTI_EXTICR2 __AT (0x40021864);
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI4 ---------------------------------
// SVD Line: 1311
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// EXTI4
//
// [Bits 1..0] RW (@ 0x40021864) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR2 >> 0) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI5 ---------------------------------
// SVD Line: 1316
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// EXTI5
//
// [Bits 9..8] RW (@ 0x40021864) GPIO exti line select
//
// ( (unsigned char)((EXTI_EXTICR2 >> 8) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR2 ----------------------------------
// SVD Line: 1307
// SFDITEM_REG__EXTI_EXTICR2
// EXTICR2
//
// [Bits 31..0] RW (@ 0x40021864) EXTICR2
// ( (unsigned int)((EXTI_EXTICR2 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 1323
unsigned int EXTI_IMR __AT (0x40021880);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 1328
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 1333
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 1338
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 1343
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 1348
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 1353
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 1358
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 1363
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM8 ------------------------------------
// SVD Line: 1368
// - SFDITEM_FIELD__EXTI_IMR_IM8
// IM8
//
// [Bit 8] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM8
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM9 ------------------------------------
// SVD Line: 1373
// - SFDITEM_FIELD__EXTI_IMR_IM9
// IM9
//
// [Bit 9] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM9
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM10 -----------------------------------
// SVD Line: 1378
// - SFDITEM_FIELD__EXTI_IMR_IM10
// IM10
//
// [Bit 10] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM10
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM11 -----------------------------------
// SVD Line: 1383
// - SFDITEM_FIELD__EXTI_IMR_IM11
// IM11
//
// [Bit 11] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM11
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM12 -----------------------------------
// SVD Line: 1388
// - SFDITEM_FIELD__EXTI_IMR_IM12
// IM12
//
// [Bit 12] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM12
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM13 -----------------------------------
// SVD Line: 1393
// - SFDITEM_FIELD__EXTI_IMR_IM13
// IM13
//
// [Bit 13] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM13
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM14 -----------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__EXTI_IMR_IM14
// IM14
//
// [Bit 14] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM14
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM15 -----------------------------------
// SVD Line: 1403
// - SFDITEM_FIELD__EXTI_IMR_IM15
// IM15
//
// [Bit 15] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM15
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM17 -----------------------------------
// SVD Line: 1408
// - SFDITEM_FIELD__EXTI_IMR_IM17
// IM17
//
// [Bit 17] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM17
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM18 -----------------------------------
// SVD Line: 1413
// - SFDITEM_FIELD__EXTI_IMR_IM18
// IM18
//
// [Bit 18] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM18
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM19 -----------------------------------
// SVD Line: 1418
// - SFDITEM_FIELD__EXTI_IMR_IM19
// IM19
//
// [Bit 19] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM19
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM23 -----------------------------------
// SVD Line: 1423
// - SFDITEM_FIELD__EXTI_IMR_IM23
// IM23
//
// [Bit 23] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM23
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM28 -----------------------------------
// SVD Line: 1428
// - SFDITEM_FIELD__EXTI_IMR_IM28
// IM28
//
// [Bit 28] RW (@ 0x40021880) EXIT Mask enable
//
// ( (unsigned int) EXTI_IMR )
// IM28
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 1323
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021880) EXTI CPU wakeup with interrupt mask register
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0x108EFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x108EFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM8
// - SFDITEM_FIELD__EXTI_IMR_IM9
// - SFDITEM_FIELD__EXTI_IMR_IM10
// - SFDITEM_FIELD__EXTI_IMR_IM11
// - SFDITEM_FIELD__EXTI_IMR_IM12
// - SFDITEM_FIELD__EXTI_IMR_IM13
// - SFDITEM_FIELD__EXTI_IMR_IM14
// - SFDITEM_FIELD__EXTI_IMR_IM15
// - SFDITEM_FIELD__EXTI_IMR_IM17
// - SFDITEM_FIELD__EXTI_IMR_IM18
// - SFDITEM_FIELD__EXTI_IMR_IM19
// - SFDITEM_FIELD__EXTI_IMR_IM23
// - SFDITEM_FIELD__EXTI_IMR_IM28
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 1435
unsigned int EXTI_EMR __AT (0x40021884);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 1440
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 1445
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 1450
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 1455
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 1460
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 1465
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 1470
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 1475
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM8 ------------------------------------
// SVD Line: 1480
// - SFDITEM_FIELD__EXTI_EMR_EM8
// EM8
//
// [Bit 8] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM8
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM9 ------------------------------------
// SVD Line: 1485
// - SFDITEM_FIELD__EXTI_EMR_EM9
// EM9
//
// [Bit 9] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM9
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM10 -----------------------------------
// SVD Line: 1490
// - SFDITEM_FIELD__EXTI_EMR_EM10
// EM10
//
// [Bit 10] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM10
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM11 -----------------------------------
// SVD Line: 1495
// - SFDITEM_FIELD__EXTI_EMR_EM11
// EM11
//
// [Bit 11] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM11
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM12 -----------------------------------
// SVD Line: 1500
// - SFDITEM_FIELD__EXTI_EMR_EM12
// EM12
//
// [Bit 12] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM12
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM13 -----------------------------------
// SVD Line: 1505
// - SFDITEM_FIELD__EXTI_EMR_EM13
// EM13
//
// [Bit 13] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM13
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM14 -----------------------------------
// SVD Line: 1510
// - SFDITEM_FIELD__EXTI_EMR_EM14
// EM14
//
// [Bit 14] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM14
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM15 -----------------------------------
// SVD Line: 1515
// - SFDITEM_FIELD__EXTI_EMR_EM15
// EM15
//
// [Bit 15] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM15
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM17 -----------------------------------
// SVD Line: 1520
// - SFDITEM_FIELD__EXTI_EMR_EM17
// EM17
//
// [Bit 17] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM17
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM18 -----------------------------------
// SVD Line: 1525
// - SFDITEM_FIELD__EXTI_EMR_EM18
// EM18
//
// [Bit 18] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM18
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM19 -----------------------------------
// SVD Line: 1530
// - SFDITEM_FIELD__EXTI_EMR_EM19
// EM19
//
// [Bit 19] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM19
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM23 -----------------------------------
// SVD Line: 1535
// - SFDITEM_FIELD__EXTI_EMR_EM23
// EM23
//
// [Bit 23] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM23
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM28 -----------------------------------
// SVD Line: 1540
// - SFDITEM_FIELD__EXTI_EMR_EM28
// EM28
//
// [Bit 28] RW (@ 0x40021884) EXIT Mask enable
//
// ( (unsigned int) EXTI_EMR )
// EM28
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 1435
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x40021884) EXTI CPU wakeup with event mask register
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0x108EFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x108EFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM8
// - SFDITEM_FIELD__EXTI_EMR_EM9
// - SFDITEM_FIELD__EXTI_EMR_EM10
// - SFDITEM_FIELD__EXTI_EMR_EM11
// - SFDITEM_FIELD__EXTI_EMR_EM12
// - SFDITEM_FIELD__EXTI_EMR_EM13
// - SFDITEM_FIELD__EXTI_EMR_EM14
// - SFDITEM_FIELD__EXTI_EMR_EM15
// - SFDITEM_FIELD__EXTI_EMR_EM17
// - SFDITEM_FIELD__EXTI_EMR_EM18
// - SFDITEM_FIELD__EXTI_EMR_EM19
// - SFDITEM_FIELD__EXTI_EMR_EM23
// - SFDITEM_FIELD__EXTI_EMR_EM28
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 868
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_EXTICR1
// - SFDITEM_REG__EXTI_EXTICR2
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_ACR --------------------------------
// SVD Line: 1563
unsigned int FLASH_ACR __AT (0x40022000);
// ------------------------------ Field Item: FLASH_ACR_LATENCY ---------------------------------
// SVD Line: 1567
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
// LATENCY
//
// [Bits 1..0] RW (@ 0x40022000) Latency
//
// ( (unsigned char)((FLASH_ACR >> 0) & 0x3), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_ACR -----------------------------------
// SVD Line: 1563
// SFDITEM_REG__FLASH_ACR
// ACR
//
// [Bits 31..0] RW (@ 0x40022000) ACR
// ( (unsigned int)((FLASH_ACR >> 0) & 0xFFFFFFFF), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
//
//
// ---------------------------- Register Item Address: FLASH_KEY --------------------------------
// SVD Line: 1574
unsigned int FLASH_KEY __AT (0x40022008);
// -------------------------------- Field Item: FLASH_KEY_KEY -----------------------------------
// SVD Line: 1578
// - SFDITEM_FIELD__FLASH_KEY_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash CR key
//
// ( (unsigned int)((FLASH_KEY >> 0) & 0x0), ((FLASH_KEY = (FLASH_KEY & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_KEY -----------------------------------
// SVD Line: 1574
// SFDITEM_REG__FLASH_KEY
// KEY
//
// [Bits 31..0] RW (@ 0x40022008) KEY
// ( (unsigned int)((FLASH_KEY >> 0) & 0xFFFFFFFF), ((FLASH_KEY = (FLASH_KEY & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEY_KEY
//
//
// --------------------------- Register Item Address: FLASH_OPTKEY ------------------------------
// SVD Line: 1586
unsigned int FLASH_OPTKEY __AT (0x4002200C);
// ----------------------------- Field Item: FLASH_OPTKEY_OPTKEY --------------------------------
// SVD Line: 1590
// - SFDITEM_FIELD__FLASH_OPTKEY_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Flash Option key
//
// ( (unsigned int)((FLASH_OPTKEY >> 0) & 0x0), ((FLASH_OPTKEY = (FLASH_OPTKEY & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEY ----------------------------------
// SVD Line: 1586
// SFDITEM_REG__FLASH_OPTKEY
// OPTKEY
//
// [Bits 31..0] RW (@ 0x4002200C) OPTKEY
// ( (unsigned int)((FLASH_OPTKEY >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEY = (FLASH_OPTKEY & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEY_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 1598
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 1602
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 1607
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protection error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_USRLOCK ----------------------------------
// SVD Line: 1612
// - SFDITEM_FIELD__FLASH_SR_USRLOCK
// USRLOCK
//
// [Bit 13] RO (@ 0x40022010) Userdata Lock
//
// ( (unsigned int) FLASH_SR )
// USRLOCK
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 1618
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and trimming bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 1623
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RO (@ 0x40022010) Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 1598
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) SR
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x8011UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8011) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_USRLOCK
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 1631
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 1635
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Page Program
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 1640
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page Erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 1645
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Mass Erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 1650
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector Erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 1655
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option bytes Programming Start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_PGSTRT ----------------------------------
// SVD Line: 1660
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// PGSTRT
//
// [Bit 19] RW (@ 0x40022014) Programming Start
//
// ( (unsigned int) FLASH_CR )
// PGSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 1665
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 1670
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 1675
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option bytes loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 1680
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Option Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 1685
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 1631
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) CR
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xCB0A0807UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCB0A0807) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 1692
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------- Field Item: FLASH_OPTR_RDP -----------------------------------
// SVD Line: 1696
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// RDP
//
// [Bits 7..0] RW (@ 0x40022020) Read Protection
//
// ( (unsigned char)((FLASH_OPTR >> 0) & 0xFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_BOR_EN ---------------------------------
// SVD Line: 1701
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// BOR_EN
//
// [Bit 8] RW (@ 0x40022020) BOR enable
//
// ( (unsigned int) FLASH_OPTR )
// BOR_EN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BOR_LEV ---------------------------------
// SVD Line: 1706
// - SFDITEM_FIELD__FLASH_OPTR_BOR_LEV
// BOR_LEV
//
// [Bits 11..9] RW (@ 0x40022020) BOR Level
//
// ( (unsigned char)((FLASH_OPTR >> 9) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IWDG_SW ---------------------------------
// SVD Line: 1711
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// IWDG_SW
//
// [Bit 12] RW (@ 0x40022020) IWDG Software Enable
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_SW
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 1716
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 14] RW (@ 0x40022020) Pin n_reset Mode
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_IWDG_STOP --------------------------------
// SVD Line: 1721
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
// IWDG_STOP
//
// [Bit 15] RW (@ 0x40022020) IWDG Counting enable in Stop Mode
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_STOP
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 1692
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) OPTR
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xDFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// - SFDITEM_FIELD__FLASH_OPTR_BOR_LEV
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
//
//
// ---------------------------- Register Item Address: FLASH_SDKR -------------------------------
// SVD Line: 1728
unsigned int FLASH_SDKR __AT (0x40022024);
// ----------------------------- Field Item: FLASH_SDKR_SDK_STRT --------------------------------
// SVD Line: 1732
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// SDK_STRT
//
// [Bits 3..0] RW (@ 0x40022024) SDK Area Start Address
//
// ( (unsigned char)((FLASH_SDKR >> 0) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_SDKR_SDK_END ---------------------------------
// SVD Line: 1737
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
// SDK_END
//
// [Bits 11..8] RW (@ 0x40022024) SDK Area End Address
//
// ( (unsigned char)((FLASH_SDKR >> 8) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SDKR -----------------------------------
// SVD Line: 1728
// SFDITEM_REG__FLASH_SDKR
// SDKR
//
// [Bits 31..0] RW (@ 0x40022024) SDKR
// ( (unsigned int)((FLASH_SDKR >> 0) & 0xFFFFFFFF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xF0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
//
//
// ---------------------------- Register Item Address: FLASH_BTCR -------------------------------
// SVD Line: 1744
unsigned int FLASH_BTCR __AT (0x40022028);
// ---------------------------- Field Item: FLASH_BTCR_BOOT_SIZE --------------------------------
// SVD Line: 1748
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// BOOT_SIZE
//
// [Bits 2..0] RW (@ 0x40022028) Load Flash Size
//
// ( (unsigned char)((FLASH_BTCR >> 0) & 0x7), ((FLASH_BTCR = (FLASH_BTCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_BTCR_SWD_MODE --------------------------------
// SVD Line: 1753
// - SFDITEM_FIELD__FLASH_BTCR_SWD_MODE
// SWD_MODE
//
// [Bits 9..8] RW (@ 0x40022028) SWD Mode
//
// ( (unsigned char)((FLASH_BTCR >> 8) & 0x3), ((FLASH_BTCR = (FLASH_BTCR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_BOOT0 ----------------------------------
// SVD Line: 1758
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// BOOT0
//
// [Bit 14] RW (@ 0x40022028) BOOT0
//
// ( (unsigned int) FLASH_BTCR )
// BOOT0
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_NBOOT1 ---------------------------------
// SVD Line: 1763
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
// NBOOT1
//
// [Bit 15] RW (@ 0x40022028) nBOOT1
//
// ( (unsigned int) FLASH_BTCR )
// NBOOT1
//
//
//
// ------------------------------- Register RTree: FLASH_BTCR -----------------------------------
// SVD Line: 1744
// SFDITEM_REG__FLASH_BTCR
// BTCR
//
// [Bits 31..0] RW (@ 0x40022028) BTCR
// ( (unsigned int)((FLASH_BTCR >> 0) & 0xFFFFFFFF), ((FLASH_BTCR = (FLASH_BTCR & ~(0xC307UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC307) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// - SFDITEM_FIELD__FLASH_BTCR_SWD_MODE
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 1770
unsigned int FLASH_WRPR __AT (0x4002202C);
// ------------------------------- Field Item: FLASH_WRPR_WRP -----------------------------------
// SVD Line: 1774
// - SFDITEM_FIELD__FLASH_WRPR_WRP
// WRP
//
// [Bits 7..0] RW (@ 0x4002202C) Write Protection Disable
//
// ( (unsigned char)((FLASH_WRPR >> 0) & 0xFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 1770
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x4002202C) WRPR
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_WRP
//
//
// ---------------------------- Register Item Address: FLASH_STCR -------------------------------
// SVD Line: 1781
unsigned int FLASH_STCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_STCR_SLEEP_EN --------------------------------
// SVD Line: 1785
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) FLASH Sleep Enable
//
// ( (unsigned int) FLASH_STCR )
// SLEEP_EN
//
//
//
// ---------------------------- Field Item: FLASH_STCR_SLEEP_TIME -------------------------------
// SVD Line: 1790
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
// SLEEP_TIME
//
// [Bits 15..8] RW (@ 0x40022090) FLASH Sleep Time Configuration
//
// ( (unsigned char)((FLASH_STCR >> 8) & 0xFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_STCR -----------------------------------
// SVD Line: 1781
// SFDITEM_REG__FLASH_STCR
// STCR
//
// [Bits 31..0] RW (@ 0x40022090) STCR
// ( (unsigned int)((FLASH_STCR >> 0) & 0xFFFFFFFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFF01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF01) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 1797
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 1801
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 8..0] RW (@ 0x40022100) TS0
//
// ( (unsigned short)((FLASH_TS0 >> 0) & 0x1FF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 1797
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) TS0
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 1808
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 1812
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 9..0] RW (@ 0x40022104) TS1
//
// ( (unsigned short)((FLASH_TS1 >> 0) & 0x3FF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 1808
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) TS1
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 1819
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 1823
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 8..0] RW (@ 0x40022108) TS2P
//
// ( (unsigned short)((FLASH_TS2P >> 0) & 0x1FF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 1819
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) TS2P
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 1830
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 1834
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 11..0] RW (@ 0x4002210C) TPS3
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0xFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 1830
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) TPS3
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 1841
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 1845
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 8..0] RW (@ 0x40022110) TS3
//
// ( (unsigned short)((FLASH_TS3 >> 0) & 0x1FF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 1841
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) TS3
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_PERTPE ------------------------------
// SVD Line: 1852
unsigned int FLASH_PERTPE __AT (0x40022114);
// ----------------------------- Field Item: FLASH_PERTPE_PERTPE --------------------------------
// SVD Line: 1856
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
// PERTPE
//
// [Bits 17..0] RW (@ 0x40022114) PERTPE
//
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0x3FFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PERTPE ----------------------------------
// SVD Line: 1852
// SFDITEM_REG__FLASH_PERTPE
// PERTPE
//
// [Bits 31..0] RW (@ 0x40022114) PERTPE
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0xFFFFFFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
//
//
// -------------------------- Register Item Address: FLASH_SMERTPE ------------------------------
// SVD Line: 1863
unsigned int FLASH_SMERTPE __AT (0x40022118);
// ---------------------------- Field Item: FLASH_SMERTPE_SMERTPE -------------------------------
// SVD Line: 1867
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
// SMERTPE
//
// [Bits 17..0] RW (@ 0x40022118) SMERTPE
//
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0x3FFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_SMERTPE ---------------------------------
// SVD Line: 1863
// SFDITEM_REG__FLASH_SMERTPE
// SMERTPE
//
// [Bits 31..0] RW (@ 0x40022118) SMERTPE
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0xFFFFFFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 1874
unsigned int FLASH_PRGTPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 1878
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 15..0] RW (@ 0x4002211C) PRGTPE
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0xFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 1874
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x4002211C) PRGTPE
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 1885
unsigned int FLASH_PRETPE __AT (0x40022120);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 1889
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 13..0] RW (@ 0x40022120) PRETPE
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0x3FFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 1885
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x40022120) PRETPE
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 1549
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_ACR
// - SFDITEM_REG__FLASH_KEY
// - SFDITEM_REG__FLASH_OPTKEY
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_SDKR
// - SFDITEM_REG__FLASH_BTCR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_STCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_PERTPE
// - SFDITEM_REG__FLASH_SMERTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 1908
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 1913
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration I/O pin 0
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 1918
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration I/O pin 1
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 1923
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration I/O pin 2
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 1928
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration I/O pin 3
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 1933
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration I/O pin 4
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 1938
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration I/O pin 5
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 1943
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration I/O pin 6
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 1948
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration I/O pin 7
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE8 ---------------------------------
// SVD Line: 1953
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000000) Port x configuration I/O pin 8
//
// ( (unsigned char)((GPIOA_MODER >> 16) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE9 ---------------------------------
// SVD Line: 1958
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000000) Port x configuration I/O pin 9
//
// ( (unsigned char)((GPIOA_MODER >> 18) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE10 ---------------------------------
// SVD Line: 1963
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000000) Port x configuration I/O pin 10
//
// ( (unsigned char)((GPIOA_MODER >> 20) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE11 ---------------------------------
// SVD Line: 1968
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000000) Port x configuration I/O pin 11
//
// ( (unsigned char)((GPIOA_MODER >> 22) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE12 ---------------------------------
// SVD Line: 1973
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000000) Port x configuration I/O pin 12
//
// ( (unsigned char)((GPIOA_MODER >> 24) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE13 ---------------------------------
// SVD Line: 1978
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000000) Port x configuration I/O pin 13
//
// ( (unsigned char)((GPIOA_MODER >> 26) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE14 ---------------------------------
// SVD Line: 1983
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000000) Port x configuration I/O pin 14
//
// ( (unsigned char)((GPIOA_MODER >> 28) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE15 ---------------------------------
// SVD Line: 1988
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000000) Port x configuration I/O pin 15
//
// ( (unsigned char)((GPIOA_MODER >> 30) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 1908
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 1995
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 2000
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration I/O pin 0
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 2005
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration I/O pin 1
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 2010
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration I/O pin 2
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 2015
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration I/O pin 3
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 2020
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration I/O pin 4
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 2025
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration I/O pin 5
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 2030
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration I/O pin 6
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 2035
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration I/O pin 7
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT8 ----------------------------------
// SVD Line: 2040
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000004) Port x configuration I/O pin 8
//
// ( (unsigned int) GPIOA_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT9 ----------------------------------
// SVD Line: 2045
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000004) Port x configuration I/O pin 9
//
// ( (unsigned int) GPIOA_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT10 ---------------------------------
// SVD Line: 2050
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000004) Port x configuration I/O pin 10
//
// ( (unsigned int) GPIOA_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT11 ---------------------------------
// SVD Line: 2055
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000004) Port x configuration I/O pin 11
//
// ( (unsigned int) GPIOA_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT12 ---------------------------------
// SVD Line: 2060
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000004) Port x configuration I/O pin 12
//
// ( (unsigned int) GPIOA_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT13 ---------------------------------
// SVD Line: 2065
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000004) Port x configuration I/O pin 13
//
// ( (unsigned int) GPIOA_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT14 ---------------------------------
// SVD Line: 2070
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000004) Port x configuration I/O pin 14
//
// ( (unsigned int) GPIOA_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT15 ---------------------------------
// SVD Line: 2075
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000004) Port x configuration I/O pin 15
//
// ( (unsigned int) GPIOA_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 1995
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 2082
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2087
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration I/O pin 0
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2092
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration I/O pin 1
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2097
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration I/O pin 2
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2102
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration I/O pin 3
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2107
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration I/O pin 4
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2112
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration I/O pin 5
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2117
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration I/O pin 6
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2122
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration I/O pin 7
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2127
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000008) Port x configuration I/O pin 8
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 16) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 2132
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000008) Port x configuration I/O pin 9
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 18) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 2137
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000008) Port x configuration I/O pin 10
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 20) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 2142
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000008) Port x configuration I/O pin 11
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 22) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 2147
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000008) Port x configuration I/O pin 12
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 24) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 2152
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000008) Port x configuration I/O pin 13
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 26) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 2157
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000008) Port x configuration I/O pin 14
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 28) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 2162
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000008) Port x configuration I/O pin 15
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 30) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 2082
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 2169
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2174
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration I/O pin 0
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2179
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration I/O pin 1
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2184
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration I/O pin 2
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2189
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration I/O pin 3
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2194
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration I/O pin 4
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2199
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration I/O pin 5
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2204
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration I/O pin 6
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2209
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration I/O pin 7
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2214
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000000C) Port x configuration I/O pin 8
//
// ( (unsigned char)((GPIOA_PUPDR >> 16) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD9 ---------------------------------
// SVD Line: 2219
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000000C) Port x configuration I/O pin 9
//
// ( (unsigned char)((GPIOA_PUPDR >> 18) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD10 ---------------------------------
// SVD Line: 2224
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000000C) Port x configuration I/O pin 10
//
// ( (unsigned char)((GPIOA_PUPDR >> 20) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD11 ---------------------------------
// SVD Line: 2229
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000000C) Port x configuration I/O pin 11
//
// ( (unsigned char)((GPIOA_PUPDR >> 22) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD12 ---------------------------------
// SVD Line: 2234
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000000C) Port x configuration I/O pin 12
//
// ( (unsigned char)((GPIOA_PUPDR >> 24) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD13 ---------------------------------
// SVD Line: 2239
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000000C) Port x configuration I/O pin 13
//
// ( (unsigned char)((GPIOA_PUPDR >> 26) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD14 ---------------------------------
// SVD Line: 2244
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000000C) Port x configuration I/O pin 14
//
// ( (unsigned char)((GPIOA_PUPDR >> 28) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD15 ---------------------------------
// SVD Line: 2249
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000000C) Port x configuration I/O pin 15
//
// ( (unsigned char)((GPIOA_PUPDR >> 30) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 2169
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 2256
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 2261
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port x input data I/O pin 0
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 2267
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port x input data I/O pin 1
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 2273
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port x input data I/O pin 2
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 2279
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port x input data I/O pin 3
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 2285
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port x input data I/O pin 4
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 2291
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port x input data I/O pin 5
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 2297
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port x input data I/O pin 6
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 2303
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port x input data I/O pin 7
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID8 -----------------------------------
// SVD Line: 2309
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000010) Port x input data I/O pin 8
//
// ( (unsigned int) GPIOA_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID9 -----------------------------------
// SVD Line: 2315
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000010) Port x input data I/O pin 9
//
// ( (unsigned int) GPIOA_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID10 -----------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000010) Port x input data I/O pin 10
//
// ( (unsigned int) GPIOA_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID11 -----------------------------------
// SVD Line: 2327
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000010) Port x input data I/O pin 11
//
// ( (unsigned int) GPIOA_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID12 -----------------------------------
// SVD Line: 2333
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000010) Port x input data I/O pin 12
//
// ( (unsigned int) GPIOA_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID13 -----------------------------------
// SVD Line: 2339
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000010) Port x input data I/O pin 13
//
// ( (unsigned int) GPIOA_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID14 -----------------------------------
// SVD Line: 2345
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000010) Port x input data I/O pin 14
//
// ( (unsigned int) GPIOA_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID15 -----------------------------------
// SVD Line: 2351
// - SFDITEM_FIELD__GPIOA_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000010) Port x input data I/O pin 15
//
// ( (unsigned int) GPIOA_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 2256
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// - SFDITEM_FIELD__GPIOA_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 2359
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 2364
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data I/O pin 0
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 2369
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data I/O pin 1
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 2374
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data I/O pin 2
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 2379
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data I/O pin 3
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 2384
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data I/O pin 4
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 2389
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data I/O pin 5
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 2394
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data I/O pin 6
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 2399
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data I/O pin 7
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD8 -----------------------------------
// SVD Line: 2404
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000014) Port output data I/O pin 8
//
// ( (unsigned int) GPIOA_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD9 -----------------------------------
// SVD Line: 2409
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000014) Port output data I/O pin 9
//
// ( (unsigned int) GPIOA_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD10 -----------------------------------
// SVD Line: 2414
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000014) Port output data I/O pin 10
//
// ( (unsigned int) GPIOA_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD11 -----------------------------------
// SVD Line: 2419
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000014) Port output data I/O pin 11
//
// ( (unsigned int) GPIOA_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD12 -----------------------------------
// SVD Line: 2424
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000014) Port output data I/O pin 12
//
// ( (unsigned int) GPIOA_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD13 -----------------------------------
// SVD Line: 2429
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000014) Port output data I/O pin 13
//
// ( (unsigned int) GPIOA_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD14 -----------------------------------
// SVD Line: 2434
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000014) Port output data I/O pin 14
//
// ( (unsigned int) GPIOA_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD15 -----------------------------------
// SVD Line: 2439
// - SFDITEM_FIELD__GPIOA_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000014) Port output data I/O pin 15
//
// ( (unsigned int) GPIOA_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 2359
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// - SFDITEM_FIELD__GPIOA_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 2446
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 2451
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000018) Port x set I/O pin 0
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 2457
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000018) Port x set I/O pin 1
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 2463
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000018) Port x set I/O pin 2
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 2469
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000018) Port x set I/O pin 3
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 2475
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000018) Port x set I/O pin 4
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 2481
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000018) Port x set I/O pin 5
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 2487
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000018) Port x set I/O pin 6
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 2493
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000018) Port x set I/O pin 7
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS8 -----------------------------------
// SVD Line: 2499
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000018) Port x set I/O pin 8
//
// ( (unsigned int) GPIOA_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS9 -----------------------------------
// SVD Line: 2505
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// BS9
//
// [Bit 9] WO (@ 0x50000018) Port x set I/O pin 9
//
// ( (unsigned int) GPIOA_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS10 ----------------------------------
// SVD Line: 2511
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// BS10
//
// [Bit 10] WO (@ 0x50000018) Port x set I/O pin 10
//
// ( (unsigned int) GPIOA_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS11 ----------------------------------
// SVD Line: 2517
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// BS11
//
// [Bit 11] WO (@ 0x50000018) Port x set I/O pin 11
//
// ( (unsigned int) GPIOA_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS12 ----------------------------------
// SVD Line: 2523
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// BS12
//
// [Bit 12] WO (@ 0x50000018) Port x set I/O pin 12
//
// ( (unsigned int) GPIOA_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS13 ----------------------------------
// SVD Line: 2529
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// BS13
//
// [Bit 13] WO (@ 0x50000018) Port x set I/O pin 13
//
// ( (unsigned int) GPIOA_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS14 ----------------------------------
// SVD Line: 2535
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// BS14
//
// [Bit 14] WO (@ 0x50000018) Port x set I/O pin 14
//
// ( (unsigned int) GPIOA_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS15 ----------------------------------
// SVD Line: 2541
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// BS15
//
// [Bit 15] WO (@ 0x50000018) Port x set I/O pin 15
//
// ( (unsigned int) GPIOA_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 2547
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000018) Port x reset I/O pin 0
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 2553
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000018) Port x reset I/O pin 1
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 2559
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000018) Port x reset I/O pin 2
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 2565
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000018) Port x reset I/O pin 3
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 2571
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000018) Port x reset I/O pin 4
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 2577
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000018) Port x reset I/O pin 5
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 2583
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000018) Port x reset I/O pin 6
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 2589
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000018) Port x reset I/O pin 7
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR8 -----------------------------------
// SVD Line: 2595
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000018) Port x reset I/O pin 8
//
// ( (unsigned int) GPIOA_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR9 -----------------------------------
// SVD Line: 2601
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// BR9
//
// [Bit 25] WO (@ 0x50000018) Port x reset I/O pin 9
//
// ( (unsigned int) GPIOA_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR10 ----------------------------------
// SVD Line: 2607
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// BR10
//
// [Bit 26] WO (@ 0x50000018) Port x reset I/O pin 10
//
// ( (unsigned int) GPIOA_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR11 ----------------------------------
// SVD Line: 2613
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// BR11
//
// [Bit 27] WO (@ 0x50000018) Port x reset I/O pin 11
//
// ( (unsigned int) GPIOA_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR12 ----------------------------------
// SVD Line: 2619
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// BR12
//
// [Bit 28] WO (@ 0x50000018) Port x reset I/O pin 12
//
// ( (unsigned int) GPIOA_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR13 ----------------------------------
// SVD Line: 2625
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// BR13
//
// [Bit 29] WO (@ 0x50000018) Port x reset I/O pin 13
//
// ( (unsigned int) GPIOA_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR14 ----------------------------------
// SVD Line: 2631
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// BR14
//
// [Bit 30] WO (@ 0x50000018) Port x reset I/O pin 14
//
// ( (unsigned int) GPIOA_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR15 ----------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
// BR15
//
// [Bit 31] WO (@ 0x50000018) Port x reset I/O pin 15
//
// ( (unsigned int) GPIOA_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 2446
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 2645
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 2650
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock I/O pin 0
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 2655
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock I/O pin 1
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 2660
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock I/O pin 2
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 2665
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock I/O pin 3
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 2670
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock I/O pin 4
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 2675
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock I/O pin 5
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 2680
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock I/O pin 6
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 2685
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock I/O pin 7
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK8 ----------------------------------
// SVD Line: 2690
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000001C) Port x lock I/O pin 8
//
// ( (unsigned int) GPIOA_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK9 ----------------------------------
// SVD Line: 2695
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000001C) Port x lock I/O pin 9
//
// ( (unsigned int) GPIOA_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK10 ----------------------------------
// SVD Line: 2700
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000001C) Port x lock I/O pin 10
//
// ( (unsigned int) GPIOA_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK11 ----------------------------------
// SVD Line: 2705
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000001C) Port x lock I/O pin 11
//
// ( (unsigned int) GPIOA_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK12 ----------------------------------
// SVD Line: 2710
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000001C) Port x lock I/O pin 12
//
// ( (unsigned int) GPIOA_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK13 ----------------------------------
// SVD Line: 2715
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000001C) Port x lock I/O pin 13
//
// ( (unsigned int) GPIOA_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK14 ----------------------------------
// SVD Line: 2720
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000001C) Port x lock I/O pin 14
//
// ( (unsigned int) GPIOA_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK15 ----------------------------------
// SVD Line: 2725
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000001C) Port x lock I/O pin 15
//
// ( (unsigned int) GPIOA_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 2730
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Lock key
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 2645
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 2737
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 2742
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 2..0] RW (@ 0x50000020) Alternate function selection for port x I/O pin 0
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 2747
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 6..4] RW (@ 0x50000020) Alternate function selection for port x I/O pin 1
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 2752
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 10..8] RW (@ 0x50000020) Alternate function selection for port x I/O pin 2
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 2757
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 14..12] RW (@ 0x50000020) Alternate function selection for port x I/O pin 4
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 2762
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 18..16] RW (@ 0x50000020) Alternate function selection for port x I/O pin 4
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 2767
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 22..20] RW (@ 0x50000020) Alternate function selection for port x I/O pin 5
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 2772
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 26..24] RW (@ 0x50000020) Alternate function selection for port x I/O pin 6
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 2777
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 30..28] RW (@ 0x50000020) Alternate function selection for port x I/O pin 7
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0x7), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 2737
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0x77777777UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77777777) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_AFRH -------------------------------
// SVD Line: 2784
unsigned int GPIOA_AFRH __AT (0x50000024);
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL8 ---------------------------------
// SVD Line: 2789
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// AFSEL8
//
// [Bits 2..0] RW (@ 0x50000024) Alternate function selection for port x I/O pin 8
//
// ( (unsigned char)((GPIOA_AFRH >> 0) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL9 ---------------------------------
// SVD Line: 2794
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// AFSEL9
//
// [Bits 6..4] RW (@ 0x50000024) Alternate function selection for port x I/O pin 9
//
// ( (unsigned char)((GPIOA_AFRH >> 4) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL10 ---------------------------------
// SVD Line: 2799
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// AFSEL10
//
// [Bits 10..8] RW (@ 0x50000024) Alternate function selection for port x I/O pin 10
//
// ( (unsigned char)((GPIOA_AFRH >> 8) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL11 ---------------------------------
// SVD Line: 2804
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// AFSEL11
//
// [Bits 14..12] RW (@ 0x50000024) Alternate function selection for port x I/O pin 11
//
// ( (unsigned char)((GPIOA_AFRH >> 12) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL12 ---------------------------------
// SVD Line: 2809
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// AFSEL12
//
// [Bits 18..16] RW (@ 0x50000024) Alternate function selection for port x I/O pin 12
//
// ( (unsigned char)((GPIOA_AFRH >> 16) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL13 ---------------------------------
// SVD Line: 2814
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// AFSEL13
//
// [Bits 22..20] RW (@ 0x50000024) Alternate function selection for port x I/O pin 13
//
// ( (unsigned char)((GPIOA_AFRH >> 20) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL14 ---------------------------------
// SVD Line: 2819
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// AFSEL14
//
// [Bits 26..24] RW (@ 0x50000024) Alternate function selection for port x I/O pin 14
//
// ( (unsigned char)((GPIOA_AFRH >> 24) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL15 ---------------------------------
// SVD Line: 2824
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
// AFSEL15
//
// [Bits 30..28] RW (@ 0x50000024) Alternate function selection for port x I/O pin 15
//
// ( (unsigned char)((GPIOA_AFRH >> 28) & 0x7), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRH -----------------------------------
// SVD Line: 2784
// SFDITEM_REG__GPIOA_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000024) GPIO alternate function high register
// ( (unsigned int)((GPIOA_AFRH >> 0) & 0xFFFFFFFF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0x77777777UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77777777) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 2831
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 2836
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000028) Port x reset IO pin 0
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 2841
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000028) Port x reset IO pin 1
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 2846
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000028) Port x reset IO pin 2
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 2851
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000028) Port x reset IO pin 3
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 2856
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000028) Port x reset IO pin 4
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 2861
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000028) Port x reset IO pin 5
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 2866
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000028) Port x reset IO pin 6
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 2871
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000028) Port x reset IO pin 7
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR8 -----------------------------------
// SVD Line: 2876
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// BR8
//
// [Bit 8] RW (@ 0x50000028) Port x reset IO pin 8
//
// ( (unsigned int) GPIOA_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR9 -----------------------------------
// SVD Line: 2881
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// BR9
//
// [Bit 9] RW (@ 0x50000028) Port x reset IO pin 9
//
// ( (unsigned int) GPIOA_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR10 -----------------------------------
// SVD Line: 2886
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// BR10
//
// [Bit 10] RW (@ 0x50000028) Port x reset IO pin 10
//
// ( (unsigned int) GPIOA_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR11 -----------------------------------
// SVD Line: 2891
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// BR11
//
// [Bit 11] RW (@ 0x50000028) Port x reset IO pin 11
//
// ( (unsigned int) GPIOA_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR12 -----------------------------------
// SVD Line: 2896
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// BR12
//
// [Bit 12] RW (@ 0x50000028) Port x reset IO pin 12
//
// ( (unsigned int) GPIOA_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR13 -----------------------------------
// SVD Line: 2901
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// BR13
//
// [Bit 13] RW (@ 0x50000028) Port x reset IO pin 13
//
// ( (unsigned int) GPIOA_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR14 -----------------------------------
// SVD Line: 2906
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// BR14
//
// [Bit 14] RW (@ 0x50000028) Port x reset IO pin 14
//
// ( (unsigned int) GPIOA_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR15 -----------------------------------
// SVD Line: 2911
// - SFDITEM_FIELD__GPIOA_BRR_BR15
// BR15
//
// [Bit 15] RW (@ 0x50000028) Port x reset IO pin 15
//
// ( (unsigned int) GPIOA_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 2831
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// - SFDITEM_FIELD__GPIOA_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 1898
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_AFRH
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 2930
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 2935
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 2940
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 2945
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 2950
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 2930
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 2957
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 2962
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 2967
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 2972
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 2977
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 2957
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 2984
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2989
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2994
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2999
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 3004
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 2984
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 3011
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 3016
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 3021
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 3026
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 3031
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 3011
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 3038
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 3043
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 3049
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 3055
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 3061
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 3038
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 3069
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 3074
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 3079
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 3084
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 3089
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 3069
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 3096
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 3101
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 3106
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 3111
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 3116
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 3121
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 3126
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 3131
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 3136
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 3096
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0xF000FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF000F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 3143
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 3148
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 3153
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 3158
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 3163
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 3168
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 3143
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x1000FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1000F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 3175
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3180
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3185
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3190
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3195
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 3175
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 3202
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 3207
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 3212
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 3217
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 3222
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 3202
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 2920
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOF_MODER -------------------------------
// SVD Line: 3240
unsigned int GPIOF_MODER __AT (0x50001400);
// ------------------------------ Field Item: GPIOF_MODER_MODE0 ---------------------------------
// SVD Line: 3244
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 0) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE1 ---------------------------------
// SVD Line: 3249
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 2) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE2 ---------------------------------
// SVD Line: 3254
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 4) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE3 ---------------------------------
// SVD Line: 3259
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 6) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE4 ---------------------------------
// SVD Line: 3264
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 8) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE5 ---------------------------------
// SVD Line: 3269
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 10) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_MODER ----------------------------------
// SVD Line: 3240
// SFDITEM_REG__GPIOF_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50001400) MODER
// ( (unsigned int)((GPIOF_MODER >> 0) & 0xFFFFFFFF), ((GPIOF_MODER = (GPIOF_MODER & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
//
//
// --------------------------- Register Item Address: GPIOF_OTYPER ------------------------------
// SVD Line: 3276
unsigned int GPIOF_OTYPER __AT (0x50001404);
// ------------------------------ Field Item: GPIOF_OTYPER_OT0 ----------------------------------
// SVD Line: 3281
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT1 ----------------------------------
// SVD Line: 3286
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT2 ----------------------------------
// SVD Line: 3291
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT3 ----------------------------------
// SVD Line: 3296
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT4 ----------------------------------
// SVD Line: 3301
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT5 ----------------------------------
// SVD Line: 3306
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT5
//
//
//
// ------------------------------ Register RTree: GPIOF_OTYPER ----------------------------------
// SVD Line: 3276
// SFDITEM_REG__GPIOF_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50001404) GPIO port output type register
// ( (unsigned int)((GPIOF_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOF_OTYPER = (GPIOF_OTYPER & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
//
//
// -------------------------- Register Item Address: GPIOF_OSPEEDR ------------------------------
// SVD Line: 3313
unsigned int GPIOF_OSPEEDR __AT (0x50001408);
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 3318
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 0) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 3323
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 2) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 3328
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 4) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 3333
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 6) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 3338
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 8) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 3343
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 10) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOF_OSPEEDR ---------------------------------
// SVD Line: 3313
// SFDITEM_REG__GPIOF_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50001408) GPIO port output speed register
// ( (unsigned int)((GPIOF_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
//
//
// --------------------------- Register Item Address: GPIOF_PUPDR -------------------------------
// SVD Line: 3350
unsigned int GPIOF_PUPDR __AT (0x5000140C);
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD0 ---------------------------------
// SVD Line: 3355
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 0) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD1 ---------------------------------
// SVD Line: 3360
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 2) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD2 ---------------------------------
// SVD Line: 3365
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 4) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD3 ---------------------------------
// SVD Line: 3370
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 6) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD4 ---------------------------------
// SVD Line: 3375
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 8) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD5 ---------------------------------
// SVD Line: 3380
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 10) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_PUPDR ----------------------------------
// SVD Line: 3350
// SFDITEM_REG__GPIOF_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000140C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOF_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
//
//
// ---------------------------- Register Item Address: GPIOF_IDR --------------------------------
// SVD Line: 3387
unsigned int GPIOF_IDR __AT (0x50001410);
// -------------------------------- Field Item: GPIOF_IDR_ID0 -----------------------------------
// SVD Line: 3392
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID1 -----------------------------------
// SVD Line: 3398
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID2 -----------------------------------
// SVD Line: 3404
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID3 -----------------------------------
// SVD Line: 3410
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID4 -----------------------------------
// SVD Line: 3416
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID5 -----------------------------------
// SVD Line: 3422
// - SFDITEM_FIELD__GPIOF_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID5
//
//
//
// -------------------------------- Register RTree: GPIOF_IDR -----------------------------------
// SVD Line: 3387
// SFDITEM_REG__GPIOF_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50001410) GPIO port input data register
// ( (unsigned int)((GPIOF_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// - SFDITEM_FIELD__GPIOF_IDR_ID5
//
//
// ---------------------------- Register Item Address: GPIOF_ODR --------------------------------
// SVD Line: 3430
unsigned int GPIOF_ODR __AT (0x50001414);
// -------------------------------- Field Item: GPIOF_ODR_OD0 -----------------------------------
// SVD Line: 3435
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD1 -----------------------------------
// SVD Line: 3440
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD2 -----------------------------------
// SVD Line: 3445
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD3 -----------------------------------
// SVD Line: 3450
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD4 -----------------------------------
// SVD Line: 3455
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD5 -----------------------------------
// SVD Line: 3460
// - SFDITEM_FIELD__GPIOF_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD5
//
//
//
// -------------------------------- Register RTree: GPIOF_ODR -----------------------------------
// SVD Line: 3430
// SFDITEM_REG__GPIOF_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50001414) GPIO port output data register
// ( (unsigned int)((GPIOF_ODR >> 0) & 0xFFFFFFFF), ((GPIOF_ODR = (GPIOF_ODR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// - SFDITEM_FIELD__GPIOF_ODR_OD5
//
//
// ---------------------------- Register Item Address: GPIOF_BSRR -------------------------------
// SVD Line: 3467
unsigned int GPIOF_BSRR __AT (0x50001418);
// ------------------------------- Field Item: GPIOF_BSRR_BS0 -----------------------------------
// SVD Line: 3472
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS1 -----------------------------------
// SVD Line: 3477
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS2 -----------------------------------
// SVD Line: 3482
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS3 -----------------------------------
// SVD Line: 3487
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS4 -----------------------------------
// SVD Line: 3492
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS5 -----------------------------------
// SVD Line: 3497
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR0 -----------------------------------
// SVD Line: 3502
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR1 -----------------------------------
// SVD Line: 3507
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR2 -----------------------------------
// SVD Line: 3512
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR3 -----------------------------------
// SVD Line: 3517
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR4 -----------------------------------
// SVD Line: 3522
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR5 -----------------------------------
// SVD Line: 3527
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR5
//
//
//
// ------------------------------- Register RTree: GPIOF_BSRR -----------------------------------
// SVD Line: 3467
// SFDITEM_REG__GPIOF_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50001418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOF_BSRR >> 0) & 0xFFFFFFFF), ((GPIOF_BSRR = (GPIOF_BSRR & ~(0x3F003FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F003F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
//
//
// ---------------------------- Register Item Address: GPIOF_LCKR -------------------------------
// SVD Line: 3534
unsigned int GPIOF_LCKR __AT (0x5000141C);
// ------------------------------- Field Item: GPIOF_LCKR_LCK0 ----------------------------------
// SVD Line: 3539
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK1 ----------------------------------
// SVD Line: 3544
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK2 ----------------------------------
// SVD Line: 3549
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK3 ----------------------------------
// SVD Line: 3554
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK4 ----------------------------------
// SVD Line: 3559
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK5 ----------------------------------
// SVD Line: 3564
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCKK ----------------------------------
// SVD Line: 3569
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOF_LCKR -----------------------------------
// SVD Line: 3534
// SFDITEM_REG__GPIOF_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000141C) GPIO port configuration lock register
// ( (unsigned int)((GPIOF_LCKR >> 0) & 0xFFFFFFFF), ((GPIOF_LCKR = (GPIOF_LCKR & ~(0x1003FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1003F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOF_AFRL -------------------------------
// SVD Line: 3576
unsigned int GPIOF_AFRL __AT (0x50001420);
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3581
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 0) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3586
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 4) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3591
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 8) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3596
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 12) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3601
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 16) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3606
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 20) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_AFRL -----------------------------------
// SVD Line: 3576
// SFDITEM_REG__GPIOF_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50001420) GPIO alternate function low register
// ( (unsigned int)((GPIOF_AFRL >> 0) & 0xFFFFFFFF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
//
//
// ---------------------------- Register Item Address: GPIOF_BRR --------------------------------
// SVD Line: 3613
unsigned int GPIOF_BRR __AT (0x50001428);
// -------------------------------- Field Item: GPIOF_BRR_BR0 -----------------------------------
// SVD Line: 3618
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR1 -----------------------------------
// SVD Line: 3623
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR2 -----------------------------------
// SVD Line: 3628
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR3 -----------------------------------
// SVD Line: 3633
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR4 -----------------------------------
// SVD Line: 3638
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR5 -----------------------------------
// SVD Line: 3643
// - SFDITEM_FIELD__GPIOF_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR5
//
//
//
// -------------------------------- Register RTree: GPIOF_BRR -----------------------------------
// SVD Line: 3613
// SFDITEM_REG__GPIOF_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50001428) port bit reset register
// ( (unsigned int)((GPIOF_BRR >> 0) & 0xFFFFFFFF), ((GPIOF_BRR = (GPIOF_BRR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// - SFDITEM_FIELD__GPIOF_BRR_BR5
//
//
// --------------------------------- Peripheral View: GPIOF -------------------------------------
// SVD Line: 3231
// GPIOF
// GPIOF
// - SFDITEM_REG__GPIOF_MODER
// - SFDITEM_REG__GPIOF_OTYPER
// - SFDITEM_REG__GPIOF_OSPEEDR
// - SFDITEM_REG__GPIOF_PUPDR
// - SFDITEM_REG__GPIOF_IDR
// - SFDITEM_REG__GPIOF_ODR
// - SFDITEM_REG__GPIOF_BSRR
// - SFDITEM_REG__GPIOF_LCKR
// - SFDITEM_REG__GPIOF_AFRL
// - SFDITEM_REG__GPIOF_BRR
//
//
// ----------------------------- Register Item Address: I2C_CR1 ---------------------------------
// SVD Line: 3667
unsigned short I2C_CR1 __AT (0x40005400);
// --------------------------------- Field Item: I2C_CR1_PE -------------------------------------
// SVD Line: 3673
// - SFDITEM_FIELD__I2C_CR1_PE
// PE
//
// [Bit 0] RW (@ 0x40005400) Peripheral enable
//
// ( (unsigned short) I2C_CR1 )
// PE
//
//
//
// -------------------------------- Field Item: I2C_CR1_WUPEN -----------------------------------
// SVD Line: 3678
// - SFDITEM_FIELD__I2C_CR1_WUPEN
// WUPEN
//
// [Bit 2] RW (@ 0x40005400) Wakeup from Stop mode enable
//
// ( (unsigned short) I2C_CR1 )
// WUPEN
//
//
//
// -------------------------------- Field Item: I2C_CR1_ENGC ------------------------------------
// SVD Line: 3683
// - SFDITEM_FIELD__I2C_CR1_ENGC
// ENGC
//
// [Bit 6] RW (@ 0x40005400) General call enable
//
// ( (unsigned short) I2C_CR1 )
// ENGC
//
//
//
// ------------------------------ Field Item: I2C_CR1_NOSTRETCH ---------------------------------
// SVD Line: 3688
// - SFDITEM_FIELD__I2C_CR1_NOSTRETCH
// NOSTRETCH
//
// [Bit 7] RW (@ 0x40005400) Clock stretching disable (Slave mode)
//
// ( (unsigned short) I2C_CR1 )
// NOSTRETCH
//
//
//
// -------------------------------- Field Item: I2C_CR1_START -----------------------------------
// SVD Line: 3693
// - SFDITEM_FIELD__I2C_CR1_START
// START
//
// [Bit 8] RW (@ 0x40005400) Start generation
//
// ( (unsigned short) I2C_CR1 )
// START
//
//
//
// -------------------------------- Field Item: I2C_CR1_STOP ------------------------------------
// SVD Line: 3698
// - SFDITEM_FIELD__I2C_CR1_STOP
// STOP
//
// [Bit 9] RW (@ 0x40005400) Stop generation
//
// ( (unsigned short) I2C_CR1 )
// STOP
//
//
//
// --------------------------------- Field Item: I2C_CR1_ACK ------------------------------------
// SVD Line: 3703
// - SFDITEM_FIELD__I2C_CR1_ACK
// ACK
//
// [Bit 10] RW (@ 0x40005400) Acknowledge enable
//
// ( (unsigned short) I2C_CR1 )
// ACK
//
//
//
// --------------------------------- Field Item: I2C_CR1_POS ------------------------------------
// SVD Line: 3708
// - SFDITEM_FIELD__I2C_CR1_POS
// POS
//
// [Bit 11] RW (@ 0x40005400) Acknowledge(for data reception)
//
// ( (unsigned short) I2C_CR1 )
// POS
//
//
//
// -------------------------------- Field Item: I2C_CR1_SWRST -----------------------------------
// SVD Line: 3713
// - SFDITEM_FIELD__I2C_CR1_SWRST
// SWRST
//
// [Bit 15] RW (@ 0x40005400) Software reset
//
// ( (unsigned short) I2C_CR1 )
// SWRST
//
//
//
// --------------------------------- Register RTree: I2C_CR1 ------------------------------------
// SVD Line: 3667
// SFDITEM_REG__I2C_CR1
// CR1
//
// [Bits 15..0] RW (@ 0x40005400) Control register 1
// ( (unsigned short)((I2C_CR1 >> 0) & 0xFFFF), ((I2C_CR1 = (I2C_CR1 & ~(0x8FC5UL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x8FC5) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CR1_PE
// - SFDITEM_FIELD__I2C_CR1_WUPEN
// - SFDITEM_FIELD__I2C_CR1_ENGC
// - SFDITEM_FIELD__I2C_CR1_NOSTRETCH
// - SFDITEM_FIELD__I2C_CR1_START
// - SFDITEM_FIELD__I2C_CR1_STOP
// - SFDITEM_FIELD__I2C_CR1_ACK
// - SFDITEM_FIELD__I2C_CR1_POS
// - SFDITEM_FIELD__I2C_CR1_SWRST
//
//
// ----------------------------- Register Item Address: I2C_CR2 ---------------------------------
// SVD Line: 3720
unsigned int I2C_CR2 __AT (0x40005404);
// -------------------------------- Field Item: I2C_CR2_FREQ ------------------------------------
// SVD Line: 3725
// - SFDITEM_FIELD__I2C_CR2_FREQ
// FREQ
//
// [Bits 6..0] RW (@ 0x40005404) Peripheral clock frequency
//
// ( (unsigned char)((I2C_CR2 >> 0) & 0x7F), ((I2C_CR2 = (I2C_CR2 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITERREN ----------------------------------
// SVD Line: 3730
// - SFDITEM_FIELD__I2C_CR2_ITERREN
// ITERREN
//
// [Bit 8] RW (@ 0x40005404) Error interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITERREN
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITEVTEN ----------------------------------
// SVD Line: 3735
// - SFDITEM_FIELD__I2C_CR2_ITEVTEN
// ITEVTEN
//
// [Bit 9] RW (@ 0x40005404) Event interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITEVTEN
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITBUFEN ----------------------------------
// SVD Line: 3740
// - SFDITEM_FIELD__I2C_CR2_ITBUFEN
// ITBUFEN
//
// [Bit 10] RW (@ 0x40005404) Buffer interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITBUFEN
//
//
//
// --------------------------------- Register RTree: I2C_CR2 ------------------------------------
// SVD Line: 3720
// SFDITEM_REG__I2C_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40005404) Control register 2
// ( (unsigned int)((I2C_CR2 >> 0) & 0xFFFFFFFF), ((I2C_CR2 = (I2C_CR2 & ~(0x77FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77F) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CR2_FREQ
// - SFDITEM_FIELD__I2C_CR2_ITERREN
// - SFDITEM_FIELD__I2C_CR2_ITEVTEN
// - SFDITEM_FIELD__I2C_CR2_ITBUFEN
//
//
// ----------------------------- Register Item Address: I2C_OAR1 --------------------------------
// SVD Line: 3747
unsigned int I2C_OAR1 __AT (0x40005408);
// -------------------------------- Field Item: I2C_OAR1_ADD ------------------------------------
// SVD Line: 3752
// - SFDITEM_FIELD__I2C_OAR1_ADD
// ADD
//
// [Bits 7..1] RW (@ 0x40005408) Interface address
//
// ( (unsigned char)((I2C_OAR1 >> 1) & 0x7F), ((I2C_OAR1 = (I2C_OAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C_OAR1 ------------------------------------
// SVD Line: 3747
// SFDITEM_REG__I2C_OAR1
// OAR1
//
// [Bits 31..0] RW (@ 0x40005408) Own address register 1
// ( (unsigned int)((I2C_OAR1 >> 0) & 0xFFFFFFFF), ((I2C_OAR1 = (I2C_OAR1 & ~(0xFEUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFE) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_OAR1_ADD
//
//
// ------------------------------ Register Item Address: I2C_DR ---------------------------------
// SVD Line: 3759
unsigned int I2C_DR __AT (0x40005410);
// ---------------------------------- Field Item: I2C_DR_DR -------------------------------------
// SVD Line: 3764
// - SFDITEM_FIELD__I2C_DR_DR
// DR
//
// [Bits 7..0] RW (@ 0x40005410) 8-bit data register
//
// ( (unsigned char)((I2C_DR >> 0) & 0xFF), ((I2C_DR = (I2C_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: I2C_DR -------------------------------------
// SVD Line: 3759
// SFDITEM_REG__I2C_DR
// DR
//
// [Bits 31..0] RW (@ 0x40005410) Data register
// ( (unsigned int)((I2C_DR >> 0) & 0xFFFFFFFF), ((I2C_DR = (I2C_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_DR_DR
//
//
// ----------------------------- Register Item Address: I2C_SR1 ---------------------------------
// SVD Line: 3771
unsigned int I2C_SR1 __AT (0x40005414);
// --------------------------------- Field Item: I2C_SR1_SB -------------------------------------
// SVD Line: 3776
// - SFDITEM_FIELD__I2C_SR1_SB
// SB
//
// [Bit 0] RO (@ 0x40005414) Start bit (Master mode)
//
// ( (unsigned int) I2C_SR1 )
// SB
//
//
//
// -------------------------------- Field Item: I2C_SR1_ADDR ------------------------------------
// SVD Line: 3782
// - SFDITEM_FIELD__I2C_SR1_ADDR
// ADDR
//
// [Bit 1] RO (@ 0x40005414) Address sent (master mode)/matched (slave mode)
//
// ( (unsigned int) I2C_SR1 )
// ADDR
//
//
//
// --------------------------------- Field Item: I2C_SR1_BTF ------------------------------------
// SVD Line: 3788
// - SFDITEM_FIELD__I2C_SR1_BTF
// BTF
//
// [Bit 2] RO (@ 0x40005414) Byte transfer finished
//
// ( (unsigned int) I2C_SR1 )
// BTF
//
//
//
// -------------------------------- Field Item: I2C_SR1_STOPF -----------------------------------
// SVD Line: 3794
// - SFDITEM_FIELD__I2C_SR1_STOPF
// STOPF
//
// [Bit 4] RO (@ 0x40005414) Stop detection (slave mode)
//
// ( (unsigned int) I2C_SR1 )
// STOPF
//
//
//
// -------------------------------- Field Item: I2C_SR1_RXNE ------------------------------------
// SVD Line: 3800
// - SFDITEM_FIELD__I2C_SR1_RXNE
// RXNE
//
// [Bit 6] RO (@ 0x40005414) Data register not empty (receivers)
//
// ( (unsigned int) I2C_SR1 )
// RXNE
//
//
//
// --------------------------------- Field Item: I2C_SR1_TXE ------------------------------------
// SVD Line: 3806
// - SFDITEM_FIELD__I2C_SR1_TXE
// TXE
//
// [Bit 7] RO (@ 0x40005414) Data register empty (transmitters)
//
// ( (unsigned int) I2C_SR1 )
// TXE
//
//
//
// -------------------------------- Field Item: I2C_SR1_BERR ------------------------------------
// SVD Line: 3812
// - SFDITEM_FIELD__I2C_SR1_BERR
// BERR
//
// [Bit 8] RW (@ 0x40005414) Bus error
//
// ( (unsigned int) I2C_SR1 )
// BERR
//
//
//
// -------------------------------- Field Item: I2C_SR1_ARLO ------------------------------------
// SVD Line: 3817
// - SFDITEM_FIELD__I2C_SR1_ARLO
// ARLO
//
// [Bit 9] RW (@ 0x40005414) Arbitration lost (master mode)
//
// ( (unsigned int) I2C_SR1 )
// ARLO
//
//
//
// --------------------------------- Field Item: I2C_SR1_AF -------------------------------------
// SVD Line: 3822
// - SFDITEM_FIELD__I2C_SR1_AF
// AF
//
// [Bit 10] RW (@ 0x40005414) Acknowledge failure
//
// ( (unsigned int) I2C_SR1 )
// AF
//
//
//
// --------------------------------- Field Item: I2C_SR1_OVR ------------------------------------
// SVD Line: 3827
// - SFDITEM_FIELD__I2C_SR1_OVR
// OVR
//
// [Bit 11] RW (@ 0x40005414) Overrun/Underrun
//
// ( (unsigned int) I2C_SR1 )
// OVR
//
//
//
// ------------------------------- Field Item: I2C_SR1_TIMEOUT ----------------------------------
// SVD Line: 3832
// - SFDITEM_FIELD__I2C_SR1_TIMEOUT
// TIMEOUT
//
// [Bit 14] RW (@ 0x40005414) Timeout or Tlow error
//
// ( (unsigned int) I2C_SR1 )
// TIMEOUT
//
//
//
// --------------------------------- Register RTree: I2C_SR1 ------------------------------------
// SVD Line: 3771
// SFDITEM_REG__I2C_SR1
// SR1
//
// [Bits 31..0] RW (@ 0x40005414) Status register 1
// ( (unsigned int)((I2C_SR1 >> 0) & 0xFFFFFFFF), ((I2C_SR1 = (I2C_SR1 & ~(0x4F00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4F00) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_SR1_SB
// - SFDITEM_FIELD__I2C_SR1_ADDR
// - SFDITEM_FIELD__I2C_SR1_BTF
// - SFDITEM_FIELD__I2C_SR1_STOPF
// - SFDITEM_FIELD__I2C_SR1_RXNE
// - SFDITEM_FIELD__I2C_SR1_TXE
// - SFDITEM_FIELD__I2C_SR1_BERR
// - SFDITEM_FIELD__I2C_SR1_ARLO
// - SFDITEM_FIELD__I2C_SR1_AF
// - SFDITEM_FIELD__I2C_SR1_OVR
// - SFDITEM_FIELD__I2C_SR1_TIMEOUT
//
//
// ----------------------------- Register Item Address: I2C_SR2 ---------------------------------
// SVD Line: 3839
unsigned int I2C_SR2 __AT (0x40005418);
// --------------------------------- Field Item: I2C_SR2_MSL ------------------------------------
// SVD Line: 3844
// - SFDITEM_FIELD__I2C_SR2_MSL
// MSL
//
// [Bit 0] RO (@ 0x40005418) Master/slave
//
// ( (unsigned int) I2C_SR2 )
// MSL
//
//
//
// -------------------------------- Field Item: I2C_SR2_BUSY ------------------------------------
// SVD Line: 3850
// - SFDITEM_FIELD__I2C_SR2_BUSY
// BUSY
//
// [Bit 1] RO (@ 0x40005418) Bus busy
//
// ( (unsigned int) I2C_SR2 )
// BUSY
//
//
//
// --------------------------------- Field Item: I2C_SR2_TRA ------------------------------------
// SVD Line: 3856
// - SFDITEM_FIELD__I2C_SR2_TRA
// TRA
//
// [Bit 2] RO (@ 0x40005418) Transmitter/receiver
//
// ( (unsigned int) I2C_SR2 )
// TRA
//
//
//
// ------------------------------- Field Item: I2C_SR2_GENCALL ----------------------------------
// SVD Line: 3862
// - SFDITEM_FIELD__I2C_SR2_GENCALL
// GENCALL
//
// [Bit 4] RO (@ 0x40005418) General call address (Slave mode)
//
// ( (unsigned int) I2C_SR2 )
// GENCALL
//
//
//
// --------------------------------- Register RTree: I2C_SR2 ------------------------------------
// SVD Line: 3839
// SFDITEM_REG__I2C_SR2
// SR2
//
// [Bits 31..0] RW (@ 0x40005418) Status register 2
// ( (unsigned int)((I2C_SR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__I2C_SR2_MSL
// - SFDITEM_FIELD__I2C_SR2_BUSY
// - SFDITEM_FIELD__I2C_SR2_TRA
// - SFDITEM_FIELD__I2C_SR2_GENCALL
//
//
// ----------------------------- Register Item Address: I2C_CCR ---------------------------------
// SVD Line: 3870
unsigned int I2C_CCR __AT (0x4000541C);
// --------------------------------- Field Item: I2C_CCR_CCR ------------------------------------
// SVD Line: 3875
// - SFDITEM_FIELD__I2C_CCR_CCR
// CCR
//
// [Bits 11..0] RW (@ 0x4000541C) Clock control register in Fm/Sm mode (Master mode)
//
// ( (unsigned short)((I2C_CCR >> 0) & 0xFFF), ((I2C_CCR = (I2C_CCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: I2C_CCR_FP -------------------------------------
// SVD Line: 3880
// - SFDITEM_FIELD__I2C_CCR_FP
// FP
//
// [Bit 13] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C_CCR )
// FP
//
//
//
// -------------------------------- Field Item: I2C_CCR_DUTY ------------------------------------
// SVD Line: 3885
// - SFDITEM_FIELD__I2C_CCR_DUTY
// DUTY
//
// [Bit 14] RW (@ 0x4000541C) Fm mode duty cycle
//
// ( (unsigned int) I2C_CCR )
// DUTY
//
//
//
// --------------------------------- Field Item: I2C_CCR_FS -------------------------------------
// SVD Line: 3890
// - SFDITEM_FIELD__I2C_CCR_FS
// FS
//
// [Bit 15] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C_CCR )
// FS
//
//
//
// --------------------------------- Register RTree: I2C_CCR ------------------------------------
// SVD Line: 3870
// SFDITEM_REG__I2C_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x4000541C) Clock control register
// ( (unsigned int)((I2C_CCR >> 0) & 0xFFFFFFFF), ((I2C_CCR = (I2C_CCR & ~(0xEFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xEFFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CCR_CCR
// - SFDITEM_FIELD__I2C_CCR_FP
// - SFDITEM_FIELD__I2C_CCR_DUTY
// - SFDITEM_FIELD__I2C_CCR_FS
//
//
// ---------------------------- Register Item Address: I2C_TRISE --------------------------------
// SVD Line: 3897
unsigned int I2C_TRISE __AT (0x40005420);
// ------------------------------- Field Item: I2C_TRISE_TRISE ----------------------------------
// SVD Line: 3902
// - SFDITEM_FIELD__I2C_TRISE_TRISE
// TRISE
//
// [Bits 6..0] RW (@ 0x40005420) Maximum rise time in Fm+/Fm/Sm mode (Master mode)
//
// ( (unsigned char)((I2C_TRISE >> 0) & 0x7F), ((I2C_TRISE = (I2C_TRISE & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: I2C_TRISE_TDATAHOLD --------------------------------
// SVD Line: 3907
// - SFDITEM_FIELD__I2C_TRISE_TDATAHOLD
// TDATAHOLD
//
// [Bits 11..7] RW (@ 0x40005420) Data hold time
//
// ( (unsigned char)((I2C_TRISE >> 7) & 0x1F), ((I2C_TRISE = (I2C_TRISE & ~(0x1FUL << 7 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 7 ) ) ))
//
//
//
// --------------------------- Field Item: I2C_TRISE_TDATAHOLD_SEL ------------------------------
// SVD Line: 3912
// - SFDITEM_FIELD__I2C_TRISE_TDATAHOLD_SEL
// TDATAHOLD_SEL
//
// [Bit 12] RW (@ 0x40005420) Data hold time select
//
// ( (unsigned int) I2C_TRISE )
// TDATAHOLD_SEL
//
//
//
// -------------------------------- Register RTree: I2C_TRISE -----------------------------------
// SVD Line: 3897
// SFDITEM_REG__I2C_TRISE
// TRISE
//
// [Bits 31..0] RW (@ 0x40005420) TRISE register
// ( (unsigned int)((I2C_TRISE >> 0) & 0xFFFFFFFF), ((I2C_TRISE = (I2C_TRISE & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_TRISE_TRISE
// - SFDITEM_FIELD__I2C_TRISE_TDATAHOLD
// - SFDITEM_FIELD__I2C_TRISE_TDATAHOLD_SEL
//
//
// ------------------------------ Register Item Address: I2C_WT ---------------------------------
// SVD Line: 3919
unsigned int I2C_WT __AT (0x40005424);
// --------------------------------- Field Item: I2C_WT_DIV -------------------------------------
// SVD Line: 3924
// - SFDITEM_FIELD__I2C_WT_DIV
// DIV
//
// [Bits 1..0] RW (@ 0x40005424) PCLK division
//
// ( (unsigned char)((I2C_WT >> 0) & 0x3), ((I2C_WT = (I2C_WT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: I2C_WT_CNT -------------------------------------
// SVD Line: 3929
// - SFDITEM_FIELD__I2C_WT_CNT
// CNT
//
// [Bits 3..2] RW (@ 0x40005424) Timeout count number
//
// ( (unsigned char)((I2C_WT >> 2) & 0x3), ((I2C_WT = (I2C_WT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------------- Register RTree: I2C_WT -------------------------------------
// SVD Line: 3919
// SFDITEM_REG__I2C_WT
// WT
//
// [Bits 31..0] RW (@ 0x40005424) Wakeup Time register
// ( (unsigned int)((I2C_WT >> 0) & 0xFFFFFFFF), ((I2C_WT = (I2C_WT & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_WT_DIV
// - SFDITEM_FIELD__I2C_WT_CNT
//
//
// ---------------------------------- Peripheral View: I2C --------------------------------------
// SVD Line: 3652
// I2C
// I2C
// - SFDITEM_REG__I2C_CR1
// - SFDITEM_REG__I2C_CR2
// - SFDITEM_REG__I2C_OAR1
// - SFDITEM_REG__I2C_DR
// - SFDITEM_REG__I2C_SR1
// - SFDITEM_REG__I2C_SR2
// - SFDITEM_REG__I2C_CCR
// - SFDITEM_REG__I2C_TRISE
// - SFDITEM_REG__I2C_WT
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 3948
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 3953
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] WO (@ 0x40003000) Key value
//
// ( (unsigned short)((IWDG_KR >> 0) & 0x0), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 3948
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] RW (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 3961
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 3966
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) Prescaler divider
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 3961
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 3973
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 3978
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) Watchdog counter reload value
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 3973
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 3985
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 3990
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 3996
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 3985
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RW (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 3938
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM1_ISR -------------------------------
// SVD Line: 4022
unsigned int LPTIM1_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM1_ISR_ARRM ----------------------------------
// SVD Line: 4029
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM1_ISR )
// ARRM
//
//
//
// ------------------------------ Field Item: LPTIM1_ISR_ARROK ----------------------------------
// SVD Line: 4034
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload match update OK
//
// ( (unsigned int) LPTIM1_ISR )
// ARROK
//
//
//
// ------------------------------- Register RTree: LPTIM1_ISR -----------------------------------
// SVD Line: 4022
// SFDITEM_REG__LPTIM1_ISR
// ISR
//
// [Bits 31..0] RO (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM1_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM1_ICR -------------------------------
// SVD Line: 4041
unsigned int LPTIM1_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM1_ICR_ARRMCF ---------------------------------
// SVD Line: 4048
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] WO (@ 0x40007C04) Autoreload match Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARRMCF
//
//
//
// ----------------------------- Field Item: LPTIM1_ICR_ARROKCF ---------------------------------
// SVD Line: 4053
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] WO (@ 0x40007C04) Autoreload match update OK Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARROKCF
//
//
//
// ------------------------------- Register RTree: LPTIM1_ICR -----------------------------------
// SVD Line: 4041
// SFDITEM_REG__LPTIM1_ICR
// ICR
//
// [Bits 31..0] WO (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM1_ICR >> 0) & 0xFFFFFFFF), ((LPTIM1_ICR = (LPTIM1_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM1_IER -------------------------------
// SVD Line: 4060
unsigned int LPTIM1_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM1_IER_ARRMIE ---------------------------------
// SVD Line: 4066
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload matchInterrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARRMIE
//
//
//
// ----------------------------- Field Item: LPTIM1_IER_ARROKIE ---------------------------------
// SVD Line: 4071
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload match update OK Interrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARROKIE
//
//
//
// ------------------------------- Register RTree: LPTIM1_IER -----------------------------------
// SVD Line: 4060
// SFDITEM_REG__LPTIM1_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM1_IER >> 0) & 0xFFFFFFFF), ((LPTIM1_IER = (LPTIM1_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
//
//
// --------------------------- Register Item Address: LPTIM1_CFGR -------------------------------
// SVD Line: 4078
unsigned int LPTIM1_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM1_CFGR_PRESC ---------------------------------
// SVD Line: 4084
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM1_CFGR >> 9) & 0x7), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM1_CFGR_PRELOAD --------------------------------
// SVD Line: 4089
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM1_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM1_CFGR ----------------------------------
// SVD Line: 4078
// SFDITEM_REG__LPTIM1_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM1_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
//
//
// ---------------------------- Register Item Address: LPTIM1_CR --------------------------------
// SVD Line: 4096
unsigned int LPTIM1_CR __AT (0x40007C10);
// ------------------------------ Field Item: LPTIM1_CR_ENABLE ----------------------------------
// SVD Line: 4102
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM Enable
//
// ( (unsigned int) LPTIM1_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_SNGSTRT ---------------------------------
// SVD Line: 4107
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in single mode
//
// ( (unsigned int) LPTIM1_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_CNTSTRT ---------------------------------
// SVD Line: 4112
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) CNTSTRT
//
// ( (unsigned int) LPTIM1_CR )
// CNTSTRT
//
//
//
// ----------------------------- Field Item: LPTIM1_CR_COUNTRST ---------------------------------
// SVD Line: 4117
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) Reset counter
//
// ( (unsigned int) LPTIM1_CR )
// COUNTRST
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_RSTARE ----------------------------------
// SVD Line: 4122
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM1_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM1_CR -----------------------------------
// SVD Line: 4096
// SFDITEM_REG__LPTIM1_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM1_CR >> 0) & 0xFFFFFFFF), ((LPTIM1_CR = (LPTIM1_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM1_ARR -------------------------------
// SVD Line: 4129
unsigned int LPTIM1_ARR __AT (0x40007C18);
// ------------------------------- Field Item: LPTIM1_ARR_ARR -----------------------------------
// SVD Line: 4136
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM1_ARR >> 0) & 0xFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPTIM1_ARR -----------------------------------
// SVD Line: 4129
// SFDITEM_REG__LPTIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM1_ARR >> 0) & 0xFFFFFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM1_CNT -------------------------------
// SVD Line: 4143
unsigned int LPTIM1_CNT __AT (0x40007C1C);
// ------------------------------- Field Item: LPTIM1_CNT_CNT -----------------------------------
// SVD Line: 4150
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM1_CNT >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: LPTIM1_CNT -----------------------------------
// SVD Line: 4143
// SFDITEM_REG__LPTIM1_CNT
// CNT
//
// [Bits 31..0] RO (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM1_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM1 ------------------------------------
// SVD Line: 4006
// LPTIM1
// LPTIM1
// - SFDITEM_REG__LPTIM1_ISR
// - SFDITEM_REG__LPTIM1_ICR
// - SFDITEM_REG__LPTIM1_IER
// - SFDITEM_REG__LPTIM1_CFGR
// - SFDITEM_REG__LPTIM1_CR
// - SFDITEM_REG__LPTIM1_ARR
// - SFDITEM_REG__LPTIM1_CNT
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 4169
unsigned int PWR_CR1 __AT (0x40007000);
// --------------------------------- Field Item: PWR_CR1_DBP ------------------------------------
// SVD Line: 4174
// - SFDITEM_FIELD__PWR_CR1_DBP
// DBP
//
// [Bit 8] RW (@ 0x40007000) dbg mode protect enable
//
// ( (unsigned int) PWR_CR1 )
// DBP
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 4179
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) flash sleep time control
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------------- Field Item: PWR_CR1_LPR ------------------------------------
// SVD Line: 4184
// - SFDITEM_FIELD__PWR_CR1_LPR
// LPR
//
// [Bits 15..14] RW (@ 0x40007000) pmu mode control
//
// ( (unsigned char)((PWR_CR1 >> 14) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// --------------------------- Field Item: PWR_CR1_SRAM_RETV_CTRL -------------------------------
// SVD Line: 4189
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV_CTRL
// SRAM_RETV_CTRL
//
// [Bits 18..17] RW (@ 0x40007000) sram retev control
//
// ( (unsigned char)((PWR_CR1 >> 17) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 17 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 17 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_HSION_CTRL ---------------------------------
// SVD Line: 4194
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
// HSION_CTRL
//
// [Bit 19] RW (@ 0x40007000) HSION CTRL
//
// ( (unsigned int) PWR_CR1 )
// HSION_CTRL
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 4169
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0xEF100UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xEF100) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_DBP
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_LPR
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV_CTRL
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 4159
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 4218
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 4223
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI clock enable bit
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 4228
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RO (@ 0x40021000) HSI clock ready logo
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 4234
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI generates the crossover factor when HSISYS clocks
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEON ------------------------------------
// SVD Line: 4239
// - SFDITEM_FIELD__RCC_CR_HSEON
// HSEON
//
// [Bit 16] RW (@ 0x40021000) HSE crystal oscillator enabled
//
// ( (unsigned int) RCC_CR )
// HSEON
//
//
//
// -------------------------------- Field Item: RCC_CR_HSERDY -----------------------------------
// SVD Line: 4244
// - SFDITEM_FIELD__RCC_CR_HSERDY
// HSERDY
//
// [Bit 17] RO (@ 0x40021000) HSE crystal clock ready flag
//
// ( (unsigned int) RCC_CR )
// HSERDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEBYP -----------------------------------
// SVD Line: 4250
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// HSEBYP
//
// [Bit 18] RW (@ 0x40021000) HSE shields the crystal oscillator and selects the pin input clock
//
// ( (unsigned int) RCC_CR )
// HSEBYP
//
//
//
// ------------------------------ Field Item: RCC_CR_HSE_CSSON ----------------------------------
// SVD Line: 4255
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
// HSE_CSSON
//
// [Bit 19] RW (@ 0x40021000) HSE clock security system enabled
//
// ( (unsigned int) RCC_CR )
// HSE_CSSON
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 4218
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0xD3900UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xD3900) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// - SFDITEM_FIELD__RCC_CR_HSEON
// - SFDITEM_FIELD__RCC_CR_HSERDY
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 4262
unsigned int RCC_ICSCR __AT (0x40021004);
// ----------------------------- Field Item: RCC_ICSCR_HSI_TRIM ---------------------------------
// SVD Line: 4267
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// HSI_TRIM
//
// [Bits 12..0] RW (@ 0x40021004) Clock frequency calibration value
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0x1FFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 4272
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bits 15..13] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 13) & 0x7), ((RCC_ICSCR = (RCC_ICSCR & ~(0x7UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 13 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 4277
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 24..16] RW (@ 0x40021004) Internal low-speed clock frequency calibration
//
// ( (unsigned short)((RCC_ICSCR >> 16) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 4262
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibration register
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 4284
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 4289
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 4294
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 4299
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) The AHB clock HCLK is based on the crossover coefficient of SYSCLK
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 4304
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB clock division factor
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 4309
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 27..24] RW (@ 0x40021008) MCO output clock selection
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 4314
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 30..28] RW (@ 0x40021008) Microprocessor output clock (MCO) divider factor
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 4284
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0x7F007F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F007F3F) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 4321
unsigned int RCC_ECSCR __AT (0x40021010);
// ------------------------------ Field Item: RCC_ECSCR_HSE_DRV ---------------------------------
// SVD Line: 4326
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRV
// HSE_DRV
//
// [Bit 0] RW (@ 0x40021010) HSE drive capability setting
//
// ( (unsigned int) RCC_ECSCR )
// HSE_DRV
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_HSE_STARTUP -------------------------------
// SVD Line: 4331
// - SFDITEM_FIELD__RCC_ECSCR_HSE_STARTUP
// HSE_STARTUP
//
// [Bits 4..3] RW (@ 0x40021010) HSE stabilization time selection
//
// ( (unsigned char)((RCC_ECSCR >> 3) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_DRIVER --------------------------------
// SVD Line: 4336
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// LSE_DRIVER
//
// [Bits 17..16] RW (@ 0x40021010) LSE drive capability setting
//
// ( (unsigned char)((RCC_ECSCR >> 16) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_STARTUP -------------------------------
// SVD Line: 4341
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
// LSE_STARTUP
//
// [Bits 21..20] RW (@ 0x40021010) LSE crystal oscillator stabilization time selection
//
// ( (unsigned char)((RCC_ECSCR >> 20) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 4321
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x330019UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x330019) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRV
// - SFDITEM_FIELD__RCC_ECSCR_HSE_STARTUP
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 4348
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 4353
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_LSERDYIE ---------------------------------
// SVD Line: 4358
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// LSERDYIE
//
// [Bit 1] RW (@ 0x40021018) LSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 4363
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSERDYIE ---------------------------------
// SVD Line: 4368
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
// HSERDYIE
//
// [Bit 4] RW (@ 0x40021018) HSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// HSERDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 4348
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enable register
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0x1BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 4375
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 4380
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSERDYF ----------------------------------
// SVD Line: 4386
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// LSERDYF
//
// [Bit 1] RO (@ 0x4002101C) LSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIFR )
// LSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 4392
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSERDYF ----------------------------------
// SVD Line: 4398
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// HSERDYF
//
// [Bit 4] RO (@ 0x4002101C) HSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIFR )
// HSERDYF
//
//
//
// -------------------------------- Field Item: RCC_CIFR_CSSF -----------------------------------
// SVD Line: 4404
// - SFDITEM_FIELD__RCC_CIFR_CSSF
// CSSF
//
// [Bit 8] RO (@ 0x4002101C) HSE Clock Security System (CSS) interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// CSSF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSECSSF ----------------------------------
// SVD Line: 4410
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
// LSECSSF
//
// [Bit 9] RO (@ 0x4002101C) LSE Clock Security System (CSS) interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSECSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 4375
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RW (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// - SFDITEM_FIELD__RCC_CIFR_CSSF
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 4418
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 4423
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] WO (@ 0x40021020) The LSI ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSERDYC ----------------------------------
// SVD Line: 4429
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// LSERDYC
//
// [Bit 1] WO (@ 0x40021020) The LSE ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 4435
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] WO (@ 0x40021020) The HSI ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSERDYC ----------------------------------
// SVD Line: 4441
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// HSERDYC
//
// [Bit 4] WO (@ 0x40021020) The HSE ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// HSERDYC
//
//
//
// -------------------------------- Field Item: RCC_CICR_CSSC -----------------------------------
// SVD Line: 4447
// - SFDITEM_FIELD__RCC_CICR_CSSC
// CSSC
//
// [Bit 8] WO (@ 0x40021020) The HSE Clock Security System (CSS) interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// CSSC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSECSSC ----------------------------------
// SVD Line: 4453
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
// LSECSSC
//
// [Bit 9] WO (@ 0x40021020) The LSE Clock Security System (CSS) interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSECSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 4418
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] RW (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x31BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x31B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// - SFDITEM_FIELD__RCC_CICR_CSSC
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 4461
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 4466
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O PortA reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 4471
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O PortB reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOFRST --------------------------------
// SVD Line: 4476
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
// GPIOFRST
//
// [Bit 5] RW (@ 0x40021024) I/O PortF reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOFRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 4461
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
//
//
// --------------------------- Register Item Address: RCC_AHBRSTR -------------------------------
// SVD Line: 4483
unsigned int RCC_AHBRSTR __AT (0x40021028);
// ----------------------------- Field Item: RCC_AHBRSTR_CRCRST ---------------------------------
// SVD Line: 4488
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// CRCRST
//
// [Bit 12] RW (@ 0x40021028) The CRC module is reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CRCRST
//
//
//
// ------------------------------- Register RTree: RCC_AHBRSTR ----------------------------------
// SVD Line: 4483
// SFDITEM_REG__RCC_AHBRSTR
// AHBRSTR
//
// [Bits 31..0] RW (@ 0x40021028) AHB peripheral reset register
// ( (unsigned int)((RCC_AHBRSTR >> 0) & 0xFFFFFFFF), ((RCC_AHBRSTR = (RCC_AHBRSTR & ~(0x1000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 4495
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// --------------------------- Field Item: RCC_APBRSTR1_RTCAPBRST -------------------------------
// SVD Line: 4500
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// RTCAPBRST
//
// [Bit 10] RW (@ 0x4002102C) The RTC module APB is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// RTCAPBRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_UART1RST -------------------------------
// SVD Line: 4505
// - SFDITEM_FIELD__RCC_APBRSTR1_UART1RST
// UART1RST
//
// [Bit 17] RW (@ 0x4002102C) The UART1 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// UART1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_UART2RST -------------------------------
// SVD Line: 4510
// - SFDITEM_FIELD__RCC_APBRSTR1_UART2RST
// UART2RST
//
// [Bit 18] RW (@ 0x4002102C) The UART2 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// UART2RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_I2C1RST --------------------------------
// SVD Line: 4515
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// I2C1RST
//
// [Bit 21] RW (@ 0x4002102C) The I2C1 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// I2C1RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 4520
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) The MCU Debug module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 4525
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) The Power interface module is reset.
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 4495
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APB peripheral reset register 1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0x18260400UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x18260400) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// - SFDITEM_FIELD__RCC_APBRSTR1_UART1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_UART2RST
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 4532
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 4537
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) The SYSCFG module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 4542
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) The TIM1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_SPI1RST --------------------------------
// SVD Line: 4547
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// SPI1RST
//
// [Bit 12] RW (@ 0x40021030) The SPI1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SPI1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_UART3RST -------------------------------
// SVD Line: 4552
// - SFDITEM_FIELD__RCC_APBRSTR2_UART3RST
// UART3RST
//
// [Bit 13] RW (@ 0x40021030) The UART3 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// UART3RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 4557
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) The TIM14 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_ADCRST --------------------------------
// SVD Line: 4562
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// ADCRST
//
// [Bit 20] RW (@ 0x40021030) The ADC block is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// ADCRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP1RST -------------------------------
// SVD Line: 4567
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// COMP1RST
//
// [Bit 21] RW (@ 0x40021030) The COMP1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP2RST -------------------------------
// SVD Line: 4572
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// COMP2RST
//
// [Bit 22] RW (@ 0x40021030) The COMP2 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP2RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_TKRST ---------------------------------
// SVD Line: 4577
// - SFDITEM_FIELD__RCC_APBRSTR2_TKRST
// TKRST
//
// [Bit 25] RW (@ 0x40021030) TK module reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TKRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 4532
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register 2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x270B801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x270B801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_UART3RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TKRST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 4584
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 4589
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O PortA clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 4594
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O PortB clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOFEN ---------------------------------
// SVD Line: 4599
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
// GPIOFEN
//
// [Bit 5] RW (@ 0x40021034) I/O PortF clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOFEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 4584
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 4606
unsigned int RCC_AHBENR __AT (0x40021038);
// ------------------------------ Field Item: RCC_AHBENR_CRCEN ----------------------------------
// SVD Line: 4611
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// CRCEN
//
// [Bit 12] RW (@ 0x40021038) CRC module clock enabled
//
// ( (unsigned int) RCC_AHBENR )
// CRCEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 4606
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enable register
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x1000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 4618
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ---------------------------- Field Item: RCC_APBENR1_RTCAPBEN --------------------------------
// SVD Line: 4623
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// RTCAPBEN
//
// [Bit 10] RW (@ 0x4002103C) The RTC module APB clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// RTCAPBEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_UART1EN --------------------------------
// SVD Line: 4628
// - SFDITEM_FIELD__RCC_APBENR1_UART1EN
// UART1EN
//
// [Bit 17] RW (@ 0x4002103C) The UART1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// UART1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_UART2EN --------------------------------
// SVD Line: 4633
// - SFDITEM_FIELD__RCC_APBENR1_UART2EN
// UART2EN
//
// [Bit 18] RW (@ 0x4002103C) The UART2 module clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// UART2EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_I2C1EN ---------------------------------
// SVD Line: 4638
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// I2C1EN
//
// [Bit 21] RW (@ 0x4002103C) I2C1 module clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// I2C1EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 4643
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) MCU Debug module clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 4648
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) The Power interface module clock enables
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 4618
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register 1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0x18260400UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x18260400) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// - SFDITEM_FIELD__RCC_APBENR1_UART1EN
// - SFDITEM_FIELD__RCC_APBENR1_UART2EN
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 4655
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 4660
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) The SYSCFG module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 4665
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) The TIM1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_SPI1EN ---------------------------------
// SVD Line: 4670
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// SPI1EN
//
// [Bit 12] RW (@ 0x40021040) The SPI1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// SPI1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_UART3EN --------------------------------
// SVD Line: 4675
// - SFDITEM_FIELD__RCC_APBENR2_UART3EN
// UART3EN
//
// [Bit 13] RW (@ 0x40021040) The UART3 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// UART3EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 4680
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 module clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_ADCEN ---------------------------------
// SVD Line: 4685
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// ADCEN
//
// [Bit 20] RW (@ 0x40021040) ADC block clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// ADCEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP1EN --------------------------------
// SVD Line: 4690
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// COMP1EN
//
// [Bit 21] RW (@ 0x40021040) COMP1 module clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP2EN --------------------------------
// SVD Line: 4695
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// COMP2EN
//
// [Bit 22] RW (@ 0x40021040) COMP2 module clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// COMP2EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_TKEN ----------------------------------
// SVD Line: 4700
// - SFDITEM_FIELD__RCC_APBENR2_TKEN
// TKEN
//
// [Bit 25] RW (@ 0x40021040) TK module clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// TKEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 4655
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register 2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x270B801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x270B801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// - SFDITEM_FIELD__RCC_APBENR2_UART3EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// - SFDITEM_FIELD__RCC_APBENR2_TKEN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 4707
unsigned int RCC_CCIPR __AT (0x40021054);
// ---------------------------- Field Item: RCC_CCIPR_TIMCLK_CTRL -------------------------------
// SVD Line: 4712
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLK_CTRL
// TIMCLK_CTRL
//
// [Bit 0] RW (@ 0x40021054) TIMER PCLK FREQUENCY CONTROL
//
// ( (unsigned int) RCC_CCIPR )
// TIMCLK_CTRL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP1SEL ---------------------------------
// SVD Line: 4717
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// COMP1SEL
//
// [Bit 8] RW (@ 0x40021054) COMP1 module clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP1SEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP2SEL ---------------------------------
// SVD Line: 4722
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// COMP2SEL
//
// [Bit 9] RW (@ 0x40021054) COMP2 module clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP2SEL
//
//
//
// ------------------------------ Field Item: RCC_CCIPR_IWDGSEL ---------------------------------
// SVD Line: 4727
// - SFDITEM_FIELD__RCC_CCIPR_IWDGSEL
// IWDGSEL
//
// [Bit 12] RW (@ 0x40021054) IWDG internal clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// IWDGSEL
//
//
//
// ---------------------------- Field Item: RCC_CCIPR_ADC_CKMODE --------------------------------
// SVD Line: 4732
// - SFDITEM_FIELD__RCC_CCIPR_ADC_CKMODE
// ADC_CKMODE
//
// [Bits 23..20] RW (@ 0x40021054) ADC clock mode
//
// ( (unsigned char)((RCC_CCIPR >> 20) & 0xF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 4707
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configuration register
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xF01301UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF01301) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLK_CTRL
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// - SFDITEM_FIELD__RCC_CCIPR_IWDGSEL
// - SFDITEM_FIELD__RCC_CCIPR_ADC_CKMODE
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 4739
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_LSEON -----------------------------------
// SVD Line: 4744
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// LSEON
//
// [Bit 0] RW (@ 0x4002105C) LSE OSC enabled
//
// ( (unsigned int) RCC_BDCR )
// LSEON
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSERDY ----------------------------------
// SVD Line: 4749
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// LSERDY
//
// [Bit 1] RW (@ 0x4002105C) LSE OSC ready
//
// ( (unsigned int) RCC_BDCR )
// LSERDY
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSEBYP ----------------------------------
// SVD Line: 4754
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// LSEBYP
//
// [Bit 2] RW (@ 0x4002105C) LSE OSC bypass
//
// ( (unsigned int) RCC_BDCR )
// LSEBYP
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSON ---------------------------------
// SVD Line: 4759
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// LSECSSON
//
// [Bit 5] RW (@ 0x4002105C) LSE CSS enables
//
// ( (unsigned int) RCC_BDCR )
// LSECSSON
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSD ----------------------------------
// SVD Line: 4764
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// LSECSSD
//
// [Bit 6] RW (@ 0x4002105C) LSE CSS (clock security system) detection failed
//
// ( (unsigned int) RCC_BDCR )
// LSECSSD
//
//
//
// ------------------------------- Field Item: RCC_BDCR_RTCSEL ----------------------------------
// SVD Line: 4769
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// RTCSEL
//
// [Bits 9..8] RW (@ 0x4002105C) RTC clock source selection
//
// ( (unsigned char)((RCC_BDCR >> 8) & 0x3), ((RCC_BDCR = (RCC_BDCR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: RCC_BDCR_RTC_HSEDIV_SEL ------------------------------
// SVD Line: 4774
// - SFDITEM_FIELD__RCC_BDCR_RTC_HSEDIV_SEL
// RTC_HSEDIV_SEL
//
// [Bits 11..10] RW (@ 0x4002105C) The RTC clock source is selected as the division of the HSE clock
//
// ( (unsigned char)((RCC_BDCR >> 10) & 0x3), ((RCC_BDCR = (RCC_BDCR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_BDCR_RTCEN -----------------------------------
// SVD Line: 4779
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// RTCEN
//
// [Bit 15] RW (@ 0x4002105C) RTC clock enabled
//
// ( (unsigned int) RCC_BDCR )
// RTCEN
//
//
//
// ------------------------------- Field Item: RCC_BDCR_BDRST -----------------------------------
// SVD Line: 4784
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// BDRST
//
// [Bit 16] RW (@ 0x4002105C) RTC soft reset
//
// ( (unsigned int) RCC_BDCR )
// BDRST
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCSEL ----------------------------------
// SVD Line: 4789
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
// LSCSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock selection
//
// ( (unsigned int) RCC_BDCR )
// LSCSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 4739
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x2018F67UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2018F67) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// - SFDITEM_FIELD__RCC_BDCR_RTC_HSEDIV_SEL
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 4796
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 4801
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI OSC enabled
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 4806
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RO (@ 0x40021060) LSI OSC stability flag
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// ---------------------------- Field Item: RCC_CSR_PINRST_FLTDIS -------------------------------
// SVD Line: 4812
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// PINRST_FLTDIS
//
// [Bit 8] RW (@ 0x40021060) NRST filtering is prohibited
//
// ( (unsigned int) RCC_CSR )
// PINRST_FLTDIS
//
//
//
// ------------------------------- Field Item: RCC_CSR_BORRSTF ----------------------------------
// SVD Line: 4817
// - SFDITEM_FIELD__RCC_CSR_BORRSTF
// BORRSTF
//
// [Bit 9] RO (@ 0x40021060) BOR reset flag
//
// ( (unsigned int) RCC_CSR )
// BORRSTF
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 4823
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Clear the reset flag
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 4828
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RO (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 4834
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RO (@ 0x40021060) External NRST pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PORRSTF ----------------------------------
// SVD Line: 4840
// - SFDITEM_FIELD__RCC_CSR_PORRSTF
// PORRSTF
//
// [Bit 27] RO (@ 0x40021060) POR reset flag
//
// ( (unsigned int) RCC_CSR )
// PORRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 4846
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RO (@ 0x40021060) Soft reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 4852
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RO (@ 0x40021060) IWDG reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 4796
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x800101UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800101) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// - SFDITEM_FIELD__RCC_CSR_BORRSTF
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PORRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 4203
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_AHBRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// ----------------------------- Register Item Address: RTC_CRH ---------------------------------
// SVD Line: 4877
unsigned int RTC_CRH __AT (0x40002800);
// -------------------------------- Field Item: RTC_CRH_SECIE -----------------------------------
// SVD Line: 4882
// - SFDITEM_FIELD__RTC_CRH_SECIE
// SECIE
//
// [Bit 0] RW (@ 0x40002800) Seconds interrupt allowed bits
//
// ( (unsigned int) RTC_CRH )
// SECIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_ALRIE -----------------------------------
// SVD Line: 4887
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// ALRIE
//
// [Bit 1] RW (@ 0x40002800) Alarm interrupt allowed bits
//
// ( (unsigned int) RTC_CRH )
// ALRIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_OWIE ------------------------------------
// SVD Line: 4892
// - SFDITEM_FIELD__RTC_CRH_OWIE
// OWIE
//
// [Bit 2] RW (@ 0x40002800) Overflow interrupt allow bits
//
// ( (unsigned int) RTC_CRH )
// OWIE
//
//
//
// ------------------------------ Field Item: RTC_CRH_TK_SECIE ----------------------------------
// SVD Line: 4897
// - SFDITEM_FIELD__RTC_CRH_TK_SECIE
// TK_SECIE
//
// [Bit 3] RW (@ 0x40002800) TK sec interrupt allowable bits
//
// ( (unsigned int) RTC_CRH )
// TK_SECIE
//
//
//
// ------------------------------ Field Item: RTC_CRH_TK_ALRIE ----------------------------------
// SVD Line: 4902
// - SFDITEM_FIELD__RTC_CRH_TK_ALRIE
// TK_ALRIE
//
// [Bit 4] RW (@ 0x40002800) TK alarm interrupt allowed bits
//
// ( (unsigned int) RTC_CRH )
// TK_ALRIE
//
//
//
// ------------------------------- Field Item: RTC_CRH_TK_OWIE ----------------------------------
// SVD Line: 4907
// - SFDITEM_FIELD__RTC_CRH_TK_OWIE
// TK_OWIE
//
// [Bit 5] RW (@ 0x40002800) TK overflow interrupt allowable bits
//
// ( (unsigned int) RTC_CRH )
// TK_OWIE
//
//
//
// --------------------------------- Register RTree: RTC_CRH ------------------------------------
// SVD Line: 4877
// SFDITEM_REG__RTC_CRH
// CRH
//
// [Bits 31..0] RW (@ 0x40002800) RTC Control Register High
// ( (unsigned int)((RTC_CRH >> 0) & 0xFFFFFFFF), ((RTC_CRH = (RTC_CRH & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRH_SECIE
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// - SFDITEM_FIELD__RTC_CRH_OWIE
// - SFDITEM_FIELD__RTC_CRH_TK_SECIE
// - SFDITEM_FIELD__RTC_CRH_TK_ALRIE
// - SFDITEM_FIELD__RTC_CRH_TK_OWIE
//
//
// ----------------------------- Register Item Address: RTC_CRL ---------------------------------
// SVD Line: 4914
unsigned int RTC_CRL __AT (0x40002804);
// -------------------------------- Field Item: RTC_CRL_SECF ------------------------------------
// SVD Line: 4919
// - SFDITEM_FIELD__RTC_CRL_SECF
// SECF
//
// [Bit 0] RW (@ 0x40002804) Second flag
//
// ( (unsigned int) RTC_CRL )
// SECF
//
//
//
// -------------------------------- Field Item: RTC_CRL_ALRF ------------------------------------
// SVD Line: 4924
// - SFDITEM_FIELD__RTC_CRL_ALRF
// ALRF
//
// [Bit 1] RW (@ 0x40002804) Alarm flag
//
// ( (unsigned int) RTC_CRL )
// ALRF
//
//
//
// --------------------------------- Field Item: RTC_CRL_OWF ------------------------------------
// SVD Line: 4929
// - SFDITEM_FIELD__RTC_CRL_OWF
// OWF
//
// [Bit 2] RW (@ 0x40002804) Overflow flag
//
// ( (unsigned int) RTC_CRL )
// OWF
//
//
//
// --------------------------------- Field Item: RTC_CRL_RSF ------------------------------------
// SVD Line: 4934
// - SFDITEM_FIELD__RTC_CRL_RSF
// RSF
//
// [Bit 3] RW (@ 0x40002804) Registers synchronized flag
//
// ( (unsigned int) RTC_CRL )
// RSF
//
//
//
// --------------------------------- Field Item: RTC_CRL_CNF ------------------------------------
// SVD Line: 4939
// - SFDITEM_FIELD__RTC_CRL_CNF
// CNF
//
// [Bit 4] RW (@ 0x40002804) Configuration flag
//
// ( (unsigned int) RTC_CRL )
// CNF
//
//
//
// -------------------------------- Field Item: RTC_CRL_RTOFF -----------------------------------
// SVD Line: 4944
// - SFDITEM_FIELD__RTC_CRL_RTOFF
// RTOFF
//
// [Bit 5] RO (@ 0x40002804) RTC operation OFF
//
// ( (unsigned int) RTC_CRL )
// RTOFF
//
//
//
// --------------------------------- Register RTree: RTC_CRL ------------------------------------
// SVD Line: 4914
// SFDITEM_REG__RTC_CRL
// CRL
//
// [Bits 31..0] RW (@ 0x40002804) RTC Control Register Low
// ( (unsigned int)((RTC_CRL >> 0) & 0xFFFFFFFF), ((RTC_CRL = (RTC_CRL & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRL_SECF
// - SFDITEM_FIELD__RTC_CRL_ALRF
// - SFDITEM_FIELD__RTC_CRL_OWF
// - SFDITEM_FIELD__RTC_CRL_RSF
// - SFDITEM_FIELD__RTC_CRL_CNF
// - SFDITEM_FIELD__RTC_CRL_RTOFF
//
//
// ----------------------------- Register Item Address: RTC_PRLH --------------------------------
// SVD Line: 4952
unsigned int RTC_PRLH __AT (0x40002808);
// -------------------------------- Field Item: RTC_PRLH_PRL ------------------------------------
// SVD Line: 4957
// - SFDITEM_FIELD__RTC_PRLH_PRL
// PRL
//
// [Bits 5..0] WO (@ 0x40002808) RTC prescaler reload value high
//
// ( (unsigned char)((RTC_PRLH >> 0) & 0x0), ((RTC_PRLH = (RTC_PRLH & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLH ------------------------------------
// SVD Line: 4952
// SFDITEM_REG__RTC_PRLH
// PRLH
//
// [Bits 31..0] RW (@ 0x40002808) RTC Prescaler Load Register High
// ( (unsigned int)((RTC_PRLH >> 0) & 0xFFFFFFFF), ((RTC_PRLH = (RTC_PRLH & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLH_PRL
//
//
// ----------------------------- Register Item Address: RTC_PRLL --------------------------------
// SVD Line: 4965
unsigned int RTC_PRLL __AT (0x4000280C);
// -------------------------------- Field Item: RTC_PRLL_PRL ------------------------------------
// SVD Line: 4970
// - SFDITEM_FIELD__RTC_PRLL_PRL
// PRL
//
// [Bits 15..0] WO (@ 0x4000280C) RTC prescaler reload value high
//
// ( (unsigned short)((RTC_PRLL >> 0) & 0x0), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLL ------------------------------------
// SVD Line: 4965
// SFDITEM_REG__RTC_PRLL
// PRLL
//
// [Bits 31..0] RW (@ 0x4000280C) RTC Prescaler Load Register Low
// ( (unsigned int)((RTC_PRLL >> 0) & 0xFFFFFFFF), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLL_PRL
//
//
// ----------------------------- Register Item Address: RTC_DIVH --------------------------------
// SVD Line: 4978
unsigned int RTC_DIVH __AT (0x40002810);
// ------------------------------ Field Item: RTC_DIVH_RTC_DIV ----------------------------------
// SVD Line: 4983
// - SFDITEM_FIELD__RTC_DIVH_RTC_DIV
// RTC_DIV
//
// [Bits 3..0] RO (@ 0x40002810) RTC clock divider
//
// ( (unsigned char)((RTC_DIVH >> 0) & 0xF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVH ------------------------------------
// SVD Line: 4978
// SFDITEM_REG__RTC_DIVH
// DIVH
//
// [Bits 31..0] RW (@ 0x40002810) RTC Prescaler Divider Register High
// ( (unsigned int)((RTC_DIVH >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVH_RTC_DIV
//
//
// ----------------------------- Register Item Address: RTC_DIVL --------------------------------
// SVD Line: 4991
unsigned int RTC_DIVL __AT (0x40002814);
// ------------------------------ Field Item: RTC_DIVL_RTC_DIV ----------------------------------
// SVD Line: 4996
// - SFDITEM_FIELD__RTC_DIVL_RTC_DIV
// RTC_DIV
//
// [Bits 15..0] RO (@ 0x40002814) RTC clock divider
//
// ( (unsigned short)((RTC_DIVL >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVL ------------------------------------
// SVD Line: 4991
// SFDITEM_REG__RTC_DIVL
// DIVL
//
// [Bits 31..0] RW (@ 0x40002814) RTC Prescaler Divider Register Low
// ( (unsigned int)((RTC_DIVL >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVL_RTC_DIV
//
//
// ----------------------------- Register Item Address: RTC_CNTH --------------------------------
// SVD Line: 5004
unsigned int RTC_CNTH __AT (0x40002818);
// ------------------------------ Field Item: RTC_CNTH_RTC_CNT ----------------------------------
// SVD Line: 5009
// - SFDITEM_FIELD__RTC_CNTH_RTC_CNT
// RTC_CNT
//
// [Bits 15..0] RW (@ 0x40002818) RTC core counter
//
// ( (unsigned short)((RTC_CNTH >> 0) & 0xFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTH ------------------------------------
// SVD Line: 5004
// SFDITEM_REG__RTC_CNTH
// CNTH
//
// [Bits 31..0] RW (@ 0x40002818) RTC Counter Register High
// ( (unsigned int)((RTC_CNTH >> 0) & 0xFFFFFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTH_RTC_CNT
//
//
// ----------------------------- Register Item Address: RTC_CNTL --------------------------------
// SVD Line: 5016
unsigned int RTC_CNTL __AT (0x4000281C);
// ------------------------------ Field Item: RTC_CNTL_RTC_CNT ----------------------------------
// SVD Line: 5021
// - SFDITEM_FIELD__RTC_CNTL_RTC_CNT
// RTC_CNT
//
// [Bits 15..0] RW (@ 0x4000281C) RTC core counter
//
// ( (unsigned short)((RTC_CNTL >> 0) & 0xFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTL ------------------------------------
// SVD Line: 5016
// SFDITEM_REG__RTC_CNTL
// CNTL
//
// [Bits 31..0] RW (@ 0x4000281C) RTC Counter Register Low
// ( (unsigned int)((RTC_CNTL >> 0) & 0xFFFFFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTL_RTC_CNT
//
//
// ----------------------------- Register Item Address: RTC_ALRH --------------------------------
// SVD Line: 5028
unsigned int RTC_ALRH __AT (0x40002820);
// -------------------------------- Field Item: RTC_ALRH_ALR ------------------------------------
// SVD Line: 5033
// - SFDITEM_FIELD__RTC_ALRH_ALR
// ALR
//
// [Bits 15..0] RW (@ 0x40002820) RTC alarm value
//
// ( (unsigned short)((RTC_ALRH >> 0) & 0xFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRH ------------------------------------
// SVD Line: 5028
// SFDITEM_REG__RTC_ALRH
// ALRH
//
// [Bits 31..0] RW (@ 0x40002820) RTC Alarm Register High
// ( (unsigned int)((RTC_ALRH >> 0) & 0xFFFFFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRH_ALR
//
//
// ----------------------------- Register Item Address: RTC_ALRL --------------------------------
// SVD Line: 5040
unsigned int RTC_ALRL __AT (0x40002824);
// -------------------------------- Field Item: RTC_ALRL_ALR ------------------------------------
// SVD Line: 5045
// - SFDITEM_FIELD__RTC_ALRL_ALR
// ALR
//
// [Bits 15..0] RW (@ 0x40002824) RTC alarm value
//
// ( (unsigned short)((RTC_ALRL >> 0) & 0xFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRL ------------------------------------
// SVD Line: 5040
// SFDITEM_REG__RTC_ALRL
// ALRL
//
// [Bits 31..0] RW (@ 0x40002824) RTC Alarm Register Low
// ( (unsigned int)((RTC_ALRL >> 0) & 0xFFFFFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRL_ALR
//
//
// -------------------------- Register Item Address: RTC_BKP_RTCCR ------------------------------
// SVD Line: 5052
unsigned int RTC_BKP_RTCCR __AT (0x4000282C);
// ------------------------------ Field Item: RTC_BKP_RTCCR_CAL ---------------------------------
// SVD Line: 5056
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CAL
// CAL
//
// [Bits 6..0] RW (@ 0x4000282C) Calibration value
//
// ( (unsigned char)((RTC_BKP_RTCCR >> 0) & 0x7F), ((RTC_BKP_RTCCR = (RTC_BKP_RTCCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RTC_BKP_RTCCR_CCO ---------------------------------
// SVD Line: 5061
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CCO
// CCO
//
// [Bit 7] RW (@ 0x4000282C) Calibrate the clock output bits
//
// ( (unsigned int) RTC_BKP_RTCCR )
// CCO
//
//
//
// ----------------------------- Field Item: RTC_BKP_RTCCR_ASOE ---------------------------------
// SVD Line: 5066
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOE
// ASOE
//
// [Bit 8] RW (@ 0x4000282C) Seconds/alarm pulse output enable bit
//
// ( (unsigned int) RTC_BKP_RTCCR )
// ASOE
//
//
//
// ----------------------------- Field Item: RTC_BKP_RTCCR_ASOS ---------------------------------
// SVD Line: 5071
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOS
// ASOS
//
// [Bit 9] RW (@ 0x4000282C) Seconds/alarm pulse output select bits
//
// ( (unsigned int) RTC_BKP_RTCCR )
// ASOS
//
//
//
// ------------------------------ Register RTree: RTC_BKP_RTCCR ---------------------------------
// SVD Line: 5052
// SFDITEM_REG__RTC_BKP_RTCCR
// BKP_RTCCR
//
// [Bits 31..0] RW (@ 0x4000282C) BKP_RTCCR
// ( (unsigned int)((RTC_BKP_RTCCR >> 0) & 0xFFFFFFFF), ((RTC_BKP_RTCCR = (RTC_BKP_RTCCR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CAL
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CCO
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOE
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOS
//
//
// ---------------------------------- Peripheral View: RTC --------------------------------------
// SVD Line: 4862
// RTC
// RTC
// - SFDITEM_REG__RTC_CRH
// - SFDITEM_REG__RTC_CRL
// - SFDITEM_REG__RTC_PRLH
// - SFDITEM_REG__RTC_PRLL
// - SFDITEM_REG__RTC_DIVH
// - SFDITEM_REG__RTC_DIVL
// - SFDITEM_REG__RTC_CNTH
// - SFDITEM_REG__RTC_CNTL
// - SFDITEM_REG__RTC_ALRH
// - SFDITEM_REG__RTC_ALRL
// - SFDITEM_REG__RTC_BKP_RTCCR
//
//
// ----------------------------- Register Item Address: SPI1_CR1 --------------------------------
// SVD Line: 5096
unsigned int SPI1_CR1 __AT (0x40013000);
// -------------------------------- Field Item: SPI1_CR1_CPHA -----------------------------------
// SVD Line: 5100
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// CPHA
//
// [Bit 0] RW (@ 0x40013000) Clock Phase
//
// ( (unsigned int) SPI1_CR1 )
// CPHA
//
//
//
// -------------------------------- Field Item: SPI1_CR1_CPOL -----------------------------------
// SVD Line: 5105
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// CPOL
//
// [Bit 1] RW (@ 0x40013000) Clock Polarity
//
// ( (unsigned int) SPI1_CR1 )
// CPOL
//
//
//
// -------------------------------- Field Item: SPI1_CR1_MSTR -----------------------------------
// SVD Line: 5110
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// MSTR
//
// [Bit 2] RW (@ 0x40013000) Master Selection
//
// ( (unsigned int) SPI1_CR1 )
// MSTR
//
//
//
// --------------------------------- Field Item: SPI1_CR1_BR ------------------------------------
// SVD Line: 5115
// - SFDITEM_FIELD__SPI1_CR1_BR
// BR
//
// [Bits 5..3] RW (@ 0x40013000) Baud Rate Control
//
// ( (unsigned char)((SPI1_CR1 >> 3) & 0x7), ((SPI1_CR1 = (SPI1_CR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SPE ------------------------------------
// SVD Line: 5120
// - SFDITEM_FIELD__SPI1_CR1_SPE
// SPE
//
// [Bit 6] RW (@ 0x40013000) SPI Enable
//
// ( (unsigned int) SPI1_CR1 )
// SPE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_LSBFIRST ---------------------------------
// SVD Line: 5125
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// LSBFIRST
//
// [Bit 7] RW (@ 0x40013000) Frame Format
//
// ( (unsigned int) SPI1_CR1 )
// LSBFIRST
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSI ------------------------------------
// SVD Line: 5130
// - SFDITEM_FIELD__SPI1_CR1_SSI
// SSI
//
// [Bit 8] RW (@ 0x40013000) Internal slave select
//
// ( (unsigned int) SPI1_CR1 )
// SSI
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSM ------------------------------------
// SVD Line: 5135
// - SFDITEM_FIELD__SPI1_CR1_SSM
// SSM
//
// [Bit 9] RW (@ 0x40013000) Software slave management
//
// ( (unsigned int) SPI1_CR1 )
// SSM
//
//
//
// ------------------------------- Field Item: SPI1_CR1_RXONLY ----------------------------------
// SVD Line: 5140
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// RXONLY
//
// [Bit 10] RW (@ 0x40013000) Receive only
//
// ( (unsigned int) SPI1_CR1 )
// RXONLY
//
//
//
// -------------------------------- Field Item: SPI1_CR1_DFF ------------------------------------
// SVD Line: 5145
// - SFDITEM_FIELD__SPI1_CR1_DFF
// DFF
//
// [Bit 11] RW (@ 0x40013000) Data frame format
//
// ( (unsigned int) SPI1_CR1 )
// DFF
//
//
//
// ------------------------------- Field Item: SPI1_CR1_BIDIOE ----------------------------------
// SVD Line: 5150
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// BIDIOE
//
// [Bit 14] RW (@ 0x40013000) Output enable in bidirectional mode
//
// ( (unsigned int) SPI1_CR1 )
// BIDIOE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_BIDIMODE ---------------------------------
// SVD Line: 5155
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
// BIDIMODE
//
// [Bit 15] RW (@ 0x40013000) Bidirectional data mode enable
//
// ( (unsigned int) SPI1_CR1 )
// BIDIMODE
//
//
//
// -------------------------------- Register RTree: SPI1_CR1 ------------------------------------
// SVD Line: 5096
// SFDITEM_REG__SPI1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40013000) CR1
// ( (unsigned int)((SPI1_CR1 >> 0) & 0xFFFFFFFF), ((SPI1_CR1 = (SPI1_CR1 & ~(0xCFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// - SFDITEM_FIELD__SPI1_CR1_BR
// - SFDITEM_FIELD__SPI1_CR1_SPE
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// - SFDITEM_FIELD__SPI1_CR1_SSI
// - SFDITEM_FIELD__SPI1_CR1_SSM
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// - SFDITEM_FIELD__SPI1_CR1_DFF
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
//
//
// ----------------------------- Register Item Address: SPI1_CR2 --------------------------------
// SVD Line: 5162
unsigned int SPI1_CR2 __AT (0x40013004);
// -------------------------------- Field Item: SPI1_CR2_SSOE -----------------------------------
// SVD Line: 5166
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// SSOE
//
// [Bit 2] RW (@ 0x40013004) SS Output Enable
//
// ( (unsigned int) SPI1_CR2 )
// SSOE
//
//
//
// ----------------------------- Field Item: SPI1_CR2_CLRTXFIFO ---------------------------------
// SVD Line: 5171
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// CLRTXFIFO
//
// [Bit 4] RW (@ 0x40013004) Clear FIFO
//
// ( (unsigned int) SPI1_CR2 )
// CLRTXFIFO
//
//
//
// ------------------------------- Field Item: SPI1_CR2_ERRIE -----------------------------------
// SVD Line: 5176
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// ERRIE
//
// [Bit 5] RW (@ 0x40013004) Error Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// ERRIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_RXNEIE ----------------------------------
// SVD Line: 5181
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// RXNEIE
//
// [Bit 6] RW (@ 0x40013004) RX buffer Not Empty Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_TXEIE -----------------------------------
// SVD Line: 5186
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40013004) Tx buffer Empty Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: SPI1_CR2 ------------------------------------
// SVD Line: 5162
// SFDITEM_REG__SPI1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013004) CR2
// ( (unsigned int)((SPI1_CR2 >> 0) & 0xFFFFFFFF), ((SPI1_CR2 = (SPI1_CR2 & ~(0xF4UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF4) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
//
//
// ----------------------------- Register Item Address: SPI1_SR ---------------------------------
// SVD Line: 5193
unsigned int SPI1_SR __AT (0x40013008);
// -------------------------------- Field Item: SPI1_SR_RXNE ------------------------------------
// SVD Line: 5197
// - SFDITEM_FIELD__SPI1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40013008) Receive buffer Not Empty
//
// ( (unsigned int) SPI1_SR )
// RXNE
//
//
//
// --------------------------------- Field Item: SPI1_SR_TXE ------------------------------------
// SVD Line: 5203
// - SFDITEM_FIELD__SPI1_SR_TXE
// TXE
//
// [Bit 1] RO (@ 0x40013008) Transmit buffer Empty
//
// ( (unsigned int) SPI1_SR )
// TXE
//
//
//
// -------------------------------- Field Item: SPI1_SR_MODF ------------------------------------
// SVD Line: 5209
// - SFDITEM_FIELD__SPI1_SR_MODF
// MODF
//
// [Bit 5] RW (@ 0x40013008) Mode fault
//
// ( (unsigned int) SPI1_SR )
// MODF
//
//
//
// --------------------------------- Field Item: SPI1_SR_OVR ------------------------------------
// SVD Line: 5214
// - SFDITEM_FIELD__SPI1_SR_OVR
// OVR
//
// [Bit 6] RO (@ 0x40013008) Overrun flag
//
// ( (unsigned int) SPI1_SR )
// OVR
//
//
//
// --------------------------------- Field Item: SPI1_SR_BSY ------------------------------------
// SVD Line: 5220
// - SFDITEM_FIELD__SPI1_SR_BSY
// BSY
//
// [Bit 7] RO (@ 0x40013008) Busy flag
//
// ( (unsigned int) SPI1_SR )
// BSY
//
//
//
// -------------------------------- Field Item: SPI1_SR_FRLVL -----------------------------------
// SVD Line: 5226
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// FRLVL
//
// [Bits 10..9] RO (@ 0x40013008) FIFO Reception Level
//
// ( (unsigned char)((SPI1_SR >> 9) & 0x3) )
//
//
//
// -------------------------------- Field Item: SPI1_SR_FTLVL -----------------------------------
// SVD Line: 5232
// - SFDITEM_FIELD__SPI1_SR_FTLVL
// FTLVL
//
// [Bits 12..11] RO (@ 0x40013008) FIFO Transmission Level
//
// ( (unsigned char)((SPI1_SR >> 11) & 0x3) )
//
//
//
// --------------------------------- Register RTree: SPI1_SR ------------------------------------
// SVD Line: 5193
// SFDITEM_REG__SPI1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013008) SR
// ( (unsigned int)((SPI1_SR >> 0) & 0xFFFFFFFF), ((SPI1_SR = (SPI1_SR & ~(0x20UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x20) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_SR_RXNE
// - SFDITEM_FIELD__SPI1_SR_TXE
// - SFDITEM_FIELD__SPI1_SR_MODF
// - SFDITEM_FIELD__SPI1_SR_OVR
// - SFDITEM_FIELD__SPI1_SR_BSY
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// - SFDITEM_FIELD__SPI1_SR_FTLVL
//
//
// ----------------------------- Register Item Address: SPI1_DR ---------------------------------
// SVD Line: 5240
unsigned int SPI1_DR __AT (0x4001300C);
// --------------------------------- Field Item: SPI1_DR_DR -------------------------------------
// SVD Line: 5244
// - SFDITEM_FIELD__SPI1_DR_DR
// DR
//
// [Bits 15..0] RW (@ 0x4001300C) Data Register
//
// ( (unsigned short)((SPI1_DR >> 0) & 0xFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: SPI1_DR ------------------------------------
// SVD Line: 5240
// SFDITEM_REG__SPI1_DR
// DR
//
// [Bits 31..0] RW (@ 0x4001300C) DR
// ( (unsigned int)((SPI1_DR >> 0) & 0xFFFFFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_DR_DR
//
//
// ---------------------------------- Peripheral View: SPI1 -------------------------------------
// SVD Line: 5080
// SPI1
// SPI1
// - SFDITEM_REG__SPI1_CR1
// - SFDITEM_REG__SPI1_CR2
// - SFDITEM_REG__SPI1_SR
// - SFDITEM_REG__SPI1_DR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR1 ------------------------------
// SVD Line: 5263
unsigned int SYSCFG_CFGR1 __AT (0x40010000);
// ---------------------------- Field Item: SYSCFG_CFGR1_MEM_MODE -------------------------------
// SVD Line: 5268
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// MEM_MODE
//
// [Bits 1..0] RW (@ 0x40010000) Storage Area Mapping Selection
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 0) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_TIM1_IC1_SRC -----------------------------
// SVD Line: 5273
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM1_IC1_SRC
// TIM1_IC1_SRC
//
// [Bits 3..2] RW (@ 0x40010000) Timer1 CH1 Input Selection
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 2) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_ETR_SRC_TIM1 -----------------------------
// SVD Line: 5278
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM1
// ETR_SRC_TIM1
//
// [Bits 9..8] RW (@ 0x40010000) Timer1 ETR Input Selection
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 8) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR1 ----------------------------------
// SVD Line: 5263
// SFDITEM_REG__SYSCFG_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x40010000) SYSCFG configuration register 1
// ( (unsigned int)((SYSCFG_CFGR1 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x30FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// - SFDITEM_FIELD__SYSCFG_CFGR1_TIM1_IC1_SRC
// - SFDITEM_FIELD__SYSCFG_CFGR1_ETR_SRC_TIM1
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 5285
unsigned int SYSCFG_CFGR2 __AT (0x40010004);
// -------------------------- Field Item: SYSCFG_CFGR2_LOCKUP_LOCK ------------------------------
// SVD Line: 5290
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// LOCKUP_LOCK
//
// [Bit 0] RW (@ 0x40010004) LOCK_UP as TIM1 Break Enable
//
// ( (unsigned int) SYSCFG_CFGR2 )
// LOCKUP_LOCK
//
//
//
// ------------------------- Field Item: SYSCFG_CFGR2_COMP1_BRK_TIM1 ----------------------------
// SVD Line: 5295
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM1
// COMP1_BRK_TIM1
//
// [Bit 3] RW (@ 0x40010004) COMP1 as TIM1 Break Enable
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_BRK_TIM1
//
//
//
// ------------------------- Field Item: SYSCFG_CFGR2_COMP2_BRK_TIM1 ----------------------------
// SVD Line: 5300
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM1
// COMP2_BRK_TIM1
//
// [Bit 4] RW (@ 0x40010004) COMP2 as TIM1 Break Enable
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_BRK_TIM1
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP1_OCREF_CLR_TIM1 -------------------------
// SVD Line: 5305
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_OCREF_CLR_TIM1
// COMP1_OCREF_CLR_TIM1
//
// [Bit 9] RW (@ 0x40010004) COMP1 as TIM1 ocref_clr Enable
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP1_OCREF_CLR_TIM1
//
//
//
// ---------------------- Field Item: SYSCFG_CFGR2_COMP2_OCREF_CLR_TIM1 -------------------------
// SVD Line: 5310
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_OCREF_CLR_TIM1
// COMP2_OCREF_CLR_TIM1
//
// [Bit 11] RW (@ 0x40010004) COMP2 as TIM1 ocref_clr Enable
//
// ( (unsigned int) SYSCFG_CFGR2 )
// COMP2_OCREF_CLR_TIM1
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 5285
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010004) SYSCFG configuration register 2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0xA19UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA19) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_BRK_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_BRK_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP1_OCREF_CLR_TIM1
// - SFDITEM_FIELD__SYSCFG_CFGR2_COMP2_OCREF_CLR_TIM1
//
//
// -------------------------- Register Item Address: SYSCFG_PA_ENS ------------------------------
// SVD Line: 5317
unsigned int SYSCFG_PA_ENS __AT (0x40010010);
// ---------------------------- Field Item: SYSCFG_PA_ENS_PA_ENS --------------------------------
// SVD Line: 5321
// - SFDITEM_FIELD__SYSCFG_PA_ENS_PA_ENS
// PA_ENS
//
// [Bits 15..0] RW (@ 0x40010010) Pa Noise filter enable
//
// ( (unsigned short)((SYSCFG_PA_ENS >> 0) & 0xFFFF), ((SYSCFG_PA_ENS = (SYSCFG_PA_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PA_ENS ---------------------------------
// SVD Line: 5317
// SFDITEM_REG__SYSCFG_PA_ENS
// PA_ENS
//
// [Bits 31..0] RW (@ 0x40010010) PA_ENS
// ( (unsigned int)((SYSCFG_PA_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ENS = (SYSCFG_PA_ENS & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ENS_PA_ENS
//
//
// -------------------------- Register Item Address: SYSCFG_PB_ENS ------------------------------
// SVD Line: 5328
unsigned int SYSCFG_PB_ENS __AT (0x40010014);
// ---------------------------- Field Item: SYSCFG_PB_ENS_PB_ENS --------------------------------
// SVD Line: 5332
// - SFDITEM_FIELD__SYSCFG_PB_ENS_PB_ENS
// PB_ENS
//
// [Bits 3..0] RW (@ 0x40010014) Pb Noise filter enable
//
// ( (unsigned char)((SYSCFG_PB_ENS >> 0) & 0xF), ((SYSCFG_PB_ENS = (SYSCFG_PB_ENS & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PB_ENS ---------------------------------
// SVD Line: 5328
// SFDITEM_REG__SYSCFG_PB_ENS
// PB_ENS
//
// [Bits 31..0] RW (@ 0x40010014) PB_ENS
// ( (unsigned int)((SYSCFG_PB_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_ENS = (SYSCFG_PB_ENS & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_ENS_PB_ENS
//
//
// -------------------------- Register Item Address: SYSCFG_PF_ENS ------------------------------
// SVD Line: 5339
unsigned int SYSCFG_PF_ENS __AT (0x40010018);
// ---------------------------- Field Item: SYSCFG_PF_ENS_PF_ENS --------------------------------
// SVD Line: 5343
// - SFDITEM_FIELD__SYSCFG_PF_ENS_PF_ENS
// PF_ENS
//
// [Bits 5..0] RW (@ 0x40010018) Pf Noise filter enable
//
// ( (unsigned char)((SYSCFG_PF_ENS >> 0) & 0x3F), ((SYSCFG_PF_ENS = (SYSCFG_PF_ENS & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_PF_ENS ---------------------------------
// SVD Line: 5339
// SFDITEM_REG__SYSCFG_PF_ENS
// PF_ENS
//
// [Bits 31..0] RW (@ 0x40010018) PF_ENS
// ( (unsigned int)((SYSCFG_PF_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_ENS = (SYSCFG_PF_ENS & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_ENS_PF_ENS
//
//
// --------------------------- Register Item Address: SYSCFG_IOCFG ------------------------------
// SVD Line: 5350
unsigned int SYSCFG_IOCFG __AT (0x4001001C);
// ---------------------------- Field Item: SYSCFG_IOCFG_PA_EIIC --------------------------------
// SVD Line: 5354
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EIIC
// PA_EIIC
//
// [Bits 1..0] RW (@ 0x4001001C) Pa I2C IO enable
//
// ( (unsigned char)((SYSCFG_IOCFG >> 0) & 0x3), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IOCFG_PF_EIIC --------------------------------
// SVD Line: 5359
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_EIIC
// PF_EIIC
//
// [Bits 4..2] RW (@ 0x4001001C) Pf I2C IO enable
//
// ( (unsigned char)((SYSCFG_IOCFG >> 2) & 0x7), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x7UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_IOCFG_PF_PU_IIC -------------------------------
// SVD Line: 5364
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_PU_IIC
// PF_PU_IIC
//
// [Bits 7..6] RW (@ 0x4001001C) Pf I2C Pull-up resistor control enable
//
// ( (unsigned char)((SYSCFG_IOCFG >> 6) & 0x3), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ----------------------------- Field Item: SYSCFG_IOCFG_PA_EHS --------------------------------
// SVD Line: 5369
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EHS
// PA_EHS
//
// [Bits 12..8] RW (@ 0x4001001C) Pa LED IO Conrtol
//
// ( (unsigned char)((SYSCFG_IOCFG >> 8) & 0x1F), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_IOCFG_PA_IODRVP -------------------------------
// SVD Line: 5374
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_IODRVP
// PA_IODRVP
//
// [Bits 14..13] RW (@ 0x4001001C) Pa I2C_VCC Output Drive config
//
// ( (unsigned char)((SYSCFG_IOCFG >> 13) & 0x3), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IOCFG_PA_ENSEG -------------------------------
// SVD Line: 5379
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_ENSEG
// PA_ENSEG
//
// [Bits 21..16] RW (@ 0x4001001C) Pa Seg Mode enable
//
// ( (unsigned char)((SYSCFG_IOCFG >> 16) & 0x3F), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IOCFG_PB_ENSEG -------------------------------
// SVD Line: 5384
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_ENSEG
// PB_ENSEG
//
// [Bits 23..22] RW (@ 0x4001001C) Pb Seg Mode enable
//
// ( (unsigned char)((SYSCFG_IOCFG >> 22) & 0x3), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_IOCFG ----------------------------------
// SVD Line: 5350
// SFDITEM_REG__SYSCFG_IOCFG
// IOCFG
//
// [Bits 31..0] RW (@ 0x4001001C) IOCFG
// ( (unsigned int)((SYSCFG_IOCFG >> 0) & 0xFFFFFFFF), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0xFF7FDFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF7FDF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_PU_IIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EHS
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_IODRVP
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_ENSEG
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_ENSEG
//
//
// ------------------------- Register Item Address: SYSCFG_PA_ANA2EN ----------------------------
// SVD Line: 5391
unsigned int SYSCFG_PA_ANA2EN __AT (0x40010020);
// ------------------------- Field Item: SYSCFG_PA_ANA2EN_PA_ANA2EN -----------------------------
// SVD Line: 5395
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA_ANA2EN
// PA_ANA2EN
//
// [Bits 15..0] RW (@ 0x40010020) Pa Analog Noise filter enable
//
// ( (unsigned short)((SYSCFG_PA_ANA2EN >> 0) & 0xFFFF), ((SYSCFG_PA_ANA2EN = (SYSCFG_PA_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PA_ANA2EN --------------------------------
// SVD Line: 5391
// SFDITEM_REG__SYSCFG_PA_ANA2EN
// PA_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010020) PA_ANA2EN
// ( (unsigned int)((SYSCFG_PA_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ANA2EN = (SYSCFG_PA_ANA2EN & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA_ANA2EN
//
//
// ------------------------- Register Item Address: SYSCFG_PB_ANA2EN ----------------------------
// SVD Line: 5402
unsigned int SYSCFG_PB_ANA2EN __AT (0x40010024);
// --------------------------- Field Item: SYSCFG_PB_ANA2EN_PB_ENS ------------------------------
// SVD Line: 5406
// - SFDITEM_FIELD__SYSCFG_PB_ANA2EN_PB_ENS
// PB_ENS
//
// [Bits 3..0] RW (@ 0x40010024) Pb Analog Noise filter enable
//
// ( (unsigned char)((SYSCFG_PB_ANA2EN >> 0) & 0xF), ((SYSCFG_PB_ANA2EN = (SYSCFG_PB_ANA2EN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PB_ANA2EN --------------------------------
// SVD Line: 5402
// SFDITEM_REG__SYSCFG_PB_ANA2EN
// PB_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010024) PB_ANA2EN
// ( (unsigned int)((SYSCFG_PB_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_ANA2EN = (SYSCFG_PB_ANA2EN & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_ANA2EN_PB_ENS
//
//
// ------------------------- Register Item Address: SYSCFG_PF_ANA2EN ----------------------------
// SVD Line: 5413
unsigned int SYSCFG_PF_ANA2EN __AT (0x40010028);
// ------------------------- Field Item: SYSCFG_PF_ANA2EN_PF_ANA2EN -----------------------------
// SVD Line: 5417
// - SFDITEM_FIELD__SYSCFG_PF_ANA2EN_PF_ANA2EN
// PF_ANA2EN
//
// [Bits 5..0] RW (@ 0x40010028) Pf Analog Noise filter enable
//
// ( (unsigned char)((SYSCFG_PF_ANA2EN >> 0) & 0x3F), ((SYSCFG_PF_ANA2EN = (SYSCFG_PF_ANA2EN & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PF_ANA2EN --------------------------------
// SVD Line: 5413
// SFDITEM_REG__SYSCFG_PF_ANA2EN
// PF_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010028) PF_ANA2EN
// ( (unsigned int)((SYSCFG_PF_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_ANA2EN = (SYSCFG_PF_ANA2EN & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_ANA2EN_PF_ANA2EN
//
//
// -------------------------- Register Item Address: SYSCFG_PA_IORP -----------------------------
// SVD Line: 5424
unsigned int SYSCFG_PA_IORP __AT (0x40010030);
// --------------------------- Field Item: SYSCFG_PA_IORP_PA0_IORP ------------------------------
// SVD Line: 5428
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA0_IORP
// PA0_IORP
//
// [Bits 1..0] RW (@ 0x40010030) Pa0 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 0) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA1_IORP ------------------------------
// SVD Line: 5433
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA1_IORP
// PA1_IORP
//
// [Bits 3..2] RW (@ 0x40010030) Pa1 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 2) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA2_IORP ------------------------------
// SVD Line: 5438
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA2_IORP
// PA2_IORP
//
// [Bits 5..4] RW (@ 0x40010030) Pa2 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 4) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA3_IORP ------------------------------
// SVD Line: 5443
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA3_IORP
// PA3_IORP
//
// [Bits 7..6] RW (@ 0x40010030) Pa3 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 6) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA4_IORP ------------------------------
// SVD Line: 5448
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA4_IORP
// PA4_IORP
//
// [Bits 9..8] RW (@ 0x40010030) Pa4 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 8) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA5_IORP ------------------------------
// SVD Line: 5453
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA5_IORP
// PA5_IORP
//
// [Bits 11..10] RW (@ 0x40010030) Pa5 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 10) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA6_IORP ------------------------------
// SVD Line: 5458
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA6_IORP
// PA6_IORP
//
// [Bits 13..12] RW (@ 0x40010030) Pa6 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 12) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA7_IORP ------------------------------
// SVD Line: 5463
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA7_IORP
// PA7_IORP
//
// [Bits 15..14] RW (@ 0x40010030) Pa7 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 14) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA8_IORP ------------------------------
// SVD Line: 5468
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA8_IORP
// PA8_IORP
//
// [Bits 17..16] RW (@ 0x40010030) Pa8 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 16) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PA_IORP_PA9_IORP ------------------------------
// SVD Line: 5473
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA9_IORP
// PA9_IORP
//
// [Bits 19..18] RW (@ 0x40010030) Pa9 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 18) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA10_IORP ------------------------------
// SVD Line: 5478
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA10_IORP
// PA10_IORP
//
// [Bits 21..20] RW (@ 0x40010030) Pa10 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 20) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA11_IORP ------------------------------
// SVD Line: 5483
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA11_IORP
// PA11_IORP
//
// [Bits 23..22] RW (@ 0x40010030) Pa11 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 22) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA12_IORP ------------------------------
// SVD Line: 5488
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA12_IORP
// PA12_IORP
//
// [Bits 25..24] RW (@ 0x40010030) Pa12 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 24) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA13_IORP ------------------------------
// SVD Line: 5493
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA13_IORP
// PA13_IORP
//
// [Bits 27..26] RW (@ 0x40010030) Pa13 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 26) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA14_IORP ------------------------------
// SVD Line: 5498
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA14_IORP
// PA14_IORP
//
// [Bits 29..28] RW (@ 0x40010030) Pa14 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 28) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_PA_IORP_PA15_IORP ------------------------------
// SVD Line: 5503
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA15_IORP
// PA15_IORP
//
// [Bits 31..30] RW (@ 0x40010030) Pa15 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PA_IORP >> 30) & 0x3), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_PA_IORP ---------------------------------
// SVD Line: 5424
// SFDITEM_REG__SYSCFG_PA_IORP
// PA_IORP
//
// [Bits 31..0] RW (@ 0x40010030) PA_IORP
// ( (unsigned int)((SYSCFG_PA_IORP >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_IORP = (SYSCFG_PA_IORP & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA0_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA1_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA2_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA3_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA4_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA5_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA6_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA7_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA8_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA9_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA10_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA11_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA12_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA13_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA14_IORP
// - SFDITEM_FIELD__SYSCFG_PA_IORP_PA15_IORP
//
//
// -------------------------- Register Item Address: SYSCFG_PB_IORP -----------------------------
// SVD Line: 5510
unsigned int SYSCFG_PB_IORP __AT (0x40010034);
// --------------------------- Field Item: SYSCFG_PB_IORP_PB0_IORP ------------------------------
// SVD Line: 5514
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB0_IORP
// PB0_IORP
//
// [Bits 1..0] RW (@ 0x40010034) Pb0 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PB_IORP >> 0) & 0x3), ((SYSCFG_PB_IORP = (SYSCFG_PB_IORP & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PB_IORP_PB1_IORP ------------------------------
// SVD Line: 5519
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB1_IORP
// PB1_IORP
//
// [Bits 3..2] RW (@ 0x40010034) Pb1 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PB_IORP >> 2) & 0x3), ((SYSCFG_PB_IORP = (SYSCFG_PB_IORP & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PB_IORP_PB2_IORP ------------------------------
// SVD Line: 5524
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB2_IORP
// PB2_IORP
//
// [Bits 5..4] RW (@ 0x40010034) Pb2 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PB_IORP >> 4) & 0x3), ((SYSCFG_PB_IORP = (SYSCFG_PB_IORP & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PB_IORP_PB3_IORP ------------------------------
// SVD Line: 5529
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB3_IORP
// PB3_IORP
//
// [Bits 7..6] RW (@ 0x40010034) Pb3 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PB_IORP >> 6) & 0x3), ((SYSCFG_PB_IORP = (SYSCFG_PB_IORP & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_PB_IORP ---------------------------------
// SVD Line: 5510
// SFDITEM_REG__SYSCFG_PB_IORP
// PB_IORP
//
// [Bits 31..0] RW (@ 0x40010034) PB_IORP
// ( (unsigned int)((SYSCFG_PB_IORP >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_IORP = (SYSCFG_PB_IORP & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB0_IORP
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB1_IORP
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB2_IORP
// - SFDITEM_FIELD__SYSCFG_PB_IORP_PB3_IORP
//
//
// -------------------------- Register Item Address: SYSCFG_PF_IORP -----------------------------
// SVD Line: 5536
unsigned int SYSCFG_PF_IORP __AT (0x40010038);
// --------------------------- Field Item: SYSCFG_PF_IORP_PF0_IORP ------------------------------
// SVD Line: 5540
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF0_IORP
// PF0_IORP
//
// [Bits 1..0] RW (@ 0x40010038) Pf0 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 0) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PF_IORP_PF1_IORP ------------------------------
// SVD Line: 5545
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF1_IORP
// PF1_IORP
//
// [Bits 3..2] RW (@ 0x40010038) Pf1 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 2) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PF_IORP_PF2_IORP ------------------------------
// SVD Line: 5550
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF2_IORP
// PF2_IORP
//
// [Bits 5..4] RW (@ 0x40010038) Pf2 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 4) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PF_IORP_PF3_IORP ------------------------------
// SVD Line: 5555
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF3_IORP
// PF3_IORP
//
// [Bits 7..6] RW (@ 0x40010038) Pf3 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 6) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PF_IORP_PF4_IORP ------------------------------
// SVD Line: 5560
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF4_IORP
// PF4_IORP
//
// [Bits 9..8] RW (@ 0x40010038) Pf4 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 8) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_PF_IORP_PF5_IORP ------------------------------
// SVD Line: 5565
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF5_IORP
// PF5_IORP
//
// [Bits 11..10] RW (@ 0x40010038) Pf5 IO pull-up pull-down resistance config
//
// ( (unsigned char)((SYSCFG_PF_IORP >> 10) & 0x3), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_PF_IORP ---------------------------------
// SVD Line: 5536
// SFDITEM_REG__SYSCFG_PF_IORP
// PF_IORP
//
// [Bits 31..0] RW (@ 0x40010038) PF_IORP
// ( (unsigned int)((SYSCFG_PF_IORP >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_IORP = (SYSCFG_PF_IORP & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF0_IORP
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF1_IORP
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF2_IORP
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF3_IORP
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF4_IORP
// - SFDITEM_FIELD__SYSCFG_PF_IORP_PF5_IORP
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 5253
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR1
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_PA_ENS
// - SFDITEM_REG__SYSCFG_PB_ENS
// - SFDITEM_REG__SYSCFG_PF_ENS
// - SFDITEM_REG__SYSCFG_IOCFG
// - SFDITEM_REG__SYSCFG_PA_ANA2EN
// - SFDITEM_REG__SYSCFG_PB_ANA2EN
// - SFDITEM_REG__SYSCFG_PF_ANA2EN
// - SFDITEM_REG__SYSCFG_PA_IORP
// - SFDITEM_REG__SYSCFG_PB_IORP
// - SFDITEM_REG__SYSCFG_PF_IORP
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 5595
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 5600
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) CEN
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 5604
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) UDIS
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 5608
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) URS
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 5612
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) OPM
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 5616
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) DIR
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 5620
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) CMS
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 5624
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) ARPE
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 5628
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) CKD
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 5595
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) CR1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 5634
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 5639
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) CCPC
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 5643
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) CCUS
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_MMS ------------------------------------
// SVD Line: 5647
// - SFDITEM_FIELD__TIM1_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40012C04) MMS
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 5651
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) TI1S
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 5655
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) OIS1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 5659
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) OIS1N
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 5663
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) OIS2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 5667
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) OIS2N
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 5671
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) OIS3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 5675
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) OIS3N
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 5679
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) OIS4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 5634
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) CR2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7FF5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF5) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_MMS
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 5685
unsigned int TIM1_SMCR __AT (0x40012C08);
// -------------------------------- Field Item: TIM1_SMCR_SMS -----------------------------------
// SVD Line: 5690
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40012C08) SMS
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 5694
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) OCCS
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_TS ------------------------------------
// SVD Line: 5698
// - SFDITEM_FIELD__TIM1_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40012C08) TS
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 5702
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) MSM
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 5706
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) ETF
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 5710
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) ETPS
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 5714
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) ECE
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 5718
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) ETP
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_SMS_3 ----------------------------------
// SVD Line: 5722
// - SFDITEM_FIELD__TIM1_SMCR_SMS_3
// SMS_3
//
// [Bit 16] RW (@ 0x40012C08) SMS_3
//
// ( (unsigned int) TIM1_SMCR )
// SMS_3
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 5685
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) SMCR
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// - SFDITEM_FIELD__TIM1_SMCR_SMS_3
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 5728
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 5733
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) UIE
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 5737
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) CC1IE
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 5741
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) CC2IE
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 5745
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) CC3IE
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 5749
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) CC4IE
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 5753
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) COMIE
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 5757
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) TIE
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 5761
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) BIE
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 5728
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) DIER
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 5767
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 5772
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) UIF
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 5776
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) CC1IF
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 5780
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) CC2IF
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 5784
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) CC3IF
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 5788
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) CC4IF
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 5792
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) COMIF
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 5796
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) TIF
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 5800
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) BIF
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 5804
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) CC1OF
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 5808
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) CC2OF
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 5812
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) CC3OF
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 5816
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) CC4OF
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 5820
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40012C10) IC1IR
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 5824
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 17] RW (@ 0x40012C10) IC2IR
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 5828
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 18] RW (@ 0x40012C10) IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 5832
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 19] RW (@ 0x40012C10) IC4IR
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 5836
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40012C10) IC1IF
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 5840
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 21] RW (@ 0x40012C10) IC2IF
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 5844
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 22] RW (@ 0x40012C10) IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 5848
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 23] RW (@ 0x40012C10) IC4IF
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 5767
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) SR
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0xFF1EFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1EFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 5854
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 5860
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40012C14) UG
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 5865
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40012C14) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 5871
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] WO (@ 0x40012C14) CC2G
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 5876
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] WO (@ 0x40012C14) CC3G
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 5881
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] WO (@ 0x40012C14) CC4G
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 5886
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40012C14) COMG
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 5891
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] WO (@ 0x40012C14) TG
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 5896
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40012C14) BG
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 5854
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40012C14) EGR
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_OUTPUT ----------------------------
// SVD Line: 5903
unsigned int TIM1_CCMR1_OUTPUT __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 5908
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) CC1S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 0) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 5912
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) OC1FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 5916
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) OC1PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M -------------------------------
// SVD Line: 5920
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40012C18) OC1M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 4) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 5924
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) OC1CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 5928
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) CC2S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 8) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 5932
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) OC2FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 5936
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) OC2PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M -------------------------------
// SVD Line: 5940
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40012C18) OC2M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 12) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 5944
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) OC2CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M_3 ------------------------------
// SVD Line: 5948
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_3
// OC1M_3
//
// [Bit 16] RW (@ 0x40012C18) OC1M_3
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1M_3
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M_3 ------------------------------
// SVD Line: 5952
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_3
// OC2M_3
//
// [Bit 24] RW (@ 0x40012C18) OC2M_3
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2M_3
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_OUTPUT -------------------------------
// SVD Line: 5903
// SFDITEM_REG__TIM1_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C18) CCMR1_OUTPUT
// ( (unsigned int)((TIM1_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_3
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_3
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_INPUT ----------------------------
// SVD Line: 5958
unsigned int TIM1_CCMR1_INPUT __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 5964
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) CC1S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 0) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 5968
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40012C18) IC1PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 2) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 5972
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) IC1F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 4) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 5976
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) CC2S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 8) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 5980
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) IC2PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 10) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 5984
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) IC2F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 12) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_INPUT --------------------------------
// SVD Line: 5958
// SFDITEM_REG__TIM1_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40012C18) CCMR1_INPUT
// ( (unsigned int)((TIM1_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_OUTPUT ----------------------------
// SVD Line: 5990
unsigned int TIM1_CCMR2_OUTPUT __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 5995
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) CC3S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 0) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 5999
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) OC3FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 6003
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) OC3PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M -------------------------------
// SVD Line: 6007
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x40012C1C) OC3M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 4) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 6011
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) OC3CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 6015
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) CC4S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 8) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 6019
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) OC4FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 6023
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) OC4PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M -------------------------------
// SVD Line: 6027
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x40012C1C) OC4M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 12) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 6031
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) OC4CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4CE
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M_3 ------------------------------
// SVD Line: 6035
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_3
// OC3M_3
//
// [Bit 16] RW (@ 0x40012C1C) OC3M_3
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3M_3
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M_3 ------------------------------
// SVD Line: 6039
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_3
// OC4M_3
//
// [Bit 24] RW (@ 0x40012C1C) OC4M_3
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4M_3
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_OUTPUT -------------------------------
// SVD Line: 5990
// SFDITEM_REG__TIM1_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) CCMR2_OUTPUT
// ( (unsigned int)((TIM1_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_3
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_3
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_INPUT ----------------------------
// SVD Line: 6045
unsigned int TIM1_CCMR2_INPUT __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 6051
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) CC3S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 0) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 6055
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) IC3PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 2) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 6059
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) IC3F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 4) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 6063
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) CC4S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 8) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 6067
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) IC4PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 10) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 6071
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) IC4F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 12) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_INPUT --------------------------------
// SVD Line: 6045
// SFDITEM_REG__TIM1_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) CCMR2_INPUT
// ( (unsigned int)((TIM1_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 6077
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 6082
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) CC1E
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 6086
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) CC1P
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 6090
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) CC1NE
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 6094
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) CC1NP
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 6098
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) CC2E
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 6102
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) CC2P
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 6106
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) CC2NE
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 6110
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) CC2NP
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 6114
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) CC3E
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 6118
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) CC3P
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 6122
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) CC3NE
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 6126
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) CC3NP
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 6130
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) CC4E
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 6134
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) CC4P
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 6077
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) CCER
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 6140
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 6145
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) CNT
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 6140
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) CNT
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 6151
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 6156
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) PSC
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 6151
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) PSC
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 6162
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 6168
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) ARR
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 6162
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) ARR
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 6174
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 6180
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) REP
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 6174
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) RCR
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 6186
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 6191
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) CCR1
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 6186
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) CCR1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 6197
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 6202
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) CCR2
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 6197
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) CCR2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 6208
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 6213
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) CCR3
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 6208
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) CCR3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 6219
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 6224
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) CCR4
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 6219
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) CCR4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 6230
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 6235
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) DTG
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 6239
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) LOCK
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 6243
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) OSSI
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 6247
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) OSSR
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 6251
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) BKE
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 6255
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) BKP
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 6259
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) AOE
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 6263
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) MOE
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 6230
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) BDTR
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 5574
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_OUTPUT
// - SFDITEM_REG__TIM1_CCMR1_INPUT
// - SFDITEM_REG__TIM1_CCMR2_OUTPUT
// - SFDITEM_REG__TIM1_CCMR2_INPUT
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 6287
unsigned int TIM14_CR1 __AT (0x40002000);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 6292
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002000) CEN
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 6296
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002000) UDIS
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 6300
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002000) URS
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_OPM -----------------------------------
// SVD Line: 6304
// - SFDITEM_FIELD__TIM14_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40002000) OPM
//
// ( (unsigned int) TIM14_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 6308
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002000) ARPE
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 6312
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002000) CKD
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 6287
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002000) CR1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_OPM
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 6318
unsigned int TIM14_DIER __AT (0x4000200C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 6323
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000200C) UIE
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 6327
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000200C) CC1IE
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 6318
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000200C) DIER
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 6333
unsigned int TIM14_SR __AT (0x40002010);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 6338
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002010) UIF
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 6342
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002010) CC1IF
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 6346
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002010) CC1OF
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 6333
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002010) SR
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x203UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x203) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 6352
unsigned int TIM14_EGR __AT (0x40002014);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 6358
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40002014) UG
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 6363
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40002014) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 6352
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40002014) EGR
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_OUTPUT ---------------------------
// SVD Line: 6371
unsigned int TIM14_CCMR1_OUTPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 6376
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) CC1S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 0) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 6380
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002018) OC1PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M ------------------------------
// SVD Line: 6384
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40002018) OC1M
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 4) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_OUTPUT -------------------------------
// SVD Line: 6371
// SFDITEM_REG__TIM14_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40002018) CCMR1_OUTPUT
// ( (unsigned int)((TIM14_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7B) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_INPUT ----------------------------
// SVD Line: 6390
unsigned int TIM14_CCMR1_INPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 6396
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) CC1S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 0) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 6400
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002018) IC1PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 2) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 6404
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002018) IC1F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 4) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_INPUT -------------------------------
// SVD Line: 6390
// SFDITEM_REG__TIM14_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40002018) CCMR1_INPUT
// ( (unsigned int)((TIM14_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 6410
unsigned int TIM14_CCER __AT (0x40002020);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 6415
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002020) CC1E
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 6419
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002020) CC1P
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 6423
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002020) CC1NP
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 6410
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002020) CCER
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 6429
unsigned int TIM14_CNT __AT (0x40002024);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 6434
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002024) CNT
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 6429
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002024) CNT
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 6440
unsigned int TIM14_PSC __AT (0x40002028);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 6445
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002028) PSC
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 6440
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002028) PSC
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 6451
unsigned int TIM14_ARR __AT (0x4000202C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 6457
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000202C) ARR
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 6451
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000202C) ARR
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 6463
unsigned int TIM14_CCR1 __AT (0x40002034);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 6468
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002034) CCR1
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 6463
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002034) CCR1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// ----------------------------- Register Item Address: TIM14_OR --------------------------------
// SVD Line: 6474
unsigned int TIM14_OR __AT (0x40002050);
// ------------------------------ Field Item: TIM14_OR_TI1_RMP ----------------------------------
// SVD Line: 6478
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
// TI1_RMP
//
// [Bits 1..0] RW (@ 0x40002050) TI1_RMP
//
// ( (unsigned char)((TIM14_OR >> 0) & 0x3), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_OR ------------------------------------
// SVD Line: 6474
// SFDITEM_REG__TIM14_OR
// OR
//
// [Bits 31..0] RW (@ 0x40002050) OR
// ( (unsigned int)((TIM14_OR >> 0) & 0xFFFFFFFF), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 6271
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_OUTPUT
// - SFDITEM_REG__TIM14_CCMR1_INPUT
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_OR
//
//
// ------------------------------ Register Item Address: TK_CR1 ---------------------------------
// SVD Line: 6501
unsigned int TK_CR1 __AT (0x40003800);
// ---------------------------------- Field Item: TK_CR1_EN -------------------------------------
// SVD Line: 6506
// - SFDITEM_FIELD__TK_CR1_EN
// EN
//
// [Bit 0] RW (@ 0x40003800) TK enable
//
// ( (unsigned int) TK_CR1 )
// EN
//
//
//
// --------------------------------- Field Item: TK_CR1_MODE ------------------------------------
// SVD Line: 6511
// - SFDITEM_FIELD__TK_CR1_MODE
// MODE
//
// [Bits 2..1] RW (@ 0x40003800) TK mode select
//
// ( (unsigned char)((TK_CR1 >> 1) & 0x3), ((TK_CR1 = (TK_CR1 & ~(0x3UL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 1 ) ) ))
//
//
//
// ------------------------------ Field Item: TK_CR1_EXTCMODEN ----------------------------------
// SVD Line: 6516
// - SFDITEM_FIELD__TK_CR1_EXTCMODEN
// EXTCMODEN
//
// [Bit 3] RW (@ 0x40003800) External CMOD enable
//
// ( (unsigned int) TK_CR1 )
// EXTCMODEN
//
//
//
// -------------------------------- Field Item: TK_CR1_ICOPA ------------------------------------
// SVD Line: 6521
// - SFDITEM_FIELD__TK_CR1_ICOPA
// ICOPA
//
// [Bit 4] RW (@ 0x40003800) SIDAC source current or sink current select
//
// ( (unsigned int) TK_CR1 )
// ICOPA
//
//
//
// ------------------------------- Field Item: TK_CR1_COPAMODE ----------------------------------
// SVD Line: 6526
// - SFDITEM_FIELD__TK_CR1_COPAMODE
// COPAMODE
//
// [Bit 5] RW (@ 0x40003800) Key compensation enable
//
// ( (unsigned int) TK_CR1 )
// COPAMODE
//
//
//
// ------------------------------- Field Item: TK_CR1_COPADATA ----------------------------------
// SVD Line: 6531
// - SFDITEM_FIELD__TK_CR1_COPADATA
// COPADATA
//
// [Bits 7..6] RW (@ 0x40003800) unsensed key output control
//
// ( (unsigned char)((TK_CR1 >> 6) & 0x3), ((TK_CR1 = (TK_CR1 & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: TK_CR1_VCCTKCR -----------------------------------
// SVD Line: 6536
// - SFDITEM_FIELD__TK_CR1_VCCTKCR
// VCCTKCR
//
// [Bits 10..8] RW (@ 0x40003800) VCCTK voltage select
//
// ( (unsigned char)((TK_CR1 >> 8) & 0x7), ((TK_CR1 = (TK_CR1 & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: TK_CR1_VCC1CR -----------------------------------
// SVD Line: 6541
// - SFDITEM_FIELD__TK_CR1_VCC1CR
// VCC1CR
//
// [Bits 13..11] RW (@ 0x40003800) VCC1 voltage select
//
// ( (unsigned char)((TK_CR1 >> 11) & 0x7), ((TK_CR1 = (TK_CR1 & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// ------------------------------ Field Item: TK_CR1_MIDACSTEP ----------------------------------
// SVD Line: 6546
// - SFDITEM_FIELD__TK_CR1_MIDACSTEP
// MIDACSTEP
//
// [Bit 14] RW (@ 0x40003800) MIDAC step select
//
// ( (unsigned int) TK_CR1 )
// MIDACSTEP
//
//
//
// ------------------------------ Field Item: TK_CR1_SIDACSTEP ----------------------------------
// SVD Line: 6551
// - SFDITEM_FIELD__TK_CR1_SIDACSTEP
// SIDACSTEP
//
// [Bit 15] RW (@ 0x40003800) SIDAC step select
//
// ( (unsigned int) TK_CR1 )
// SIDACSTEP
//
//
//
// --------------------------------- Field Item: TK_CR1_CFT -------------------------------------
// SVD Line: 6556
// - SFDITEM_FIELD__TK_CR1_CFT
// CFT
//
// [Bits 18..16] RW (@ 0x40003800) CMP OUT filter select
//
// ( (unsigned char)((TK_CR1 >> 16) & 0x7), ((TK_CR1 = (TK_CR1 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ------------------------------- Field Item: TK_CR1_VCCTKEN -----------------------------------
// SVD Line: 6561
// - SFDITEM_FIELD__TK_CR1_VCCTKEN
// VCCTKEN
//
// [Bit 19] RW (@ 0x40003800) VCCTK voltage enable
//
// ( (unsigned int) TK_CR1 )
// VCCTKEN
//
//
//
// ------------------------------ Field Item: TK_CR1_INTCMODEN ----------------------------------
// SVD Line: 6566
// - SFDITEM_FIELD__TK_CR1_INTCMODEN
// INTCMODEN
//
// [Bit 20] RW (@ 0x40003800) Internal CMOD enable
//
// ( (unsigned int) TK_CR1 )
// INTCMODEN
//
//
//
// ------------------------------- Field Item: TK_CR1_CMPHYSEN ----------------------------------
// SVD Line: 6571
// - SFDITEM_FIELD__TK_CR1_CMPHYSEN
// CMPHYSEN
//
// [Bit 21] RW (@ 0x40003800) CMP hysteresis enable
//
// ( (unsigned int) TK_CR1 )
// CMPHYSEN
//
//
//
// ------------------------------- Field Item: TK_CR1_BUFFEREN ----------------------------------
// SVD Line: 6576
// - SFDITEM_FIELD__TK_CR1_BUFFEREN
// BUFFEREN
//
// [Bit 22] RW (@ 0x40003800) Discharge buffer enable
//
// ( (unsigned int) TK_CR1 )
// BUFFEREN
//
//
//
// --------------------------------- Field Item: TK_CR1_DIV -------------------------------------
// SVD Line: 6581
// - SFDITEM_FIELD__TK_CR1_DIV
// DIV
//
// [Bits 26..24] RW (@ 0x40003800) PCLK division(TK_CLK)
//
// ( (unsigned char)((TK_CR1 >> 24) & 0x7), ((TK_CR1 = (TK_CR1 & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// -------------------------------- Field Item: TK_CR1_STDIV ------------------------------------
// SVD Line: 6586
// - SFDITEM_FIELD__TK_CR1_STDIV
// STDIV
//
// [Bits 29..27] RW (@ 0x40003800) PCLK division(ST_CLK)
//
// ( (unsigned char)((TK_CR1 >> 27) & 0x7), ((TK_CR1 = (TK_CR1 & ~(0x7UL << 27 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 27 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_CR1 -------------------------------------
// SVD Line: 6501
// SFDITEM_REG__TK_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40003800) Control register 1
// ( (unsigned int)((TK_CR1 >> 0) & 0xFFFFFFFF), ((TK_CR1 = (TK_CR1 & ~(0x3F7FFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F7FFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_CR1_EN
// - SFDITEM_FIELD__TK_CR1_MODE
// - SFDITEM_FIELD__TK_CR1_EXTCMODEN
// - SFDITEM_FIELD__TK_CR1_ICOPA
// - SFDITEM_FIELD__TK_CR1_COPAMODE
// - SFDITEM_FIELD__TK_CR1_COPADATA
// - SFDITEM_FIELD__TK_CR1_VCCTKCR
// - SFDITEM_FIELD__TK_CR1_VCC1CR
// - SFDITEM_FIELD__TK_CR1_MIDACSTEP
// - SFDITEM_FIELD__TK_CR1_SIDACSTEP
// - SFDITEM_FIELD__TK_CR1_CFT
// - SFDITEM_FIELD__TK_CR1_VCCTKEN
// - SFDITEM_FIELD__TK_CR1_INTCMODEN
// - SFDITEM_FIELD__TK_CR1_CMPHYSEN
// - SFDITEM_FIELD__TK_CR1_BUFFEREN
// - SFDITEM_FIELD__TK_CR1_DIV
// - SFDITEM_FIELD__TK_CR1_STDIV
//
//
// ------------------------------ Register Item Address: TK_CR2 ---------------------------------
// SVD Line: 6593
unsigned int TK_CR2 __AT (0x40003804);
// -------------------------------- Field Item: TK_CR2_START ------------------------------------
// SVD Line: 6598
// - SFDITEM_FIELD__TK_CR2_START
// START
//
// [Bit 0] RW (@ 0x40003804) Sense start
//
// ( (unsigned int) TK_CR2 )
// START
//
//
//
// --------------------------------- Field Item: TK_CR2_RSTB ------------------------------------
// SVD Line: 6603
// - SFDITEM_FIELD__TK_CR2_RSTB
// RSTB
//
// [Bit 1] RW (@ 0x40003804) Counter reset
//
// ( (unsigned int) TK_CR2 )
// RSTB
//
//
//
// -------------------------------- Field Item: TK_CR2_SWCTRL -----------------------------------
// SVD Line: 6608
// - SFDITEM_FIELD__TK_CR2_SWCTRL
// SWCTRL
//
// [Bit 2] RW (@ 0x40003804) TK_SW control
//
// ( (unsigned int) TK_CR2 )
// SWCTRL
//
//
//
// ------------------------------- Field Item: TK_CR2_CMODCHRG ----------------------------------
// SVD Line: 6613
// - SFDITEM_FIELD__TK_CR2_CMODCHRG
// CMODCHRG
//
// [Bit 3] RW (@ 0x40003804) CMOD charge enable
//
// ( (unsigned int) TK_CR2 )
// CMODCHRG
//
//
//
// ------------------------------ Field Item: TK_CR2_CMODDISCH ----------------------------------
// SVD Line: 6618
// - SFDITEM_FIELD__TK_CR2_CMODDISCH
// CMODDISCH
//
// [Bit 4] RW (@ 0x40003804) CMOD discharge enable
//
// ( (unsigned int) TK_CR2 )
// CMODDISCH
//
//
//
// ------------------------------- Field Item: TK_CR2_MIDACEN -----------------------------------
// SVD Line: 6623
// - SFDITEM_FIELD__TK_CR2_MIDACEN
// MIDACEN
//
// [Bit 5] RW (@ 0x40003804) Main IDAC enable
//
// ( (unsigned int) TK_CR2 )
// MIDACEN
//
//
//
// ------------------------------- Field Item: TK_CR2_SIDACEN -----------------------------------
// SVD Line: 6628
// - SFDITEM_FIELD__TK_CR2_SIDACEN
// SIDACEN
//
// [Bit 6] RW (@ 0x40003804) Slave IDAC enable
//
// ( (unsigned int) TK_CR2 )
// SIDACEN
//
//
//
// ------------------------------ Field Item: TK_CR2_CMODVTINIT ---------------------------------
// SVD Line: 6633
// - SFDITEM_FIELD__TK_CR2_CMODVTINIT
// CMODVTINIT
//
// [Bit 7] RW (@ 0x40003804) The voltage of CMOD initialization
//
// ( (unsigned int) TK_CR2 )
// CMODVTINIT
//
//
//
// --------------------------------- Field Item: TK_CR2_PWMM ------------------------------------
// SVD Line: 6638
// - SFDITEM_FIELD__TK_CR2_PWMM
// PWMM
//
// [Bit 8] RW (@ 0x40003804) PWM mode select
//
// ( (unsigned int) TK_CR2 )
// PWMM
//
//
//
// ------------------------------ Field Item: TK_CR2_CTRLSOURCE ---------------------------------
// SVD Line: 6643
// - SFDITEM_FIELD__TK_CR2_CTRLSOURCE
// CTRLSOURCE
//
// [Bit 9] RW (@ 0x40003804) Software or hardware select
//
// ( (unsigned int) TK_CR2 )
// CTRLSOURCE
//
//
//
// ------------------------------ Field Item: TK_CR2_LPABNORMAL ---------------------------------
// SVD Line: 6648
// - SFDITEM_FIELD__TK_CR2_LPABNORMAL
// LPABNORMAL
//
// [Bit 10] RW (@ 0x40003804) Lowpower wake up control
//
// ( (unsigned int) TK_CR2 )
// LPABNORMAL
//
//
//
// ---------------------------- Field Item: TK_CR2_CSA_DISCH_SEL --------------------------------
// SVD Line: 6653
// - SFDITEM_FIELD__TK_CR2_CSA_DISCH_SEL
// CSA_DISCH_SEL
//
// [Bit 11] RW (@ 0x40003804) CMOD discharge select in CSA mode
//
// ( (unsigned int) TK_CR2 )
// CSA_DISCH_SEL
//
//
//
// ----------------------------- Field Item: TK_CR2_SHORTSW_NUM ---------------------------------
// SVD Line: 6658
// - SFDITEM_FIELD__TK_CR2_SHORTSW_NUM
// SHORTSW_NUM
//
// [Bits 13..12] RW (@ 0x40003804) Short switch times of hardware mode in CSD mode
//
// ( (unsigned char)((TK_CR2 >> 12) & 0x3), ((TK_CR2 = (TK_CR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------------- Field Item: TK_CR2_LPEN ------------------------------------
// SVD Line: 6663
// - SFDITEM_FIELD__TK_CR2_LPEN
// LPEN
//
// [Bit 14] RW (@ 0x40003804) Lowpower wake up enable
//
// ( (unsigned int) TK_CR2 )
// LPEN
//
//
//
// -------------------------------- Field Item: TK_CR2_KVREF ------------------------------------
// SVD Line: 6668
// - SFDITEM_FIELD__TK_CR2_KVREF
// KVREF
//
// [Bits 17..16] RW (@ 0x40003804) Reference voltage select
//
// ( (unsigned char)((TK_CR2 >> 16) & 0x3), ((TK_CR2 = (TK_CR2 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// --------------------------- Field Item: TK_CR2_KVREF_CSA_TARGET ------------------------------
// SVD Line: 6673
// - SFDITEM_FIELD__TK_CR2_KVREF_CSA_TARGET
// KVREF_CSA_TARGET
//
// [Bits 19..18] RW (@ 0x40003804) Vref charging target value in CSA mode
//
// ( (unsigned char)((TK_CR2 >> 18) & 0x3), ((TK_CR2 = (TK_CR2 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: TK_CR2_LFSRW ------------------------------------
// SVD Line: 6678
// - SFDITEM_FIELD__TK_CR2_LFSRW
// LFSRW
//
// [Bits 23..20] RW (@ 0x40003804) LFSR valid bit
//
// ( (unsigned char)((TK_CR2 >> 20) & 0xF), ((TK_CR2 = (TK_CR2 & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_CR2 -------------------------------------
// SVD Line: 6593
// SFDITEM_REG__TK_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40003804) Control register 2
// ( (unsigned int)((TK_CR2 >> 0) & 0xFFFFFFFF), ((TK_CR2 = (TK_CR2 & ~(0xFF7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_CR2_START
// - SFDITEM_FIELD__TK_CR2_RSTB
// - SFDITEM_FIELD__TK_CR2_SWCTRL
// - SFDITEM_FIELD__TK_CR2_CMODCHRG
// - SFDITEM_FIELD__TK_CR2_CMODDISCH
// - SFDITEM_FIELD__TK_CR2_MIDACEN
// - SFDITEM_FIELD__TK_CR2_SIDACEN
// - SFDITEM_FIELD__TK_CR2_CMODVTINIT
// - SFDITEM_FIELD__TK_CR2_PWMM
// - SFDITEM_FIELD__TK_CR2_CTRLSOURCE
// - SFDITEM_FIELD__TK_CR2_LPABNORMAL
// - SFDITEM_FIELD__TK_CR2_CSA_DISCH_SEL
// - SFDITEM_FIELD__TK_CR2_SHORTSW_NUM
// - SFDITEM_FIELD__TK_CR2_LPEN
// - SFDITEM_FIELD__TK_CR2_KVREF
// - SFDITEM_FIELD__TK_CR2_KVREF_CSA_TARGET
// - SFDITEM_FIELD__TK_CR2_LFSRW
//
//
// ----------------------------- Register Item Address: TK_IDACR --------------------------------
// SVD Line: 6685
unsigned int TK_IDACR __AT (0x40003808);
// ------------------------------- Field Item: TK_IDACR_MIDAC -----------------------------------
// SVD Line: 6690
// - SFDITEM_FIELD__TK_IDACR_MIDAC
// MIDAC
//
// [Bits 7..0] RW (@ 0x40003808) Main IDAC configuration
//
// ( (unsigned char)((TK_IDACR >> 0) & 0xFF), ((TK_IDACR = (TK_IDACR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TK_IDACR_SIDAC -----------------------------------
// SVD Line: 6695
// - SFDITEM_FIELD__TK_IDACR_SIDAC
// SIDAC
//
// [Bits 23..16] RW (@ 0x40003808) Slave IDAC configuration
//
// ( (unsigned char)((TK_IDACR >> 16) & 0xFF), ((TK_IDACR = (TK_IDACR & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) ))
//
//
//
// -------------------------- Field Item: TK_IDACR_SIDAC_CSA_TARGET -----------------------------
// SVD Line: 6700
// - SFDITEM_FIELD__TK_IDACR_SIDAC_CSA_TARGET
// SIDAC_CSA_TARGET
//
// [Bits 31..24] RW (@ 0x40003808) SIDAC target value in CSA mode
//
// ( (unsigned char)((TK_IDACR >> 24) & 0xFF), ((TK_IDACR = (TK_IDACR & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: TK_IDACR ------------------------------------
// SVD Line: 6685
// SFDITEM_REG__TK_IDACR
// IDACR
//
// [Bits 31..0] RW (@ 0x40003808) IDAC Control register
// ( (unsigned int)((TK_IDACR >> 0) & 0xFFFFFFFF), ((TK_IDACR = (TK_IDACR & ~(0xFFFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_IDACR_MIDAC
// - SFDITEM_FIELD__TK_IDACR_SIDAC
// - SFDITEM_FIELD__TK_IDACR_SIDAC_CSA_TARGET
//
//
// ------------------------------ Register Item Address: TK_KR ----------------------------------
// SVD Line: 6707
unsigned int TK_KR __AT (0x4000380C);
// ---------------------------------- Field Item: TK_KR_KEN -------------------------------------
// SVD Line: 6712
// - SFDITEM_FIELD__TK_KR_KEN
// KEN
//
// [Bits 25..0] RW (@ 0x4000380C) Sense function enable
//
// ( (unsigned int)((TK_KR >> 0) & 0x3FFFFFF), ((TK_KR = (TK_KR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
//
//
//
// ---------------------------------- Register RTree: TK_KR -------------------------------------
// SVD Line: 6707
// SFDITEM_REG__TK_KR
// KR
//
// [Bits 31..0] RW (@ 0x4000380C) Key enable register
// ( (unsigned int)((TK_KR >> 0) & 0xFFFFFFFF), ((TK_KR = (TK_KR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_KR_KEN
//
//
// ------------------------------ Register Item Address: TK_CSR ---------------------------------
// SVD Line: 6719
unsigned int TK_CSR __AT (0x40003810);
// --------------------------------- Field Item: TK_CSR_CHS -------------------------------------
// SVD Line: 6724
// - SFDITEM_FIELD__TK_CSR_CHS
// CHS
//
// [Bits 25..0] RW (@ 0x40003810) Sense key select
//
// ( (unsigned int)((TK_CSR >> 0) & 0x3FFFFFF), ((TK_CSR = (TK_CSR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_CSR -------------------------------------
// SVD Line: 6719
// SFDITEM_REG__TK_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40003810) Channel Select register
// ( (unsigned int)((TK_CSR >> 0) & 0xFFFFFFFF), ((TK_CSR = (TK_CSR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_CSR_CHS
//
//
// ------------------------------ Register Item Address: TK_UCR ---------------------------------
// SVD Line: 6731
unsigned int TK_UCR __AT (0x40003814);
// ------------------------------ Field Item: TK_UCR_COPAMODEIO ---------------------------------
// SVD Line: 6736
// - SFDITEM_FIELD__TK_UCR_COPAMODEIO
// COPAMODEIO
//
// [Bits 25..0] RW (@ 0x40003814) IO compensation enable
//
// ( (unsigned int)((TK_UCR >> 0) & 0x3FFFFFF), ((TK_UCR = (TK_UCR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_UCR -------------------------------------
// SVD Line: 6731
// SFDITEM_REG__TK_UCR
// UCR
//
// [Bits 31..0] RW (@ 0x40003814) Unsel Control register
// ( (unsigned int)((TK_UCR >> 0) & 0xFFFFFFFF), ((TK_UCR = (TK_UCR & ~(0x3FFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_UCR_COPAMODEIO
//
//
// ----------------------------- Register Item Address: TK_STR1 ---------------------------------
// SVD Line: 6743
unsigned int TK_STR1 __AT (0x40003818);
// ------------------------------- Field Item: TK_STR1_SETTIME ----------------------------------
// SVD Line: 6748
// - SFDITEM_FIELD__TK_STR1_SETTIME
// SETTIME
//
// [Bits 9..0] RW (@ 0x40003818) Voltage building time in CSA mode or short switch time in CSD mode or discharge time in PCI mode
//
// ( (unsigned short)((TK_STR1 >> 0) & 0x3FF), ((TK_STR1 = (TK_STR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: TK_STR1_VTINITTIME ---------------------------------
// SVD Line: 6753
// - SFDITEM_FIELD__TK_STR1_VTINITTIME
// VTINITTIME
//
// [Bits 23..16] RW (@ 0x40003818) CMOD dischsrge time in CSA mode
//
// ( (unsigned char)((TK_STR1 >> 16) & 0xFF), ((TK_STR1 = (TK_STR1 & ~(0xFFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_STR1 ------------------------------------
// SVD Line: 6743
// SFDITEM_REG__TK_STR1
// STR1
//
// [Bits 31..0] RW (@ 0x40003818) Stable Time register 1
// ( (unsigned int)((TK_STR1 >> 0) & 0xFFFFFFFF), ((TK_STR1 = (TK_STR1 & ~(0xFF03FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF03FF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_STR1_SETTIME
// - SFDITEM_FIELD__TK_STR1_VTINITTIME
//
//
// ----------------------------- Register Item Address: TK_STR2 ---------------------------------
// SVD Line: 6760
unsigned int TK_STR2 __AT (0x4000381C);
// --------------------------- Field Item: TK_STR2_VREF_MIDAC_TIME ------------------------------
// SVD Line: 6765
// - SFDITEM_FIELD__TK_STR2_VREF_MIDAC_TIME
// VREF_MIDAC_TIME
//
// [Bits 4..0] RW (@ 0x4000381C) VREF or MIDAC stabilization time in CSA mode
//
// ( (unsigned char)((TK_STR2 >> 0) & 0x1F), ((TK_STR2 = (TK_STR2 & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TK_STR2_DISCH_CHRG_TIME ------------------------------
// SVD Line: 6770
// - SFDITEM_FIELD__TK_STR2_DISCH_CHRG_TIME
// DISCH_CHRG_TIME
//
// [Bits 14..8] RW (@ 0x4000381C) CMOD discharging or charging time in CSA mode
//
// ( (unsigned char)((TK_STR2 >> 8) & 0x7F), ((TK_STR2 = (TK_STR2 & ~(0x7FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: TK_STR2_SIDACTIME ---------------------------------
// SVD Line: 6775
// - SFDITEM_FIELD__TK_STR2_SIDACTIME
// SIDACTIME
//
// [Bits 20..16] RW (@ 0x4000381C) SIDAC stabilization time in CSA mode
//
// ( (unsigned char)((TK_STR2 >> 16) & 0x1F), ((TK_STR2 = (TK_STR2 & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) ))
//
//
//
// --------------------------- Field Item: TK_STR2_BEFORE_SW_TIME -------------------------------
// SVD Line: 6780
// - SFDITEM_FIELD__TK_STR2_BEFORE_SW_TIME
// BEFORE_SW_TIME
//
// [Bits 27..24] RW (@ 0x4000381C) From setting SIDACEN to switching TK_SW time in CSA mode or from clearing CMODDISCH to switching TK_SW time in PCI mode
//
// ( (unsigned char)((TK_STR2 >> 24) & 0xF), ((TK_STR2 = (TK_STR2 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------- Field Item: TK_STR2_CHRG_SIDACEN_TIME -----------------------------
// SVD Line: 6785
// - SFDITEM_FIELD__TK_STR2_CHRG_SIDACEN_TIME
// CHRG_SIDACEN_TIME
//
// [Bits 29..28] RW (@ 0x4000381C) From clearing CMODCHRG to setting SIDACEN time in CSA mode
//
// ( (unsigned char)((TK_STR2 >> 28) & 0x3), ((TK_STR2 = (TK_STR2 & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_STR2 ------------------------------------
// SVD Line: 6760
// SFDITEM_REG__TK_STR2
// STR2
//
// [Bits 31..0] RW (@ 0x4000381C) Stable Time register 2
// ( (unsigned int)((TK_STR2 >> 0) & 0xFFFFFFFF), ((TK_STR2 = (TK_STR2 & ~(0x3F1F7F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F1F7F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TK_STR2_VREF_MIDAC_TIME
// - SFDITEM_FIELD__TK_STR2_DISCH_CHRG_TIME
// - SFDITEM_FIELD__TK_STR2_SIDACTIME
// - SFDITEM_FIELD__TK_STR2_BEFORE_SW_TIME
// - SFDITEM_FIELD__TK_STR2_CHRG_SIDACEN_TIME
//
//
// ------------------------------ Register Item Address: TK_WR ----------------------------------
// SVD Line: 6792
unsigned int TK_WR __AT (0x40003820);
// ---------------------------------- Field Item: TK_WR_WIN -------------------------------------
// SVD Line: 6797
// - SFDITEM_FIELD__TK_WR_WIN
// WIN
//
// [Bits 15..0] RW (@ 0x40003820) Window time
//
// ( (unsigned short)((TK_WR >> 0) & 0xFFFF), ((TK_WR = (TK_WR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------------- Register RTree: TK_WR -------------------------------------
// SVD Line: 6792
// SFDITEM_REG__TK_WR
// WR
//
// [Bits 31..0] RW (@ 0x40003820) Window register
// ( (unsigned int)((TK_WR >> 0) & 0xFFFFFFFF), ((TK_WR = (TK_WR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_WR_WIN
//
//
// ------------------------------ Register Item Address: TK_SDR ---------------------------------
// SVD Line: 6804
unsigned int TK_SDR __AT (0x40003824);
// -------------------------------- Field Item: TK_SDR_SWDIV ------------------------------------
// SVD Line: 6809
// - SFDITEM_FIELD__TK_SDR_SWDIV
// SWDIV
//
// [Bits 8..0] RW (@ 0x40003824) TK_CLK division(TK_SW)
//
// ( (unsigned short)((TK_SDR >> 0) & 0x1FF), ((TK_SDR = (TK_SDR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_SDR -------------------------------------
// SVD Line: 6804
// SFDITEM_REG__TK_SDR
// SDR
//
// [Bits 31..0] RW (@ 0x40003824) Switch Divide register
// ( (unsigned int)((TK_SDR >> 0) & 0xFFFFFFFF), ((TK_SDR = (TK_SDR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_SDR_SWDIV
//
//
// ----------------------------- Register Item Address: TK_PRSR ---------------------------------
// SVD Line: 6816
unsigned int TK_PRSR __AT (0x40003828);
// -------------------------------- Field Item: TK_PRSR_LFSRP -----------------------------------
// SVD Line: 6821
// - SFDITEM_FIELD__TK_PRSR_LFSRP
// LFSRP
//
// [Bits 15..0] RW (@ 0x40003828) LFSR polynomial
//
// ( (unsigned short)((TK_PRSR >> 0) & 0xFFFF), ((TK_PRSR = (TK_PRSR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TK_PRSR_SEED ------------------------------------
// SVD Line: 6826
// - SFDITEM_FIELD__TK_PRSR_SEED
// SEED
//
// [Bits 31..16] RW (@ 0x40003828) LFSR seed
//
// ( (unsigned short)((TK_PRSR >> 16) & 0xFFFF), ((TK_PRSR = (TK_PRSR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_PRSR ------------------------------------
// SVD Line: 6816
// SFDITEM_REG__TK_PRSR
// PRSR
//
// [Bits 31..0] RW (@ 0x40003828) Pseudo Random Sequence register
// ( (unsigned int)((TK_PRSR >> 0) & 0xFFFFFFFF), ((TK_PRSR = (TK_PRSR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_PRSR_LFSRP
// - SFDITEM_FIELD__TK_PRSR_SEED
//
//
// ------------------------------ Register Item Address: TK_DR ----------------------------------
// SVD Line: 6833
unsigned int TK_DR __AT (0x4000382C);
// --------------------------------- Field Item: TK_DR_DATA -------------------------------------
// SVD Line: 6838
// - SFDITEM_FIELD__TK_DR_DATA
// DATA
//
// [Bits 15..0] RO (@ 0x4000382C) Sense data
//
// ( (unsigned short)((TK_DR >> 0) & 0xFFFF) )
//
//
//
// ---------------------------------- Register RTree: TK_DR -------------------------------------
// SVD Line: 6833
// SFDITEM_REG__TK_DR
// DR
//
// [Bits 31..0] RW (@ 0x4000382C) Data register
// ( (unsigned int)((TK_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__TK_DR_DATA
//
//
// ------------------------------ Register Item Address: TK_SR ----------------------------------
// SVD Line: 6846
unsigned int TK_SR __AT (0x40003830);
// ------------------------------- Field Item: TK_SR_SENSEDONE ----------------------------------
// SVD Line: 6851
// - SFDITEM_FIELD__TK_SR_SENSEDONE
// SENSEDONE
//
// [Bit 0] RO (@ 0x40003830) Sense finished
//
// ( (unsigned int) TK_SR )
// SENSEDONE
//
//
//
// -------------------------------- Field Item: TK_SR_CMPOUT ------------------------------------
// SVD Line: 6857
// - SFDITEM_FIELD__TK_SR_CMPOUT
// CMPOUT
//
// [Bit 1] RO (@ 0x40003830) CMP output
//
// ( (unsigned int) TK_SR )
// CMPOUT
//
//
//
// ------------------------------ Field Item: TK_SR_SHORTSWERR ----------------------------------
// SVD Line: 6863
// - SFDITEM_FIELD__TK_SR_SHORTSWERR
// SHORTSWERR
//
// [Bit 2] RO (@ 0x40003830) Short switch error of hardware in CSD mode
//
// ( (unsigned int) TK_SR )
// SHORTSWERR
//
//
//
// ---------------------------------- Register RTree: TK_SR -------------------------------------
// SVD Line: 6846
// SFDITEM_REG__TK_SR
// SR
//
// [Bits 31..0] RW (@ 0x40003830) Status register
// ( (unsigned int)((TK_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__TK_SR_SENSEDONE
// - SFDITEM_FIELD__TK_SR_CMPOUT
// - SFDITEM_FIELD__TK_SR_SHORTSWERR
//
//
// ------------------------------ Register Item Address: TK_IER ---------------------------------
// SVD Line: 6871
unsigned int TK_IER __AT (0x40003834);
// ------------------------------- Field Item: TK_IER_EVTINTEN ----------------------------------
// SVD Line: 6876
// - SFDITEM_FIELD__TK_IER_EVTINTEN
// EVTINTEN
//
// [Bit 0] RW (@ 0x40003834) Event interrupt enable
//
// ( (unsigned int) TK_IER )
// EVTINTEN
//
//
//
// ------------------------------- Field Item: TK_IER_ERRINTEN ----------------------------------
// SVD Line: 6881
// - SFDITEM_FIELD__TK_IER_ERRINTEN
// ERRINTEN
//
// [Bit 1] RW (@ 0x40003834) Error interrupt enable
//
// ( (unsigned int) TK_IER )
// ERRINTEN
//
//
//
// --------------------------------- Register RTree: TK_IER -------------------------------------
// SVD Line: 6871
// SFDITEM_REG__TK_IER
// IER
//
// [Bits 31..0] RW (@ 0x40003834) Interrupt enable register
// ( (unsigned int)((TK_IER >> 0) & 0xFFFFFFFF), ((TK_IER = (TK_IER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TK_IER_EVTINTEN
// - SFDITEM_FIELD__TK_IER_ERRINTEN
//
//
// ------------------------------ Register Item Address: TK_ICR ---------------------------------
// SVD Line: 6888
unsigned int TK_ICR __AT (0x40003838);
// ------------------------------ Field Item: TK_ICR_EVTINTCLR ----------------------------------
// SVD Line: 6893
// - SFDITEM_FIELD__TK_ICR_EVTINTCLR
// EVTINTCLR
//
// [Bit 0] RW (@ 0x40003838) Event interrupt clear
//
// ( (unsigned int) TK_ICR )
// EVTINTCLR
//
//
//
// ------------------------------ Field Item: TK_ICR_ERRINTCLR ----------------------------------
// SVD Line: 6898
// - SFDITEM_FIELD__TK_ICR_ERRINTCLR
// ERRINTCLR
//
// [Bit 1] RW (@ 0x40003838) Error interrupt clear
//
// ( (unsigned int) TK_ICR )
// ERRINTCLR
//
//
//
// --------------------------------- Register RTree: TK_ICR -------------------------------------
// SVD Line: 6888
// SFDITEM_REG__TK_ICR
// ICR
//
// [Bits 31..0] RW (@ 0x40003838) Interrupt clear register
// ( (unsigned int)((TK_ICR >> 0) & 0xFFFFFFFF), ((TK_ICR = (TK_ICR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TK_ICR_EVTINTCLR
// - SFDITEM_FIELD__TK_ICR_ERRINTCLR
//
//
// ------------------------------ Register Item Address: TK_CDR ---------------------------------
// SVD Line: 6905
unsigned int TK_CDR __AT (0x4000383C);
// -------------------------------- Field Item: TK_CDR_CDATA ------------------------------------
// SVD Line: 6910
// - SFDITEM_FIELD__TK_CDR_CDATA
// CDATA
//
// [Bits 15..0] RW (@ 0x4000383C) Compare data in lowpower
//
// ( (unsigned short)((TK_CDR >> 0) & 0xFFFF), ((TK_CDR = (TK_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_CDR -------------------------------------
// SVD Line: 6905
// SFDITEM_REG__TK_CDR
// CDR
//
// [Bits 31..0] RW (@ 0x4000383C) Compare Data register
// ( (unsigned int)((TK_CDR >> 0) & 0xFFFFFFFF), ((TK_CDR = (TK_CDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_CDR_CDATA
//
//
// ----------------------------- Register Item Address: TK_LPDR ---------------------------------
// SVD Line: 6917
unsigned int TK_LPDR __AT (0x40003840);
// ----------------------------- Field Item: TK_LPDR_NORMALDELTA --------------------------------
// SVD Line: 6922
// - SFDITEM_FIELD__TK_LPDR_NORMALDELTA
// NORMALDELTA
//
// [Bits 9..0] RW (@ 0x40003840) Delta1
//
// ( (unsigned short)((TK_LPDR >> 0) & 0x3FF), ((TK_LPDR = (TK_LPDR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: TK_LPDR_ABNORMALDELTA -------------------------------
// SVD Line: 6927
// - SFDITEM_FIELD__TK_LPDR_ABNORMALDELTA
// ABNORMALDELTA
//
// [Bits 25..16] RW (@ 0x40003840) Delta2
//
// ( (unsigned short)((TK_LPDR >> 16) & 0x3FF), ((TK_LPDR = (TK_LPDR & ~(0x3FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_LPDR ------------------------------------
// SVD Line: 6917
// SFDITEM_REG__TK_LPDR
// LPDR
//
// [Bits 31..0] RW (@ 0x40003840) Lowpower Delta register
// ( (unsigned int)((TK_LPDR >> 0) & 0xFFFFFFFF), ((TK_LPDR = (TK_LPDR & ~(0x3FF03FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF03FF) << 0 ) ) ))
// - SFDITEM_FIELD__TK_LPDR_NORMALDELTA
// - SFDITEM_FIELD__TK_LPDR_ABNORMALDELTA
//
//
// ----------------------------- Register Item Address: TK_LPTR ---------------------------------
// SVD Line: 6934
unsigned int TK_LPTR __AT (0x40003844);
// ------------------------------- Field Item: TK_LPTR_LPWAIT -----------------------------------
// SVD Line: 6939
// - SFDITEM_FIELD__TK_LPTR_LPWAIT
// LPWAIT
//
// [Bits 6..0] RW (@ 0x40003844) Wait time in lowpower
//
// ( (unsigned char)((TK_LPTR >> 0) & 0x7F), ((TK_LPTR = (TK_LPTR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_LPTR ------------------------------------
// SVD Line: 6934
// SFDITEM_REG__TK_LPTR
// LPTR
//
// [Bits 31..0] RW (@ 0x40003844) Lowpower Time register
// ( (unsigned int)((TK_LPTR >> 0) & 0xFFFFFFFF), ((TK_LPTR = (TK_LPTR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__TK_LPTR_LPWAIT
//
//
// ------------------------------ Register Item Address: TK_OPR ---------------------------------
// SVD Line: 6946
unsigned int TK_OPR __AT (0x40003848);
// ---------------------------------- Field Item: TK_OPR_OP -------------------------------------
// SVD Line: 6950
// - SFDITEM_FIELD__TK_OPR_OP
// OP
//
// [Bits 5..0] RW (@ 0x40003848) CMP control
//
// ( (unsigned char)((TK_OPR >> 0) & 0x3F), ((TK_OPR = (TK_OPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: TK_OPR -------------------------------------
// SVD Line: 6946
// SFDITEM_REG__TK_OPR
// OPR
//
// [Bits 31..0] RW (@ 0x40003848) OPR
// ( (unsigned int)((TK_OPR >> 0) & 0xFFFFFFFF), ((TK_OPR = (TK_OPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__TK_OPR_OP
//
//
// ------------------------------ Register Item Address: TK_TR ----------------------------------
// SVD Line: 6957
unsigned int TK_TR __AT (0x4000384C);
// --------------------------------- Field Item: TK_TR_TMODE ------------------------------------
// SVD Line: 6961
// - SFDITEM_FIELD__TK_TR_TMODE
// TMODE
//
// [Bits 2..0] RW (@ 0x4000384C) Test mode select
//
// ( (unsigned char)((TK_TR >> 0) & 0x7), ((TK_TR = (TK_TR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TK_TR_DBGSEL ------------------------------------
// SVD Line: 6966
// - SFDITEM_FIELD__TK_TR_DBGSEL
// DBGSEL
//
// [Bits 19..16] RW (@ 0x4000384C) Debug signal select
//
// ( (unsigned char)((TK_TR >> 16) & 0xF), ((TK_TR = (TK_TR & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ---------------------------------- Register RTree: TK_TR -------------------------------------
// SVD Line: 6957
// SFDITEM_REG__TK_TR
// TR
//
// [Bits 31..0] RW (@ 0x4000384C) TR
// ( (unsigned int)((TK_TR >> 0) & 0xFFFFFFFF), ((TK_TR = (TK_TR & ~(0xF0007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0007) << 0 ) ) ))
// - SFDITEM_FIELD__TK_TR_TMODE
// - SFDITEM_FIELD__TK_TR_DBGSEL
//
//
// ------------------------------ Register Item Address: TK_DDR ---------------------------------
// SVD Line: 6973
unsigned int TK_DDR __AT (0x40003850);
// ----------------------------- Field Item: TK_DDR_SHORTSW_DATA --------------------------------
// SVD Line: 6977
// - SFDITEM_FIELD__TK_DDR_SHORTSW_DATA
// SHORTSW_DATA
//
// [Bits 9..0] RO (@ 0x40003850) Short switch data in CSD mode
//
// ( (unsigned short)((TK_DDR >> 0) & 0x3FF) )
//
//
//
// --------------------------------- Register RTree: TK_DDR -------------------------------------
// SVD Line: 6973
// SFDITEM_REG__TK_DDR
// DDR
//
// [Bits 31..0] RW (@ 0x40003850) DDR
// ( (unsigned int)((TK_DDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__TK_DDR_SHORTSW_DATA
//
//
// ----------------------------------- Peripheral View: TK --------------------------------------
// SVD Line: 6486
// TK
// TK
// - SFDITEM_REG__TK_CR1
// - SFDITEM_REG__TK_CR2
// - SFDITEM_REG__TK_IDACR
// - SFDITEM_REG__TK_KR
// - SFDITEM_REG__TK_CSR
// - SFDITEM_REG__TK_UCR
// - SFDITEM_REG__TK_STR1
// - SFDITEM_REG__TK_STR2
// - SFDITEM_REG__TK_WR
// - SFDITEM_REG__TK_SDR
// - SFDITEM_REG__TK_PRSR
// - SFDITEM_REG__TK_DR
// - SFDITEM_REG__TK_SR
// - SFDITEM_REG__TK_IER
// - SFDITEM_REG__TK_ICR
// - SFDITEM_REG__TK_CDR
// - SFDITEM_REG__TK_LPDR
// - SFDITEM_REG__TK_LPTR
// - SFDITEM_REG__TK_OPR
// - SFDITEM_REG__TK_TR
// - SFDITEM_REG__TK_DDR
//
//
// ----------------------------- Register Item Address: UART1_DR --------------------------------
// SVD Line: 7003
unsigned int UART1_DR __AT (0x40004400);
// --------------------------------- Field Item: UART1_DR_DR ------------------------------------
// SVD Line: 7008
// - SFDITEM_FIELD__UART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004400) Receive/send data register
//
// ( (unsigned short)((UART1_DR >> 0) & 0x1FF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_DR ------------------------------------
// SVD Line: 7003
// SFDITEM_REG__UART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004400) Data register
// ( (unsigned int)((UART1_DR >> 0) & 0xFFFFFFFF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_DR_DR
//
//
// ---------------------------- Register Item Address: UART1_BRR --------------------------------
// SVD Line: 7015
unsigned int UART1_BRR __AT (0x40004404);
// -------------------------------- Field Item: UART1_BRR_BRR -----------------------------------
// SVD Line: 7020
// - SFDITEM_FIELD__UART1_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40004404) Baud rate register
//
// ( (unsigned short)((UART1_BRR >> 0) & 0xFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_BRR -----------------------------------
// SVD Line: 7015
// SFDITEM_REG__UART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004404) Baud rate register
// ( (unsigned int)((UART1_BRR >> 0) & 0xFFFFFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART1_SR --------------------------------
// SVD Line: 7027
unsigned int UART1_SR __AT (0x40004410);
// -------------------------------- Field Item: UART1_SR_RXNE -----------------------------------
// SVD Line: 7032
// - SFDITEM_FIELD__UART1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40004410) Receive register not empty
//
// ( (unsigned int) UART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART1_SR_ORE ------------------------------------
// SVD Line: 7038
// - SFDITEM_FIELD__UART1_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40004410) Overrun error bit
//
// ( (unsigned int) UART1_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART1_SR_PE ------------------------------------
// SVD Line: 7043
// - SFDITEM_FIELD__UART1_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40004410) Parity Error bit
//
// ( (unsigned int) UART1_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART1_SR_FE ------------------------------------
// SVD Line: 7048
// - SFDITEM_FIELD__UART1_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40004410) Framing Error bit
//
// ( (unsigned int) UART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART1_SR_BRI ------------------------------------
// SVD Line: 7053
// - SFDITEM_FIELD__UART1_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40004410) Break Interrupt bit
//
// ( (unsigned int) UART1_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART1_SR_TDRE -----------------------------------
// SVD Line: 7058
// - SFDITEM_FIELD__UART1_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40004410) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART1_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART1_SR_TXE ------------------------------------
// SVD Line: 7064
// - SFDITEM_FIELD__UART1_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40004410) Transmitter Empty bit
//
// ( (unsigned int) UART1_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART1_SR_ADDR_RCVD ---------------------------------
// SVD Line: 7070
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40004410) Address Received Bit
//
// ( (unsigned int) UART1_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART1_SR_BUSY -----------------------------------
// SVD Line: 7075
// - SFDITEM_FIELD__UART1_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40004410) UART Busy
//
// ( (unsigned int) UART1_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART1_SR_BUSY_ERR ---------------------------------
// SVD Line: 7081
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40004410) Busy Detect Error
//
// ( (unsigned int) UART1_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART1_SR ------------------------------------
// SVD Line: 7027
// SFDITEM_REG__UART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004410) Status register
// ( (unsigned int)((UART1_SR >> 0) & 0xFFFFFFFF), ((UART1_SR = (UART1_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_SR_RXNE
// - SFDITEM_FIELD__UART1_SR_ORE
// - SFDITEM_FIELD__UART1_SR_PE
// - SFDITEM_FIELD__UART1_SR_FE
// - SFDITEM_FIELD__UART1_SR_BRI
// - SFDITEM_FIELD__UART1_SR_TDRE
// - SFDITEM_FIELD__UART1_SR_TXE
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART1_SR_BUSY
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART1_CR1 --------------------------------
// SVD Line: 7088
unsigned int UART1_CR1 __AT (0x40004414);
// --------------------------------- Field Item: UART1_CR1_M ------------------------------------
// SVD Line: 7093
// - SFDITEM_FIELD__UART1_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40004414) Data Length Select
//
// ( (unsigned char)((UART1_CR1 >> 0) & 0x3), ((UART1_CR1 = (UART1_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART1_CR1_STOP -----------------------------------
// SVD Line: 7098
// - SFDITEM_FIELD__UART1_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40004414) Number of stop bits
//
// ( (unsigned int) UART1_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART1_CR1_PCE -----------------------------------
// SVD Line: 7103
// - SFDITEM_FIELD__UART1_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40004414) Parity Enable
//
// ( (unsigned int) UART1_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART1_CR1_PS ------------------------------------
// SVD Line: 7108
// - SFDITEM_FIELD__UART1_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40004414) Even Parity Select
//
// ( (unsigned int) UART1_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART1_CR1_SP ------------------------------------
// SVD Line: 7113
// - SFDITEM_FIELD__UART1_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40004414) Stick Parity
//
// ( (unsigned int) UART1_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART1_CR1_SBK -----------------------------------
// SVD Line: 7118
// - SFDITEM_FIELD__UART1_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40004414) Send Break
//
// ( (unsigned int) UART1_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART1_CR1_SWAP -----------------------------------
// SVD Line: 7123
// - SFDITEM_FIELD__UART1_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40004414) TX/RX pin swap
//
// ( (unsigned int) UART1_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART1_CR1_MSBFIRST ---------------------------------
// SVD Line: 7128
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40004414) MSB first mode
//
// ( (unsigned int) UART1_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART1_CR1 -----------------------------------
// SVD Line: 7088
// SFDITEM_REG__UART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40004414) Control register 1
// ( (unsigned int)((UART1_CR1 >> 0) & 0xFFFFFFFF), ((UART1_CR1 = (UART1_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR1_M
// - SFDITEM_FIELD__UART1_CR1_STOP
// - SFDITEM_FIELD__UART1_CR1_PCE
// - SFDITEM_FIELD__UART1_CR1_PS
// - SFDITEM_FIELD__UART1_CR1_SP
// - SFDITEM_FIELD__UART1_CR1_SBK
// - SFDITEM_FIELD__UART1_CR1_SWAP
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART1_CR2 --------------------------------
// SVD Line: 7135
unsigned int UART1_CR2 __AT (0x40004418);
// ------------------------------ Field Item: UART1_CR2_RXNEIE ----------------------------------
// SVD Line: 7140
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40004418) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART1_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART1_CR2_TDREIE ----------------------------------
// SVD Line: 7145
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40004418) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART1_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART1_CR2_LSIE -----------------------------------
// SVD Line: 7150
// - SFDITEM_FIELD__UART1_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40004418) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART1_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART1_CR2_BUSYERRIE --------------------------------
// SVD Line: 7155
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40004418) Enable Busyerr state interruption
//
// ( (unsigned int) UART1_CR2 )
// BUSYERRIE
//
//
//
// -------------------------------- Register RTree: UART1_CR2 -----------------------------------
// SVD Line: 7135
// SFDITEM_REG__UART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004418) Control register 2
// ( (unsigned int)((UART1_CR2 >> 0) & 0xFFFFFFFF), ((UART1_CR2 = (UART1_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// - SFDITEM_FIELD__UART1_CR2_LSIE
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
//
//
// ---------------------------- Register Item Address: UART1_CR3 --------------------------------
// SVD Line: 7162
unsigned int UART1_CR3 __AT (0x4000441C);
// -------------------------------- Field Item: UART1_CR3_M_E -----------------------------------
// SVD Line: 7167
// - SFDITEM_FIELD__UART1_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x4000441C) Extension for DLS
//
// ( (unsigned int) UART1_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART1_CR3_ADDR_MATCH --------------------------------
// SVD Line: 7172
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x4000441C) Address Match Mode
//
// ( (unsigned int) UART1_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART1_CR3_SEND_ADDR --------------------------------
// SVD Line: 7177
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x4000441C) Send address control bit
//
// ( (unsigned int) UART1_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART1_CR3_TX_MODE ---------------------------------
// SVD Line: 7182
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x4000441C) Transmit mode control bit
//
// ( (unsigned int) UART1_CR3 )
// TX_MODE
//
//
//
// -------------------------------- Register RTree: UART1_CR3 -----------------------------------
// SVD Line: 7162
// SFDITEM_REG__UART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x4000441C) Control register 3
// ( (unsigned int)((UART1_CR3 >> 0) & 0xFFFFFFFF), ((UART1_CR3 = (UART1_CR3 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR3_M_E
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
//
//
// ---------------------------- Register Item Address: UART1_RAR --------------------------------
// SVD Line: 7189
unsigned int UART1_RAR __AT (0x40004420);
// -------------------------------- Field Item: UART1_RAR_RAR -----------------------------------
// SVD Line: 7193
// - SFDITEM_FIELD__UART1_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40004420) Receive address matching register
//
// ( (unsigned char)((UART1_RAR >> 0) & 0xFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_RAR -----------------------------------
// SVD Line: 7189
// SFDITEM_REG__UART1_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40004420) RAR
// ( (unsigned int)((UART1_RAR >> 0) & 0xFFFFFFFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART1_TAR --------------------------------
// SVD Line: 7200
unsigned int UART1_TAR __AT (0x40004424);
// -------------------------------- Field Item: UART1_TAR_TAR -----------------------------------
// SVD Line: 7204
// - SFDITEM_FIELD__UART1_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40004424) Transmit address matching register
//
// ( (unsigned char)((UART1_TAR >> 0) & 0xFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_TAR -----------------------------------
// SVD Line: 7200
// SFDITEM_REG__UART1_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40004424) TAR
// ( (unsigned int)((UART1_TAR >> 0) & 0xFFFFFFFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_TAR_TAR
//
//
// --------------------------------- Peripheral View: UART1 -------------------------------------
// SVD Line: 6987
// UART1
// UART1
// - SFDITEM_REG__UART1_DR
// - SFDITEM_REG__UART1_BRR
// - SFDITEM_REG__UART1_SR
// - SFDITEM_REG__UART1_CR1
// - SFDITEM_REG__UART1_CR2
// - SFDITEM_REG__UART1_CR3
// - SFDITEM_REG__UART1_RAR
// - SFDITEM_REG__UART1_TAR
//
//
// ----------------------------- Register Item Address: UART2_DR --------------------------------
// SVD Line: 7003
unsigned int UART2_DR __AT (0x40014400);
// --------------------------------- Field Item: UART2_DR_DR ------------------------------------
// SVD Line: 7008
// - SFDITEM_FIELD__UART2_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40014400) Receive/send data register
//
// ( (unsigned short)((UART2_DR >> 0) & 0x1FF), ((UART2_DR = (UART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_DR ------------------------------------
// SVD Line: 7003
// SFDITEM_REG__UART2_DR
// DR
//
// [Bits 31..0] RW (@ 0x40014400) Data register
// ( (unsigned int)((UART2_DR >> 0) & 0xFFFFFFFF), ((UART2_DR = (UART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_DR_DR
//
//
// ---------------------------- Register Item Address: UART2_BRR --------------------------------
// SVD Line: 7015
unsigned int UART2_BRR __AT (0x40014404);
// -------------------------------- Field Item: UART2_BRR_BRR -----------------------------------
// SVD Line: 7020
// - SFDITEM_FIELD__UART2_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40014404) Baud rate register
//
// ( (unsigned short)((UART2_BRR >> 0) & 0xFFFF), ((UART2_BRR = (UART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_BRR -----------------------------------
// SVD Line: 7015
// SFDITEM_REG__UART2_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40014404) Baud rate register
// ( (unsigned int)((UART2_BRR >> 0) & 0xFFFFFFFF), ((UART2_BRR = (UART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART2_SR --------------------------------
// SVD Line: 7027
unsigned int UART2_SR __AT (0x40014410);
// -------------------------------- Field Item: UART2_SR_RXNE -----------------------------------
// SVD Line: 7032
// - SFDITEM_FIELD__UART2_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40014410) Receive register not empty
//
// ( (unsigned int) UART2_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART2_SR_ORE ------------------------------------
// SVD Line: 7038
// - SFDITEM_FIELD__UART2_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40014410) Overrun error bit
//
// ( (unsigned int) UART2_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART2_SR_PE ------------------------------------
// SVD Line: 7043
// - SFDITEM_FIELD__UART2_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40014410) Parity Error bit
//
// ( (unsigned int) UART2_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART2_SR_FE ------------------------------------
// SVD Line: 7048
// - SFDITEM_FIELD__UART2_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40014410) Framing Error bit
//
// ( (unsigned int) UART2_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART2_SR_BRI ------------------------------------
// SVD Line: 7053
// - SFDITEM_FIELD__UART2_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40014410) Break Interrupt bit
//
// ( (unsigned int) UART2_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART2_SR_TDRE -----------------------------------
// SVD Line: 7058
// - SFDITEM_FIELD__UART2_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40014410) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART2_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART2_SR_TXE ------------------------------------
// SVD Line: 7064
// - SFDITEM_FIELD__UART2_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40014410) Transmitter Empty bit
//
// ( (unsigned int) UART2_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART2_SR_ADDR_RCVD ---------------------------------
// SVD Line: 7070
// - SFDITEM_FIELD__UART2_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40014410) Address Received Bit
//
// ( (unsigned int) UART2_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART2_SR_BUSY -----------------------------------
// SVD Line: 7075
// - SFDITEM_FIELD__UART2_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40014410) UART Busy
//
// ( (unsigned int) UART2_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART2_SR_BUSY_ERR ---------------------------------
// SVD Line: 7081
// - SFDITEM_FIELD__UART2_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40014410) Busy Detect Error
//
// ( (unsigned int) UART2_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART2_SR ------------------------------------
// SVD Line: 7027
// SFDITEM_REG__UART2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40014410) Status register
// ( (unsigned int)((UART2_SR >> 0) & 0xFFFFFFFF), ((UART2_SR = (UART2_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_SR_RXNE
// - SFDITEM_FIELD__UART2_SR_ORE
// - SFDITEM_FIELD__UART2_SR_PE
// - SFDITEM_FIELD__UART2_SR_FE
// - SFDITEM_FIELD__UART2_SR_BRI
// - SFDITEM_FIELD__UART2_SR_TDRE
// - SFDITEM_FIELD__UART2_SR_TXE
// - SFDITEM_FIELD__UART2_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART2_SR_BUSY
// - SFDITEM_FIELD__UART2_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART2_CR1 --------------------------------
// SVD Line: 7088
unsigned int UART2_CR1 __AT (0x40014414);
// --------------------------------- Field Item: UART2_CR1_M ------------------------------------
// SVD Line: 7093
// - SFDITEM_FIELD__UART2_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40014414) Data Length Select
//
// ( (unsigned char)((UART2_CR1 >> 0) & 0x3), ((UART2_CR1 = (UART2_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART2_CR1_STOP -----------------------------------
// SVD Line: 7098
// - SFDITEM_FIELD__UART2_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40014414) Number of stop bits
//
// ( (unsigned int) UART2_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART2_CR1_PCE -----------------------------------
// SVD Line: 7103
// - SFDITEM_FIELD__UART2_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40014414) Parity Enable
//
// ( (unsigned int) UART2_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART2_CR1_PS ------------------------------------
// SVD Line: 7108
// - SFDITEM_FIELD__UART2_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40014414) Even Parity Select
//
// ( (unsigned int) UART2_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART2_CR1_SP ------------------------------------
// SVD Line: 7113
// - SFDITEM_FIELD__UART2_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40014414) Stick Parity
//
// ( (unsigned int) UART2_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART2_CR1_SBK -----------------------------------
// SVD Line: 7118
// - SFDITEM_FIELD__UART2_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40014414) Send Break
//
// ( (unsigned int) UART2_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART2_CR1_SWAP -----------------------------------
// SVD Line: 7123
// - SFDITEM_FIELD__UART2_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40014414) TX/RX pin swap
//
// ( (unsigned int) UART2_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART2_CR1_MSBFIRST ---------------------------------
// SVD Line: 7128
// - SFDITEM_FIELD__UART2_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40014414) MSB first mode
//
// ( (unsigned int) UART2_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART2_CR1 -----------------------------------
// SVD Line: 7088
// SFDITEM_REG__UART2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40014414) Control register 1
// ( (unsigned int)((UART2_CR1 >> 0) & 0xFFFFFFFF), ((UART2_CR1 = (UART2_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR1_M
// - SFDITEM_FIELD__UART2_CR1_STOP
// - SFDITEM_FIELD__UART2_CR1_PCE
// - SFDITEM_FIELD__UART2_CR1_PS
// - SFDITEM_FIELD__UART2_CR1_SP
// - SFDITEM_FIELD__UART2_CR1_SBK
// - SFDITEM_FIELD__UART2_CR1_SWAP
// - SFDITEM_FIELD__UART2_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART2_CR2 --------------------------------
// SVD Line: 7135
unsigned int UART2_CR2 __AT (0x40014418);
// ------------------------------ Field Item: UART2_CR2_RXNEIE ----------------------------------
// SVD Line: 7140
// - SFDITEM_FIELD__UART2_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40014418) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART2_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART2_CR2_TDREIE ----------------------------------
// SVD Line: 7145
// - SFDITEM_FIELD__UART2_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40014418) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART2_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART2_CR2_LSIE -----------------------------------
// SVD Line: 7150
// - SFDITEM_FIELD__UART2_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40014418) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART2_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART2_CR2_BUSYERRIE --------------------------------
// SVD Line: 7155
// - SFDITEM_FIELD__UART2_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40014418) Enable Busyerr state interruption
//
// ( (unsigned int) UART2_CR2 )
// BUSYERRIE
//
//
//
// -------------------------------- Register RTree: UART2_CR2 -----------------------------------
// SVD Line: 7135
// SFDITEM_REG__UART2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40014418) Control register 2
// ( (unsigned int)((UART2_CR2 >> 0) & 0xFFFFFFFF), ((UART2_CR2 = (UART2_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR2_RXNEIE
// - SFDITEM_FIELD__UART2_CR2_TDREIE
// - SFDITEM_FIELD__UART2_CR2_LSIE
// - SFDITEM_FIELD__UART2_CR2_BUSYERRIE
//
//
// ---------------------------- Register Item Address: UART2_CR3 --------------------------------
// SVD Line: 7162
unsigned int UART2_CR3 __AT (0x4001441C);
// -------------------------------- Field Item: UART2_CR3_M_E -----------------------------------
// SVD Line: 7167
// - SFDITEM_FIELD__UART2_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x4001441C) Extension for DLS
//
// ( (unsigned int) UART2_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART2_CR3_ADDR_MATCH --------------------------------
// SVD Line: 7172
// - SFDITEM_FIELD__UART2_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x4001441C) Address Match Mode
//
// ( (unsigned int) UART2_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART2_CR3_SEND_ADDR --------------------------------
// SVD Line: 7177
// - SFDITEM_FIELD__UART2_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x4001441C) Send address control bit
//
// ( (unsigned int) UART2_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART2_CR3_TX_MODE ---------------------------------
// SVD Line: 7182
// - SFDITEM_FIELD__UART2_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x4001441C) Transmit mode control bit
//
// ( (unsigned int) UART2_CR3 )
// TX_MODE
//
//
//
// -------------------------------- Register RTree: UART2_CR3 -----------------------------------
// SVD Line: 7162
// SFDITEM_REG__UART2_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x4001441C) Control register 3
// ( (unsigned int)((UART2_CR3 >> 0) & 0xFFFFFFFF), ((UART2_CR3 = (UART2_CR3 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR3_M_E
// - SFDITEM_FIELD__UART2_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART2_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART2_CR3_TX_MODE
//
//
// ---------------------------- Register Item Address: UART2_RAR --------------------------------
// SVD Line: 7189
unsigned int UART2_RAR __AT (0x40014420);
// -------------------------------- Field Item: UART2_RAR_RAR -----------------------------------
// SVD Line: 7193
// - SFDITEM_FIELD__UART2_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40014420) Receive address matching register
//
// ( (unsigned char)((UART2_RAR >> 0) & 0xFF), ((UART2_RAR = (UART2_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_RAR -----------------------------------
// SVD Line: 7189
// SFDITEM_REG__UART2_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40014420) RAR
// ( (unsigned int)((UART2_RAR >> 0) & 0xFFFFFFFF), ((UART2_RAR = (UART2_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART2_TAR --------------------------------
// SVD Line: 7200
unsigned int UART2_TAR __AT (0x40014424);
// -------------------------------- Field Item: UART2_TAR_TAR -----------------------------------
// SVD Line: 7204
// - SFDITEM_FIELD__UART2_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40014424) Transmit address matching register
//
// ( (unsigned char)((UART2_TAR >> 0) & 0xFF), ((UART2_TAR = (UART2_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_TAR -----------------------------------
// SVD Line: 7200
// SFDITEM_REG__UART2_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40014424) TAR
// ( (unsigned int)((UART2_TAR >> 0) & 0xFFFFFFFF), ((UART2_TAR = (UART2_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_TAR_TAR
//
//
// --------------------------------- Peripheral View: UART2 -------------------------------------
// SVD Line: 7213
// UART2
// UART2
// - SFDITEM_REG__UART2_DR
// - SFDITEM_REG__UART2_BRR
// - SFDITEM_REG__UART2_SR
// - SFDITEM_REG__UART2_CR1
// - SFDITEM_REG__UART2_CR2
// - SFDITEM_REG__UART2_CR3
// - SFDITEM_REG__UART2_RAR
// - SFDITEM_REG__UART2_TAR
//
//
// ----------------------------- Register Item Address: UART3_DR --------------------------------
// SVD Line: 7003
unsigned int UART3_DR __AT (0x40013800);
// --------------------------------- Field Item: UART3_DR_DR ------------------------------------
// SVD Line: 7008
// - SFDITEM_FIELD__UART3_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40013800) Receive/send data register
//
// ( (unsigned short)((UART3_DR >> 0) & 0x1FF), ((UART3_DR = (UART3_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART3_DR ------------------------------------
// SVD Line: 7003
// SFDITEM_REG__UART3_DR
// DR
//
// [Bits 31..0] RW (@ 0x40013800) Data register
// ( (unsigned int)((UART3_DR >> 0) & 0xFFFFFFFF), ((UART3_DR = (UART3_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_DR_DR
//
//
// ---------------------------- Register Item Address: UART3_BRR --------------------------------
// SVD Line: 7015
unsigned int UART3_BRR __AT (0x40013804);
// -------------------------------- Field Item: UART3_BRR_BRR -----------------------------------
// SVD Line: 7020
// - SFDITEM_FIELD__UART3_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40013804) Baud rate register
//
// ( (unsigned short)((UART3_BRR >> 0) & 0xFFFF), ((UART3_BRR = (UART3_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART3_BRR -----------------------------------
// SVD Line: 7015
// SFDITEM_REG__UART3_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40013804) Baud rate register
// ( (unsigned int)((UART3_BRR >> 0) & 0xFFFFFFFF), ((UART3_BRR = (UART3_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART3_SR --------------------------------
// SVD Line: 7027
unsigned int UART3_SR __AT (0x40013810);
// -------------------------------- Field Item: UART3_SR_RXNE -----------------------------------
// SVD Line: 7032
// - SFDITEM_FIELD__UART3_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40013810) Receive register not empty
//
// ( (unsigned int) UART3_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART3_SR_ORE ------------------------------------
// SVD Line: 7038
// - SFDITEM_FIELD__UART3_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40013810) Overrun error bit
//
// ( (unsigned int) UART3_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART3_SR_PE ------------------------------------
// SVD Line: 7043
// - SFDITEM_FIELD__UART3_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40013810) Parity Error bit
//
// ( (unsigned int) UART3_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART3_SR_FE ------------------------------------
// SVD Line: 7048
// - SFDITEM_FIELD__UART3_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40013810) Framing Error bit
//
// ( (unsigned int) UART3_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART3_SR_BRI ------------------------------------
// SVD Line: 7053
// - SFDITEM_FIELD__UART3_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40013810) Break Interrupt bit
//
// ( (unsigned int) UART3_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART3_SR_TDRE -----------------------------------
// SVD Line: 7058
// - SFDITEM_FIELD__UART3_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40013810) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART3_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART3_SR_TXE ------------------------------------
// SVD Line: 7064
// - SFDITEM_FIELD__UART3_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40013810) Transmitter Empty bit
//
// ( (unsigned int) UART3_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART3_SR_ADDR_RCVD ---------------------------------
// SVD Line: 7070
// - SFDITEM_FIELD__UART3_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40013810) Address Received Bit
//
// ( (unsigned int) UART3_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART3_SR_BUSY -----------------------------------
// SVD Line: 7075
// - SFDITEM_FIELD__UART3_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40013810) UART Busy
//
// ( (unsigned int) UART3_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART3_SR_BUSY_ERR ---------------------------------
// SVD Line: 7081
// - SFDITEM_FIELD__UART3_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40013810) Busy Detect Error
//
// ( (unsigned int) UART3_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART3_SR ------------------------------------
// SVD Line: 7027
// SFDITEM_REG__UART3_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013810) Status register
// ( (unsigned int)((UART3_SR >> 0) & 0xFFFFFFFF), ((UART3_SR = (UART3_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_SR_RXNE
// - SFDITEM_FIELD__UART3_SR_ORE
// - SFDITEM_FIELD__UART3_SR_PE
// - SFDITEM_FIELD__UART3_SR_FE
// - SFDITEM_FIELD__UART3_SR_BRI
// - SFDITEM_FIELD__UART3_SR_TDRE
// - SFDITEM_FIELD__UART3_SR_TXE
// - SFDITEM_FIELD__UART3_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART3_SR_BUSY
// - SFDITEM_FIELD__UART3_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART3_CR1 --------------------------------
// SVD Line: 7088
unsigned int UART3_CR1 __AT (0x40013814);
// --------------------------------- Field Item: UART3_CR1_M ------------------------------------
// SVD Line: 7093
// - SFDITEM_FIELD__UART3_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40013814) Data Length Select
//
// ( (unsigned char)((UART3_CR1 >> 0) & 0x3), ((UART3_CR1 = (UART3_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART3_CR1_STOP -----------------------------------
// SVD Line: 7098
// - SFDITEM_FIELD__UART3_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40013814) Number of stop bits
//
// ( (unsigned int) UART3_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART3_CR1_PCE -----------------------------------
// SVD Line: 7103
// - SFDITEM_FIELD__UART3_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40013814) Parity Enable
//
// ( (unsigned int) UART3_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART3_CR1_PS ------------------------------------
// SVD Line: 7108
// - SFDITEM_FIELD__UART3_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40013814) Even Parity Select
//
// ( (unsigned int) UART3_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART3_CR1_SP ------------------------------------
// SVD Line: 7113
// - SFDITEM_FIELD__UART3_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40013814) Stick Parity
//
// ( (unsigned int) UART3_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART3_CR1_SBK -----------------------------------
// SVD Line: 7118
// - SFDITEM_FIELD__UART3_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40013814) Send Break
//
// ( (unsigned int) UART3_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART3_CR1_SWAP -----------------------------------
// SVD Line: 7123
// - SFDITEM_FIELD__UART3_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40013814) TX/RX pin swap
//
// ( (unsigned int) UART3_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART3_CR1_MSBFIRST ---------------------------------
// SVD Line: 7128
// - SFDITEM_FIELD__UART3_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40013814) MSB first mode
//
// ( (unsigned int) UART3_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART3_CR1 -----------------------------------
// SVD Line: 7088
// SFDITEM_REG__UART3_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40013814) Control register 1
// ( (unsigned int)((UART3_CR1 >> 0) & 0xFFFFFFFF), ((UART3_CR1 = (UART3_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_CR1_M
// - SFDITEM_FIELD__UART3_CR1_STOP
// - SFDITEM_FIELD__UART3_CR1_PCE
// - SFDITEM_FIELD__UART3_CR1_PS
// - SFDITEM_FIELD__UART3_CR1_SP
// - SFDITEM_FIELD__UART3_CR1_SBK
// - SFDITEM_FIELD__UART3_CR1_SWAP
// - SFDITEM_FIELD__UART3_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART3_CR2 --------------------------------
// SVD Line: 7135
unsigned int UART3_CR2 __AT (0x40013818);
// ------------------------------ Field Item: UART3_CR2_RXNEIE ----------------------------------
// SVD Line: 7140
// - SFDITEM_FIELD__UART3_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40013818) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART3_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART3_CR2_TDREIE ----------------------------------
// SVD Line: 7145
// - SFDITEM_FIELD__UART3_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40013818) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART3_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART3_CR2_LSIE -----------------------------------
// SVD Line: 7150
// - SFDITEM_FIELD__UART3_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40013818) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART3_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART3_CR2_BUSYERRIE --------------------------------
// SVD Line: 7155
// - SFDITEM_FIELD__UART3_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40013818) Enable Busyerr state interruption
//
// ( (unsigned int) UART3_CR2 )
// BUSYERRIE
//
//
//
// -------------------------------- Register RTree: UART3_CR2 -----------------------------------
// SVD Line: 7135
// SFDITEM_REG__UART3_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013818) Control register 2
// ( (unsigned int)((UART3_CR2 >> 0) & 0xFFFFFFFF), ((UART3_CR2 = (UART3_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_CR2_RXNEIE
// - SFDITEM_FIELD__UART3_CR2_TDREIE
// - SFDITEM_FIELD__UART3_CR2_LSIE
// - SFDITEM_FIELD__UART3_CR2_BUSYERRIE
//
//
// ---------------------------- Register Item Address: UART3_CR3 --------------------------------
// SVD Line: 7162
unsigned int UART3_CR3 __AT (0x4001381C);
// -------------------------------- Field Item: UART3_CR3_M_E -----------------------------------
// SVD Line: 7167
// - SFDITEM_FIELD__UART3_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x4001381C) Extension for DLS
//
// ( (unsigned int) UART3_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART3_CR3_ADDR_MATCH --------------------------------
// SVD Line: 7172
// - SFDITEM_FIELD__UART3_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x4001381C) Address Match Mode
//
// ( (unsigned int) UART3_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART3_CR3_SEND_ADDR --------------------------------
// SVD Line: 7177
// - SFDITEM_FIELD__UART3_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x4001381C) Send address control bit
//
// ( (unsigned int) UART3_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART3_CR3_TX_MODE ---------------------------------
// SVD Line: 7182
// - SFDITEM_FIELD__UART3_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x4001381C) Transmit mode control bit
//
// ( (unsigned int) UART3_CR3 )
// TX_MODE
//
//
//
// -------------------------------- Register RTree: UART3_CR3 -----------------------------------
// SVD Line: 7162
// SFDITEM_REG__UART3_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x4001381C) Control register 3
// ( (unsigned int)((UART3_CR3 >> 0) & 0xFFFFFFFF), ((UART3_CR3 = (UART3_CR3 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_CR3_M_E
// - SFDITEM_FIELD__UART3_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART3_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART3_CR3_TX_MODE
//
//
// ---------------------------- Register Item Address: UART3_RAR --------------------------------
// SVD Line: 7189
unsigned int UART3_RAR __AT (0x40013820);
// -------------------------------- Field Item: UART3_RAR_RAR -----------------------------------
// SVD Line: 7193
// - SFDITEM_FIELD__UART3_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40013820) Receive address matching register
//
// ( (unsigned char)((UART3_RAR >> 0) & 0xFF), ((UART3_RAR = (UART3_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART3_RAR -----------------------------------
// SVD Line: 7189
// SFDITEM_REG__UART3_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40013820) RAR
// ( (unsigned int)((UART3_RAR >> 0) & 0xFFFFFFFF), ((UART3_RAR = (UART3_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART3_TAR --------------------------------
// SVD Line: 7200
unsigned int UART3_TAR __AT (0x40013824);
// -------------------------------- Field Item: UART3_TAR_TAR -----------------------------------
// SVD Line: 7204
// - SFDITEM_FIELD__UART3_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40013824) Transmit address matching register
//
// ( (unsigned char)((UART3_TAR >> 0) & 0xFF), ((UART3_TAR = (UART3_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART3_TAR -----------------------------------
// SVD Line: 7200
// SFDITEM_REG__UART3_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40013824) TAR
// ( (unsigned int)((UART3_TAR >> 0) & 0xFFFFFFFF), ((UART3_TAR = (UART3_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART3_TAR_TAR
//
//
// --------------------------------- Peripheral View: UART3 -------------------------------------
// SVD Line: 7222
// UART3
// UART3
// - SFDITEM_REG__UART3_DR
// - SFDITEM_REG__UART3_BRR
// - SFDITEM_REG__UART3_SR
// - SFDITEM_REG__UART3_CR1
// - SFDITEM_REG__UART3_CR2
// - SFDITEM_REG__UART3_CR3
// - SFDITEM_REG__UART3_RAR
// - SFDITEM_REG__UART3_TAR
//
//
// ---------------------------- IRQ Num definition: PY32F020Bxx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// ------------------------- PY32F020Bxx Specific Interrupt Numbers -----------------------------
// RTC_IRQ
// RTC
// RTC Interrupt through EXTI Lines 19
// 18
//
//
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 19
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 20
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 21
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 22
//
//
// EXTI4_15_IRQ
// EXTI4_15
// EXTI Line 4 to 15 Interrupt
// 23
//
//
// TK_IRQ
// TK
// TK Interrupt
// 24
//
//
// ADC_COMP_IRQ
// ADC_COMP
// ADC and COMP Interrupts
// 28
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 29
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 30
//
//
// LPTIM1_DAC_IRQ
// LPTIM1_DAC
// LPTIM1, DAC global Interrupts
// 33
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupt
// 35
//
//
// I2C1_IRQ
// I2C1
// I2C1 global Interrupt
// 39
//
//
// SPI1_IRQ
// SPI1
// SPI1 global Interrupt
// 41
//
//
// UART3_IRQ
// UART3
// UART3 global Interrupt
// 45
//
//
// UART2_IRQ
// UART2
// UART2 global Interrupt
// 46
//
//
// UART1_IRQ
// UART1
// UART1 global Interrupt
// 47
//
//
// PY32F020Bxx_IRQTable
// PY32F020Bxx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// RTC_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_15_IRQ
// TK_IRQ
// ADC_COMP_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// LPTIM1_DAC_IRQ
// TIM14_IRQ
// I2C1_IRQ
// SPI1_IRQ
// UART3_IRQ
// UART2_IRQ
// UART1_IRQ
//
// ----------------------------------- Menu: PY32F020Bxx ---------------------------------------
// SVD Line: 2
// ----------------------------- Peripheral Menu: 'PY32F020Bxx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// ADC
// ADC
//
//
// COMP
// COMP1
// COMP2
//
//
// CRC
// CRC
//
//
// DBGMCU
// DBGMCU
//
//
// EXTI
// EXTI
//
//
// FLASH
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOF
//
//
// I
// I2C
//
//
// IWDG
// IWDG
//
//
// LPTIM1
// LPTIM1
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// RTC
// RTC
//
//
// SPI
// SPI1
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM14
//
//
// TK
// TK
//
//
// UART
// UART1
// UART2
// UART3
//
//