/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F002Zxx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:14:57 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F002Zxx.svd',
* last modified on Sat Oct 11 17:45:44 2025
*/
// ----------------------------- Register Item Address: ADC_ISR ---------------------------------
// SVD Line: 41
unsigned int ADC_ISR __AT (0x40012400);
// -------------------------------- Field Item: ADC_ISR_EOSMP -----------------------------------
// SVD Line: 47
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// EOSMP
//
// [Bit 1] RW (@ 0x40012400) ADC group regular end of sampling flag
//
// ( (unsigned int) ADC_ISR )
// EOSMP
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOC ------------------------------------
// SVD Line: 52
// - SFDITEM_FIELD__ADC_ISR_EOC
// EOC
//
// [Bit 2] RW (@ 0x40012400) ADC group regular end of unitary conversion flag
//
// ( (unsigned int) ADC_ISR )
// EOC
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOSEQ -----------------------------------
// SVD Line: 57
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// EOSEQ
//
// [Bit 3] RW (@ 0x40012400) ADC group regular end of sequence conversions flag
//
// ( (unsigned int) ADC_ISR )
// EOSEQ
//
//
//
// --------------------------------- Field Item: ADC_ISR_OVR ------------------------------------
// SVD Line: 62
// - SFDITEM_FIELD__ADC_ISR_OVR
// OVR
//
// [Bit 4] RW (@ 0x40012400) ADC group regular overrun flag
//
// ( (unsigned int) ADC_ISR )
// OVR
//
//
//
// --------------------------------- Field Item: ADC_ISR_AWD ------------------------------------
// SVD Line: 67
// - SFDITEM_FIELD__ADC_ISR_AWD
// AWD
//
// [Bit 7] RW (@ 0x40012400) ADC analog watchdog flag
//
// ( (unsigned int) ADC_ISR )
// AWD
//
//
//
// --------------------------------- Register RTree: ADC_ISR ------------------------------------
// SVD Line: 41
// SFDITEM_REG__ADC_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40012400) ADC interrupt and status register
// ( (unsigned int)((ADC_ISR >> 0) & 0xFFFFFFFF), ((ADC_ISR = (ADC_ISR & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// - SFDITEM_FIELD__ADC_ISR_EOC
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// - SFDITEM_FIELD__ADC_ISR_OVR
// - SFDITEM_FIELD__ADC_ISR_AWD
//
//
// ----------------------------- Register Item Address: ADC_IER ---------------------------------
// SVD Line: 74
unsigned int ADC_IER __AT (0x40012404);
// ------------------------------- Field Item: ADC_IER_EOSMPIE ----------------------------------
// SVD Line: 80
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// EOSMPIE
//
// [Bit 1] RW (@ 0x40012404) ADC group regular end of sampling interrupt
//
// ( (unsigned int) ADC_IER )
// EOSMPIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOCIE -----------------------------------
// SVD Line: 85
// - SFDITEM_FIELD__ADC_IER_EOCIE
// EOCIE
//
// [Bit 2] RW (@ 0x40012404) ADC group regular end of unitary conversion interrupt
//
// ( (unsigned int) ADC_IER )
// EOCIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOSEQIE ----------------------------------
// SVD Line: 90
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// EOSEQIE
//
// [Bit 3] RW (@ 0x40012404) ADC group regular end of sequence conversions interrupt
//
// ( (unsigned int) ADC_IER )
// EOSEQIE
//
//
//
// -------------------------------- Field Item: ADC_IER_OVRIE -----------------------------------
// SVD Line: 95
// - SFDITEM_FIELD__ADC_IER_OVRIE
// OVRIE
//
// [Bit 4] RW (@ 0x40012404) ADC group regular overrun interrupt
//
// ( (unsigned int) ADC_IER )
// OVRIE
//
//
//
// -------------------------------- Field Item: ADC_IER_AWDIE -----------------------------------
// SVD Line: 100
// - SFDITEM_FIELD__ADC_IER_AWDIE
// AWDIE
//
// [Bit 7] RW (@ 0x40012404) ADC analog watchdog interrupt
//
// ( (unsigned int) ADC_IER )
// AWDIE
//
//
//
// --------------------------------- Register RTree: ADC_IER ------------------------------------
// SVD Line: 74
// SFDITEM_REG__ADC_IER
// IER
//
// [Bits 31..0] RW (@ 0x40012404) ADC interrupt enable register
// ( (unsigned int)((ADC_IER >> 0) & 0xFFFFFFFF), ((ADC_IER = (ADC_IER & ~(0x9EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x9E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// - SFDITEM_FIELD__ADC_IER_EOCIE
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// - SFDITEM_FIELD__ADC_IER_OVRIE
// - SFDITEM_FIELD__ADC_IER_AWDIE
//
//
// ------------------------------ Register Item Address: ADC_CR ---------------------------------
// SVD Line: 107
unsigned int ADC_CR __AT (0x40012408);
// --------------------------------- Field Item: ADC_CR_ADEN ------------------------------------
// SVD Line: 113
// - SFDITEM_FIELD__ADC_CR_ADEN
// ADEN
//
// [Bit 0] RW (@ 0x40012408) ADC enable
//
// ( (unsigned int) ADC_CR )
// ADEN
//
//
//
// -------------------------------- Field Item: ADC_CR_ADDIS ------------------------------------
// SVD Line: 118
// - SFDITEM_FIELD__ADC_CR_ADDIS
// ADDIS
//
// [Bit 1] RW (@ 0x40012408) ADC enable
//
// ( (unsigned int) ADC_CR )
// ADDIS
//
//
//
// ------------------------------- Field Item: ADC_CR_ADSTART -----------------------------------
// SVD Line: 123
// - SFDITEM_FIELD__ADC_CR_ADSTART
// ADSTART
//
// [Bit 2] RW (@ 0x40012408) ADC group regular conversion start
//
// ( (unsigned int) ADC_CR )
// ADSTART
//
//
//
// -------------------------------- Field Item: ADC_CR_ADSTP ------------------------------------
// SVD Line: 128
// - SFDITEM_FIELD__ADC_CR_ADSTP
// ADSTP
//
// [Bit 4] RW (@ 0x40012408) ADC group regular conversion stop
//
// ( (unsigned int) ADC_CR )
// ADSTP
//
//
//
// ----------------------------- Field Item: ADC_CR_VREF_BUFFERE --------------------------------
// SVD Line: 133
// - SFDITEM_FIELD__ADC_CR_VREF_BUFFERE
// VREF_BUFFERE
//
// [Bit 5] RW (@ 0x40012408) desc VREF_BUFFERE
//
// ( (unsigned int) ADC_CR )
// VREF_BUFFERE
//
//
//
// ----------------------------- Field Item: ADC_CR_VERBUFF_SEL ---------------------------------
// SVD Line: 138
// - SFDITEM_FIELD__ADC_CR_VERBUFF_SEL
// VERBUFF_SEL
//
// [Bits 7..6] RW (@ 0x40012408) desc VERBUFF_SEL
//
// ( (unsigned char)((ADC_CR >> 6) & 0x3), ((ADC_CR = (ADC_CR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_CR_ADCAL ------------------------------------
// SVD Line: 143
// - SFDITEM_FIELD__ADC_CR_ADCAL
// ADCAL
//
// [Bit 31] RW (@ 0x40012408) ADC group regular conversion calibration
//
// ( (unsigned int) ADC_CR )
// ADCAL
//
//
//
// --------------------------------- Register RTree: ADC_CR -------------------------------------
// SVD Line: 107
// SFDITEM_REG__ADC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40012408) ADC control register
// ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0x800000F7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800000F7) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CR_ADEN
// - SFDITEM_FIELD__ADC_CR_ADDIS
// - SFDITEM_FIELD__ADC_CR_ADSTART
// - SFDITEM_FIELD__ADC_CR_ADSTP
// - SFDITEM_FIELD__ADC_CR_VREF_BUFFERE
// - SFDITEM_FIELD__ADC_CR_VERBUFF_SEL
// - SFDITEM_FIELD__ADC_CR_ADCAL
//
//
// ---------------------------- Register Item Address: ADC_CFGR1 --------------------------------
// SVD Line: 150
unsigned int ADC_CFGR1 __AT (0x4001240C);
// ------------------------------ Field Item: ADC_CFGR1_SCANDIR ---------------------------------
// SVD Line: 156
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// SCANDIR
//
// [Bit 2] RW (@ 0x4001240C) Scan sequence direction
//
// ( (unsigned int) ADC_CFGR1 )
// SCANDIR
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_RESSEL ----------------------------------
// SVD Line: 161
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// RESSEL
//
// [Bits 4..3] RW (@ 0x4001240C) ADC data resolution
//
// ( (unsigned char)((ADC_CFGR1 >> 3) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_ALIGN ----------------------------------
// SVD Line: 166
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// ALIGN
//
// [Bit 5] RW (@ 0x4001240C) ADC data alignement
//
// ( (unsigned int) ADC_CFGR1 )
// ALIGN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_EXTSEL ----------------------------------
// SVD Line: 171
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// EXTSEL
//
// [Bits 8..6] RW (@ 0x4001240C) ADC group regular external trigger source
//
// ( (unsigned char)((ADC_CFGR1 >> 6) & 0x7), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_EXTEN ----------------------------------
// SVD Line: 176
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// EXTEN
//
// [Bits 11..10] RW (@ 0x4001240C) ADC group regular external trigger polarity
//
// ( (unsigned char)((ADC_CFGR1 >> 10) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_OVRMOD ----------------------------------
// SVD Line: 181
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// OVRMOD
//
// [Bit 12] RW (@ 0x4001240C) ADC group regular overrun configuration
//
// ( (unsigned int) ADC_CFGR1 )
// OVRMOD
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_CONT -----------------------------------
// SVD Line: 186
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// CONT
//
// [Bit 13] RW (@ 0x4001240C) ADC group regular continuous conversion mode
//
// ( (unsigned int) ADC_CFGR1 )
// CONT
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_WAIT -----------------------------------
// SVD Line: 191
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// WAIT
//
// [Bit 14] RW (@ 0x4001240C) Wait conversion mode
//
// ( (unsigned int) ADC_CFGR1 )
// WAIT
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_DISCEN ----------------------------------
// SVD Line: 196
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// DISCEN
//
// [Bit 16] RW (@ 0x4001240C) ADC group regular sequencer discontinuous mode
//
// ( (unsigned int) ADC_CFGR1 )
// DISCEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_AWDSGL ----------------------------------
// SVD Line: 201
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// AWDSGL
//
// [Bit 22] RW (@ 0x4001240C) ADC analog watchdog monitoring a single channel or all channels
//
// ( (unsigned int) ADC_CFGR1 )
// AWDSGL
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDEN ----------------------------------
// SVD Line: 206
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// AWDEN
//
// [Bit 23] RW (@ 0x4001240C) ADC analog watchdog enable on scope ADC group regular
//
// ( (unsigned int) ADC_CFGR1 )
// AWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDCH ----------------------------------
// SVD Line: 211
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
// AWDCH
//
// [Bits 29..26] RW (@ 0x4001240C) ADC analog watchdog monitored channel selection
//
// ( (unsigned char)((ADC_CFGR1 >> 26) & 0xF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR1 -----------------------------------
// SVD Line: 150
// SFDITEM_REG__ADC_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x4001240C) ADC configuration register 1
// ( (unsigned int)((ADC_CFGR1 >> 0) & 0xFFFFFFFF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3CC17DFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CC17DFC) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR1_SCANDIR
// - SFDITEM_FIELD__ADC_CFGR1_RESSEL
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
//
//
// ---------------------------- Register Item Address: ADC_CFGR2 --------------------------------
// SVD Line: 218
unsigned int ADC_CFGR2 __AT (0x40012410);
// ------------------------------ Field Item: ADC_CFGR2_CKMODE ----------------------------------
// SVD Line: 224
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
// CKMODE
//
// [Bits 31..28] RW (@ 0x40012410) ADC clock mode
//
// ( (unsigned char)((ADC_CFGR2 >> 28) & 0xF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR2 -----------------------------------
// SVD Line: 218
// SFDITEM_REG__ADC_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40012410) ADC configuration register 2
// ( (unsigned int)((ADC_CFGR2 >> 0) & 0xFFFFFFFF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xF0000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0000000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
//
//
// ----------------------------- Register Item Address: ADC_SMPR --------------------------------
// SVD Line: 231
unsigned int ADC_SMPR __AT (0x40012414);
// -------------------------------- Field Item: ADC_SMPR_SMP ------------------------------------
// SVD Line: 237
// - SFDITEM_FIELD__ADC_SMPR_SMP
// SMP
//
// [Bits 2..0] RW (@ 0x40012414) Sampling time selection
//
// ( (unsigned char)((ADC_SMPR >> 0) & 0x7), ((ADC_SMPR = (ADC_SMPR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR ------------------------------------
// SVD Line: 231
// SFDITEM_REG__ADC_SMPR
// SMPR
//
// [Bits 31..0] RW (@ 0x40012414) ADC sampling time register
// ( (unsigned int)((ADC_SMPR >> 0) & 0xFFFFFFFF), ((ADC_SMPR = (ADC_SMPR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR_SMP
//
//
// ------------------------------ Register Item Address: ADC_TR ---------------------------------
// SVD Line: 244
unsigned int ADC_TR __AT (0x40012420);
// ---------------------------------- Field Item: ADC_TR_LT -------------------------------------
// SVD Line: 251
// - SFDITEM_FIELD__ADC_TR_LT
// LT
//
// [Bits 11..0] RW (@ 0x40012420) ADC analog watchdog threshold low
//
// ( (unsigned short)((ADC_TR >> 0) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ---------------------------------- Field Item: ADC_TR_HT -------------------------------------
// SVD Line: 256
// - SFDITEM_FIELD__ADC_TR_HT
// HT
//
// [Bits 27..16] RW (@ 0x40012420) ADC analog watchdog threshold high
//
// ( (unsigned short)((ADC_TR >> 16) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_TR -------------------------------------
// SVD Line: 244
// SFDITEM_REG__ADC_TR
// TR
//
// [Bits 31..0] RW (@ 0x40012420) ADC analog watchdog 1 threshold register
// ( (unsigned int)((ADC_TR >> 0) & 0xFFFFFFFF), ((ADC_TR = (ADC_TR & ~(0xFFF0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF0FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_TR_LT
// - SFDITEM_FIELD__ADC_TR_HT
//
//
// ---------------------------- Register Item Address: ADC_CHSELR -------------------------------
// SVD Line: 263
unsigned int ADC_CHSELR __AT (0x40012428);
// ------------------------------ Field Item: ADC_CHSELR_CHSEL0 ---------------------------------
// SVD Line: 270
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL0
// CHSEL0
//
// [Bit 0] RW (@ 0x40012428) Channel-0 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL0
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL1 ---------------------------------
// SVD Line: 275
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL1
// CHSEL1
//
// [Bit 1] RW (@ 0x40012428) Channel-1 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL1
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL2 ---------------------------------
// SVD Line: 280
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL2
// CHSEL2
//
// [Bit 2] RW (@ 0x40012428) Channel-2 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL2
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL3 ---------------------------------
// SVD Line: 285
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL3
// CHSEL3
//
// [Bit 3] RW (@ 0x40012428) Channel-3 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL3
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL4 ---------------------------------
// SVD Line: 290
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL4
// CHSEL4
//
// [Bit 4] RW (@ 0x40012428) Channel-4 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL4
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL5 ---------------------------------
// SVD Line: 295
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL5
// CHSEL5
//
// [Bit 5] RW (@ 0x40012428) Channel-5 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL5
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL6 ---------------------------------
// SVD Line: 300
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL6
// CHSEL6
//
// [Bit 6] RW (@ 0x40012428) Channel-6 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL6
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL7 ---------------------------------
// SVD Line: 305
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL7
// CHSEL7
//
// [Bit 7] RW (@ 0x40012428) Channel-7 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL7
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL8 ---------------------------------
// SVD Line: 310
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL8
// CHSEL8
//
// [Bit 8] RW (@ 0x40012428) Channel-8 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL8
//
//
//
// ------------------------------ Field Item: ADC_CHSELR_CHSEL9 ---------------------------------
// SVD Line: 315
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL9
// CHSEL9
//
// [Bit 9] RW (@ 0x40012428) Channel-9 selection
//
// ( (unsigned int) ADC_CHSELR )
// CHSEL9
//
//
//
// ------------------------------- Register RTree: ADC_CHSELR -----------------------------------
// SVD Line: 263
// SFDITEM_REG__ADC_CHSELR
// CHSELR
//
// [Bits 31..0] RW (@ 0x40012428) ADC group regular sequencer register
// ( (unsigned int)((ADC_CHSELR >> 0) & 0xFFFFFFFF), ((ADC_CHSELR = (ADC_CHSELR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL0
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL1
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL2
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL3
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL4
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL5
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL6
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL7
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL8
// - SFDITEM_FIELD__ADC_CHSELR_CHSEL9
//
//
// ------------------------------ Register Item Address: ADC_DR ---------------------------------
// SVD Line: 322
unsigned int ADC_DR __AT (0x40012440);
// --------------------------------- Field Item: ADC_DR_DATA ------------------------------------
// SVD Line: 329
// - SFDITEM_FIELD__ADC_DR_DATA
// DATA
//
// [Bits 15..0] RO (@ 0x40012440) ADC group regular conversion data
//
// ( (unsigned short)((ADC_DR >> 0) & 0xFFFF) )
//
//
//
// --------------------------------- Register RTree: ADC_DR -------------------------------------
// SVD Line: 322
// SFDITEM_REG__ADC_DR
// DR
//
// [Bits 31..0] RO (@ 0x40012440) ADC group regular data register
// ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_DR_DATA
//
//
// ----------------------------- Register Item Address: ADC_CCSR --------------------------------
// SVD Line: 336
unsigned int ADC_CCSR __AT (0x40012444);
// ------------------------------- Field Item: ADC_CCSR_CALSEL ----------------------------------
// SVD Line: 342
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// CALSEL
//
// [Bit 11] RW (@ 0x40012444) Calibration contents selection
//
// ( (unsigned int) ADC_CCSR )
// CALSEL
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSMP ----------------------------------
// SVD Line: 347
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// CALSMP
//
// [Bits 13..12] RW (@ 0x40012444) Calibration sample time selection
//
// ( (unsigned char)((ADC_CCSR >> 12) & 0x3), ((ADC_CCSR = (ADC_CCSR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALBYP ----------------------------------
// SVD Line: 352
// - SFDITEM_FIELD__ADC_CCSR_CALBYP
// CALBYP
//
// [Bit 14] RW (@ 0x40012444) desc CALBYP
//
// ( (unsigned int) ADC_CCSR )
// CALBYP
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSET ----------------------------------
// SVD Line: 357
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// CALSET
//
// [Bit 15] RW (@ 0x40012444) Calibration factor selection
//
// ( (unsigned int) ADC_CCSR )
// CALSET
//
//
//
// ------------------------------- Field Item: ADC_CCSR_OFFSUC ----------------------------------
// SVD Line: 362
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// OFFSUC
//
// [Bit 29] RW (@ 0x40012444) desc OFFSUC
//
// ( (unsigned int) ADC_CCSR )
// OFFSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALSUC ----------------------------------
// SVD Line: 367
// - SFDITEM_FIELD__ADC_CCSR_CALSUC
// CALSUC
//
// [Bit 30] RW (@ 0x40012444) desc CALSUC
//
// ( (unsigned int) ADC_CCSR )
// CALSUC
//
//
//
// ------------------------------- Field Item: ADC_CCSR_CALON -----------------------------------
// SVD Line: 372
// - SFDITEM_FIELD__ADC_CCSR_CALON
// CALON
//
// [Bit 31] RO (@ 0x40012444) Calibration flag
//
// ( (unsigned int) ADC_CCSR )
// CALON
//
//
//
// -------------------------------- Register RTree: ADC_CCSR ------------------------------------
// SVD Line: 336
// SFDITEM_REG__ADC_CCSR
// CCSR
//
// [Bits 31..0] RW (@ 0x40012444) ADC calibration configuration and status register
// ( (unsigned int)((ADC_CCSR >> 0) & 0xFFFFFFFF), ((ADC_CCSR = (ADC_CCSR & ~(0x6000F800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6000F800) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCSR_CALSEL
// - SFDITEM_FIELD__ADC_CCSR_CALSMP
// - SFDITEM_FIELD__ADC_CCSR_CALBYP
// - SFDITEM_FIELD__ADC_CCSR_CALSET
// - SFDITEM_FIELD__ADC_CCSR_OFFSUC
// - SFDITEM_FIELD__ADC_CCSR_CALSUC
// - SFDITEM_FIELD__ADC_CCSR_CALON
//
//
// ----------------------------- Register Item Address: ADC_CCR ---------------------------------
// SVD Line: 380
unsigned int ADC_CCR __AT (0x40012708);
// ------------------------------- Field Item: ADC_CCR_VREFEN -----------------------------------
// SVD Line: 386
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// VREFEN
//
// [Bit 22] RW (@ 0x40012708) VREFINT enable
//
// ( (unsigned int) ADC_CCR )
// VREFEN
//
//
//
// -------------------------------- Field Item: ADC_CCR_TSEN ------------------------------------
// SVD Line: 391
// - SFDITEM_FIELD__ADC_CCR_TSEN
// TSEN
//
// [Bit 23] RW (@ 0x40012708) Temperature sensor enable
//
// ( (unsigned int) ADC_CCR )
// TSEN
//
//
//
// --------------------------------- Register RTree: ADC_CCR ------------------------------------
// SVD Line: 380
// SFDITEM_REG__ADC_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x40012708) ADC common configuration register
// ( (unsigned int)((ADC_CCR >> 0) & 0xFFFFFFFF), ((ADC_CCR = (ADC_CCR & ~(0xC00000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC00000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// - SFDITEM_FIELD__ADC_CCR_TSEN
//
//
// ---------------------------------- Peripheral View: ADC --------------------------------------
// SVD Line: 25
// ADC
// ADC
// - SFDITEM_REG__ADC_ISR
// - SFDITEM_REG__ADC_IER
// - SFDITEM_REG__ADC_CR
// - SFDITEM_REG__ADC_CFGR1
// - SFDITEM_REG__ADC_CFGR2
// - SFDITEM_REG__ADC_SMPR
// - SFDITEM_REG__ADC_TR
// - SFDITEM_REG__ADC_CHSELR
// - SFDITEM_REG__ADC_DR
// - SFDITEM_REG__ADC_CCSR
// - SFDITEM_REG__ADC_CCR
//
//
// ------------------------------ Register Item Address: CRC_DR ---------------------------------
// SVD Line: 411
unsigned int CRC_DR __AT (0x40023000);
// ---------------------------------- Field Item: CRC_DR_DR -------------------------------------
// SVD Line: 418
// - SFDITEM_FIELD__CRC_DR_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data Register
//
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_DR -------------------------------------
// SVD Line: 411
// SFDITEM_REG__CRC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_DR_DR
//
//
// ----------------------------- Register Item Address: CRC_IDR ---------------------------------
// SVD Line: 425
unsigned int CRC_IDR __AT (0x40023004);
// --------------------------------- Field Item: CRC_IDR_IDR ------------------------------------
// SVD Line: 431
// - SFDITEM_FIELD__CRC_IDR_IDR
// IDR
//
// [Bits 7..0] RW (@ 0x40023004) Independent Data register
//
// ( (unsigned char)((CRC_IDR >> 0) & 0xFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_IDR ------------------------------------
// SVD Line: 425
// SFDITEM_REG__CRC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x40023004) Independent Data register
// ( (unsigned int)((CRC_IDR >> 0) & 0xFFFFFFFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_IDR_IDR
//
//
// ------------------------------ Register Item Address: CRC_CR ---------------------------------
// SVD Line: 438
unsigned int CRC_CR __AT (0x40023008);
// -------------------------------- Field Item: CRC_CR_RESET ------------------------------------
// SVD Line: 445
// - SFDITEM_FIELD__CRC_CR_RESET
// RESET
//
// [Bit 0] WO (@ 0x40023008) Reset bit
//
// ( (unsigned int) CRC_CR )
// RESET
//
//
//
// --------------------------------- Register RTree: CRC_CR -------------------------------------
// SVD Line: 438
// SFDITEM_REG__CRC_CR
// CR
//
// [Bits 31..0] WO (@ 0x40023008) Control register
// ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_CR_RESET
//
//
// ---------------------------------- Peripheral View: CRC --------------------------------------
// SVD Line: 400
// CRC
// CRC
// - SFDITEM_REG__CRC_DR
// - SFDITEM_REG__CRC_IDR
// - SFDITEM_REG__CRC_CR
//
//
// -------------------------- Register Item Address: DBGMCU_IDCODE ------------------------------
// SVD Line: 465
unsigned int DBGMCU_IDCODE __AT (0x40015800);
// ---------------------------- Field Item: DBGMCU_IDCODE_REV_ID --------------------------------
// SVD Line: 472
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
// REV_ID
//
// [Bits 31..0] RO (@ 0x40015800) REV_ID
//
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
//
//
//
// ------------------------------ Register RTree: DBGMCU_IDCODE ---------------------------------
// SVD Line: 465
// SFDITEM_REG__DBGMCU_IDCODE
// IDCODE
//
// [Bits 31..0] RO (@ 0x40015800) MCU Device ID Code Register
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 479
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 485
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) Debug Stop Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 479
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x2UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ1 -----------------------------
// SVD Line: 492
unsigned int DBGMCU_APB_FZ1 __AT (0x40015808);
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_LPTIM_STOP ---------------------------
// SVD Line: 498
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
// DBG_LPTIM_STOP
//
// [Bit 31] RW (@ 0x40015808) Debug LPTIM stopped when Core ishalted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_LPTIM_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ1 ---------------------------------
// SVD Line: 492
// SFDITEM_REG__DBGMCU_APB_FZ1
// APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) APB Freeze Register1
// ( (unsigned int)((DBGMCU_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ1 = (DBGMCU_APB_FZ1 & ~(0x80000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80000000) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ2 -----------------------------
// SVD Line: 505
unsigned int DBGMCU_APB_FZ2 __AT (0x4001580C);
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER1_STOP ---------------------------
// SVD Line: 511
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// DBG_TIMER1_STOP
//
// [Bit 11] RW (@ 0x4001580C) Debug Timer 1 stopped when Core ishalted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER1_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ2_DBG_TIM14_STOP ---------------------------
// SVD Line: 516
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
// DBG_TIM14_STOP
//
// [Bit 15] RW (@ 0x4001580C) Debug TIM 14 stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIM14_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ2 ---------------------------------
// SVD Line: 505
// SFDITEM_REG__DBGMCU_APB_FZ2
// APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) APB Freeze Register2
// ( (unsigned int)((DBGMCU_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ2 = (DBGMCU_APB_FZ2 & ~(0x8800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8800) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 454
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_APB_FZ1
// - SFDITEM_REG__DBGMCU_APB_FZ2
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 551
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 557
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 562
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 567
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 572
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 577
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 582
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 587
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 592
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT17 -----------------------------------
// SVD Line: 597
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// RT17
//
// [Bit 17] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT17
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT18 -----------------------------------
// SVD Line: 602
// - SFDITEM_FIELD__EXTI_RTSR_RT18
// RT18
//
// [Bit 18] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT18
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 551
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selection register
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0x600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// - SFDITEM_FIELD__EXTI_RTSR_RT18
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 609
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 615
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 620
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 625
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 630
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 635
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 640
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 645
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 650
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT17 -----------------------------------
// SVD Line: 655
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// FT17
//
// [Bit 17] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT17
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT18 -----------------------------------
// SVD Line: 660
// - SFDITEM_FIELD__EXTI_FTSR_FT18
// FT18
//
// [Bit 18] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT18
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 609
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selection register
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0x600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// - SFDITEM_FIELD__EXTI_FTSR_FT18
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 667
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------- Field Item: EXTI_SWIER_SWI0 ----------------------------------
// SVD Line: 673
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// SWI0
//
// [Bit 0] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI0
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI1 ----------------------------------
// SVD Line: 678
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// SWI1
//
// [Bit 1] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI1
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI2 ----------------------------------
// SVD Line: 683
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// SWI2
//
// [Bit 2] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI2
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI3 ----------------------------------
// SVD Line: 688
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// SWI3
//
// [Bit 3] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI3
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI4 ----------------------------------
// SVD Line: 693
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// SWI4
//
// [Bit 4] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI4
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI5 ----------------------------------
// SVD Line: 698
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// SWI5
//
// [Bit 5] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI5
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI6 ----------------------------------
// SVD Line: 703
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// SWI6
//
// [Bit 6] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI6
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI7 ----------------------------------
// SVD Line: 708
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// SWI7
//
// [Bit 7] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI7
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI17 ----------------------------------
// SVD Line: 713
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// SWI17
//
// [Bit 17] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI17
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI18 ----------------------------------
// SVD Line: 718
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
// SWI18
//
// [Bit 18] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI18
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 667
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt event register
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0x600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 725
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 731
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 736
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 741
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 746
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 751
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 756
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 761
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 766
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR17 ------------------------------------
// SVD Line: 771
// - SFDITEM_FIELD__EXTI_PR_PR17
// PR17
//
// [Bit 17] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR17
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR18 ------------------------------------
// SVD Line: 776
// - SFDITEM_FIELD__EXTI_PR_PR18
// PR18
//
// [Bit 18] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR18
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 725
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pending register
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0x600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
// - SFDITEM_FIELD__EXTI_PR_PR17
// - SFDITEM_FIELD__EXTI_PR_PR18
//
//
// --------------------------- Register Item Address: EXTI_EXTICR1 ------------------------------
// SVD Line: 783
unsigned int EXTI_EXTICR1 __AT (0x40021860);
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI0 ---------------------------------
// SVD Line: 789
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// EXTI0
//
// [Bits 1..0] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 0) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI1 ---------------------------------
// SVD Line: 794
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// EXTI1
//
// [Bits 9..8] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 8) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI2 ---------------------------------
// SVD Line: 799
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// EXTI2
//
// [Bits 17..16] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 16) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI3 ---------------------------------
// SVD Line: 804
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
// EXTI3
//
// [Bits 25..24] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 24) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR1 ----------------------------------
// SVD Line: 783
// SFDITEM_REG__EXTI_EXTICR1
// EXTICR1
//
// [Bits 31..0] RW (@ 0x40021860) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR1 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
//
//
// --------------------------- Register Item Address: EXTI_EXTICR2 ------------------------------
// SVD Line: 811
unsigned int EXTI_EXTICR2 __AT (0x40021864);
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI4 ---------------------------------
// SVD Line: 817
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// EXTI4
//
// [Bits 1..0] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 0) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI5 ---------------------------------
// SVD Line: 822
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// EXTI5
//
// [Bit 8] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI5
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI6 ---------------------------------
// SVD Line: 827
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// EXTI6
//
// [Bit 16] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI6
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI7 ---------------------------------
// SVD Line: 832
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
// EXTI7
//
// [Bit 24] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI7
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR2 ----------------------------------
// SVD Line: 811
// SFDITEM_REG__EXTI_EXTICR2
// EXTICR2
//
// [Bits 31..0] RW (@ 0x40021864) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR2 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x1010103UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1010103) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 839
unsigned int EXTI_IMR __AT (0x40021880);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 846
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 851
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 856
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 861
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 866
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 871
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 876
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 881
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM17 -----------------------------------
// SVD Line: 886
// - SFDITEM_FIELD__EXTI_IMR_IM17
// IM17
//
// [Bit 17] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM17
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM18 -----------------------------------
// SVD Line: 891
// - SFDITEM_FIELD__EXTI_IMR_IM18
// IM18
//
// [Bit 18] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM18
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM29 -----------------------------------
// SVD Line: 896
// - SFDITEM_FIELD__EXTI_IMR_IM29
// IM29
//
// [Bit 29] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM29
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 839
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021880) EXTI CPU wakeup with interrupt mask register
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0x200600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM17
// - SFDITEM_FIELD__EXTI_IMR_IM18
// - SFDITEM_FIELD__EXTI_IMR_IM29
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 903
unsigned int EXTI_EMR __AT (0x40021884);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 909
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 914
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 919
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 924
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 929
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 934
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 939
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 944
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM17 -----------------------------------
// SVD Line: 949
// - SFDITEM_FIELD__EXTI_EMR_EM17
// EM17
//
// [Bit 17] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM17
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM18 -----------------------------------
// SVD Line: 954
// - SFDITEM_FIELD__EXTI_EMR_EM18
// EM18
//
// [Bit 18] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM18
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM29 -----------------------------------
// SVD Line: 959
// - SFDITEM_FIELD__EXTI_EMR_EM29
// EM29
//
// [Bit 29] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM29
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 903
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x40021884) EXTI CPU wakeup with event mask register
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0x200600FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200600FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM17
// - SFDITEM_FIELD__EXTI_EMR_EM18
// - SFDITEM_FIELD__EXTI_EMR_EM29
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 525
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_EXTICR1
// - SFDITEM_REG__EXTI_EXTICR2
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_ACR --------------------------------
// SVD Line: 984
unsigned int FLASH_ACR __AT (0x40022000);
// ------------------------------ Field Item: FLASH_ACR_LATENCY ---------------------------------
// SVD Line: 991
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
// LATENCY
//
// [Bit 0] RW (@ 0x40022000) Latency
//
// ( (unsigned int) FLASH_ACR )
// LATENCY
//
//
//
// -------------------------------- Register RTree: FLASH_ACR -----------------------------------
// SVD Line: 984
// SFDITEM_REG__FLASH_ACR
// ACR
//
// [Bits 31..0] RW (@ 0x40022000) Access control register
// ( (unsigned int)((FLASH_ACR >> 0) & 0xFFFFFFFF), ((FLASH_ACR = (FLASH_ACR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
//
//
// ---------------------------- Register Item Address: FLASH_KEYR -------------------------------
// SVD Line: 998
unsigned int FLASH_KEYR __AT (0x40022008);
// ------------------------------- Field Item: FLASH_KEYR_KEY -----------------------------------
// SVD Line: 1005
// - SFDITEM_FIELD__FLASH_KEYR_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash key
//
// ( (unsigned int)((FLASH_KEYR >> 0) & 0x0), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_KEYR -----------------------------------
// SVD Line: 998
// SFDITEM_REG__FLASH_KEYR
// KEYR
//
// [Bits 31..0] WO (@ 0x40022008) Flash key register
// ( (unsigned int)((FLASH_KEYR >> 0) & 0xFFFFFFFF), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEYR_KEY
//
//
// -------------------------- Register Item Address: FLASH_OPTKEYR ------------------------------
// SVD Line: 1012
unsigned int FLASH_OPTKEYR __AT (0x4002200C);
// ---------------------------- Field Item: FLASH_OPTKEYR_OPTKEY --------------------------------
// SVD Line: 1019
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key
//
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0x0), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEYR ---------------------------------
// SVD Line: 1012
// SFDITEM_REG__FLASH_OPTKEYR
// OPTKEYR
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key register
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 1026
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 1032
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 1037
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protected error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 1042
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and Engineering bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 1047
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RW (@ 0x40022010) Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 1026
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) Status register
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x18011UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x18011) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 1054
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 1061
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Programming
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 1066
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 1071
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Mass erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 1076
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 1081
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option byte program start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_PGSTRT ----------------------------------
// SVD Line: 1086
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// PGSTRT
//
// [Bit 19] RW (@ 0x40022014) Flash main memory program start
//
// ( (unsigned int) FLASH_CR )
// PGSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 1091
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 1096
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 1101
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option byte loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 1106
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Options Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 1111
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) FLASH_CR Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 1054
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) Flash control register
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xCB0A0807UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCB0A0807) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 1118
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------ Field Item: FLASH_OPTR_BOREN ----------------------------------
// SVD Line: 1125
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// BOREN
//
// [Bit 8] RW (@ 0x40022020) BOR reset Level
//
// ( (unsigned int) FLASH_OPTR )
// BOREN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BORF_LEV --------------------------------
// SVD Line: 1130
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
// BORF_LEV
//
// [Bits 11..9] RW (@ 0x40022020) These bits contain the VDD supply level threshold that activates the reset
//
// ( (unsigned char)((FLASH_OPTR >> 9) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IWDG_SW ---------------------------------
// SVD Line: 1135
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// IWDG_SW
//
// [Bit 12] RW (@ 0x40022020) Independent watchdog selection
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_SW
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_SWD_MODE --------------------------------
// SVD Line: 1140
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
// SWD_MODE
//
// [Bit 13] RW (@ 0x40022020) SWD_MODE
//
// ( (unsigned int) FLASH_OPTR )
// SWD_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 1145
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 14] RW (@ 0x40022020) NRST_MODE
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 1118
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) Flash option register
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7F00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F00) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
//
//
// ---------------------------- Register Item Address: FLASH_SDKR -------------------------------
// SVD Line: 1152
unsigned int FLASH_SDKR __AT (0x40022024);
// ----------------------------- Field Item: FLASH_SDKR_SDK_STRT --------------------------------
// SVD Line: 1159
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// SDK_STRT
//
// [Bits 3..0] RW (@ 0x40022024) SDK area start address
//
// ( (unsigned char)((FLASH_SDKR >> 0) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_SDKR_SDK_END ---------------------------------
// SVD Line: 1164
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
// SDK_END
//
// [Bits 11..8] RW (@ 0x40022024) SDK area end address
//
// ( (unsigned char)((FLASH_SDKR >> 8) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SDKR -----------------------------------
// SVD Line: 1152
// SFDITEM_REG__FLASH_SDKR
// SDKR
//
// [Bits 31..0] RW (@ 0x40022024) Flash SDK address register
// ( (unsigned int)((FLASH_SDKR >> 0) & 0xFFFFFFFF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xF0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
//
//
// ---------------------------- Register Item Address: FLASH_BTCR -------------------------------
// SVD Line: 1171
unsigned int FLASH_BTCR __AT (0x40022028);
// ---------------------------- Field Item: FLASH_BTCR_BOOT_SIZE --------------------------------
// SVD Line: 1177
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// BOOT_SIZE
//
// [Bits 2..0] RW (@ 0x40022028) desc BOOT_SIZE
//
// ( (unsigned char)((FLASH_BTCR >> 0) & 0x7), ((FLASH_BTCR = (FLASH_BTCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_BOOT0 ----------------------------------
// SVD Line: 1182
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// BOOT0
//
// [Bit 14] RW (@ 0x40022028) desc BOOT0
//
// ( (unsigned int) FLASH_BTCR )
// BOOT0
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_NBOOT1 ---------------------------------
// SVD Line: 1187
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
// NBOOT1
//
// [Bit 15] RW (@ 0x40022028) desc NBOOT1
//
// ( (unsigned int) FLASH_BTCR )
// NBOOT1
//
//
//
// ------------------------------- Register RTree: FLASH_BTCR -----------------------------------
// SVD Line: 1171
// SFDITEM_REG__FLASH_BTCR
// BTCR
//
// [Bits 31..0] RW (@ 0x40022028) FLASH boot control register
// ( (unsigned int)((FLASH_BTCR >> 0) & 0xFFFFFFFF), ((FLASH_BTCR = (FLASH_BTCR & ~(0xC007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC007) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 1194
unsigned int FLASH_WRPR __AT (0x4002202C);
// ------------------------------- Field Item: FLASH_WRPR_WRP -----------------------------------
// SVD Line: 1201
// - SFDITEM_FIELD__FLASH_WRPR_WRP
// WRP
//
// [Bits 5..0] RW (@ 0x4002202C) WRP address
//
// ( (unsigned char)((FLASH_WRPR >> 0) & 0x3F), ((FLASH_WRPR = (FLASH_WRPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 1194
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x4002202C) Flash WRP address register
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_WRP
//
//
// ---------------------------- Register Item Address: FLASH_STCR -------------------------------
// SVD Line: 1208
unsigned int FLASH_STCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_STCR_SLEEP_EN --------------------------------
// SVD Line: 1215
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) FLash sleep enable
//
// ( (unsigned int) FLASH_STCR )
// SLEEP_EN
//
//
//
// ---------------------------- Field Item: FLASH_STCR_SLEEP_TIME -------------------------------
// SVD Line: 1220
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
// SLEEP_TIME
//
// [Bits 15..8] RW (@ 0x40022090) FLash sleep time configuration(counter based on HSI_10M)
//
// ( (unsigned char)((FLASH_STCR >> 8) & 0xFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_STCR -----------------------------------
// SVD Line: 1208
// SFDITEM_REG__FLASH_STCR
// STCR
//
// [Bits 31..0] RW (@ 0x40022090) Flash sleep time config register
// ( (unsigned int)((FLASH_STCR >> 0) & 0xFFFFFFFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFF01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF01) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 1227
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 1234
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 8..0] RW (@ 0x40022100) FLash TS0 register
//
// ( (unsigned short)((FLASH_TS0 >> 0) & 0x1FF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 1227
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) Flash TS0 register
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 1241
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 1248
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 9..0] RW (@ 0x40022104) FLash TS1 register
//
// ( (unsigned short)((FLASH_TS1 >> 0) & 0x3FF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 1241
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) Flash TS1 register
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 1255
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 1262
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 8..0] RW (@ 0x40022108) FLash TS2P register
//
// ( (unsigned short)((FLASH_TS2P >> 0) & 0x1FF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 1255
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) Flash TS2P register
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 1269
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 1276
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 11..0] RW (@ 0x4002210C) FLash TPS3 register
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0xFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 1269
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) Flash TPS3 register
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 1283
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 1290
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 8..0] RW (@ 0x40022110) FLash TS3 register
//
// ( (unsigned short)((FLASH_TS3 >> 0) & 0x1FF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 1283
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) Flash TS3 register
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_PERTPE ------------------------------
// SVD Line: 1297
unsigned int FLASH_PERTPE __AT (0x40022114);
// ----------------------------- Field Item: FLASH_PERTPE_PERTPE --------------------------------
// SVD Line: 1304
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
// PERTPE
//
// [Bits 17..0] RW (@ 0x40022114) FLash PERTPE register
//
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0x3FFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PERTPE ----------------------------------
// SVD Line: 1297
// SFDITEM_REG__FLASH_PERTPE
// PERTPE
//
// [Bits 31..0] RW (@ 0x40022114) Flash PERTPE register
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0xFFFFFFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
//
//
// -------------------------- Register Item Address: FLASH_SMERTPE ------------------------------
// SVD Line: 1311
unsigned int FLASH_SMERTPE __AT (0x40022118);
// ---------------------------- Field Item: FLASH_SMERTPE_SMERTPE -------------------------------
// SVD Line: 1318
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
// SMERTPE
//
// [Bits 17..0] RW (@ 0x40022118) FLash SMERTPE register
//
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0x3FFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_SMERTPE ---------------------------------
// SVD Line: 1311
// SFDITEM_REG__FLASH_SMERTPE
// SMERTPE
//
// [Bits 31..0] RW (@ 0x40022118) Flash SMERTPE register
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0xFFFFFFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 1325
unsigned int FLASH_PRGTPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 1332
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 15..0] RW (@ 0x4002211C) FLash PRGTPE register
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0xFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 1325
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x4002211C) Flash PRGTPE register
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 1339
unsigned int FLASH_PRETPE __AT (0x40022120);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 1346
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 13..0] RW (@ 0x40022120) FLash PRETPE register
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0x3FFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 1339
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x40022120) Flash PRETPE register
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 968
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_ACR
// - SFDITEM_REG__FLASH_KEYR
// - SFDITEM_REG__FLASH_OPTKEYR
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_SDKR
// - SFDITEM_REG__FLASH_BTCR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_STCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_PERTPE
// - SFDITEM_REG__FLASH_SMERTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 1366
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 1373
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 1378
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 1383
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 1388
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 1393
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 1403
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 1408
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 1366
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 1415
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 1421
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 1426
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 1431
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 1436
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 1441
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 1446
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 1451
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 1456
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 1415
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 1463
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1470
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1475
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1480
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1485
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1490
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1495
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1500
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1505
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 1463
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 1512
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1519
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1524
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1529
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1534
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1539
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1544
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1549
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1554
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 1512
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 1561
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 1568
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 1573
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 1578
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 1583
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 1588
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 1593
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 1598
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 1603
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 1561
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 1610
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 1616
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 1621
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 1626
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 1631
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 1636
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 1641
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 1646
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 1651
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 1610
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 1658
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 1665
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 1670
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 1675
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 1680
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 1685
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 1690
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 1695
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 1700
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 1705
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 1710
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 1715
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 1720
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 1725
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 1730
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 1735
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 1740
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 1658
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 1747
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 1753
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 1758
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 1763
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 1768
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 1773
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 1778
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 1783
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 1788
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 1793
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 1747
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 1800
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1806
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1811
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1816
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1821
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1826
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1831
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1836
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1841
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 1800
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 1848
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 1855
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 1860
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 1865
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 1870
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 1875
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 1880
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 1885
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 1890
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 1848
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 1355
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 1366
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 1373
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 1378
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 1383
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 1388
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE4 ---------------------------------
// SVD Line: 1393
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 8) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE5 ---------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 10) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE6 ---------------------------------
// SVD Line: 1403
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 12) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE7 ---------------------------------
// SVD Line: 1408
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 14) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 1366
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 1415
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 1421
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 1426
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 1431
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 1436
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT4 ----------------------------------
// SVD Line: 1441
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT5 ----------------------------------
// SVD Line: 1446
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT6 ----------------------------------
// SVD Line: 1451
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT7 ----------------------------------
// SVD Line: 1456
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT7
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 1415
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 1463
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1470
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1475
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1480
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1485
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1490
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 8) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1495
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 10) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1500
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 12) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1505
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 14) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 1463
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 1512
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1519
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1524
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1529
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1534
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1539
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 8) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1544
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 10) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1549
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 12) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1554
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 14) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 1512
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 1561
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 1568
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 1573
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 1578
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 1583
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID4 -----------------------------------
// SVD Line: 1588
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID5 -----------------------------------
// SVD Line: 1593
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID6 -----------------------------------
// SVD Line: 1598
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID7 -----------------------------------
// SVD Line: 1603
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID7
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 1561
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// - SFDITEM_FIELD__GPIOB_IDR_ID7
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 1610
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 1616
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 1621
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 1626
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 1631
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD4 -----------------------------------
// SVD Line: 1636
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD5 -----------------------------------
// SVD Line: 1641
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD6 -----------------------------------
// SVD Line: 1646
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD7 -----------------------------------
// SVD Line: 1651
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD7
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 1610
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// - SFDITEM_FIELD__GPIOB_ODR_OD7
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 1658
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 1665
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 1670
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 1675
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 1680
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS4 -----------------------------------
// SVD Line: 1685
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS5 -----------------------------------
// SVD Line: 1690
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS6 -----------------------------------
// SVD Line: 1695
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS7 -----------------------------------
// SVD Line: 1700
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 1705
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 1710
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 1715
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 1720
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR4 -----------------------------------
// SVD Line: 1725
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR5 -----------------------------------
// SVD Line: 1730
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR6 -----------------------------------
// SVD Line: 1735
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR7 -----------------------------------
// SVD Line: 1740
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR7
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 1658
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0xFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 1747
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 1753
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 1758
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 1763
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 1768
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK4 ----------------------------------
// SVD Line: 1773
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK5 ----------------------------------
// SVD Line: 1778
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK6 ----------------------------------
// SVD Line: 1783
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK7 ----------------------------------
// SVD Line: 1788
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 1793
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 1747
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 1800
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1806
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1811
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1816
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1821
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1826
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 16) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1831
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 20) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1836
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 24) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1841
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 28) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 1800
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 1848
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 1855
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 1860
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 1865
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 1870
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR4 -----------------------------------
// SVD Line: 1875
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR5 -----------------------------------
// SVD Line: 1880
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR6 -----------------------------------
// SVD Line: 1885
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR7 -----------------------------------
// SVD Line: 1890
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR7
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 1848
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// - SFDITEM_FIELD__GPIOB_BRR_BR7
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 1899
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOC_MODER -------------------------------
// SVD Line: 1914
unsigned int GPIOC_MODER __AT (0x50000800);
// ------------------------------ Field Item: GPIOC_MODER_MODE0 ---------------------------------
// SVD Line: 1921
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 0) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE1 ---------------------------------
// SVD Line: 1926
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 2) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_MODER ----------------------------------
// SVD Line: 1914
// SFDITEM_REG__GPIOC_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000800) GPIO port mode register
// ( (unsigned int)((GPIOC_MODER >> 0) & 0xFFFFFFFF), ((GPIOC_MODER = (GPIOC_MODER & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
//
//
// --------------------------- Register Item Address: GPIOC_OTYPER ------------------------------
// SVD Line: 1933
unsigned int GPIOC_OTYPER __AT (0x50000804);
// ------------------------------ Field Item: GPIOC_OTYPER_OT0 ----------------------------------
// SVD Line: 1939
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT1 ----------------------------------
// SVD Line: 1944
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT1
//
//
//
// ------------------------------ Register RTree: GPIOC_OTYPER ----------------------------------
// SVD Line: 1933
// SFDITEM_REG__GPIOC_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000804) GPIO port output type register
// ( (unsigned int)((GPIOC_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOC_OTYPER = (GPIOC_OTYPER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
//
//
// -------------------------- Register Item Address: GPIOC_OSPEEDR ------------------------------
// SVD Line: 1951
unsigned int GPIOC_OSPEEDR __AT (0x50000808);
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1958
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 0) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1963
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 2) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOC_OSPEEDR ---------------------------------
// SVD Line: 1951
// SFDITEM_REG__GPIOC_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000808) GPIO port output speed register
// ( (unsigned int)((GPIOC_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
//
//
// --------------------------- Register Item Address: GPIOC_PUPDR -------------------------------
// SVD Line: 1970
unsigned int GPIOC_PUPDR __AT (0x5000080C);
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1977
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 0) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1982
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 2) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_PUPDR ----------------------------------
// SVD Line: 1970
// SFDITEM_REG__GPIOC_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000080C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOC_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
//
//
// ---------------------------- Register Item Address: GPIOC_IDR --------------------------------
// SVD Line: 1989
unsigned int GPIOC_IDR __AT (0x50000810);
// -------------------------------- Field Item: GPIOC_IDR_ID0 -----------------------------------
// SVD Line: 1996
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID1 -----------------------------------
// SVD Line: 2001
// - SFDITEM_FIELD__GPIOC_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID1
//
//
//
// -------------------------------- Register RTree: GPIOC_IDR -----------------------------------
// SVD Line: 1989
// SFDITEM_REG__GPIOC_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000810) GPIO port input data register
// ( (unsigned int)((GPIOC_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// - SFDITEM_FIELD__GPIOC_IDR_ID1
//
//
// ---------------------------- Register Item Address: GPIOC_ODR --------------------------------
// SVD Line: 2008
unsigned int GPIOC_ODR __AT (0x50000814);
// -------------------------------- Field Item: GPIOC_ODR_OD0 -----------------------------------
// SVD Line: 2014
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD1 -----------------------------------
// SVD Line: 2019
// - SFDITEM_FIELD__GPIOC_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD1
//
//
//
// -------------------------------- Register RTree: GPIOC_ODR -----------------------------------
// SVD Line: 2008
// SFDITEM_REG__GPIOC_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000814) GPIO port output data register
// ( (unsigned int)((GPIOC_ODR >> 0) & 0xFFFFFFFF), ((GPIOC_ODR = (GPIOC_ODR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// - SFDITEM_FIELD__GPIOC_ODR_OD1
//
//
// ---------------------------- Register Item Address: GPIOC_BSRR -------------------------------
// SVD Line: 2026
unsigned int GPIOC_BSRR __AT (0x50000818);
// ------------------------------- Field Item: GPIOC_BSRR_BS0 -----------------------------------
// SVD Line: 2033
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS1 -----------------------------------
// SVD Line: 2038
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR0 -----------------------------------
// SVD Line: 2043
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR1 -----------------------------------
// SVD Line: 2048
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR1
//
//
//
// ------------------------------- Register RTree: GPIOC_BSRR -----------------------------------
// SVD Line: 2026
// SFDITEM_REG__GPIOC_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000818) GPIO port bit set/reset register
// ( (unsigned int)((GPIOC_BSRR >> 0) & 0xFFFFFFFF), ((GPIOC_BSRR = (GPIOC_BSRR & ~(0x30003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30003) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
//
//
// ---------------------------- Register Item Address: GPIOC_LCKR -------------------------------
// SVD Line: 2055
unsigned int GPIOC_LCKR __AT (0x5000081C);
// ------------------------------- Field Item: GPIOC_LCKR_LCK0 ----------------------------------
// SVD Line: 2061
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK1 ----------------------------------
// SVD Line: 2066
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCKK ----------------------------------
// SVD Line: 2071
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOC_LCKR -----------------------------------
// SVD Line: 2055
// SFDITEM_REG__GPIOC_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000081C) GPIO port configuration lock register
// ( (unsigned int)((GPIOC_LCKR >> 0) & 0xFFFFFFFF), ((GPIOC_LCKR = (GPIOC_LCKR & ~(0x10003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x10003) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOC_AFRL -------------------------------
// SVD Line: 2078
unsigned int GPIOC_AFRL __AT (0x50000820);
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL0 ---------------------------------
// SVD Line: 2084
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 0) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL1 ---------------------------------
// SVD Line: 2089
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 4) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_AFRL -----------------------------------
// SVD Line: 2078
// SFDITEM_REG__GPIOC_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000820) GPIO alternate function low register
// ( (unsigned int)((GPIOC_AFRL >> 0) & 0xFFFFFFFF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
//
//
// ---------------------------- Register Item Address: GPIOC_BRR --------------------------------
// SVD Line: 2096
unsigned int GPIOC_BRR __AT (0x50000828);
// -------------------------------- Field Item: GPIOC_BRR_BR0 -----------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR1 -----------------------------------
// SVD Line: 2108
// - SFDITEM_FIELD__GPIOC_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR1
//
//
//
// -------------------------------- Register RTree: GPIOC_BRR -----------------------------------
// SVD Line: 2096
// SFDITEM_REG__GPIOC_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000828) port bit reset register
// ( (unsigned int)((GPIOC_BRR >> 0) & 0xFFFFFFFF), ((GPIOC_BRR = (GPIOC_BRR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// - SFDITEM_FIELD__GPIOC_BRR_BR1
//
//
// --------------------------------- Peripheral View: GPIOC -------------------------------------
// SVD Line: 1903
// GPIOC
// GPIOC
// - SFDITEM_REG__GPIOC_MODER
// - SFDITEM_REG__GPIOC_OTYPER
// - SFDITEM_REG__GPIOC_OSPEEDR
// - SFDITEM_REG__GPIOC_PUPDR
// - SFDITEM_REG__GPIOC_IDR
// - SFDITEM_REG__GPIOC_ODR
// - SFDITEM_REG__GPIOC_BSRR
// - SFDITEM_REG__GPIOC_LCKR
// - SFDITEM_REG__GPIOC_AFRL
// - SFDITEM_REG__GPIOC_BRR
//
//
// ----------------------------- Register Item Address: I2C_CR1 ---------------------------------
// SVD Line: 2133
unsigned int I2C_CR1 __AT (0x40005400);
// --------------------------------- Field Item: I2C_CR1_PE -------------------------------------
// SVD Line: 2139
// - SFDITEM_FIELD__I2C_CR1_PE
// PE
//
// [Bit 0] RW (@ 0x40005400) Peripheral enable
//
// ( (unsigned int) I2C_CR1 )
// PE
//
//
//
// -------------------------------- Field Item: I2C_CR1_ENGC ------------------------------------
// SVD Line: 2144
// - SFDITEM_FIELD__I2C_CR1_ENGC
// ENGC
//
// [Bit 6] RW (@ 0x40005400) General call enable
//
// ( (unsigned int) I2C_CR1 )
// ENGC
//
//
//
// ------------------------------ Field Item: I2C_CR1_NOSTRETCH ---------------------------------
// SVD Line: 2149
// - SFDITEM_FIELD__I2C_CR1_NOSTRETCH
// NOSTRETCH
//
// [Bit 7] RW (@ 0x40005400) Clock stretching disable (Slavemode)
//
// ( (unsigned int) I2C_CR1 )
// NOSTRETCH
//
//
//
// -------------------------------- Field Item: I2C_CR1_START -----------------------------------
// SVD Line: 2154
// - SFDITEM_FIELD__I2C_CR1_START
// START
//
// [Bit 8] RW (@ 0x40005400) Start generation
//
// ( (unsigned int) I2C_CR1 )
// START
//
//
//
// -------------------------------- Field Item: I2C_CR1_STOP ------------------------------------
// SVD Line: 2159
// - SFDITEM_FIELD__I2C_CR1_STOP
// STOP
//
// [Bit 9] RW (@ 0x40005400) Stop generation
//
// ( (unsigned int) I2C_CR1 )
// STOP
//
//
//
// --------------------------------- Field Item: I2C_CR1_ACK ------------------------------------
// SVD Line: 2164
// - SFDITEM_FIELD__I2C_CR1_ACK
// ACK
//
// [Bit 10] RW (@ 0x40005400) Acknowledge enable
//
// ( (unsigned int) I2C_CR1 )
// ACK
//
//
//
// --------------------------------- Field Item: I2C_CR1_POS ------------------------------------
// SVD Line: 2169
// - SFDITEM_FIELD__I2C_CR1_POS
// POS
//
// [Bit 11] RW (@ 0x40005400) Acknowledge/PEC Position (for datareception)
//
// ( (unsigned int) I2C_CR1 )
// POS
//
//
//
// -------------------------------- Field Item: I2C_CR1_SWRST -----------------------------------
// SVD Line: 2174
// - SFDITEM_FIELD__I2C_CR1_SWRST
// SWRST
//
// [Bit 15] RW (@ 0x40005400) Software reset
//
// ( (unsigned int) I2C_CR1 )
// SWRST
//
//
//
// --------------------------------- Register RTree: I2C_CR1 ------------------------------------
// SVD Line: 2133
// SFDITEM_REG__I2C_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40005400) Control register 1
// ( (unsigned int)((I2C_CR1 >> 0) & 0xFFFFFFFF), ((I2C_CR1 = (I2C_CR1 & ~(0x8FC1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8FC1) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CR1_PE
// - SFDITEM_FIELD__I2C_CR1_ENGC
// - SFDITEM_FIELD__I2C_CR1_NOSTRETCH
// - SFDITEM_FIELD__I2C_CR1_START
// - SFDITEM_FIELD__I2C_CR1_STOP
// - SFDITEM_FIELD__I2C_CR1_ACK
// - SFDITEM_FIELD__I2C_CR1_POS
// - SFDITEM_FIELD__I2C_CR1_SWRST
//
//
// ----------------------------- Register Item Address: I2C_CR2 ---------------------------------
// SVD Line: 2181
unsigned int I2C_CR2 __AT (0x40005404);
// -------------------------------- Field Item: I2C_CR2_FREQ ------------------------------------
// SVD Line: 2187
// - SFDITEM_FIELD__I2C_CR2_FREQ
// FREQ
//
// [Bits 5..0] RW (@ 0x40005404) Peripheral clock frequency
//
// ( (unsigned char)((I2C_CR2 >> 0) & 0x3F), ((I2C_CR2 = (I2C_CR2 & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITERREN ----------------------------------
// SVD Line: 2192
// - SFDITEM_FIELD__I2C_CR2_ITERREN
// ITERREN
//
// [Bit 8] RW (@ 0x40005404) Error interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITERREN
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITEVTEN ----------------------------------
// SVD Line: 2197
// - SFDITEM_FIELD__I2C_CR2_ITEVTEN
// ITEVTEN
//
// [Bit 9] RW (@ 0x40005404) Event interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITEVTEN
//
//
//
// ------------------------------- Field Item: I2C_CR2_ITBUFEN ----------------------------------
// SVD Line: 2202
// - SFDITEM_FIELD__I2C_CR2_ITBUFEN
// ITBUFEN
//
// [Bit 10] RW (@ 0x40005404) Buffer interrupt enable
//
// ( (unsigned int) I2C_CR2 )
// ITBUFEN
//
//
//
// --------------------------------- Register RTree: I2C_CR2 ------------------------------------
// SVD Line: 2181
// SFDITEM_REG__I2C_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40005404) Control register 2
// ( (unsigned int)((I2C_CR2 >> 0) & 0xFFFFFFFF), ((I2C_CR2 = (I2C_CR2 & ~(0x73FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x73F) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CR2_FREQ
// - SFDITEM_FIELD__I2C_CR2_ITERREN
// - SFDITEM_FIELD__I2C_CR2_ITEVTEN
// - SFDITEM_FIELD__I2C_CR2_ITBUFEN
//
//
// ----------------------------- Register Item Address: I2C_OAR1 --------------------------------
// SVD Line: 2209
unsigned int I2C_OAR1 __AT (0x40005408);
// -------------------------------- Field Item: I2C_OAR1_ADD ------------------------------------
// SVD Line: 2215
// - SFDITEM_FIELD__I2C_OAR1_ADD
// ADD
//
// [Bits 7..1] RW (@ 0x40005408) Interface address
//
// ( (unsigned char)((I2C_OAR1 >> 1) & 0x7F), ((I2C_OAR1 = (I2C_OAR1 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C_OAR1 ------------------------------------
// SVD Line: 2209
// SFDITEM_REG__I2C_OAR1
// OAR1
//
// [Bits 31..0] RW (@ 0x40005408) Own address register 1
// ( (unsigned int)((I2C_OAR1 >> 0) & 0xFFFFFFFF), ((I2C_OAR1 = (I2C_OAR1 & ~(0xFEUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFE) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_OAR1_ADD
//
//
// ------------------------------ Register Item Address: I2C_DR ---------------------------------
// SVD Line: 2222
unsigned int I2C_DR __AT (0x40005410);
// ---------------------------------- Field Item: I2C_DR_DR -------------------------------------
// SVD Line: 2228
// - SFDITEM_FIELD__I2C_DR_DR
// DR
//
// [Bits 7..0] RW (@ 0x40005410) 8-bit data register
//
// ( (unsigned char)((I2C_DR >> 0) & 0xFF), ((I2C_DR = (I2C_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: I2C_DR -------------------------------------
// SVD Line: 2222
// SFDITEM_REG__I2C_DR
// DR
//
// [Bits 31..0] RW (@ 0x40005410) Data register
// ( (unsigned int)((I2C_DR >> 0) & 0xFFFFFFFF), ((I2C_DR = (I2C_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_DR_DR
//
//
// ----------------------------- Register Item Address: I2C_SR1 ---------------------------------
// SVD Line: 2235
unsigned int I2C_SR1 __AT (0x40005414);
// --------------------------------- Field Item: I2C_SR1_SB -------------------------------------
// SVD Line: 2241
// - SFDITEM_FIELD__I2C_SR1_SB
// SB
//
// [Bit 0] RO (@ 0x40005414) Start bit (Master mode)
//
// ( (unsigned int) I2C_SR1 )
// SB
//
//
//
// -------------------------------- Field Item: I2C_SR1_ADDR ------------------------------------
// SVD Line: 2247
// - SFDITEM_FIELD__I2C_SR1_ADDR
// ADDR
//
// [Bit 1] RO (@ 0x40005414) Address sent (master mode)/matched(slave mode)
//
// ( (unsigned int) I2C_SR1 )
// ADDR
//
//
//
// --------------------------------- Field Item: I2C_SR1_BTF ------------------------------------
// SVD Line: 2253
// - SFDITEM_FIELD__I2C_SR1_BTF
// BTF
//
// [Bit 2] RO (@ 0x40005414) Byte transfer finished
//
// ( (unsigned int) I2C_SR1 )
// BTF
//
//
//
// -------------------------------- Field Item: I2C_SR1_STOPF -----------------------------------
// SVD Line: 2259
// - SFDITEM_FIELD__I2C_SR1_STOPF
// STOPF
//
// [Bit 4] RO (@ 0x40005414) Stop detection (slavemode)
//
// ( (unsigned int) I2C_SR1 )
// STOPF
//
//
//
// -------------------------------- Field Item: I2C_SR1_RxNE ------------------------------------
// SVD Line: 2265
// - SFDITEM_FIELD__I2C_SR1_RxNE
// RxNE
//
// [Bit 6] RO (@ 0x40005414) Data register not empty(receivers)
//
// ( (unsigned int) I2C_SR1 )
// RxNE
//
//
//
// --------------------------------- Field Item: I2C_SR1_TxE ------------------------------------
// SVD Line: 2271
// - SFDITEM_FIELD__I2C_SR1_TxE
// TxE
//
// [Bit 7] RO (@ 0x40005414) Data register empty(transmitters)
//
// ( (unsigned int) I2C_SR1 )
// TxE
//
//
//
// -------------------------------- Field Item: I2C_SR1_BERR ------------------------------------
// SVD Line: 2277
// - SFDITEM_FIELD__I2C_SR1_BERR
// BERR
//
// [Bit 8] RW (@ 0x40005414) Bus error
//
// ( (unsigned int) I2C_SR1 )
// BERR
//
//
//
// -------------------------------- Field Item: I2C_SR1_ARLO ------------------------------------
// SVD Line: 2282
// - SFDITEM_FIELD__I2C_SR1_ARLO
// ARLO
//
// [Bit 9] RW (@ 0x40005414) Arbitration lost (mastermode)
//
// ( (unsigned int) I2C_SR1 )
// ARLO
//
//
//
// --------------------------------- Field Item: I2C_SR1_AF -------------------------------------
// SVD Line: 2287
// - SFDITEM_FIELD__I2C_SR1_AF
// AF
//
// [Bit 10] RW (@ 0x40005414) Acknowledge failure
//
// ( (unsigned int) I2C_SR1 )
// AF
//
//
//
// --------------------------------- Field Item: I2C_SR1_OVR ------------------------------------
// SVD Line: 2292
// - SFDITEM_FIELD__I2C_SR1_OVR
// OVR
//
// [Bit 11] RW (@ 0x40005414) Overrun/Underrun
//
// ( (unsigned int) I2C_SR1 )
// OVR
//
//
//
// --------------------------------- Register RTree: I2C_SR1 ------------------------------------
// SVD Line: 2235
// SFDITEM_REG__I2C_SR1
// SR1
//
// [Bits 31..0] RW (@ 0x40005414) Status register 1
// ( (unsigned int)((I2C_SR1 >> 0) & 0xFFFFFFFF), ((I2C_SR1 = (I2C_SR1 & ~(0xF00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF00) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_SR1_SB
// - SFDITEM_FIELD__I2C_SR1_ADDR
// - SFDITEM_FIELD__I2C_SR1_BTF
// - SFDITEM_FIELD__I2C_SR1_STOPF
// - SFDITEM_FIELD__I2C_SR1_RxNE
// - SFDITEM_FIELD__I2C_SR1_TxE
// - SFDITEM_FIELD__I2C_SR1_BERR
// - SFDITEM_FIELD__I2C_SR1_ARLO
// - SFDITEM_FIELD__I2C_SR1_AF
// - SFDITEM_FIELD__I2C_SR1_OVR
//
//
// ----------------------------- Register Item Address: I2C_SR2 ---------------------------------
// SVD Line: 2299
unsigned int I2C_SR2 __AT (0x40005418);
// --------------------------------- Field Item: I2C_SR2_MSL ------------------------------------
// SVD Line: 2306
// - SFDITEM_FIELD__I2C_SR2_MSL
// MSL
//
// [Bit 0] RO (@ 0x40005418) Master/slave
//
// ( (unsigned int) I2C_SR2 )
// MSL
//
//
//
// -------------------------------- Field Item: I2C_SR2_BUSY ------------------------------------
// SVD Line: 2311
// - SFDITEM_FIELD__I2C_SR2_BUSY
// BUSY
//
// [Bit 1] RO (@ 0x40005418) Bus busy
//
// ( (unsigned int) I2C_SR2 )
// BUSY
//
//
//
// --------------------------------- Field Item: I2C_SR2_TRA ------------------------------------
// SVD Line: 2316
// - SFDITEM_FIELD__I2C_SR2_TRA
// TRA
//
// [Bit 2] RO (@ 0x40005418) Transmitter/receiver
//
// ( (unsigned int) I2C_SR2 )
// TRA
//
//
//
// ------------------------------- Field Item: I2C_SR2_GENCALL ----------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__I2C_SR2_GENCALL
// GENCALL
//
// [Bit 4] RO (@ 0x40005418) General call address (Slavemode)
//
// ( (unsigned int) I2C_SR2 )
// GENCALL
//
//
//
// --------------------------------- Register RTree: I2C_SR2 ------------------------------------
// SVD Line: 2299
// SFDITEM_REG__I2C_SR2
// SR2
//
// [Bits 31..0] RO (@ 0x40005418) Status register 2
// ( (unsigned int)((I2C_SR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__I2C_SR2_MSL
// - SFDITEM_FIELD__I2C_SR2_BUSY
// - SFDITEM_FIELD__I2C_SR2_TRA
// - SFDITEM_FIELD__I2C_SR2_GENCALL
//
//
// ----------------------------- Register Item Address: I2C_CCR ---------------------------------
// SVD Line: 2328
unsigned int I2C_CCR __AT (0x4000541C);
// --------------------------------- Field Item: I2C_CCR_CCR ------------------------------------
// SVD Line: 2334
// - SFDITEM_FIELD__I2C_CCR_CCR
// CCR
//
// [Bits 11..0] RW (@ 0x4000541C) Clock control register in Fast/Standardmode (Master mode)
//
// ( (unsigned short)((I2C_CCR >> 0) & 0xFFF), ((I2C_CCR = (I2C_CCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: I2C_CCR_DUTY ------------------------------------
// SVD Line: 2339
// - SFDITEM_FIELD__I2C_CCR_DUTY
// DUTY
//
// [Bit 14] RW (@ 0x4000541C) Fast mode duty cycle
//
// ( (unsigned int) I2C_CCR )
// DUTY
//
//
//
// --------------------------------- Field Item: I2C_CCR_F_S ------------------------------------
// SVD Line: 2344
// - SFDITEM_FIELD__I2C_CCR_F_S
// F_S
//
// [Bit 15] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C_CCR )
// F_S
//
//
//
// --------------------------------- Register RTree: I2C_CCR ------------------------------------
// SVD Line: 2328
// SFDITEM_REG__I2C_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x4000541C) Clock control register
// ( (unsigned int)((I2C_CCR >> 0) & 0xFFFFFFFF), ((I2C_CCR = (I2C_CCR & ~(0xCFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCFFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_CCR_CCR
// - SFDITEM_FIELD__I2C_CCR_DUTY
// - SFDITEM_FIELD__I2C_CCR_F_S
//
//
// ---------------------------- Register Item Address: I2C_TRISE --------------------------------
// SVD Line: 2351
unsigned int I2C_TRISE __AT (0x40005420);
// ------------------------------- Field Item: I2C_TRISE_TRISE ----------------------------------
// SVD Line: 2358
// - SFDITEM_FIELD__I2C_TRISE_TRISE
// TRISE
//
// [Bits 5..0] RW (@ 0x40005420) Maximum rise time in Fast/Standard mode(Master mode)
//
// ( (unsigned char)((I2C_TRISE >> 0) & 0x3F), ((I2C_TRISE = (I2C_TRISE & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C_TRISE -----------------------------------
// SVD Line: 2351
// SFDITEM_REG__I2C_TRISE
// TRISE
//
// [Bits 31..0] RW (@ 0x40005420) TRISE register
// ( (unsigned int)((I2C_TRISE >> 0) & 0xFFFFFFFF), ((I2C_TRISE = (I2C_TRISE & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__I2C_TRISE_TRISE
//
//
// ---------------------------------- Peripheral View: I2C --------------------------------------
// SVD Line: 2117
// I2C
// I2C
// - SFDITEM_REG__I2C_CR1
// - SFDITEM_REG__I2C_CR2
// - SFDITEM_REG__I2C_OAR1
// - SFDITEM_REG__I2C_DR
// - SFDITEM_REG__I2C_SR1
// - SFDITEM_REG__I2C_SR2
// - SFDITEM_REG__I2C_CCR
// - SFDITEM_REG__I2C_TRISE
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 2378
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 2385
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] WO (@ 0x40003000) Key value
//
// ( (unsigned short)((IWDG_KR >> 0) & 0x0), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 2378
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] WO (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 2392
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 2398
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) Prescaler divider
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 2392
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 2405
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 2412
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) Watchdog counter reload value
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 2405
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 2419
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 2426
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 2431
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 2419
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RO (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 2367
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM1_ISR -------------------------------
// SVD Line: 2456
unsigned int LPTIM1_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM1_ISR_ARRM ----------------------------------
// SVD Line: 2463
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM1_ISR )
// ARRM
//
//
//
// ------------------------------ Field Item: LPTIM1_ISR_ARROK ----------------------------------
// SVD Line: 2468
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload match update OK
//
// ( (unsigned int) LPTIM1_ISR )
// ARROK
//
//
//
// ------------------------------- Register RTree: LPTIM1_ISR -----------------------------------
// SVD Line: 2456
// SFDITEM_REG__LPTIM1_ISR
// ISR
//
// [Bits 31..0] RO (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM1_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM1_ICR -------------------------------
// SVD Line: 2475
unsigned int LPTIM1_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM1_ICR_ARRMCF ---------------------------------
// SVD Line: 2482
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] WO (@ 0x40007C04) Autoreload match Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARRMCF
//
//
//
// ----------------------------- Field Item: LPTIM1_ICR_ARROKCF ---------------------------------
// SVD Line: 2487
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] WO (@ 0x40007C04) Autoreload match update OK Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARROKCF
//
//
//
// ------------------------------- Register RTree: LPTIM1_ICR -----------------------------------
// SVD Line: 2475
// SFDITEM_REG__LPTIM1_ICR
// ICR
//
// [Bits 31..0] WO (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM1_ICR >> 0) & 0xFFFFFFFF), ((LPTIM1_ICR = (LPTIM1_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM1_IER -------------------------------
// SVD Line: 2494
unsigned int LPTIM1_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM1_IER_ARRMIE ---------------------------------
// SVD Line: 2500
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload matchInterrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARRMIE
//
//
//
// ----------------------------- Field Item: LPTIM1_IER_ARROKIE ---------------------------------
// SVD Line: 2505
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload match update OK Interrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARROKIE
//
//
//
// ------------------------------- Register RTree: LPTIM1_IER -----------------------------------
// SVD Line: 2494
// SFDITEM_REG__LPTIM1_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM1_IER >> 0) & 0xFFFFFFFF), ((LPTIM1_IER = (LPTIM1_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
//
//
// --------------------------- Register Item Address: LPTIM1_CFGR -------------------------------
// SVD Line: 2512
unsigned int LPTIM1_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM1_CFGR_PRESC ---------------------------------
// SVD Line: 2518
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM1_CFGR >> 9) & 0x7), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM1_CFGR_PRELOAD --------------------------------
// SVD Line: 2523
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM1_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM1_CFGR ----------------------------------
// SVD Line: 2512
// SFDITEM_REG__LPTIM1_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM1_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
//
//
// ---------------------------- Register Item Address: LPTIM1_CR --------------------------------
// SVD Line: 2530
unsigned int LPTIM1_CR __AT (0x40007C10);
// ------------------------------ Field Item: LPTIM1_CR_ENABLE ----------------------------------
// SVD Line: 2536
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM Enable
//
// ( (unsigned int) LPTIM1_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_SNGSTRT ---------------------------------
// SVD Line: 2541
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in single mode
//
// ( (unsigned int) LPTIM1_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_CNTSTRT ---------------------------------
// SVD Line: 2546
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) CNTSTRT
//
// ( (unsigned int) LPTIM1_CR )
// CNTSTRT
//
//
//
// ----------------------------- Field Item: LPTIM1_CR_COUNTRST ---------------------------------
// SVD Line: 2551
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) Reset counter
//
// ( (unsigned int) LPTIM1_CR )
// COUNTRST
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_RSTARE ----------------------------------
// SVD Line: 2556
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM1_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM1_CR -----------------------------------
// SVD Line: 2530
// SFDITEM_REG__LPTIM1_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM1_CR >> 0) & 0xFFFFFFFF), ((LPTIM1_CR = (LPTIM1_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM1_ARR -------------------------------
// SVD Line: 2563
unsigned int LPTIM1_ARR __AT (0x40007C18);
// ------------------------------- Field Item: LPTIM1_ARR_ARR -----------------------------------
// SVD Line: 2570
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM1_ARR >> 0) & 0xFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPTIM1_ARR -----------------------------------
// SVD Line: 2563
// SFDITEM_REG__LPTIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM1_ARR >> 0) & 0xFFFFFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM1_CNT -------------------------------
// SVD Line: 2577
unsigned int LPTIM1_CNT __AT (0x40007C1C);
// ------------------------------- Field Item: LPTIM1_CNT_CNT -----------------------------------
// SVD Line: 2584
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM1_CNT >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: LPTIM1_CNT -----------------------------------
// SVD Line: 2577
// SFDITEM_REG__LPTIM1_CNT
// CNT
//
// [Bits 31..0] RO (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM1_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM1 ------------------------------------
// SVD Line: 2440
// LPTIM1
// LPTIM1
// - SFDITEM_REG__LPTIM1_ISR
// - SFDITEM_REG__LPTIM1_ICR
// - SFDITEM_REG__LPTIM1_IER
// - SFDITEM_REG__LPTIM1_CFGR
// - SFDITEM_REG__LPTIM1_CR
// - SFDITEM_REG__LPTIM1_ARR
// - SFDITEM_REG__LPTIM1_CNT
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 2604
unsigned int PWR_CR1 __AT (0x40007000);
// ------------------------------- Field Item: PWR_CR1_BIAS_CR ----------------------------------
// SVD Line: 2611
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR
// BIAS_CR
//
// [Bits 3..0] RW (@ 0x40007000) MR Bias current
//
// ( (unsigned char)((PWR_CR1 >> 0) & 0xF), ((PWR_CR1 = (PWR_CR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_BIAS_CR_SEL --------------------------------
// SVD Line: 2616
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR_SEL
// BIAS_CR_SEL
//
// [Bit 4] RW (@ 0x40007000) MR Bias current selection
//
// ( (unsigned int) PWR_CR1 )
// BIAS_CR_SEL
//
//
//
// --------------------------------- Field Item: PWR_CR1_DBP ------------------------------------
// SVD Line: 2621
// - SFDITEM_FIELD__PWR_CR1_DBP
// DBP
//
// [Bit 7] RW (@ 0x40007000) Disable backup domain write protection
//
// ( (unsigned int) PWR_CR1 )
// DBP
//
//
//
// --------------------------------- Field Item: PWR_CR1_VOS ------------------------------------
// SVD Line: 2626
// - SFDITEM_FIELD__PWR_CR1_VOS
// VOS
//
// [Bits 9..8] RW (@ 0x40007000) Voltage scaling range selection
//
// ( (unsigned char)((PWR_CR1 >> 8) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_MRRDY_TIME ---------------------------------
// SVD Line: 2631
// - SFDITEM_FIELD__PWR_CR1_MRRDY_TIME
// MRRDY_TIME
//
// [Bits 11..10] RW (@ 0x40007000) Time selection wakeup from LP to VR
//
// ( (unsigned char)((PWR_CR1 >> 10) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 2636
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) Flash wait time after wakeup from the stop mode
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------------- Field Item: PWR_CR1_LPR ------------------------------------
// SVD Line: 2641
// - SFDITEM_FIELD__PWR_CR1_LPR
// LPR
//
// [Bits 15..14] RW (@ 0x40007000) Low-power run
//
// ( (unsigned char)((PWR_CR1 >> 14) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: PWR_CR1_SRAM_RETV ---------------------------------
// SVD Line: 2646
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV
// SRAM_RETV
//
// [Bits 18..16] RW (@ 0x40007000) SRAM retention voltage control
//
// ( (unsigned char)((PWR_CR1 >> 16) & 0x7), ((PWR_CR1 = (PWR_CR1 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_HSION_CTRL ---------------------------------
// SVD Line: 2651
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
// HSION_CTRL
//
// [Bit 19] RW (@ 0x40007000) HSI open time control
//
// ( (unsigned int) PWR_CR1 )
// HSION_CTRL
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 2604
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0xFFF9FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF9F) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR_SEL
// - SFDITEM_FIELD__PWR_CR1_DBP
// - SFDITEM_FIELD__PWR_CR1_VOS
// - SFDITEM_FIELD__PWR_CR1_MRRDY_TIME
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_LPR
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
//
//
// ----------------------------- Register Item Address: PWR_CR2 ---------------------------------
// SVD Line: 2658
unsigned int PWR_CR2 __AT (0x40007004);
// -------------------------------- Field Item: PWR_CR2_FLTEN -----------------------------------
// SVD Line: 2665
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// FLTEN
//
// [Bit 8] RW (@ 0x40007004) Digital filter enable
//
// ( (unsigned int) PWR_CR2 )
// FLTEN
//
//
//
// ------------------------------ Field Item: PWR_CR2_FLT_TIME ----------------------------------
// SVD Line: 2670
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
// FLT_TIME
//
// [Bits 11..9] RW (@ 0x40007004) Digital filter time configuration
//
// ( (unsigned char)((PWR_CR2 >> 9) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWR_CR2 ------------------------------------
// SVD Line: 2658
// SFDITEM_REG__PWR_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40007004) Power control register 2
// ( (unsigned int)((PWR_CR2 >> 0) & 0xFFFFFFFF), ((PWR_CR2 = (PWR_CR2 & ~(0xF00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF00) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 2593
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
// - SFDITEM_REG__PWR_CR2
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 2695
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 2702
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI16 clock enable
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 2707
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RW (@ 0x40021000) HSI16 clock ready flag
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 2712
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI16 clock division factor
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEEN ------------------------------------
// SVD Line: 2717
// - SFDITEM_FIELD__RCC_CR_HSEEN
// HSEEN
//
// [Bit 18] RW (@ 0x40021000) HSEEN
//
// ( (unsigned int) RCC_CR )
// HSEEN
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 2695
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0x43D00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x43D00) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// - SFDITEM_FIELD__RCC_CR_HSEEN
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 2723
unsigned int RCC_ICSCR __AT (0x40021004);
// ----------------------------- Field Item: RCC_ICSCR_HSI_TRIM ---------------------------------
// SVD Line: 2730
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// HSI_TRIM
//
// [Bits 12..0] RW (@ 0x40021004) HSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0x1FFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 2735
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bits 15..13] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 13) & 0x7), ((RCC_ICSCR = (RCC_ICSCR & ~(0x7UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 13 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 2740
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 24..16] RW (@ 0x40021004) LSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 16) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ICSCR_LSI_STARTUP -------------------------------
// SVD Line: 2745
// - SFDITEM_FIELD__RCC_ICSCR_LSI_STARTUP
// LSI_STARTUP
//
// [Bits 27..26] RW (@ 0x40021004) LSI startup time
//
// ( (unsigned char)((RCC_ICSCR >> 26) & 0x3), ((RCC_ICSCR = (RCC_ICSCR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 2723
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibration register
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xDFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_LSI_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 2752
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 2758
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock switch
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 2763
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RO (@ 0x40021008) System clock switch status
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7) )
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 2769
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) AHB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 2774
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 2779
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 26..24] RW (@ 0x40021008) Microcontroller clock output
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 2784
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 30..28] RW (@ 0x40021008) Microcontroller clock output prescaler
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 2752
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0x77007F07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77007F07) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 2791
unsigned int RCC_ECSCR __AT (0x40021010);
// ---------------------------- Field Item: RCC_ECSCR_LSE_DRIVER --------------------------------
// SVD Line: 2797
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// LSE_DRIVER
//
// [Bits 17..16] RW (@ 0x40021010) desc LSE_DRIVER
//
// ( (unsigned char)((RCC_ECSCR >> 16) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_STARTUP -------------------------------
// SVD Line: 2802
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
// LSE_STARTUP
//
// [Bits 21..20] RW (@ 0x40021010) desc LSE_STARTUP
//
// ( (unsigned char)((RCC_ECSCR >> 20) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 2791
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x330000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x330000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 2809
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 2815
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_LSERDYIE ---------------------------------
// SVD Line: 2820
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// LSERDYIE
//
// [Bit 1] RW (@ 0x40021018) LSE ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// LSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 2825
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 2809
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enable register
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 2832
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 2839
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSERDYF ----------------------------------
// SVD Line: 2844
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// LSERDYF
//
// [Bit 2] RO (@ 0x4002101C) LSE ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 2849
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSECSSF ----------------------------------
// SVD Line: 2854
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
// LSECSSF
//
// [Bit 9] RO (@ 0x4002101C) LSE clock secure system interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSECSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 2832
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RO (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 2861
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 2868
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] WO (@ 0x40021020) LSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSERDYC ----------------------------------
// SVD Line: 2873
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// LSERDYC
//
// [Bit 1] WO (@ 0x40021020) LSE ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// LSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 2878
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] WO (@ 0x40021020) HSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSECSSC ----------------------------------
// SVD Line: 2883
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
// LSECSSC
//
// [Bit 9] WO (@ 0x40021020) LSE clock secure system interrupt flag clear
//
// ( (unsigned int) RCC_CICR )
// LSECSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 2861
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] WO (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x20BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x20B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 2890
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 2896
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O port A reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 2901
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O port B reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOCRST --------------------------------
// SVD Line: 2906
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
// GPIOCRST
//
// [Bit 2] RW (@ 0x40021024) I/O port C reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOCRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 2890
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
//
//
// --------------------------- Register Item Address: RCC_AHBRSTR -------------------------------
// SVD Line: 2913
unsigned int RCC_AHBRSTR __AT (0x40021028);
// ---------------------------- Field Item: RCC_AHBRSTR_FLASHRST --------------------------------
// SVD Line: 2919
// - SFDITEM_FIELD__RCC_AHBRSTR_FLASHRST
// FLASHRST
//
// [Bit 8] RW (@ 0x40021028) FLASH reset
//
// ( (unsigned int) RCC_AHBRSTR )
// FLASHRST
//
//
//
// ----------------------------- Field Item: RCC_AHBRSTR_CRCRST ---------------------------------
// SVD Line: 2924
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// CRCRST
//
// [Bit 12] RW (@ 0x40021028) CRC reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CRCRST
//
//
//
// ------------------------------- Register RTree: RCC_AHBRSTR ----------------------------------
// SVD Line: 2913
// SFDITEM_REG__RCC_AHBRSTR
// AHBRSTR
//
// [Bits 31..0] RW (@ 0x40021028) AHB peripheral reset register
// ( (unsigned int)((RCC_AHBRSTR >> 0) & 0xFFFFFFFF), ((RCC_AHBRSTR = (RCC_AHBRSTR & ~(0x1100UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1100) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBRSTR_FLASHRST
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 2931
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// ----------------------------- Field Item: RCC_APBRSTR1_I2CRST --------------------------------
// SVD Line: 2937
// - SFDITEM_FIELD__RCC_APBRSTR1_I2CRST
// I2CRST
//
// [Bit 21] RW (@ 0x4002102C) I2C reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// I2CRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 2942
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) Debug support reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 2947
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) Power interface reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_LPTIMRST -------------------------------
// SVD Line: 2952
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
// LPTIMRST
//
// [Bit 31] RW (@ 0x4002102C) Low Power Timer reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPTIMRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 2931
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APB peripheral reset register 1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0x98200000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98200000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_I2CRST
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 2959
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 2965
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) SYSCFG reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 2970
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) TIM1 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR2_USART1RST -------------------------------
// SVD Line: 2975
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// USART1RST
//
// [Bit 14] RW (@ 0x40021030) USART1 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// USART1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 2980
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) TIM14 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_ADCRST --------------------------------
// SVD Line: 2985
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// ADCRST
//
// [Bit 20] RW (@ 0x40021030) ADC reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// ADCRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 2959
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register 2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x10C801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x10C801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 2992
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 2998
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O port A clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 3003
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O port B clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOCEN ---------------------------------
// SVD Line: 3008
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
// GPIOCEN
//
// [Bit 2] RW (@ 0x40021034) I/O port C clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOCEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 2992
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 3015
unsigned int RCC_AHBENR __AT (0x40021038);
// ----------------------------- Field Item: RCC_AHBENR_FLASHEN ---------------------------------
// SVD Line: 3021
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// FLASHEN
//
// [Bit 8] RW (@ 0x40021038) Flash memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// FLASHEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_SRAMEN ---------------------------------
// SVD Line: 3026
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// SRAMEN
//
// [Bit 9] RW (@ 0x40021038) SRAM memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// SRAMEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_CRCEN ----------------------------------
// SVD Line: 3031
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// CRCEN
//
// [Bit 12] RW (@ 0x40021038) CRC clock enable
//
// ( (unsigned int) RCC_AHBENR )
// CRCEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 3015
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enable register
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x1300UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1300) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 3038
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ------------------------------ Field Item: RCC_APBENR1_I2CEN ---------------------------------
// SVD Line: 3044
// - SFDITEM_FIELD__RCC_APBENR1_I2CEN
// I2CEN
//
// [Bit 21] RW (@ 0x4002103C) I2C clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// I2CEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 3049
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) Debug support clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 3054
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) Power interface clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_LPTIMEN --------------------------------
// SVD Line: 3059
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
// LPTIMEN
//
// [Bit 31] RW (@ 0x4002103C) LPTIM clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// LPTIMEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 3038
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register 1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0x98200000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98200000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_I2CEN
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 3066
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 3072
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) SYSCFG and VREFBUF clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 3077
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) TIM1 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR2_USART1EN --------------------------------
// SVD Line: 3082
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// USART1EN
//
// [Bit 14] RW (@ 0x40021040) USART1 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// USART1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 3087
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_ADCEN ---------------------------------
// SVD Line: 3092
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// ADCEN
//
// [Bit 20] RW (@ 0x40021040) ADC clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// ADCEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 3066
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register 2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x10C801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x10C801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 3099
unsigned int RCC_CCIPR __AT (0x40021054);
// ----------------------------- Field Item: RCC_CCIPR_LPTIM1SEL --------------------------------
// SVD Line: 3105
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// LPTIM1SEL
//
// [Bits 19..18] RW (@ 0x40021054) LPTIM1 clock source selection
//
// ( (unsigned char)((RCC_CCIPR >> 18) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 3099
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configuration register
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xC0000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC0000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 3112
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_LSEON -----------------------------------
// SVD Line: 3118
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// LSEON
//
// [Bit 0] RW (@ 0x4002105C) LSE oscillator enable
//
// ( (unsigned int) RCC_BDCR )
// LSEON
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSERDY ----------------------------------
// SVD Line: 3123
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// LSERDY
//
// [Bit 1] RW (@ 0x4002105C) LSE oscillator ready
//
// ( (unsigned int) RCC_BDCR )
// LSERDY
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSEBYP ----------------------------------
// SVD Line: 3128
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// LSEBYP
//
// [Bit 2] RW (@ 0x4002105C) LSE oscillator bypass
//
// ( (unsigned int) RCC_BDCR )
// LSEBYP
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSON ---------------------------------
// SVD Line: 3133
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// LSECSSON
//
// [Bit 5] RW (@ 0x4002105C) LSE CSS enable
//
// ( (unsigned int) RCC_BDCR )
// LSECSSON
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSD ----------------------------------
// SVD Line: 3138
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// LSECSSD
//
// [Bit 6] RW (@ 0x4002105C) LSE CSS detect
//
// ( (unsigned int) RCC_BDCR )
// LSECSSD
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCOEN ----------------------------------
// SVD Line: 3143
// - SFDITEM_FIELD__RCC_BDCR_LSCOEN
// LSCOEN
//
// [Bit 24] RW (@ 0x4002105C) Low-speed clock output (LSCO) enable
//
// ( (unsigned int) RCC_BDCR )
// LSCOEN
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSCOSEL ----------------------------------
// SVD Line: 3148
// - SFDITEM_FIELD__RCC_BDCR_LSCOSEL
// LSCOSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock output selection
//
// ( (unsigned int) RCC_BDCR )
// LSCOSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 3112
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x3000067UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3000067) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// - SFDITEM_FIELD__RCC_BDCR_LSCOEN
// - SFDITEM_FIELD__RCC_BDCR_LSCOSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 3155
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 3161
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI oscillator enable
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 3166
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RW (@ 0x40021060) LSI oscillator ready
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// ---------------------------- Field Item: RCC_CSR_PINRST_FLTDIS -------------------------------
// SVD Line: 3171
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// PINRST_FLTDIS
//
// [Bit 8] RW (@ 0x40021060) desc PINRST_FLTDIS
//
// ( (unsigned int) RCC_CSR )
// PINRST_FLTDIS
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 3176
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Remove reset flags
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 3181
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RW (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 3186
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RW (@ 0x40021060) Pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PWRRSTF ----------------------------------
// SVD Line: 3191
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// PWRRSTF
//
// [Bit 27] RW (@ 0x40021060) BOR or POR/PDR flag
//
// ( (unsigned int) RCC_CSR )
// PWRRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 3196
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RW (@ 0x40021060) Software reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 3201
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RW (@ 0x40021060) Independent window watchdog reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 3155
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x3E800103UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3E800103) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 2679
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_AHBRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR1 ------------------------------
// SVD Line: 3221
unsigned int SYSCFG_CFGR1 __AT (0x40010000);
// ---------------------------- Field Item: SYSCFG_CFGR1_MEM_MODE -------------------------------
// SVD Line: 3227
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// MEM_MODE
//
// [Bits 1..0] RW (@ 0x40010000) Memory mapping selection bits
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 0) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_I2C_PA2_FMP ------------------------------
// SVD Line: 3232
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PA2_FMP
// I2C_PA2_FMP
//
// [Bit 16] RW (@ 0x40010000) desc I2C_PA2_FMP
//
// ( (unsigned int) SYSCFG_CFGR1 )
// I2C_PA2_FMP
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_I2C_PB3_FMP ------------------------------
// SVD Line: 3237
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB3_FMP
// I2C_PB3_FMP
//
// [Bit 17] RW (@ 0x40010000) desc I2C_PB3_FMP
//
// ( (unsigned int) SYSCFG_CFGR1 )
// I2C_PB3_FMP
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_I2C_PB4_FMP ------------------------------
// SVD Line: 3242
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB4_FMP
// I2C_PB4_FMP
//
// [Bit 18] RW (@ 0x40010000) desc I2C_PB4_FMP
//
// ( (unsigned int) SYSCFG_CFGR1 )
// I2C_PB4_FMP
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_I2C_PB6_FMP ------------------------------
// SVD Line: 3247
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB6_FMP
// I2C_PB6_FMP
//
// [Bit 19] RW (@ 0x40010000) desc I2C_PB6_FMP
//
// ( (unsigned int) SYSCFG_CFGR1 )
// I2C_PB6_FMP
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR1 ----------------------------------
// SVD Line: 3221
// SFDITEM_REG__SYSCFG_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x40010000) SYSCFG configuration register 1
// ( (unsigned int)((SYSCFG_CFGR1 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0xF0003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0003) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PA2_FMP
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB3_FMP
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB4_FMP
// - SFDITEM_FIELD__SYSCFG_CFGR1_I2C_PB6_FMP
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 3254
unsigned int SYSCFG_CFGR2 __AT (0x40010018);
// -------------------------- Field Item: SYSCFG_CFGR2_LOCKUP_LOCK ------------------------------
// SVD Line: 3260
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// LOCKUP_LOCK
//
// [Bit 0] RW (@ 0x40010018) Cortex-M0+ LOCKUP bit enable bit
//
// ( (unsigned int) SYSCFG_CFGR2 )
// LOCKUP_LOCK
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR2_ETR_SRC_TIM1 -----------------------------
// SVD Line: 3265
// - SFDITEM_FIELD__SYSCFG_CFGR2_ETR_SRC_TIM1
// ETR_SRC_TIM1
//
// [Bits 10..9] RW (@ 0x40010018) TIM1 ETR source selection
//
// ( (unsigned char)((SYSCFG_CFGR2 >> 9) & 0x3), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 3254
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010018) SYSCFG configuration register 2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x601UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x601) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_ETR_SRC_TIM1
//
//
// ------------------------- Register Item Address: SYSCFG_GPIO_ENS -----------------------------
// SVD Line: 3272
unsigned int SYSCFG_GPIO_ENS __AT (0x4001001C);
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PA_ENS -------------------------------
// SVD Line: 3277
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// PA_ENS
//
// [Bits 7..0] RW (@ 0x4001001C) desc PA_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 0) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PB_ENS -------------------------------
// SVD Line: 3282
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// PB_ENS
//
// [Bits 15..8] RW (@ 0x4001001C) desc PB_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 8) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PC_ENS -------------------------------
// SVD Line: 3287
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
// PC_ENS
//
// [Bits 17..16] RW (@ 0x4001001C) desc PC_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 16) & 0x3), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_GPIO_ENS --------------------------------
// SVD Line: 3272
// SFDITEM_REG__SYSCFG_GPIO_ENS
// GPIO_ENS
//
// [Bits 31..0] RW (@ 0x4001001C) desc GPIO_ENS
// ( (unsigned int)((SYSCFG_GPIO_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 3210
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR1
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_GPIO_ENS
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 3317
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 3323
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) desc CEN
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 3328
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) desc UDIS
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 3333
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) desc URS
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 3338
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) desc OPM
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 3343
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) desc DIR
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 3348
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) desc CMS
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 3353
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) desc ARPE
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 3358
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) desc CKD
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 3317
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) desc CR1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 3365
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 3371
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) desc CCPC
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 3376
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) desc CCUS
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_MMS ------------------------------------
// SVD Line: 3381
// - SFDITEM_FIELD__TIM1_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40012C04) desc MMS
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 3386
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) desc TI1S
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 3391
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) desc OIS1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 3396
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) desc OIS1N
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 3401
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) desc OIS2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 3406
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) desc OIS2N
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 3411
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) desc OIS3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 3416
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) desc OIS3N
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 3421
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) desc OIS4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 3365
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) desc CR2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7FF5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF5) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_MMS
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 3428
unsigned int TIM1_SMCR __AT (0x40012C08);
// -------------------------------- Field Item: TIM1_SMCR_SMS -----------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40012C08) desc SMS
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 3439
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) desc OCCS
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_TS ------------------------------------
// SVD Line: 3444
// - SFDITEM_FIELD__TIM1_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40012C08) desc TS
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 3449
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) desc MSM
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 3454
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) desc ETF
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 3459
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) desc ETPS
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 3464
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) desc ECE
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 3469
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) desc ETP
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 3428
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) desc SMCR
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 3476
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 3482
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) desc UIE
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 3487
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) desc CC1IE
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 3492
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) desc CC2IE
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 3497
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) desc CC3IE
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 3502
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) desc CC4IE
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 3507
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) desc COMIE
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 3512
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) desc TIE
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 3517
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) desc BIE
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 3476
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) desc DIER
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 3524
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 3530
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) desc UIF
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 3535
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) desc CC1IF
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 3540
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) desc CC2IF
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 3545
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) desc CC3IF
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 3550
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) desc CC4IF
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 3555
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) desc COMIF
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 3560
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) desc TIF
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 3565
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) desc BIF
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 3570
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) desc CC1OF
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 3575
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) desc CC2OF
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 3580
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) desc CC3OF
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 3585
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) desc CC4OF
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 3590
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40012C10) desc IC1IR
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 3595
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 17] RW (@ 0x40012C10) desc IC2IR
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 3600
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 18] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 3605
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 19] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 3610
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40012C10) desc IC1IF
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 3615
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 21] RW (@ 0x40012C10) desc IC2IF
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 3620
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 22] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 3625
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 23] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 3524
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) desc SR
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0xFF1EFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1EFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 3632
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 3639
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40012C14) desc UG
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 3645
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40012C14) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] WO (@ 0x40012C14) desc CC2G
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 3657
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] WO (@ 0x40012C14) desc CC3G
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 3663
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] WO (@ 0x40012C14) desc CC4G
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 3669
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40012C14) desc COMG
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 3675
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] WO (@ 0x40012C14) desc TG
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 3681
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40012C14) desc BG
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 3632
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40012C14) desc EGR
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_OUTPUT ----------------------------
// SVD Line: 3689
unsigned int TIM1_CCMR1_OUTPUT __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 3695
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 0) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 3700
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) desc OC1FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 3705
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) desc OC1PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M -------------------------------
// SVD Line: 3710
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40012C18) desc OC1M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 4) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 3715
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) desc OC1CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 3720
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 8) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 3725
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) desc OC2FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 3730
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) desc OC2PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M -------------------------------
// SVD Line: 3735
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40012C18) desc OC2M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 12) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 3740
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) desc OC2CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_OUTPUT -------------------------------
// SVD Line: 3689
// SFDITEM_REG__TIM1_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:OUTPUT
// ( (unsigned int)((TIM1_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_INPUT ----------------------------
// SVD Line: 3747
unsigned int TIM1_CCMR1_INPUT __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 3754
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 0) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 3759
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40012C18) desc IC1PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 2) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 3764
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) desc IC1F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 4) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 3769
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 8) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 3774
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) desc IC2PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 10) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 3779
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) desc IC2F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 12) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_INPUT --------------------------------
// SVD Line: 3747
// SFDITEM_REG__TIM1_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:INPUT
// ( (unsigned int)((TIM1_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_OUTPUT ----------------------------
// SVD Line: 3786
unsigned int TIM1_CCMR2_OUTPUT __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 3792
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 0) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 3797
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) desc OC3FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 3802
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) desc OC3PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M -------------------------------
// SVD Line: 3807
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x40012C1C) desc OC3M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 4) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 3812
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) desc OC3CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 3817
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 8) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 3822
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) desc OC4FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 3827
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) desc OC4PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M -------------------------------
// SVD Line: 3832
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x40012C1C) desc OC4M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 12) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 3837
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) desc OC4CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_OUTPUT -------------------------------
// SVD Line: 3786
// SFDITEM_REG__TIM1_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:OUTPUT
// ( (unsigned int)((TIM1_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_INPUT ----------------------------
// SVD Line: 3844
unsigned int TIM1_CCMR2_INPUT __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 3851
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 0) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 3856
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) desc IC3PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 2) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 3861
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) desc IC3F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 4) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 3866
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 8) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 3871
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) desc IC4PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 10) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 3876
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) desc IC4F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 12) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_INPUT --------------------------------
// SVD Line: 3844
// SFDITEM_REG__TIM1_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:INPUT
// ( (unsigned int)((TIM1_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 3883
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 3889
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) desc CC1E
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 3894
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) desc CC1P
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 3899
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) desc CC1NE
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 3904
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) desc CC1NP
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 3909
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) desc CC2E
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 3914
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) desc CC2P
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 3919
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) desc CC2NE
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 3924
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) desc CC2NP
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 3929
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) desc CC3E
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 3934
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) desc CC3P
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 3939
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) desc CC3NE
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 3944
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) desc CC3NP
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 3949
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) desc CC4E
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 3954
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) desc CC4P
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 3883
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) desc CCER
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 3961
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 3967
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) desc CNT
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 3961
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) desc CNT
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 3974
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 3980
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) desc PSC
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 3974
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) desc PSC
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 3987
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 3994
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) desc ARR
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 3987
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) desc ARR
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 4001
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 4008
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) desc REP
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 4001
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) desc RCR
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 4015
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 4021
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) desc CCR1
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 4015
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) desc CCR1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 4028
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 4034
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) desc CCR2
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 4028
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) desc CCR2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 4041
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 4047
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) desc CCR3
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 4041
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) desc CCR3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 4054
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 4060
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) desc CCR4
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 4054
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) desc CCR4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 4067
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 4073
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) desc DTG
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 4078
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) desc LOCK
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 4083
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) desc OSSI
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 4088
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) desc OSSR
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 4093
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) desc BKE
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 4098
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) desc BKP
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 4103
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) desc AOE
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 4108
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) desc MOE
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 4067
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) desc BDTR
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 3296
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_OUTPUT
// - SFDITEM_REG__TIM1_CCMR1_INPUT
// - SFDITEM_REG__TIM1_CCMR2_OUTPUT
// - SFDITEM_REG__TIM1_CCMR2_INPUT
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 4133
unsigned int TIM14_CR1 __AT (0x40002000);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 4139
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002000) desc CEN
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 4144
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002000) desc UDIS
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 4149
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002000) desc URS
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_OPM -----------------------------------
// SVD Line: 4154
// - SFDITEM_FIELD__TIM14_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40002000) desc OPM
//
// ( (unsigned int) TIM14_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 4159
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002000) desc ARPE
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 4164
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002000) desc CKD
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 4133
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002000) desc CR1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_OPM
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 4171
unsigned int TIM14_DIER __AT (0x4000200C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 4177
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000200C) desc UIE
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 4182
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000200C) desc CC1IE
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 4171
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000200C) desc DIER
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 4189
unsigned int TIM14_SR __AT (0x40002010);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 4195
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002010) desc UIF
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 4200
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002010) desc CC1IF
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 4205
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002010) desc CC1OF
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IR -----------------------------------
// SVD Line: 4210
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40002010) desc IC1IR
//
// ( (unsigned int) TIM14_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IF -----------------------------------
// SVD Line: 4215
// - SFDITEM_FIELD__TIM14_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40002010) desc IC1IF
//
// ( (unsigned int) TIM14_SR )
// IC1IF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 4189
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002010) desc SR
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x110203UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x110203) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// - SFDITEM_FIELD__TIM14_SR_IC1IF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 4222
unsigned int TIM14_EGR __AT (0x40002014);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 4229
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40002014) desc UG
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 4235
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40002014) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 4222
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40002014) desc EGR
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_OUTPUT ---------------------------
// SVD Line: 4243
unsigned int TIM14_CCMR1_OUTPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 4249
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 0) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 4254
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002018) desc OC1PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M ------------------------------
// SVD Line: 4259
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40002018) desc OC1M
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 4) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_OUTPUT -------------------------------
// SVD Line: 4243
// SFDITEM_REG__TIM14_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40002018) desc CCMR1:OUTPUT
// ( (unsigned int)((TIM14_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7B) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_INPUT ----------------------------
// SVD Line: 4266
unsigned int TIM14_CCMR1_INPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 4273
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 0) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 4278
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002018) desc IC1PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 2) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 4283
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002018) desc IC1F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 4) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_INPUT -------------------------------
// SVD Line: 4266
// SFDITEM_REG__TIM14_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40002018) desc CCMR1:INPUT
// ( (unsigned int)((TIM14_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 4290
unsigned int TIM14_CCER __AT (0x40002020);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 4296
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002020) desc CC1E
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 4301
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002020) desc CC1P
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 4306
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002020) desc CC1NP
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 4290
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002020) desc CCER
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 4313
unsigned int TIM14_CNT __AT (0x40002024);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 4319
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002024) desc CNT
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 4313
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002024) desc CNT
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 4326
unsigned int TIM14_PSC __AT (0x40002028);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 4332
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002028) desc PSC
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 4326
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002028) desc PSC
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 4339
unsigned int TIM14_ARR __AT (0x4000202C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 4346
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000202C) desc ARR
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 4339
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000202C) desc ARR
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 4353
unsigned int TIM14_CCR1 __AT (0x40002034);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 4359
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002034) desc CCR1
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 4353
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002034) desc CCR1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// ----------------------------- Register Item Address: TIM14_OR --------------------------------
// SVD Line: 4366
unsigned int TIM14_OR __AT (0x40002050);
// ------------------------------ Field Item: TIM14_OR_TI1_RMP ----------------------------------
// SVD Line: 4371
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
// TI1_RMP
//
// [Bits 1..0] RW (@ 0x40002050) desc TI1_RMP
//
// ( (unsigned char)((TIM14_OR >> 0) & 0x3), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_OR ------------------------------------
// SVD Line: 4366
// SFDITEM_REG__TIM14_OR
// OR
//
// [Bits 31..0] RW (@ 0x40002050) desc OR
// ( (unsigned int)((TIM14_OR >> 0) & 0xFFFFFFFF), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 4117
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_OUTPUT
// - SFDITEM_REG__TIM14_CCMR1_INPUT
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_OR
//
//
// ---------------------------- Register Item Address: USART1_SR --------------------------------
// SVD Line: 4396
unsigned int USART1_SR __AT (0x40013800);
// -------------------------------- Field Item: USART1_SR_PE ------------------------------------
// SVD Line: 4403
// - SFDITEM_FIELD__USART1_SR_PE
// PE
//
// [Bit 0] RO (@ 0x40013800) Parity error
//
// ( (unsigned int) USART1_SR )
// PE
//
//
//
// -------------------------------- Field Item: USART1_SR_FE ------------------------------------
// SVD Line: 4409
// - SFDITEM_FIELD__USART1_SR_FE
// FE
//
// [Bit 1] RO (@ 0x40013800) Framing error
//
// ( (unsigned int) USART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: USART1_SR_NE ------------------------------------
// SVD Line: 4415
// - SFDITEM_FIELD__USART1_SR_NE
// NE
//
// [Bit 2] RO (@ 0x40013800) Noise error flag
//
// ( (unsigned int) USART1_SR )
// NE
//
//
//
// -------------------------------- Field Item: USART1_SR_ORE -----------------------------------
// SVD Line: 4421
// - SFDITEM_FIELD__USART1_SR_ORE
// ORE
//
// [Bit 3] RO (@ 0x40013800) Overrun error
//
// ( (unsigned int) USART1_SR )
// ORE
//
//
//
// ------------------------------- Field Item: USART1_SR_IDLE -----------------------------------
// SVD Line: 4427
// - SFDITEM_FIELD__USART1_SR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x40013800) IDLE line detected
//
// ( (unsigned int) USART1_SR )
// IDLE
//
//
//
// ------------------------------- Field Item: USART1_SR_RXNE -----------------------------------
// SVD Line: 4433
// - SFDITEM_FIELD__USART1_SR_RXNE
// RXNE
//
// [Bit 5] RW (@ 0x40013800) Read data register not empty
//
// ( (unsigned int) USART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: USART1_SR_TC ------------------------------------
// SVD Line: 4438
// - SFDITEM_FIELD__USART1_SR_TC
// TC
//
// [Bit 6] RW (@ 0x40013800) Transmission complete
//
// ( (unsigned int) USART1_SR )
// TC
//
//
//
// -------------------------------- Field Item: USART1_SR_TXE -----------------------------------
// SVD Line: 4443
// - SFDITEM_FIELD__USART1_SR_TXE
// TXE
//
// [Bit 7] RO (@ 0x40013800) Transmit data register empty
//
// ( (unsigned int) USART1_SR )
// TXE
//
//
//
// -------------------------------- Field Item: USART1_SR_CTS -----------------------------------
// SVD Line: 4449
// - SFDITEM_FIELD__USART1_SR_CTS
// CTS
//
// [Bit 9] RW (@ 0x40013800) CTS flag
//
// ( (unsigned int) USART1_SR )
// CTS
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRF -----------------------------------
// SVD Line: 4454
// - SFDITEM_FIELD__USART1_SR_ABRF
// ABRF
//
// [Bit 10] RO (@ 0x40013800) Automate baudrate detection flag
//
// ( (unsigned int) USART1_SR )
// ABRF
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRE -----------------------------------
// SVD Line: 4460
// - SFDITEM_FIELD__USART1_SR_ABRE
// ABRE
//
// [Bit 11] RO (@ 0x40013800) Automate baudrate detection error flag
//
// ( (unsigned int) USART1_SR )
// ABRE
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRRQ ----------------------------------
// SVD Line: 4466
// - SFDITEM_FIELD__USART1_SR_ABRRQ
// ABRRQ
//
// [Bit 12] WO (@ 0x40013800) Automate baudrate detection requeset
//
// ( (unsigned int) USART1_SR )
// ABRRQ
//
//
//
// -------------------------------- Register RTree: USART1_SR -----------------------------------
// SVD Line: 4396
// SFDITEM_REG__USART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013800) Status register
// ( (unsigned int)((USART1_SR >> 0) & 0xFFFFFFFF), ((USART1_SR = (USART1_SR & ~(0x1260UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1260) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_SR_PE
// - SFDITEM_FIELD__USART1_SR_FE
// - SFDITEM_FIELD__USART1_SR_NE
// - SFDITEM_FIELD__USART1_SR_ORE
// - SFDITEM_FIELD__USART1_SR_IDLE
// - SFDITEM_FIELD__USART1_SR_RXNE
// - SFDITEM_FIELD__USART1_SR_TC
// - SFDITEM_FIELD__USART1_SR_TXE
// - SFDITEM_FIELD__USART1_SR_CTS
// - SFDITEM_FIELD__USART1_SR_ABRF
// - SFDITEM_FIELD__USART1_SR_ABRE
// - SFDITEM_FIELD__USART1_SR_ABRRQ
//
//
// ---------------------------- Register Item Address: USART1_DR --------------------------------
// SVD Line: 4474
unsigned int USART1_DR __AT (0x40013804);
// -------------------------------- Field Item: USART1_DR_DR ------------------------------------
// SVD Line: 4480
// - SFDITEM_FIELD__USART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40013804) Data value
//
// ( (unsigned short)((USART1_DR >> 0) & 0x1FF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: USART1_DR -----------------------------------
// SVD Line: 4474
// SFDITEM_REG__USART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40013804) Data register
// ( (unsigned int)((USART1_DR >> 0) & 0xFFFFFFFF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_DR_DR
//
//
// ---------------------------- Register Item Address: USART1_BRR -------------------------------
// SVD Line: 4487
unsigned int USART1_BRR __AT (0x40013808);
// --------------------------- Field Item: USART1_BRR_DIV_Fraction ------------------------------
// SVD Line: 4493
// - SFDITEM_FIELD__USART1_BRR_DIV_Fraction
// DIV_Fraction
//
// [Bits 3..0] RW (@ 0x40013808) fraction of USARTDIV
//
// ( (unsigned char)((USART1_BRR >> 0) & 0xF), ((USART1_BRR = (USART1_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: USART1_BRR_DIV_Mantissa ------------------------------
// SVD Line: 4498
// - SFDITEM_FIELD__USART1_BRR_DIV_Mantissa
// DIV_Mantissa
//
// [Bits 15..4] RW (@ 0x40013808) mantissa of USARTDIV
//
// ( (unsigned short)((USART1_BRR >> 4) & 0xFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFUL << 4 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_BRR -----------------------------------
// SVD Line: 4487
// SFDITEM_REG__USART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40013808) Baud rate register
// ( (unsigned int)((USART1_BRR >> 0) & 0xFFFFFFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_BRR_DIV_Fraction
// - SFDITEM_FIELD__USART1_BRR_DIV_Mantissa
//
//
// ---------------------------- Register Item Address: USART1_CR1 -------------------------------
// SVD Line: 4505
unsigned int USART1_CR1 __AT (0x4001380C);
// ------------------------------- Field Item: USART1_CR1_RWU -----------------------------------
// SVD Line: 4511
// - SFDITEM_FIELD__USART1_CR1_RWU
// RWU
//
// [Bit 1] RW (@ 0x4001380C) Receiver wakeup
//
// ( (unsigned int) USART1_CR1 )
// RWU
//
//
//
// -------------------------------- Field Item: USART1_CR1_RE -----------------------------------
// SVD Line: 4516
// - SFDITEM_FIELD__USART1_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x4001380C) Receiver enable
//
// ( (unsigned int) USART1_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: USART1_CR1_TE -----------------------------------
// SVD Line: 4521
// - SFDITEM_FIELD__USART1_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x4001380C) Transmitter enable
//
// ( (unsigned int) USART1_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: USART1_CR1_IDLEIE ---------------------------------
// SVD Line: 4526
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x4001380C) IDLE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_RXNEIE ---------------------------------
// SVD Line: 4531
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x4001380C) RXNE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_TCIE ----------------------------------
// SVD Line: 4536
// - SFDITEM_FIELD__USART1_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x4001380C) Transmission complete interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_TXEIE ----------------------------------
// SVD Line: 4541
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x4001380C) TXE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_PEIE ----------------------------------
// SVD Line: 4546
// - SFDITEM_FIELD__USART1_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x4001380C) PE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: USART1_CR1_PS -----------------------------------
// SVD Line: 4551
// - SFDITEM_FIELD__USART1_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x4001380C) Parity selection
//
// ( (unsigned int) USART1_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: USART1_CR1_PCE -----------------------------------
// SVD Line: 4556
// - SFDITEM_FIELD__USART1_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x4001380C) Parity control enable
//
// ( (unsigned int) USART1_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: USART1_CR1_WAKE ----------------------------------
// SVD Line: 4561
// - SFDITEM_FIELD__USART1_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x4001380C) Wakeup method
//
// ( (unsigned int) USART1_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: USART1_CR1_M ------------------------------------
// SVD Line: 4566
// - SFDITEM_FIELD__USART1_CR1_M
// M
//
// [Bit 12] RW (@ 0x4001380C) Word length
//
// ( (unsigned int) USART1_CR1 )
// M
//
//
//
// -------------------------------- Field Item: USART1_CR1_UE -----------------------------------
// SVD Line: 4571
// - SFDITEM_FIELD__USART1_CR1_UE
// UE
//
// [Bit 13] RW (@ 0x4001380C) USART enable
//
// ( (unsigned int) USART1_CR1 )
// UE
//
//
//
// ------------------------------- Register RTree: USART1_CR1 -----------------------------------
// SVD Line: 4505
// SFDITEM_REG__USART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x4001380C) Control register 1
// ( (unsigned int)((USART1_CR1 >> 0) & 0xFFFFFFFF), ((USART1_CR1 = (USART1_CR1 & ~(0x3FFEUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFE) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR1_RWU
// - SFDITEM_FIELD__USART1_CR1_RE
// - SFDITEM_FIELD__USART1_CR1_TE
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// - SFDITEM_FIELD__USART1_CR1_TCIE
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// - SFDITEM_FIELD__USART1_CR1_PEIE
// - SFDITEM_FIELD__USART1_CR1_PS
// - SFDITEM_FIELD__USART1_CR1_PCE
// - SFDITEM_FIELD__USART1_CR1_WAKE
// - SFDITEM_FIELD__USART1_CR1_M
// - SFDITEM_FIELD__USART1_CR1_UE
//
//
// ---------------------------- Register Item Address: USART1_CR2 -------------------------------
// SVD Line: 4578
unsigned int USART1_CR2 __AT (0x40013810);
// ------------------------------- Field Item: USART1_CR2_ADD -----------------------------------
// SVD Line: 4584
// - SFDITEM_FIELD__USART1_CR2_ADD
// ADD
//
// [Bits 3..0] RW (@ 0x40013810) Address of the USART node
//
// ( (unsigned char)((USART1_CR2 >> 0) & 0xF), ((USART1_CR2 = (USART1_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART1_CR2_LBCL ----------------------------------
// SVD Line: 4589
// - SFDITEM_FIELD__USART1_CR2_LBCL
// LBCL
//
// [Bit 8] RW (@ 0x40013810) Last bit clock pulse
//
// ( (unsigned int) USART1_CR2 )
// LBCL
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPHA ----------------------------------
// SVD Line: 4594
// - SFDITEM_FIELD__USART1_CR2_CPHA
// CPHA
//
// [Bit 9] RW (@ 0x40013810) Clock phase
//
// ( (unsigned int) USART1_CR2 )
// CPHA
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPOL ----------------------------------
// SVD Line: 4599
// - SFDITEM_FIELD__USART1_CR2_CPOL
// CPOL
//
// [Bit 10] RW (@ 0x40013810) Clock polarity
//
// ( (unsigned int) USART1_CR2 )
// CPOL
//
//
//
// ------------------------------ Field Item: USART1_CR2_CLKEN ----------------------------------
// SVD Line: 4604
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// CLKEN
//
// [Bit 11] RW (@ 0x40013810) Clock enable
//
// ( (unsigned int) USART1_CR2 )
// CLKEN
//
//
//
// ------------------------------- Field Item: USART1_CR2_STOP ----------------------------------
// SVD Line: 4609
// - SFDITEM_FIELD__USART1_CR2_STOP
// STOP
//
// [Bits 13..12] RW (@ 0x40013810) STOP bits
//
// ( (unsigned char)((USART1_CR2 >> 12) & 0x3), ((USART1_CR2 = (USART1_CR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_CR2 -----------------------------------
// SVD Line: 4578
// SFDITEM_REG__USART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013810) Control register 2
// ( (unsigned int)((USART1_CR2 >> 0) & 0xFFFFFFFF), ((USART1_CR2 = (USART1_CR2 & ~(0x3F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR2_ADD
// - SFDITEM_FIELD__USART1_CR2_LBCL
// - SFDITEM_FIELD__USART1_CR2_CPHA
// - SFDITEM_FIELD__USART1_CR2_CPOL
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// - SFDITEM_FIELD__USART1_CR2_STOP
//
//
// ---------------------------- Register Item Address: USART1_CR3 -------------------------------
// SVD Line: 4616
unsigned int USART1_CR3 __AT (0x40013814);
// ------------------------------- Field Item: USART1_CR3_EIE -----------------------------------
// SVD Line: 4622
// - SFDITEM_FIELD__USART1_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40013814) Error interrupt enable
//
// ( (unsigned int) USART1_CR3 )
// EIE
//
//
//
// ------------------------------ Field Item: USART1_CR3_HDSEL ----------------------------------
// SVD Line: 4627
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40013814) Half-duplex selection
//
// ( (unsigned int) USART1_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: USART1_CR3_RTSE ----------------------------------
// SVD Line: 4632
// - SFDITEM_FIELD__USART1_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40013814) RTS enable
//
// ( (unsigned int) USART1_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: USART1_CR3_CTSE ----------------------------------
// SVD Line: 4637
// - SFDITEM_FIELD__USART1_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40013814) CTS enable
//
// ( (unsigned int) USART1_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: USART1_CR3_CTSIE ----------------------------------
// SVD Line: 4642
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40013814) CTS interrupt enable
//
// ( (unsigned int) USART1_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: USART1_CR3_OVER8 ----------------------------------
// SVD Line: 4647
// - SFDITEM_FIELD__USART1_CR3_OVER8
// OVER8
//
// [Bit 11] RW (@ 0x40013814) Oversampling mode
//
// ( (unsigned int) USART1_CR3 )
// OVER8
//
//
//
// ------------------------------ Field Item: USART1_CR3_ABREN ----------------------------------
// SVD Line: 4652
// - SFDITEM_FIELD__USART1_CR3_ABREN
// ABREN
//
// [Bit 12] RW (@ 0x40013814) Auto baudrate enable
//
// ( (unsigned int) USART1_CR3 )
// ABREN
//
//
//
// ------------------------------ Field Item: USART1_CR3_ABRMOD ---------------------------------
// SVD Line: 4657
// - SFDITEM_FIELD__USART1_CR3_ABRMOD
// ABRMOD
//
// [Bits 14..13] RW (@ 0x40013814) Auto baudrate mode
//
// ( (unsigned char)((USART1_CR3 >> 13) & 0x3), ((USART1_CR3 = (USART1_CR3 & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_CR3 -----------------------------------
// SVD Line: 4616
// SFDITEM_REG__USART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40013814) Control register 3
// ( (unsigned int)((USART1_CR3 >> 0) & 0xFFFFFFFF), ((USART1_CR3 = (USART1_CR3 & ~(0x7F09UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F09) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR3_EIE
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// - SFDITEM_FIELD__USART1_CR3_RTSE
// - SFDITEM_FIELD__USART1_CR3_CTSE
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// - SFDITEM_FIELD__USART1_CR3_OVER8
// - SFDITEM_FIELD__USART1_CR3_ABREN
// - SFDITEM_FIELD__USART1_CR3_ABRMOD
//
//
// --------------------------------- Peripheral View: USART1 ------------------------------------
// SVD Line: 4380
// USART1
// USART1
// - SFDITEM_REG__USART1_SR
// - SFDITEM_REG__USART1_DR
// - SFDITEM_REG__USART1_BRR
// - SFDITEM_REG__USART1_CR1
// - SFDITEM_REG__USART1_CR2
// - SFDITEM_REG__USART1_CR3
//
//
// ---------------------------- IRQ Num definition: PY32F002Zxx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// ------------------------- PY32F002Zxx Specific Interrupt Numbers -----------------------------
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 19
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 20
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 21
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 22
//
//
// EXTI4_15_IRQ
// EXTI4_15
// EXTI Line 4 to 15 Interrupt
// 23
//
//
// ADC_IRQ
// ADC
// ADC Interrupts
// 28
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 29
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 30
//
//
// LPTIM1_DAC_IRQ
// LPTIM1_DAC
// LPTIM1, DAC global Interrupts
// 33
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupt
// 35
//
//
// I2C1_IRQ
// I2C1
// I2C1 global Interrupt
// 39
//
//
// USART1_IRQ
// USART1
// USART1 global Interrupt
// 43
//
//
// PY32F002Zxx_IRQTable
// PY32F002Zxx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_15_IRQ
// ADC_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// LPTIM1_DAC_IRQ
// TIM14_IRQ
// I2C1_IRQ
// USART1_IRQ
//
// ----------------------------------- Menu: PY32F002Zxx ---------------------------------------
// SVD Line: 2
// ----------------------------- Peripheral Menu: 'PY32F002Zxx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// ADC
// ADC
//
//
// CRC
// CRC
//
//
// DBGMCU
// DBGMCU
//
//
// EXTI
// EXTI
//
//
// Flash
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOC
//
//
// I2C
// I2C
//
//
// IWDG
// IWDG
//
//
// LPTIM1
// LPTIM1
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM14
//
//
// USART
// USART1
//
//