Puya Puya PY32F001Bxx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter 0x40012400 0x0 0x400 registers ADC ADC Interrupts 8 ISR ADC interrupt and status register 0x0 EOSMP [1:1] EOC [2:2] EOSEQ [3:3] OVR [4:4] AWD [7:7] EOH [8:8] IER ADC interrupt enable register 0x4 EOSMPIE [1:1] EOCIE [2:2] EOSEQIE [3:3] OVRIE [4:4] AWDIE [7:7] EOHIE [8:8] CR ADC control register 0x8 ADEN [0:0] ADDIS [1:1] ADSTART [2:2] ADSTP [4:4] RSTCAL [29:29] ADCAL_START [30:30] ADCAL [31:31] CFGR1 0xC RES [4:3] ALIGN [5:5] EXTSEL [8:6] EXTEN [11:10] OVRMOD [12:12] CONT [13:13] WAIT [14:14] DISCEN [16:16] CALNUM [19:17] AWDSGL [22:22] AWDEN [23:23] AWDCH [29:26] CFGR2 ADC configuration register 2 0x10 CKMODE [31:28] SMPR ADC sampling time register 0x14 SMP [2:0] TR ADC analog watchdog 1 threshold register 0x18 LT1 [11:0] HT1 [27:16] SQR1 0x1C L [3:0] SQ1 [9:6] SQ2 [15:12] SQ3 [21:18] SQ4 [27:24] SQR2 0x20 SQ5 [3:0] SQ6 [9:6] SQ7 [15:12] SQ8 [21:18] SQ9 [27:24] SQR3 0x24 SQ10 [3:0] SQ11 [9:6] DR 0x28 DATA [15:0] read-only CALFACT 0x44 WCALFACT [8:0] FACTSEL [13:9] WRVLD [14:14] RDVLD [15:15] CAPSUC [21:21] RCALFACT [31:23] read-only CCR ADC common configuration register 0x48 VREFEN [22:22] TSEN [23:23] VREFSEL [24:24] PWRMODE [27:25] DBGMCU Debug support 0x40015800 0x0 0x400 registers DBG_IDCODE 0x0 DBG_ID [31:0] read-only CR Debug MCU Configuration Register 0x4 DBG_SLEEP [0:0] DBG_STOP [1:1] DBG_APB_FZ1 0x8 DBG_IWDG_STOP [12:12] DBG_LPTIM1_STOP [31:31] DBG_APB_FZ2 0xC DBG_TIM1_STOP [11:11] DBG_TIM14_STOP [15:15] DBG_PWM1_STOP [19:19] EXTI External interrupt/event controller 0x40021800 0x0 0x400 registers EXTI0_1 EXTI Line 0 and 1 Interrupt 3 EXTI2_3 EXTI Line 2 and 3 Interrupt 4 EXTI4_7 EXTI Line 4 to 7 Interrupt 5 RTSR EXTI rising trigger selection register 0x0 RT0 Rising trigger event configuration bit of Configurable Event input [0:0] RT1 Rising trigger event configuration bit of Configurable Event input [1:1] RT2 Rising trigger event configuration bit of Configurable Event input [2:2] RT3 Rising trigger event configuration bit of Configurable Event input [3:3] RT4 Rising trigger event configuration bit of Configurable Event input [4:4] RT5 Rising trigger event configuration bit of Configurable Event input [5:5] RT6 Rising trigger event configuration bit of Configurable Event input [6:6] RT7 Rising trigger event configuration bit of Configurable Event input [7:7] RT16 Rising trigger event configuration bit of Configurable Event input [16:16] RT17 Rising trigger event configuration bit of Configurable Event input [17:17] RT18 Rising trigger event configuration bit of Configurable Event input [18:18] FTSR EXTI falling trigger selection register 0x4 FT0 Falling trigger event configuration bit of Configurable Event input [0:0] FT1 Falling trigger event configuration bit of Configurable Event input [1:1] FT2 Falling trigger event configuration bit of Configurable Event input [2:2] FT3 Falling trigger event configuration bit of Configurable Event input [3:3] FT4 Falling trigger event configuration bit of Configurable Event input [4:4] FT5 Falling trigger event configuration bit of Configurable Event input [5:5] FT6 Falling trigger event configuration bit of Configurable Event input [6:6] FT7 Falling trigger event configuration bit of Configurable Event input [7:7] FT16 Falling trigger event configuration bit of Configurable Event input [16:16] FT17 Falling trigger event configuration bit of Configurable Event input [17:17] FT18 Falling trigger event configuration bit of Configurable Event input [18:18] SWIER EXTI software interrupt event register 0x8 SWI0 Rising trigger event configuration bit of Configurable Event input [0:0] SWI1 Rising trigger event configuration bit of Configurable Event input [1:1] SWI2 Rising trigger event configuration bit of Configurable Event input [2:2] SWI3 Rising trigger event configuration bit of Configurable Event input [3:3] SWI4 Rising trigger event configuration bit of Configurable Event input [4:4] SWI5 Rising trigger event configuration bit of Configurable Event input [5:5] SWI6 Rising trigger event configuration bit of Configurable Event input [6:6] SWI7 Rising trigger event configuration bit of Configurable Event input [7:7] SWI16 Rising trigger event configuration bit of Configurable Event input [16:16] SWI17 Rising trigger event configuration bit of Configurable Event input [17:17] SWI18 Rising trigger event configuration bit of Configurable Event input [18:18] PR EXTI pending register 0xC PR0 configurable event inputs x rising edge Pending bit. [0:0] PR1 configurable event inputs x rising edge Pending bit. [1:1] PR2 configurable event inputs x rising edge Pending bit. [2:2] PR3 configurable event inputs x rising edge Pending bit. [3:3] PR4 configurable event inputs x rising edge Pending bit. [4:4] PR5 configurable event inputs x rising edge Pending bit. [5:5] PR6 configurable event inputs x rising edge Pending bit. [6:6] PR7 configurable event inputs x rising edge Pending bit. [7:7] PR16 configurable event inputs x rising edge Pending bit. [16:16] PR17 configurable event inputs x rising edge Pending bit. [17:17] PR18 configurable event inputs x rising edge Pending bit. [18:18] EXTICR1 EXTI external interrupt selection register 0x60 EXTI0 GPIO port selection [1:0] EXTI1 GPIO port selection [9:8] EXTI2 GPIO port selection [17:16] EXTI3 GPIO port selection [25:24] EXTICR2 EXTI external interrupt selection register 0x64 EXTI4 GPIO port selection [1:0] EXTI5 GPIO port selection [9:8] EXTI6 GPIO port selection [16:16] EXTI7 GPIO port selection [24:24] IMR EXTI CPU wakeup with interrupt mask register 0x80 IM0 CPU wakeup with interrupt mask on event input [0:0] IM1 CPU wakeup with interrupt mask on event input [1:1] IM2 CPU wakeup with interrupt mask on event input [2:2] IM3 CPU wakeup with interrupt mask on event input [3:3] IM4 CPU wakeup with interrupt mask on event input [4:4] IM5 CPU wakeup with interrupt mask on event input [5:5] IM6 CPU wakeup with interrupt mask on event input [6:6] IM7 CPU wakeup with interrupt mask on event input [7:7] IM16 CPU wakeup with interrupt mask on event input [16:16] IM29 CPU wakeup with interrupt mask on event input [29:29] EMR EXTI CPU wakeup with event mask register 0x84 EM0 CPU wakeup with event mask on event input [0:0] EM1 CPU wakeup with event mask on event input [1:1] EM2 CPU wakeup with event mask on event input [2:2] EM3 CPU wakeup with event mask on event input [3:3] EM4 CPU wakeup with event mask on event input [4:4] EM5 CPU wakeup with event mask on event input [5:5] EM6 CPU wakeup with event mask on event input [6:6] EM7 CPU wakeup with event mask on event input [7:7] EM16 CPU wakeup with event mask on event input [16:16] EM17 CPU wakeup with event mask on event input [17:17] EM18 CPU wakeup with event mask on event input [18:18] EM29 CPU wakeup with event mask on event input [29:29] FLASH Flash 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 1 KEYR Flash key register 0x8 KEY Flash CR key [31:0] write-only OPTKEYR Option byte key register 0xC OPTKEY Flash Option key [31:0] write-only SR Status register 0x10 EOP End of operation [0:0] WRPERR Write protection error [4:4] OPTVERR Option and trimming bits loading validity error [15:15] BSY Busy [16:16] read-only CR Flash control register 0x14 PG Page Program [0:0] PER Page Erase [1:1] MER Mass Erase [2:2] SER Sector Erase [11:11] OPTSTRT Option bytes Programming Start [17:17] PGSTRT Programming Start [19:19] EOPIE End of operation interrupt enable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option bytes loading [27:27] OPTLOCK Option Lock [30:30] LOCK Lock [31:31] OPTR Flash option register 0x20 RDP Read Protection [7:0] BOR_EN [8:8] BOR_LEV [11:9] IWDG_SW [12:12] NRST_MODE [14:14] IWDG_STOP IWDG Software Enable [15:15] SDKR Flash SDK address register 0x24 SDK_STRT [3:0] SDK_END [11:8] WRPR Flash WRP address register 0x2C WRP [15:0] STCR Flash sleep time config register 0x90 SLEEP_EN Sleep enable [0:0] TS0 Flash TS0 register 0x100 TS0 TS0 [7:0] TS1 Flash TS1 register 0x104 TS1 TS1 [7:0] TS2P Flash TS2P register 0x108 TS2P TS2P [7:0] TPS3 Flash TPS3 register 0x10C TPS3 TPS3 [9:0] TS3 Flash TS3 register 0x110 TS3 TS3 [7:0] ERTPE 0x114 ERTPE ERTPE [15:0] PRGTPE Flash PRGTPE register 0x11C PRGTPE PRGTPE [15:0] PRETPE Flash PRETPE register 0x120 PRETPE PRETPE [13:0] GPIOA General-purpose I/Os 0x50000000 0x0 0x400 registers MODER GPIO port mode register 0x0 MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] MODE2 Port x configuration bits (y = 0..15) [5:4] MODE3 Port x configuration bits (y = 0..15) [7:6] MODE4 Port x configuration bits (y = 0..15) [9:8] MODE5 Port x configuration bits (y = 0..15) [11:10] MODE6 Port x configuration bits (y = 0..15) [13:12] MODE7 Port x configuration bits (y = 0..15) [15:14] OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OT2 Port x configuration bits (y = 0..15) [2:2] OT3 Port x configuration bits (y = 0..15) [3:3] OT4 Port x configuration bits (y = 0..15) [4:4] OT5 Port x configuration bits (y = 0..15) [5:5] OT6 Port x configuration bits (y = 0..15) [6:6] OT7 Port x configuration bits (y = 0..15) [7:7] OSPEEDR GPIO port output speed register 0x8 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] OSPEED2 Port x configuration bits (y = 0..15) [5:4] OSPEED3 Port x configuration bits (y = 0..15) [7:6] OSPEED4 Port x configuration bits (y = 0..15) [9:8] OSPEED5 Port x configuration bits (y = 0..15) [11:10] OSPEED6 Port x configuration bits (y = 0..15) [13:12] OSPEED7 Port x configuration bits (y = 0..15) [15:14] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] PUPD2 Port x configuration bits (y = 0..15) [5:4] PUPD3 Port x configuration bits (y = 0..15) [7:6] PUPD4 Port x configuration bits (y = 0..15) [9:8] PUPD5 Port x configuration bits (y = 0..15) [11:10] PUPD6 Port x configuration bits (y = 0..15) [13:12] PUPD7 Port x configuration bits (y = 0..15) [15:14] IDR GPIO port input data register 0x10 ID0 Port input data (y = 0..15) [0:0] read-only ID1 Port input data (y = 0..15) [1:1] read-only ID2 Port input data (y = 0..15) [2:2] read-only ID3 Port input data (y = 0..15) [3:3] read-only ID4 Port input data (y = 0..15) [4:4] read-only ID5 Port input data (y = 0..15) [5:5] read-only ID6 Port input data (y = 0..15) [6:6] read-only ID7 Port input data (y = 0..15) [7:7] read-only ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] OD2 Port output data (y = 0..15) [2:2] OD3 Port output data (y = 0..15) [3:3] OD4 Port output data (y = 0..15) [4:4] OD5 Port output data (y = 0..15) [5:5] OD6 Port output data (y = 0..15) [6:6] OD7 Port output data (y = 0..15) [7:7] BSRR GPIO port bit set/reset register 0x18 BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BS2 Port x set bit y (y= 0..15) [2:2] BS3 Port x set bit y (y= 0..15) [3:3] BS4 Port x set bit y (y= 0..15) [4:4] BS5 Port x set bit y (y= 0..15) [5:5] BS6 Port x set bit y (y= 0..15) [6:6] BS7 Port x set bit y (y= 0..15) [7:7] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] BR2 Port x reset bit y (y = 0..15) [18:18] BR3 Port x reset bit y (y = 0..15) [19:19] BR4 Port x reset bit y (y = 0..15) [20:20] BR5 Port x reset bit y (y = 0..15) [21:21] BR6 Port x reset bit y (y = 0..15) [22:22] BR7 Port x reset bit y (y = 0..15) [23:23] LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCK2 Port x lock bit y (y= 0..15) [2:2] LCK3 Port x lock bit y (y= 0..15) [3:3] LCK4 Port x lock bit y (y= 0..15) [4:4] LCK5 Port x lock bit y (y= 0..15) [5:5] LCK6 Port x lock bit y (y= 0..15) [6:6] LCK7 Port x lock bit y (y= 0..15) [7:7] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port x bit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port x bit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port x bit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port x bit y (y = 0..7) [23:20] AFSEL6 Alternate function selection for port x bit y (y = 0..7) [27:24] AFSEL7 Alternate function selection for port x bit y (y = 0..7) [31:28] BRR port bit reset register 0x28 BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] GPIOB 0x50000400 GPIOC General-purpose I/Os 0x50000800 IWDG Independent watchdog 0x40003000 0x0 0x400 registers KR Key register (IWDG_KR) 0x0 KEY Key value [15:0] PR Prescaler register (IWDG_PR) 0x4 PR Prescaler divider [2:0] RLR Reload register (IWDG_RLR) 0x8 RL Watchdog counter reload value [11:0] SR Status register (IWDG_SR) 0xC PVU Watchdog prescaler value update [0:0] read-only RVU Watchdog counter reload value update [1:1] read-only LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers LPTIM1 LPTIM1 global Interrupts 11 ISR Interrupt and Status Register 0x0 ARRM Autoreload match [1:1] read-only ARROK Autoreload match update OK [4:4] read-only ICR Interrupt Clear Register 0x4 ARRMCF Autoreload match Clear Flag [1:1] ARROKCF Autoreload match update OK Clear Flag [4:4] IER Interrupt Enable Register 0x8 ARRMIE Autoreload matchInterrupt Enable [1:1] ARROKIE Autoreload match update OK Interrupt Enable [4:4] CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR Control Register 0x10 ENABLE LPTIM Enable [0:0] SNGSTRT LPTIM start in single mode [1:1] CNTSTRT CNTSTRT [2:2] COUNTRST Reset counter [3:3] RSTARE Reset after read enable [4:4] ARR Autoreload Register 0x18 ARR Auto reload value [15:0] CNT Counter Register 0x1C CNT Counter value [15:0] read-only PWM 0x40002800 0x0 0x80 registers PWM PWM global Interrupts 16 CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] DIR [4:4] CMS [6:5] ARPE [7:7] LEDEN [16:16] LEDCEN [17:17] LEDWORD [19:18] DIER 0xC UIE [0:0] OC1IE [1:1] LED1_ENDIE [16:16] SR 0x10 UIF [0:0] OC1IF [1:1] LED1_ENDIF [16:16] EGR 0x14 UG [0:0] CMR 0x18 OC1M [1:0] OC1PE [8:8] CER 0x20 C1E [0:0] C1P [1:1] CNT 0x24 CNT [9:0] PSC 0x28 PSC [7:0] ARR 0x2C ARR [9:0] CCR1 0x34 CCR1 [9:0] LED1_DATA 0x50 LED1_DATA [23:0] PWR Power control 0x40007000 0x0 0x400 registers PVD PVD global Interrupts 0 CR1 Power control register 1 0x0 FLS_SLPTIME [13:12] VR_MODE [15:14] HSION_CTRL [22:22] CR2 0x4 PVDE [0:0] PVDT [6:4] PVD_OUT_SEL [7:7] FLTEN [8:8] FLT_TIME [11:9] SR 0x10 PVDO [11:11] read-only RCC Reset and clock control 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 2 CR Clock control register 0x0 HSION HSI clock enable bit [8:8] HSIRDY HSI clock ready logo [10:10] read-only HSIDIV HSI generates the crossover factor when HSISYS clocks [13:11] HSEON [18:18] ICSCR Internal clock sources calibration register 0x4 HSI_ABS_TRIMCR Clock frequency calibration value [11:0] HSI_TC_TRIMCR HSI frequency selection [15:12] HSI_FS HSI frequency selection [16:16] LSI_TRIM [27:19] CFGR Clock configuration register 0x8 SW System clock source selection [2:0] SWS System clock source selection [5:3] HPRE The AHB clock HCLK is based on the crossover coefficient of SYSCLK [11:8] PPRE APB clock division factor [14:12] MCOSEL MCO output clock selection [26:24] MCOPRE Microprocessor output clock (MCO) divider factor [30:28] ECSCR External clock source control register 0x10 LSE_DRIVER LSE drive capability setting [17:16] LSE_STARTUP LSE crystal oscillator stabilization time selection [21:20] CIER Clock interrupt enable register 0x18 LSIRDYIE LSI clock ready interrupt enabled [0:0] LSERDYIE LSE clock ready interrupt enabled [1:1] HSIRDYIE HSI clock ready interrupt enabled [3:3] CIFR Clock interrupt flag register 0x1C LSIRDYF LSI clock ready interrupt flag [0:0] read-only LSERDYF LSE clock ready interrupt flag [1:1] read-only HSIRDYF HSI clock ready interrupt flag [3:3] read-only LSECSSF LSE Clock Security System (CSS) interrupt flag [9:9] read-only CICR Clock interrupt clear register 0x20 LSIRDYC The LSI ready interrupt flag is cleared [0:0] write-only LSERDYC The LSE ready interrupt flag is cleared [1:1] write-only HSIRDYC The HSI ready interrupt flag is cleared to zero [3:3] write-only LSECSSC The LSE Clock Security System (CSS) interrupt flag is cleared [9:9] write-only IOPRSTR GPIO reset register 0x24 GPIOARST I/O PortA reset [0:0] GPIOBRST I/O PortB reset [1:1] GPIOCRST I/O PortC reset [2:2] APBRSTR1 APB peripheral reset register 1 0x2C UARTRST The UART module is reset [18:18] DBGRST The MCU Debug module is reset [27:27] PWRRST The Power interface module is reset. [28:28] LPTIMRST [31:31] APBRSTR2 APB peripheral reset register 2 0x30 SYSCFGRST The SYSCFG module is reset [0:0] PWMRST The PWM module is reset [9:9] TIM1RST The TIM1 module is reset [11:11] TIM14RST The TIM14 module is reset [15:15] ADCRST The ADC block is reset [20:20] VREFBUFRST [26:26] IOPENR GPIO clock enable register 0x34 GPIOAEN I/O PortA clock enable [0:0] GPIOBEN I/O PortB clock enable [1:1] GPIOCEN I/O PortC clock enable [2:2] AHBENR AHB peripheral clock enable register 0x38 FLASHEN [8:8] SRAMEN [9:9] APBENR1 APB peripheral clock enable register 1 0x3C UARTEN The UART module clock is enabled [18:18] DBGEN MCU Debug module clock enable [27:27] PWREN The Power interface module clock enables [28:28] LPTIMEN [31:31] APBENR2 APB peripheral clock enable register 2 0x40 SYSCFGEN The SYSCFG module clock is enabled [0:0] PWMEN The PWM module clock is enabled [9:9] TIM1EN The TIM1 module clock is enabled [11:11] TIM14EN TIM14 module clock enable [15:15] ADCEN ADC block clock enabled [20:20] VREFBUFEN [26:26] CCIPR Peripherals independent clock configuration register 0x54 PVDSEL PVD module clock source selection [7:7] LPTIM1SEL [19:18] BDCR RTC domain control register 0x5C LSEON LSE OSC enabled [0:0] LSERDY LSE OSC ready [1:1] LSEBYP LSE OSC bypass [2:2] LSECSSON LSE CSS enables [5:5] LSECSSD LSE CSS (clock security system) detection failed [6:6] LSCSEL Low-speed clock selection [25:25] CSR Control/status register 0x60 LSION LSI OSC enabled [0:0] LSIRDY LSI OSC stability flag [1:1] read-only PINRST_FLTDIS NRST filtering is prohibited [8:8] RMVF Clear the reset flag [23:23] OBLRSTF Option byte loader reset flag [25:25] read-only PINRSTF External NRST pin reset flag [26:26] read-only PORRSTF POR reset flag [27:27] read-only SFTRSTF Soft reset flag [28:28] read-only IWDGRSTF IWDG reset flag [29:29] read-only SYSCFG System configuration controller 0x40010000 0x0 0x30 registers CFGR2 SYSCFG configuration register 2 0x18 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit [0:0] PVD_LOCK PVD LOCK selection [2:2] GPIO_ENS desc GPIO_ENS 0x1C PA_ENS desc PA_ENS [7:0] PB_ENS desc PB_ENS [15:8] PC_ENS desc PC_ENS [17:16] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 9 TIM1_CC TIM1 Capture Compare Interrupt 10 CR1 desc CR1 0x0 CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 CCPC desc CCPC [0:0] CCUS desc CCUS [2:2] MMS desc MMS [6:4] TI1S desc TI1S [7:7] OIS1 desc OIS1 [8:8] OIS1N desc OIS1N [9:9] OIS2 desc OIS2 [10:10] OIS2N desc OIS2N [11:11] OIS3 desc OIS3 [12:12] OIS3N desc OIS3N [13:13] OIS4 desc OIS4 [14:14] SMCR desc SMCR 0x8 SMS desc SMS [2:0] OCCS desc OCCS [3:3] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] COMIE desc COMIE [5:5] TIE desc TIE [6:6] BIE desc BIE [7:7] SR desc SR 0x10 UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 UG desc UG [0:0] CC1G Capture/Compare 1 Generation [1:1] CC2G desc CC2G [2:2] CC3G desc CC3G [3:3] CC4G desc CC4G [4:4] COMG desc COMG [5:5] TG desc TG [6:6] BG desc BG [7:7] CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C CC3S desc CC3S [1:0] OC3FE desc OC3FE [2:2] OC3PE desc OC3PE [3:3] OC3M desc OC3M [6:4] OC3CE desc OC3CE [7:7] CC4S desc CC4S [9:8] OC4FE desc OC4FE [10:10] OC4PE desc OC4PE [11:11] OC4M desc OC4M [14:12] OC4CE desc OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C CC3S desc CC3S [1:0] IC3PSC desc IC3PSC [3:2] IC3F desc IC3F [7:4] CC4S desc CC4S [9:8] IC4PSC desc IC4PSC [11:10] IC4F desc IC4F [15:12] CCER desc CCER 0x20 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NE desc CC1NE [2:2] CC1NP desc CC1NP [3:3] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC2NE desc CC2NE [6:6] CC2NP desc CC2NP [7:7] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC3NE desc CC3NE [10:10] CC3NP desc CC3NP [11:11] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CNT desc CNT 0x24 CNT desc CNT [15:0] PSC desc PSC 0x28 PSC desc PSC [15:0] ARR desc ARR 0x2C ARR desc ARR [15:0] RCR desc RCR 0x30 REP desc REP [7:0] CCR1 desc CCR1 0x34 CCR1 desc CCR1 [15:0] CCR1_H desc CCR1_H [31:16] CCR2 desc CCR2 0x38 CCR2 desc CCR2 [15:0] CCR2_H desc CCR2_H [31:16] CCR3 desc CCR3 0x3C CCR3 desc CCR3 [15:0] CCR3_H desc CCR3_H [31:16] CCR4 desc CCR4 0x40 CCR4 desc CCR4 [15:0] BDTR desc BDTR 0x44 DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] TISEL 0x5C TI1SEL desc TI1SEL [3:0] TI2SEL desc TI2SEL [11:8] TI3SEL desc TI3SEL [19:16] TI4SEL desc TI4SEL [27:24] AF1 0x60 BKINE desc BKINE [0:0] BKCMP1E desc BKCMP1E [1:1] BKCMP2E desc BKCMP2E [2:2] BKINP desc BKINP [9:9] BKCMP1P desc BKCMP1P [10:10] BKCMP2P desc BKCMP2P [11:11] ETRSEL desc ETRSEL [17:14] INTR_SEL desc INTR_SEL [19:18] PWM_PHS_EN desc PWM_PHS_EN [20:20] AF2 0x64 OCRSEL desc OCRSEL [18:16] TIM14 TIM 0x40002400 0x0 0x60 registers TIM14 TIM14 global Interrupts 12 CR1 0x0 CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] ARPE desc ARPE [7:7] CKD desc CKD [9:8] DIER 0xC UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] SR 0x10 UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC1OF desc CC1OF [9:9] IC1IR desc IC1IR [16:16] IC1IF desc IC1IF [20:20] EGR 0x14 UG desc UG [0:0] CC1G Capture/Compare 1 Generation [1:1] CCMR1_OUTPUT 0x18 CC1S desc CC1S [1:0] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] CCMR1_INPUT CCMR1_OUTPUT 0x18 CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CCER 0x20 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NP desc CC1NP [3:3] CNT 0x24 CNT desc CNT [15:0] PSC 0x28 PSC desc PSC [15:0] ARR 0x2C ARR desc ARR [15:0] CCR1 0x34 CCR1 desc CCR1 [15:0] TISEL 0x5C TI1SEL desc TI1SEL [3:0] UART1 UART 0x40004800 0x0 0x30 registers UART1 UART1 global Interrupts 17 DR 0x0 DR Receive/send data register [8:0] BRR 0x4 BRR Baud rate register [15:0] SR 0x10 RXNE Receive register not empty [0:0] read-only ORE Overrun error bit [1:1] PE Parity Error bit [2:2] FE Framing Error bit [3:3] BRI Break Interrupt bit [4:4] TDRE Transmit Holding Register Empty bit [5:5] read-only TXE Transmitter Empty bit [6:6] read-only ADDR_RCVD Address Received Bit [8:8] BUSY UART Busy [9:9] read-only BUSY_ERR Busy Detect Error [10:10] CR1 0x14 M Data Length Select [1:0] STOP Number of stop bits [2:2] PCE Parity Enable [3:3] PS Even Parity Select [4:4] SP Stick Parity [5:5] SBK Send Break [6:6] SWAP TX/RX pin swap [8:8] MSBFIRST MSB first mode [9:9] CR2 0x18 RXNEIE Enable Received Data Available Interrupt [0:0] TDREIE Enable Transmit Holding Register Empty Interrupt [1:1] LSIE Enable Receiver Line Status Interrupt [2:2] BUSYERRIE Enable Busyerr state interruption [3:3] TXEIE Enable tx empty interruption [4:4] CR3 0x1C M_E Extension for DLS [0:0] ADDR_MATCH Address Match Mode [1:1] SEND_ADDR Send address control bit [2:2] TX_MODE Transmit mode control bit [3:3] DMAR DMA receive enable [4:4] DMAT DMA transmit enable [5:5] DMA_SOFT_ACK DMA software ack [6:6] RAR 0x20 RAR Receive address matching register [7:0] TAR 0x24 TAR Transmit address matching register [7:0] BRRF 0x28 BRRF Baud rate fractional register [3:0] VREF 0x40010100 0x0 0x10 registers CR 0x0 VREFBUF_OUT_SEL [1:0] VREFBUF_EN [3:3]