/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F001Bxx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:14:54 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F001Bxx.svd',
* last modified on Wed Mar 25 15:33:04 2026
*/
// ----------------------------- Register Item Address: ADC_ISR ---------------------------------
// SVD Line: 40
unsigned int ADC_ISR __AT (0x40012400);
// -------------------------------- Field Item: ADC_ISR_EOSMP -----------------------------------
// SVD Line: 45
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// EOSMP
//
// [Bit 1] RW (@ 0x40012400) EOSMP
//
// ( (unsigned int) ADC_ISR )
// EOSMP
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOC ------------------------------------
// SVD Line: 49
// - SFDITEM_FIELD__ADC_ISR_EOC
// EOC
//
// [Bit 2] RW (@ 0x40012400) EOC
//
// ( (unsigned int) ADC_ISR )
// EOC
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOSEQ -----------------------------------
// SVD Line: 53
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// EOSEQ
//
// [Bit 3] RW (@ 0x40012400) EOSEQ
//
// ( (unsigned int) ADC_ISR )
// EOSEQ
//
//
//
// --------------------------------- Field Item: ADC_ISR_OVR ------------------------------------
// SVD Line: 57
// - SFDITEM_FIELD__ADC_ISR_OVR
// OVR
//
// [Bit 4] RW (@ 0x40012400) OVR
//
// ( (unsigned int) ADC_ISR )
// OVR
//
//
//
// --------------------------------- Field Item: ADC_ISR_AWD ------------------------------------
// SVD Line: 61
// - SFDITEM_FIELD__ADC_ISR_AWD
// AWD
//
// [Bit 7] RW (@ 0x40012400) AWD
//
// ( (unsigned int) ADC_ISR )
// AWD
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOH ------------------------------------
// SVD Line: 65
// - SFDITEM_FIELD__ADC_ISR_EOH
// EOH
//
// [Bit 8] RW (@ 0x40012400) EOH
//
// ( (unsigned int) ADC_ISR )
// EOH
//
//
//
// --------------------------------- Register RTree: ADC_ISR ------------------------------------
// SVD Line: 40
// SFDITEM_REG__ADC_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40012400) ADC interrupt and status register
// ( (unsigned int)((ADC_ISR >> 0) & 0xFFFFFFFF), ((ADC_ISR = (ADC_ISR & ~(0x19EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x19E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// - SFDITEM_FIELD__ADC_ISR_EOC
// - SFDITEM_FIELD__ADC_ISR_EOSEQ
// - SFDITEM_FIELD__ADC_ISR_OVR
// - SFDITEM_FIELD__ADC_ISR_AWD
// - SFDITEM_FIELD__ADC_ISR_EOH
//
//
// ----------------------------- Register Item Address: ADC_IER ---------------------------------
// SVD Line: 71
unsigned int ADC_IER __AT (0x40012404);
// ------------------------------- Field Item: ADC_IER_EOSMPIE ----------------------------------
// SVD Line: 76
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// EOSMPIE
//
// [Bit 1] RW (@ 0x40012404) EOSMPIE
//
// ( (unsigned int) ADC_IER )
// EOSMPIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOCIE -----------------------------------
// SVD Line: 80
// - SFDITEM_FIELD__ADC_IER_EOCIE
// EOCIE
//
// [Bit 2] RW (@ 0x40012404) EOCIE
//
// ( (unsigned int) ADC_IER )
// EOCIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOSEQIE ----------------------------------
// SVD Line: 84
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// EOSEQIE
//
// [Bit 3] RW (@ 0x40012404) EOSEQIE
//
// ( (unsigned int) ADC_IER )
// EOSEQIE
//
//
//
// -------------------------------- Field Item: ADC_IER_OVRIE -----------------------------------
// SVD Line: 88
// - SFDITEM_FIELD__ADC_IER_OVRIE
// OVRIE
//
// [Bit 4] RW (@ 0x40012404) OVRIE
//
// ( (unsigned int) ADC_IER )
// OVRIE
//
//
//
// -------------------------------- Field Item: ADC_IER_AWDIE -----------------------------------
// SVD Line: 92
// - SFDITEM_FIELD__ADC_IER_AWDIE
// AWDIE
//
// [Bit 7] RW (@ 0x40012404) AWDIE
//
// ( (unsigned int) ADC_IER )
// AWDIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOHIE -----------------------------------
// SVD Line: 96
// - SFDITEM_FIELD__ADC_IER_EOHIE
// EOHIE
//
// [Bit 8] RW (@ 0x40012404) EOHIE
//
// ( (unsigned int) ADC_IER )
// EOHIE
//
//
//
// --------------------------------- Register RTree: ADC_IER ------------------------------------
// SVD Line: 71
// SFDITEM_REG__ADC_IER
// IER
//
// [Bits 31..0] RW (@ 0x40012404) ADC interrupt enable register
// ( (unsigned int)((ADC_IER >> 0) & 0xFFFFFFFF), ((ADC_IER = (ADC_IER & ~(0x19EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x19E) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// - SFDITEM_FIELD__ADC_IER_EOCIE
// - SFDITEM_FIELD__ADC_IER_EOSEQIE
// - SFDITEM_FIELD__ADC_IER_OVRIE
// - SFDITEM_FIELD__ADC_IER_AWDIE
// - SFDITEM_FIELD__ADC_IER_EOHIE
//
//
// ------------------------------ Register Item Address: ADC_CR ---------------------------------
// SVD Line: 102
unsigned int ADC_CR __AT (0x40012408);
// --------------------------------- Field Item: ADC_CR_ADEN ------------------------------------
// SVD Line: 107
// - SFDITEM_FIELD__ADC_CR_ADEN
// ADEN
//
// [Bit 0] RW (@ 0x40012408) ADEN
//
// ( (unsigned int) ADC_CR )
// ADEN
//
//
//
// -------------------------------- Field Item: ADC_CR_ADDIS ------------------------------------
// SVD Line: 111
// - SFDITEM_FIELD__ADC_CR_ADDIS
// ADDIS
//
// [Bit 1] RW (@ 0x40012408) ADDIS
//
// ( (unsigned int) ADC_CR )
// ADDIS
//
//
//
// ------------------------------- Field Item: ADC_CR_ADSTART -----------------------------------
// SVD Line: 115
// - SFDITEM_FIELD__ADC_CR_ADSTART
// ADSTART
//
// [Bit 2] RW (@ 0x40012408) ADSTART
//
// ( (unsigned int) ADC_CR )
// ADSTART
//
//
//
// -------------------------------- Field Item: ADC_CR_ADSTP ------------------------------------
// SVD Line: 119
// - SFDITEM_FIELD__ADC_CR_ADSTP
// ADSTP
//
// [Bit 4] RW (@ 0x40012408) ADSTP
//
// ( (unsigned int) ADC_CR )
// ADSTP
//
//
//
// -------------------------------- Field Item: ADC_CR_RSTCAL -----------------------------------
// SVD Line: 123
// - SFDITEM_FIELD__ADC_CR_RSTCAL
// RSTCAL
//
// [Bit 29] RW (@ 0x40012408) RSTCAL
//
// ( (unsigned int) ADC_CR )
// RSTCAL
//
//
//
// ----------------------------- Field Item: ADC_CR_ADCAL_START ---------------------------------
// SVD Line: 127
// - SFDITEM_FIELD__ADC_CR_ADCAL_START
// ADCAL_START
//
// [Bit 30] RW (@ 0x40012408) ADCAL_START
//
// ( (unsigned int) ADC_CR )
// ADCAL_START
//
//
//
// -------------------------------- Field Item: ADC_CR_ADCAL ------------------------------------
// SVD Line: 131
// - SFDITEM_FIELD__ADC_CR_ADCAL
// ADCAL
//
// [Bit 31] RW (@ 0x40012408) ADCAL
//
// ( (unsigned int) ADC_CR )
// ADCAL
//
//
//
// --------------------------------- Register RTree: ADC_CR -------------------------------------
// SVD Line: 102
// SFDITEM_REG__ADC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40012408) ADC control register
// ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0xE0000017UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xE0000017) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CR_ADEN
// - SFDITEM_FIELD__ADC_CR_ADDIS
// - SFDITEM_FIELD__ADC_CR_ADSTART
// - SFDITEM_FIELD__ADC_CR_ADSTP
// - SFDITEM_FIELD__ADC_CR_RSTCAL
// - SFDITEM_FIELD__ADC_CR_ADCAL_START
// - SFDITEM_FIELD__ADC_CR_ADCAL
//
//
// ---------------------------- Register Item Address: ADC_CFGR1 --------------------------------
// SVD Line: 137
unsigned int ADC_CFGR1 __AT (0x4001240C);
// -------------------------------- Field Item: ADC_CFGR1_RES -----------------------------------
// SVD Line: 141
// - SFDITEM_FIELD__ADC_CFGR1_RES
// RES
//
// [Bits 4..3] RW (@ 0x4001240C) RES
//
// ( (unsigned char)((ADC_CFGR1 >> 3) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_ALIGN ----------------------------------
// SVD Line: 145
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// ALIGN
//
// [Bit 5] RW (@ 0x4001240C) ALIGN
//
// ( (unsigned int) ADC_CFGR1 )
// ALIGN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_EXTSEL ----------------------------------
// SVD Line: 149
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// EXTSEL
//
// [Bits 8..6] RW (@ 0x4001240C) EXTSEL
//
// ( (unsigned char)((ADC_CFGR1 >> 6) & 0x7), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_EXTEN ----------------------------------
// SVD Line: 153
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// EXTEN
//
// [Bits 11..10] RW (@ 0x4001240C) EXTEN
//
// ( (unsigned char)((ADC_CFGR1 >> 10) & 0x3), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_OVRMOD ----------------------------------
// SVD Line: 157
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// OVRMOD
//
// [Bit 12] RW (@ 0x4001240C) OVRMOD
//
// ( (unsigned int) ADC_CFGR1 )
// OVRMOD
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_CONT -----------------------------------
// SVD Line: 161
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// CONT
//
// [Bit 13] RW (@ 0x4001240C) CONT
//
// ( (unsigned int) ADC_CFGR1 )
// CONT
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_WAIT -----------------------------------
// SVD Line: 165
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// WAIT
//
// [Bit 14] RW (@ 0x4001240C) WAIT
//
// ( (unsigned int) ADC_CFGR1 )
// WAIT
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_DISCEN ----------------------------------
// SVD Line: 169
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// DISCEN
//
// [Bit 16] RW (@ 0x4001240C) DISCEN
//
// ( (unsigned int) ADC_CFGR1 )
// DISCEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_CALNUM ----------------------------------
// SVD Line: 173
// - SFDITEM_FIELD__ADC_CFGR1_CALNUM
// CALNUM
//
// [Bits 19..17] RW (@ 0x4001240C) CALNUM
//
// ( (unsigned char)((ADC_CFGR1 >> 17) & 0x7), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x7UL << 17 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 17 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR1_AWDSGL ----------------------------------
// SVD Line: 177
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// AWDSGL
//
// [Bit 22] RW (@ 0x4001240C) AWDSGL
//
// ( (unsigned int) ADC_CFGR1 )
// AWDSGL
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDEN ----------------------------------
// SVD Line: 181
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// AWDEN
//
// [Bit 23] RW (@ 0x4001240C) AWDEN
//
// ( (unsigned int) ADC_CFGR1 )
// AWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR1_AWDCH ----------------------------------
// SVD Line: 185
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
// AWDCH
//
// [Bits 29..26] RW (@ 0x4001240C) AWDCH
//
// ( (unsigned char)((ADC_CFGR1 >> 26) & 0xF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR1 -----------------------------------
// SVD Line: 137
// SFDITEM_REG__ADC_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x4001240C) CFGR1
// ( (unsigned int)((ADC_CFGR1 >> 0) & 0xFFFFFFFF), ((ADC_CFGR1 = (ADC_CFGR1 & ~(0x3CCF7DF8UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CCF7DF8) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR1_RES
// - SFDITEM_FIELD__ADC_CFGR1_ALIGN
// - SFDITEM_FIELD__ADC_CFGR1_EXTSEL
// - SFDITEM_FIELD__ADC_CFGR1_EXTEN
// - SFDITEM_FIELD__ADC_CFGR1_OVRMOD
// - SFDITEM_FIELD__ADC_CFGR1_CONT
// - SFDITEM_FIELD__ADC_CFGR1_WAIT
// - SFDITEM_FIELD__ADC_CFGR1_DISCEN
// - SFDITEM_FIELD__ADC_CFGR1_CALNUM
// - SFDITEM_FIELD__ADC_CFGR1_AWDSGL
// - SFDITEM_FIELD__ADC_CFGR1_AWDEN
// - SFDITEM_FIELD__ADC_CFGR1_AWDCH
//
//
// ---------------------------- Register Item Address: ADC_CFGR2 --------------------------------
// SVD Line: 191
unsigned int ADC_CFGR2 __AT (0x40012410);
// ------------------------------ Field Item: ADC_CFGR2_CKMODE ----------------------------------
// SVD Line: 196
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
// CKMODE
//
// [Bits 31..28] RW (@ 0x40012410) CKMODE
//
// ( (unsigned char)((ADC_CFGR2 >> 28) & 0xF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR2 -----------------------------------
// SVD Line: 191
// SFDITEM_REG__ADC_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40012410) ADC configuration register 2
// ( (unsigned int)((ADC_CFGR2 >> 0) & 0xFFFFFFFF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0xF0000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0000000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR2_CKMODE
//
//
// ----------------------------- Register Item Address: ADC_SMPR --------------------------------
// SVD Line: 202
unsigned int ADC_SMPR __AT (0x40012414);
// -------------------------------- Field Item: ADC_SMPR_SMP ------------------------------------
// SVD Line: 207
// - SFDITEM_FIELD__ADC_SMPR_SMP
// SMP
//
// [Bits 2..0] RW (@ 0x40012414) SMP
//
// ( (unsigned char)((ADC_SMPR >> 0) & 0x7), ((ADC_SMPR = (ADC_SMPR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR ------------------------------------
// SVD Line: 202
// SFDITEM_REG__ADC_SMPR
// SMPR
//
// [Bits 31..0] RW (@ 0x40012414) ADC sampling time register
// ( (unsigned int)((ADC_SMPR >> 0) & 0xFFFFFFFF), ((ADC_SMPR = (ADC_SMPR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR_SMP
//
//
// ------------------------------ Register Item Address: ADC_TR ---------------------------------
// SVD Line: 213
unsigned int ADC_TR __AT (0x40012418);
// --------------------------------- Field Item: ADC_TR_LT1 -------------------------------------
// SVD Line: 218
// - SFDITEM_FIELD__ADC_TR_LT1
// LT1
//
// [Bits 11..0] RW (@ 0x40012418) LT1
//
// ( (unsigned short)((ADC_TR >> 0) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: ADC_TR_HT1 -------------------------------------
// SVD Line: 222
// - SFDITEM_FIELD__ADC_TR_HT1
// HT1
//
// [Bits 27..16] RW (@ 0x40012418) HT1
//
// ( (unsigned short)((ADC_TR >> 16) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_TR -------------------------------------
// SVD Line: 213
// SFDITEM_REG__ADC_TR
// TR
//
// [Bits 31..0] RW (@ 0x40012418) ADC analog watchdog 1 threshold register
// ( (unsigned int)((ADC_TR >> 0) & 0xFFFFFFFF), ((ADC_TR = (ADC_TR & ~(0xFFF0FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF0FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_TR_LT1
// - SFDITEM_FIELD__ADC_TR_HT1
//
//
// ----------------------------- Register Item Address: ADC_SQR1 --------------------------------
// SVD Line: 228
unsigned int ADC_SQR1 __AT (0x4001241C);
// --------------------------------- Field Item: ADC_SQR1_L -------------------------------------
// SVD Line: 232
// - SFDITEM_FIELD__ADC_SQR1_L
// L
//
// [Bits 3..0] RW (@ 0x4001241C) L
//
// ( (unsigned char)((ADC_SQR1 >> 0) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ1 ------------------------------------
// SVD Line: 236
// - SFDITEM_FIELD__ADC_SQR1_SQ1
// SQ1
//
// [Bits 9..6] RW (@ 0x4001241C) SQ1
//
// ( (unsigned char)((ADC_SQR1 >> 6) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ2 ------------------------------------
// SVD Line: 240
// - SFDITEM_FIELD__ADC_SQR1_SQ2
// SQ2
//
// [Bits 15..12] RW (@ 0x4001241C) SQ2
//
// ( (unsigned char)((ADC_SQR1 >> 12) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ3 ------------------------------------
// SVD Line: 244
// - SFDITEM_FIELD__ADC_SQR1_SQ3
// SQ3
//
// [Bits 21..18] RW (@ 0x4001241C) SQ3
//
// ( (unsigned char)((ADC_SQR1 >> 18) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ4 ------------------------------------
// SVD Line: 248
// - SFDITEM_FIELD__ADC_SQR1_SQ4
// SQ4
//
// [Bits 27..24] RW (@ 0x4001241C) SQ4
//
// ( (unsigned char)((ADC_SQR1 >> 24) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR1 ------------------------------------
// SVD Line: 228
// SFDITEM_REG__ADC_SQR1
// SQR1
//
// [Bits 31..0] RW (@ 0x4001241C) SQR1
// ( (unsigned int)((ADC_SQR1 >> 0) & 0xFFFFFFFF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xF3CF3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF3CF3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR1_L
// - SFDITEM_FIELD__ADC_SQR1_SQ1
// - SFDITEM_FIELD__ADC_SQR1_SQ2
// - SFDITEM_FIELD__ADC_SQR1_SQ3
// - SFDITEM_FIELD__ADC_SQR1_SQ4
//
//
// ----------------------------- Register Item Address: ADC_SQR2 --------------------------------
// SVD Line: 254
unsigned int ADC_SQR2 __AT (0x40012420);
// -------------------------------- Field Item: ADC_SQR2_SQ5 ------------------------------------
// SVD Line: 258
// - SFDITEM_FIELD__ADC_SQR2_SQ5
// SQ5
//
// [Bits 3..0] RW (@ 0x40012420) SQ5
//
// ( (unsigned char)((ADC_SQR2 >> 0) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ6 ------------------------------------
// SVD Line: 262
// - SFDITEM_FIELD__ADC_SQR2_SQ6
// SQ6
//
// [Bits 9..6] RW (@ 0x40012420) SQ6
//
// ( (unsigned char)((ADC_SQR2 >> 6) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ7 ------------------------------------
// SVD Line: 266
// - SFDITEM_FIELD__ADC_SQR2_SQ7
// SQ7
//
// [Bits 15..12] RW (@ 0x40012420) SQ7
//
// ( (unsigned char)((ADC_SQR2 >> 12) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ8 ------------------------------------
// SVD Line: 270
// - SFDITEM_FIELD__ADC_SQR2_SQ8
// SQ8
//
// [Bits 21..18] RW (@ 0x40012420) SQ8
//
// ( (unsigned char)((ADC_SQR2 >> 18) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ9 ------------------------------------
// SVD Line: 274
// - SFDITEM_FIELD__ADC_SQR2_SQ9
// SQ9
//
// [Bits 27..24] RW (@ 0x40012420) SQ9
//
// ( (unsigned char)((ADC_SQR2 >> 24) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR2 ------------------------------------
// SVD Line: 254
// SFDITEM_REG__ADC_SQR2
// SQR2
//
// [Bits 31..0] RW (@ 0x40012420) SQR2
// ( (unsigned int)((ADC_SQR2 >> 0) & 0xFFFFFFFF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xF3CF3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF3CF3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR2_SQ5
// - SFDITEM_FIELD__ADC_SQR2_SQ6
// - SFDITEM_FIELD__ADC_SQR2_SQ7
// - SFDITEM_FIELD__ADC_SQR2_SQ8
// - SFDITEM_FIELD__ADC_SQR2_SQ9
//
//
// ----------------------------- Register Item Address: ADC_SQR3 --------------------------------
// SVD Line: 280
unsigned int ADC_SQR3 __AT (0x40012424);
// -------------------------------- Field Item: ADC_SQR3_SQ10 -----------------------------------
// SVD Line: 284
// - SFDITEM_FIELD__ADC_SQR3_SQ10
// SQ10
//
// [Bits 3..0] RW (@ 0x40012424) SQ10
//
// ( (unsigned char)((ADC_SQR3 >> 0) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR3_SQ11 -----------------------------------
// SVD Line: 288
// - SFDITEM_FIELD__ADC_SQR3_SQ11
// SQ11
//
// [Bits 9..6] RW (@ 0x40012424) SQ11
//
// ( (unsigned char)((ADC_SQR3 >> 6) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR3 ------------------------------------
// SVD Line: 280
// SFDITEM_REG__ADC_SQR3
// SQR3
//
// [Bits 31..0] RW (@ 0x40012424) SQR3
// ( (unsigned int)((ADC_SQR3 >> 0) & 0xFFFFFFFF), ((ADC_SQR3 = (ADC_SQR3 & ~(0x3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR3_SQ10
// - SFDITEM_FIELD__ADC_SQR3_SQ11
//
//
// ------------------------------ Register Item Address: ADC_DR ---------------------------------
// SVD Line: 294
unsigned int ADC_DR __AT (0x40012428);
// --------------------------------- Field Item: ADC_DR_DATA ------------------------------------
// SVD Line: 298
// - SFDITEM_FIELD__ADC_DR_DATA
// DATA
//
// [Bits 15..0] RO (@ 0x40012428) DATA
//
// ( (unsigned short)((ADC_DR >> 0) & 0xFFFF) )
//
//
//
// --------------------------------- Register RTree: ADC_DR -------------------------------------
// SVD Line: 294
// SFDITEM_REG__ADC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40012428) DR
// ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_DR_DATA
//
//
// --------------------------- Register Item Address: ADC_CALFACT -------------------------------
// SVD Line: 305
unsigned int ADC_CALFACT __AT (0x40012444);
// ---------------------------- Field Item: ADC_CALFACT_WCALFACT --------------------------------
// SVD Line: 309
// - SFDITEM_FIELD__ADC_CALFACT_WCALFACT
// WCALFACT
//
// [Bits 8..0] RW (@ 0x40012444) WCALFACT
//
// ( (unsigned short)((ADC_CALFACT >> 0) & 0x1FF), ((ADC_CALFACT = (ADC_CALFACT & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFACT_FACTSEL --------------------------------
// SVD Line: 313
// - SFDITEM_FIELD__ADC_CALFACT_FACTSEL
// FACTSEL
//
// [Bits 13..9] RW (@ 0x40012444) FACTSEL
//
// ( (unsigned char)((ADC_CALFACT >> 9) & 0x1F), ((ADC_CALFACT = (ADC_CALFACT & ~(0x1FUL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 9 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CALFACT_WRVLD ---------------------------------
// SVD Line: 317
// - SFDITEM_FIELD__ADC_CALFACT_WRVLD
// WRVLD
//
// [Bit 14] RW (@ 0x40012444) WRVLD
//
// ( (unsigned int) ADC_CALFACT )
// WRVLD
//
//
//
// ------------------------------ Field Item: ADC_CALFACT_RDVLD ---------------------------------
// SVD Line: 321
// - SFDITEM_FIELD__ADC_CALFACT_RDVLD
// RDVLD
//
// [Bit 15] RW (@ 0x40012444) RDVLD
//
// ( (unsigned int) ADC_CALFACT )
// RDVLD
//
//
//
// ----------------------------- Field Item: ADC_CALFACT_CAPSUC ---------------------------------
// SVD Line: 325
// - SFDITEM_FIELD__ADC_CALFACT_CAPSUC
// CAPSUC
//
// [Bit 21] RW (@ 0x40012444) CAPSUC
//
// ( (unsigned int) ADC_CALFACT )
// CAPSUC
//
//
//
// ---------------------------- Field Item: ADC_CALFACT_RCALFACT --------------------------------
// SVD Line: 329
// - SFDITEM_FIELD__ADC_CALFACT_RCALFACT
// RCALFACT
//
// [Bits 31..23] RO (@ 0x40012444) RCALFACT
//
// ( (unsigned short)((ADC_CALFACT >> 23) & 0x1FF) )
//
//
//
// ------------------------------- Register RTree: ADC_CALFACT ----------------------------------
// SVD Line: 305
// SFDITEM_REG__ADC_CALFACT
// CALFACT
//
// [Bits 31..0] RW (@ 0x40012444) CALFACT
// ( (unsigned int)((ADC_CALFACT >> 0) & 0xFFFFFFFF), ((ADC_CALFACT = (ADC_CALFACT & ~(0x20FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x20FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFACT_WCALFACT
// - SFDITEM_FIELD__ADC_CALFACT_FACTSEL
// - SFDITEM_FIELD__ADC_CALFACT_WRVLD
// - SFDITEM_FIELD__ADC_CALFACT_RDVLD
// - SFDITEM_FIELD__ADC_CALFACT_CAPSUC
// - SFDITEM_FIELD__ADC_CALFACT_RCALFACT
//
//
// ----------------------------- Register Item Address: ADC_CCR ---------------------------------
// SVD Line: 336
unsigned int ADC_CCR __AT (0x40012448);
// ------------------------------- Field Item: ADC_CCR_VREFEN -----------------------------------
// SVD Line: 341
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// VREFEN
//
// [Bit 22] RW (@ 0x40012448) VREFEN
//
// ( (unsigned int) ADC_CCR )
// VREFEN
//
//
//
// -------------------------------- Field Item: ADC_CCR_TSEN ------------------------------------
// SVD Line: 345
// - SFDITEM_FIELD__ADC_CCR_TSEN
// TSEN
//
// [Bit 23] RW (@ 0x40012448) TSEN
//
// ( (unsigned int) ADC_CCR )
// TSEN
//
//
//
// ------------------------------- Field Item: ADC_CCR_VREFSEL ----------------------------------
// SVD Line: 349
// - SFDITEM_FIELD__ADC_CCR_VREFSEL
// VREFSEL
//
// [Bit 24] RW (@ 0x40012448) VREFSEL
//
// ( (unsigned int) ADC_CCR )
// VREFSEL
//
//
//
// ------------------------------- Field Item: ADC_CCR_PWRMODE ----------------------------------
// SVD Line: 353
// - SFDITEM_FIELD__ADC_CCR_PWRMODE
// PWRMODE
//
// [Bits 27..25] RW (@ 0x40012448) PWRMODE
//
// ( (unsigned char)((ADC_CCR >> 25) & 0x7), ((ADC_CCR = (ADC_CCR & ~(0x7UL << 25 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 25 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_CCR ------------------------------------
// SVD Line: 336
// SFDITEM_REG__ADC_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x40012448) ADC common configuration register
// ( (unsigned int)((ADC_CCR >> 0) & 0xFFFFFFFF), ((ADC_CCR = (ADC_CCR & ~(0xFC00000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFC00000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// - SFDITEM_FIELD__ADC_CCR_TSEN
// - SFDITEM_FIELD__ADC_CCR_VREFSEL
// - SFDITEM_FIELD__ADC_CCR_PWRMODE
//
//
// ---------------------------------- Peripheral View: ADC --------------------------------------
// SVD Line: 25
// ADC
// ADC
// - SFDITEM_REG__ADC_ISR
// - SFDITEM_REG__ADC_IER
// - SFDITEM_REG__ADC_CR
// - SFDITEM_REG__ADC_CFGR1
// - SFDITEM_REG__ADC_CFGR2
// - SFDITEM_REG__ADC_SMPR
// - SFDITEM_REG__ADC_TR
// - SFDITEM_REG__ADC_SQR1
// - SFDITEM_REG__ADC_SQR2
// - SFDITEM_REG__ADC_SQR3
// - SFDITEM_REG__ADC_DR
// - SFDITEM_REG__ADC_CALFACT
// - SFDITEM_REG__ADC_CCR
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_IDCODE ----------------------------
// SVD Line: 371
unsigned int DBGMCU_DBG_IDCODE __AT (0x40015800);
// -------------------------- Field Item: DBGMCU_DBG_IDCODE_DBG_ID ------------------------------
// SVD Line: 375
// - SFDITEM_FIELD__DBGMCU_DBG_IDCODE_DBG_ID
// DBG_ID
//
// [Bits 31..0] RO (@ 0x40015800) DBG_ID
//
// ( (unsigned int)((DBGMCU_DBG_IDCODE >> 0) & 0xFFFFFFFF) )
//
//
//
// ---------------------------- Register RTree: DBGMCU_DBG_IDCODE -------------------------------
// SVD Line: 371
// SFDITEM_REG__DBGMCU_DBG_IDCODE
// DBG_IDCODE
//
// [Bits 31..0] RW (@ 0x40015800) DBG_IDCODE
// ( (unsigned int)((DBGMCU_DBG_IDCODE >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DBGMCU_DBG_IDCODE_DBG_ID
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 382
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_SLEEP --------------------------------
// SVD Line: 387
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// DBG_SLEEP
//
// [Bit 0] RW (@ 0x40015804) DBG_SLEEP
//
// ( (unsigned int) DBGMCU_CR )
// DBG_SLEEP
//
//
//
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 391
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) DBG_STOP
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 382
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_APB_FZ1 ---------------------------
// SVD Line: 397
unsigned int DBGMCU_DBG_APB_FZ1 __AT (0x40015808);
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP --------------------------
// SVD Line: 401
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP
// DBG_IWDG_STOP
//
// [Bit 12] RW (@ 0x40015808) DBG_IWDG_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_IWDG_STOP
//
//
//
// --------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP -------------------------
// SVD Line: 405
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP
// DBG_LPTIM1_STOP
//
// [Bit 31] RW (@ 0x40015808) DBG_LPTIM1_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_LPTIM1_STOP
//
//
//
// --------------------------- Register RTree: DBGMCU_DBG_APB_FZ1 -------------------------------
// SVD Line: 397
// SFDITEM_REG__DBGMCU_DBG_APB_FZ1
// DBG_APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) DBG_APB_FZ1
// ( (unsigned int)((DBGMCU_DBG_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_DBG_APB_FZ1 = (DBGMCU_DBG_APB_FZ1 & ~(0x80001000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80001000) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_APB_FZ2 ---------------------------
// SVD Line: 411
unsigned int DBGMCU_DBG_APB_FZ2 __AT (0x4001580C);
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_TIM1_STOP --------------------------
// SVD Line: 415
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM1_STOP
// DBG_TIM1_STOP
//
// [Bit 11] RW (@ 0x4001580C) DBG_TIM1_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_TIM1_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP -------------------------
// SVD Line: 419
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP
// DBG_TIM14_STOP
//
// [Bit 15] RW (@ 0x4001580C) DBG_TIM14_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_TIM14_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_PWM1_STOP --------------------------
// SVD Line: 423
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_PWM1_STOP
// DBG_PWM1_STOP
//
// [Bit 19] RW (@ 0x4001580C) DBG_PWM1_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_PWM1_STOP
//
//
//
// --------------------------- Register RTree: DBGMCU_DBG_APB_FZ2 -------------------------------
// SVD Line: 411
// SFDITEM_REG__DBGMCU_DBG_APB_FZ2
// DBG_APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) DBG_APB_FZ2
// ( (unsigned int)((DBGMCU_DBG_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_DBG_APB_FZ2 = (DBGMCU_DBG_APB_FZ2 & ~(0x88800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x88800) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM1_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_PWM1_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 361
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_DBG_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_DBG_APB_FZ1
// - SFDITEM_REG__DBGMCU_DBG_APB_FZ2
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 456
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 461
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 466
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 471
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 476
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 481
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 486
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 491
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 496
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT16 -----------------------------------
// SVD Line: 501
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// RT16
//
// [Bit 16] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT16
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT17 -----------------------------------
// SVD Line: 506
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// RT17
//
// [Bit 17] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT17
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT18 -----------------------------------
// SVD Line: 511
// - SFDITEM_FIELD__EXTI_RTSR_RT18
// RT18
//
// [Bit 18] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT18
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 456
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selection register
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0x700FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x700FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// - SFDITEM_FIELD__EXTI_RTSR_RT18
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 518
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 523
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 528
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 533
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 538
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 543
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 548
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 553
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 558
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT16 -----------------------------------
// SVD Line: 563
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// FT16
//
// [Bit 16] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT16
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT17 -----------------------------------
// SVD Line: 568
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// FT17
//
// [Bit 17] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT17
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT18 -----------------------------------
// SVD Line: 573
// - SFDITEM_FIELD__EXTI_FTSR_FT18
// FT18
//
// [Bit 18] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT18
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 518
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selection register
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0x700FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x700FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// - SFDITEM_FIELD__EXTI_FTSR_FT18
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 580
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------- Field Item: EXTI_SWIER_SWI0 ----------------------------------
// SVD Line: 585
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// SWI0
//
// [Bit 0] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI0
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI1 ----------------------------------
// SVD Line: 590
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// SWI1
//
// [Bit 1] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI1
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI2 ----------------------------------
// SVD Line: 595
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// SWI2
//
// [Bit 2] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI2
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI3 ----------------------------------
// SVD Line: 600
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// SWI3
//
// [Bit 3] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI3
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI4 ----------------------------------
// SVD Line: 605
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// SWI4
//
// [Bit 4] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI4
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI5 ----------------------------------
// SVD Line: 610
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// SWI5
//
// [Bit 5] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI5
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI6 ----------------------------------
// SVD Line: 615
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// SWI6
//
// [Bit 6] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI6
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI7 ----------------------------------
// SVD Line: 620
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// SWI7
//
// [Bit 7] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI7
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI16 ----------------------------------
// SVD Line: 625
// - SFDITEM_FIELD__EXTI_SWIER_SWI16
// SWI16
//
// [Bit 16] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI16
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI17 ----------------------------------
// SVD Line: 630
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// SWI17
//
// [Bit 17] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI17
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWI18 ----------------------------------
// SVD Line: 635
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
// SWI18
//
// [Bit 18] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI18
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 580
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt event register
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0x700FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x700FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// - SFDITEM_FIELD__EXTI_SWIER_SWI16
// - SFDITEM_FIELD__EXTI_SWIER_SWI17
// - SFDITEM_FIELD__EXTI_SWIER_SWI18
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 642
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 647
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 652
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 657
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 662
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 667
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 672
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 677
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 682
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR16 ------------------------------------
// SVD Line: 687
// - SFDITEM_FIELD__EXTI_PR_PR16
// PR16
//
// [Bit 16] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR16
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR17 ------------------------------------
// SVD Line: 692
// - SFDITEM_FIELD__EXTI_PR_PR17
// PR17
//
// [Bit 17] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR17
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR18 ------------------------------------
// SVD Line: 697
// - SFDITEM_FIELD__EXTI_PR_PR18
// PR18
//
// [Bit 18] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR18
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 642
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pending register
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0x700FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x700FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
// - SFDITEM_FIELD__EXTI_PR_PR16
// - SFDITEM_FIELD__EXTI_PR_PR17
// - SFDITEM_FIELD__EXTI_PR_PR18
//
//
// --------------------------- Register Item Address: EXTI_EXTICR1 ------------------------------
// SVD Line: 704
unsigned int EXTI_EXTICR1 __AT (0x40021860);
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI0 ---------------------------------
// SVD Line: 709
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// EXTI0
//
// [Bits 1..0] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 0) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI1 ---------------------------------
// SVD Line: 714
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// EXTI1
//
// [Bits 9..8] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 8) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI2 ---------------------------------
// SVD Line: 719
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// EXTI2
//
// [Bits 17..16] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 16) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI3 ---------------------------------
// SVD Line: 724
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
// EXTI3
//
// [Bits 25..24] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 24) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR1 ----------------------------------
// SVD Line: 704
// SFDITEM_REG__EXTI_EXTICR1
// EXTICR1
//
// [Bits 31..0] RW (@ 0x40021860) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR1 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
//
//
// --------------------------- Register Item Address: EXTI_EXTICR2 ------------------------------
// SVD Line: 731
unsigned int EXTI_EXTICR2 __AT (0x40021864);
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI4 ---------------------------------
// SVD Line: 736
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// EXTI4
//
// [Bits 1..0] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 0) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI5 ---------------------------------
// SVD Line: 741
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// EXTI5
//
// [Bits 9..8] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 8) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI6 ---------------------------------
// SVD Line: 746
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// EXTI6
//
// [Bit 16] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI6
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI7 ---------------------------------
// SVD Line: 751
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
// EXTI7
//
// [Bit 24] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI7
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR2 ----------------------------------
// SVD Line: 731
// SFDITEM_REG__EXTI_EXTICR2
// EXTICR2
//
// [Bits 31..0] RW (@ 0x40021864) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR2 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x1010303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1010303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 758
unsigned int EXTI_IMR __AT (0x40021880);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 763
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 768
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 773
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 778
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 783
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 788
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 793
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 798
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM16 -----------------------------------
// SVD Line: 803
// - SFDITEM_FIELD__EXTI_IMR_IM16
// IM16
//
// [Bit 16] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM16
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM29 -----------------------------------
// SVD Line: 808
// - SFDITEM_FIELD__EXTI_IMR_IM29
// IM29
//
// [Bit 29] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM29
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 758
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021880) EXTI CPU wakeup with interrupt mask register
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0x200100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200100FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM16
// - SFDITEM_FIELD__EXTI_IMR_IM29
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 815
unsigned int EXTI_EMR __AT (0x40021884);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 820
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 825
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 830
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 835
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 840
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 845
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 850
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 855
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM16 -----------------------------------
// SVD Line: 860
// - SFDITEM_FIELD__EXTI_EMR_EM16
// EM16
//
// [Bit 16] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM16
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM17 -----------------------------------
// SVD Line: 865
// - SFDITEM_FIELD__EXTI_EMR_EM17
// EM17
//
// [Bit 17] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM17
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM18 -----------------------------------
// SVD Line: 870
// - SFDITEM_FIELD__EXTI_EMR_EM18
// EM18
//
// [Bit 18] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM18
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM29 -----------------------------------
// SVD Line: 875
// - SFDITEM_FIELD__EXTI_EMR_EM29
// EM29
//
// [Bit 29] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM29
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 815
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x40021884) EXTI CPU wakeup with event mask register
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0x200700FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200700FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM16
// - SFDITEM_FIELD__EXTI_EMR_EM17
// - SFDITEM_FIELD__EXTI_EMR_EM18
// - SFDITEM_FIELD__EXTI_EMR_EM29
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 431
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_EXTICR1
// - SFDITEM_REG__EXTI_EXTICR2
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_KEYR -------------------------------
// SVD Line: 899
unsigned int FLASH_KEYR __AT (0x40022008);
// ------------------------------- Field Item: FLASH_KEYR_KEY -----------------------------------
// SVD Line: 904
// - SFDITEM_FIELD__FLASH_KEYR_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash CR key
//
// ( (unsigned int)((FLASH_KEYR >> 0) & 0x0), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_KEYR -----------------------------------
// SVD Line: 899
// SFDITEM_REG__FLASH_KEYR
// KEYR
//
// [Bits 31..0] RW (@ 0x40022008) Flash key register
// ( (unsigned int)((FLASH_KEYR >> 0) & 0xFFFFFFFF), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEYR_KEY
//
//
// -------------------------- Register Item Address: FLASH_OPTKEYR ------------------------------
// SVD Line: 912
unsigned int FLASH_OPTKEYR __AT (0x4002200C);
// ---------------------------- Field Item: FLASH_OPTKEYR_OPTKEY --------------------------------
// SVD Line: 917
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Flash Option key
//
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0x0), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEYR ---------------------------------
// SVD Line: 912
// SFDITEM_REG__FLASH_OPTKEYR
// OPTKEYR
//
// [Bits 31..0] RW (@ 0x4002200C) Option byte key register
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 925
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 930
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 935
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protection error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 940
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and trimming bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 945
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RO (@ 0x40022010) Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 925
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) Status register
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x8011UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8011) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 953
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 958
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Page Program
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 963
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page Erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 968
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Mass Erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 973
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector Erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 978
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option bytes Programming Start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_PGSTRT ----------------------------------
// SVD Line: 983
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// PGSTRT
//
// [Bit 19] RW (@ 0x40022014) Programming Start
//
// ( (unsigned int) FLASH_CR )
// PGSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 988
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 993
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 998
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option bytes loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 1003
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Option Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 1008
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 953
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) Flash control register
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xCB0A0807UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCB0A0807) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 1015
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------- Field Item: FLASH_OPTR_RDP -----------------------------------
// SVD Line: 1020
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// RDP
//
// [Bits 7..0] RW (@ 0x40022020) Read Protection
//
// ( (unsigned char)((FLASH_OPTR >> 0) & 0xFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_BOR_EN ---------------------------------
// SVD Line: 1025
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// BOR_EN
//
// [Bit 8] RW (@ 0x40022020) BOR_EN
//
// ( (unsigned int) FLASH_OPTR )
// BOR_EN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BOR_LEV ---------------------------------
// SVD Line: 1029
// - SFDITEM_FIELD__FLASH_OPTR_BOR_LEV
// BOR_LEV
//
// [Bits 11..9] RW (@ 0x40022020) BOR_LEV
//
// ( (unsigned char)((FLASH_OPTR >> 9) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IWDG_SW ---------------------------------
// SVD Line: 1033
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// IWDG_SW
//
// [Bit 12] RW (@ 0x40022020) IWDG_SW
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_SW
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 1037
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 14] RW (@ 0x40022020) NRST_MODE
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_IWDG_STOP --------------------------------
// SVD Line: 1041
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
// IWDG_STOP
//
// [Bit 15] RW (@ 0x40022020) IWDG Software Enable
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_STOP
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 1015
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) Flash option register
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xDFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// - SFDITEM_FIELD__FLASH_OPTR_BOR_LEV
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
//
//
// ---------------------------- Register Item Address: FLASH_SDKR -------------------------------
// SVD Line: 1048
unsigned int FLASH_SDKR __AT (0x40022024);
// ----------------------------- Field Item: FLASH_SDKR_SDK_STRT --------------------------------
// SVD Line: 1053
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// SDK_STRT
//
// [Bits 3..0] RW (@ 0x40022024) SDK_STRT
//
// ( (unsigned char)((FLASH_SDKR >> 0) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_SDKR_SDK_END ---------------------------------
// SVD Line: 1057
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
// SDK_END
//
// [Bits 11..8] RW (@ 0x40022024) SDK_END
//
// ( (unsigned char)((FLASH_SDKR >> 8) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SDKR -----------------------------------
// SVD Line: 1048
// SFDITEM_REG__FLASH_SDKR
// SDKR
//
// [Bits 31..0] RW (@ 0x40022024) Flash SDK address register
// ( (unsigned int)((FLASH_SDKR >> 0) & 0xFFFFFFFF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xF0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 1063
unsigned int FLASH_WRPR __AT (0x4002202C);
// ------------------------------- Field Item: FLASH_WRPR_WRP -----------------------------------
// SVD Line: 1068
// - SFDITEM_FIELD__FLASH_WRPR_WRP
// WRP
//
// [Bits 15..0] RW (@ 0x4002202C) WRP
//
// ( (unsigned short)((FLASH_WRPR >> 0) & 0xFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 1063
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x4002202C) Flash WRP address register
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_WRP
//
//
// ---------------------------- Register Item Address: FLASH_STCR -------------------------------
// SVD Line: 1074
unsigned int FLASH_STCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_STCR_SLEEP_EN --------------------------------
// SVD Line: 1079
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) Sleep enable
//
// ( (unsigned int) FLASH_STCR )
// SLEEP_EN
//
//
//
// ------------------------------- Register RTree: FLASH_STCR -----------------------------------
// SVD Line: 1074
// SFDITEM_REG__FLASH_STCR
// STCR
//
// [Bits 31..0] RW (@ 0x40022090) Flash sleep time config register
// ( (unsigned int)((FLASH_STCR >> 0) & 0xFFFFFFFF), ((FLASH_STCR = (FLASH_STCR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 1086
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 1091
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 7..0] RW (@ 0x40022100) TS0
//
// ( (unsigned char)((FLASH_TS0 >> 0) & 0xFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 1086
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) Flash TS0 register
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 1098
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 1103
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 7..0] RW (@ 0x40022104) TS1
//
// ( (unsigned char)((FLASH_TS1 >> 0) & 0xFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 1098
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) Flash TS1 register
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 1110
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 1115
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 7..0] RW (@ 0x40022108) TS2P
//
// ( (unsigned char)((FLASH_TS2P >> 0) & 0xFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 1110
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) Flash TS2P register
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 1122
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 1127
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 9..0] RW (@ 0x4002210C) TPS3
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0x3FF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 1122
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) Flash TPS3 register
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 1134
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 1139
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 7..0] RW (@ 0x40022110) TS3
//
// ( (unsigned char)((FLASH_TS3 >> 0) & 0xFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 1134
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) Flash TS3 register
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_ERTPE -------------------------------
// SVD Line: 1146
unsigned int FLASH_ERTPE __AT (0x40022114);
// ------------------------------ Field Item: FLASH_ERTPE_ERTPE ---------------------------------
// SVD Line: 1150
// - SFDITEM_FIELD__FLASH_ERTPE_ERTPE
// ERTPE
//
// [Bits 15..0] RW (@ 0x40022114) ERTPE
//
// ( (unsigned short)((FLASH_ERTPE >> 0) & 0xFFFF), ((FLASH_ERTPE = (FLASH_ERTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_ERTPE ----------------------------------
// SVD Line: 1146
// SFDITEM_REG__FLASH_ERTPE
// ERTPE
//
// [Bits 31..0] RW (@ 0x40022114) ERTPE
// ( (unsigned int)((FLASH_ERTPE >> 0) & 0xFFFFFFFF), ((FLASH_ERTPE = (FLASH_ERTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ERTPE_ERTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 1157
unsigned int FLASH_PRGTPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 1162
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 15..0] RW (@ 0x4002211C) PRGTPE
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0xFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 1157
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x4002211C) Flash PRGTPE register
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 1169
unsigned int FLASH_PRETPE __AT (0x40022120);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 1174
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 13..0] RW (@ 0x40022120) PRETPE
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0x3FFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 1169
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x40022120) Flash PRETPE register
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 884
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_KEYR
// - SFDITEM_REG__FLASH_OPTKEYR
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_SDKR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_STCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_ERTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 1193
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 1198
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 1203
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 1208
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 1213
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 1218
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 1223
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 1228
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 1233
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 1193
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 1240
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 1245
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 1250
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 1255
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 1260
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 1265
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 1270
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 1275
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 1280
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 1240
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 1287
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1292
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1297
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1302
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1307
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1312
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1317
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1322
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1327
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 1287
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 1334
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1339
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1344
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1349
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1354
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1359
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1364
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1369
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1374
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 1334
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 1381
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 1386
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 1404
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 1410
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 1416
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 1422
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 1428
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 1381
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 1436
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 1441
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 1446
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 1451
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 1456
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 1461
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 1466
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 1471
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 1476
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 1436
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 1483
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 1488
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 1493
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 1498
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 1503
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 1508
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 1513
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 1518
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 1523
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 1528
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 1533
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 1538
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 1543
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 1548
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 1553
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 1558
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 1563
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 1483
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 1570
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 1575
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 1580
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 1585
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 1590
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 1595
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 1600
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 1605
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 1610
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 1615
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 1570
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 1622
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1627
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1632
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1637
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1642
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1647
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1652
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1657
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1662
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 1622
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 1669
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 1674
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 1679
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 1684
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 1689
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 1694
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 1699
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 1704
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 1709
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 1669
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 1183
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 1193
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 1198
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 1203
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 1208
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 1213
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE4 ---------------------------------
// SVD Line: 1218
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 8) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE5 ---------------------------------
// SVD Line: 1223
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 10) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE6 ---------------------------------
// SVD Line: 1228
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 12) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE7 ---------------------------------
// SVD Line: 1233
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 14) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 1193
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 1240
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 1245
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 1250
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 1255
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 1260
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT4 ----------------------------------
// SVD Line: 1265
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT5 ----------------------------------
// SVD Line: 1270
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT6 ----------------------------------
// SVD Line: 1275
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT7 ----------------------------------
// SVD Line: 1280
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT7
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 1240
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 1287
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1292
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1297
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1302
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1307
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1312
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 8) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1317
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 10) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1322
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 12) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1327
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 14) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 1287
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 1334
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1339
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1344
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1349
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1354
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1359
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 8) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1364
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 10) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1369
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 12) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1374
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 14) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 1334
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 1381
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 1386
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 1404
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID4 -----------------------------------
// SVD Line: 1410
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID5 -----------------------------------
// SVD Line: 1416
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID6 -----------------------------------
// SVD Line: 1422
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID7 -----------------------------------
// SVD Line: 1428
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID7
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 1381
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// - SFDITEM_FIELD__GPIOB_IDR_ID7
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 1436
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 1441
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 1446
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 1451
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 1456
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD4 -----------------------------------
// SVD Line: 1461
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD5 -----------------------------------
// SVD Line: 1466
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD6 -----------------------------------
// SVD Line: 1471
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD7 -----------------------------------
// SVD Line: 1476
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD7
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 1436
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// - SFDITEM_FIELD__GPIOB_ODR_OD7
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 1483
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 1488
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 1493
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 1498
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 1503
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS4 -----------------------------------
// SVD Line: 1508
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS5 -----------------------------------
// SVD Line: 1513
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS6 -----------------------------------
// SVD Line: 1518
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS7 -----------------------------------
// SVD Line: 1523
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 1528
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 1533
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 1538
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 1543
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR4 -----------------------------------
// SVD Line: 1548
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR5 -----------------------------------
// SVD Line: 1553
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR6 -----------------------------------
// SVD Line: 1558
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR7 -----------------------------------
// SVD Line: 1563
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR7
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 1483
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0xFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 1570
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 1575
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 1580
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 1585
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 1590
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK4 ----------------------------------
// SVD Line: 1595
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK5 ----------------------------------
// SVD Line: 1600
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK6 ----------------------------------
// SVD Line: 1605
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK7 ----------------------------------
// SVD Line: 1610
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 1615
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 1570
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 1622
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1627
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1632
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1637
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1642
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1647
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 16) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1652
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 20) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1657
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 24) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1662
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 28) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 1622
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 1669
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 1674
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 1679
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 1684
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 1689
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR4 -----------------------------------
// SVD Line: 1694
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR5 -----------------------------------
// SVD Line: 1699
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR6 -----------------------------------
// SVD Line: 1704
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR7 -----------------------------------
// SVD Line: 1709
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR7
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 1669
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// - SFDITEM_FIELD__GPIOB_BRR_BR7
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 1718
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOC_MODER -------------------------------
// SVD Line: 1193
unsigned int GPIOC_MODER __AT (0x50000800);
// ------------------------------ Field Item: GPIOC_MODER_MODE0 ---------------------------------
// SVD Line: 1198
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 0) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE1 ---------------------------------
// SVD Line: 1203
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 2) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE2 ---------------------------------
// SVD Line: 1208
// - SFDITEM_FIELD__GPIOC_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 4) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE3 ---------------------------------
// SVD Line: 1213
// - SFDITEM_FIELD__GPIOC_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 6) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE4 ---------------------------------
// SVD Line: 1218
// - SFDITEM_FIELD__GPIOC_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 8) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE5 ---------------------------------
// SVD Line: 1223
// - SFDITEM_FIELD__GPIOC_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 10) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE6 ---------------------------------
// SVD Line: 1228
// - SFDITEM_FIELD__GPIOC_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 12) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE7 ---------------------------------
// SVD Line: 1233
// - SFDITEM_FIELD__GPIOC_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 14) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_MODER ----------------------------------
// SVD Line: 1193
// SFDITEM_REG__GPIOC_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000800) GPIO port mode register
// ( (unsigned int)((GPIOC_MODER >> 0) & 0xFFFFFFFF), ((GPIOC_MODER = (GPIOC_MODER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
// - SFDITEM_FIELD__GPIOC_MODER_MODE2
// - SFDITEM_FIELD__GPIOC_MODER_MODE3
// - SFDITEM_FIELD__GPIOC_MODER_MODE4
// - SFDITEM_FIELD__GPIOC_MODER_MODE5
// - SFDITEM_FIELD__GPIOC_MODER_MODE6
// - SFDITEM_FIELD__GPIOC_MODER_MODE7
//
//
// --------------------------- Register Item Address: GPIOC_OTYPER ------------------------------
// SVD Line: 1240
unsigned int GPIOC_OTYPER __AT (0x50000804);
// ------------------------------ Field Item: GPIOC_OTYPER_OT0 ----------------------------------
// SVD Line: 1245
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT1 ----------------------------------
// SVD Line: 1250
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT2 ----------------------------------
// SVD Line: 1255
// - SFDITEM_FIELD__GPIOC_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT3 ----------------------------------
// SVD Line: 1260
// - SFDITEM_FIELD__GPIOC_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT4 ----------------------------------
// SVD Line: 1265
// - SFDITEM_FIELD__GPIOC_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT5 ----------------------------------
// SVD Line: 1270
// - SFDITEM_FIELD__GPIOC_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT6 ----------------------------------
// SVD Line: 1275
// - SFDITEM_FIELD__GPIOC_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT7 ----------------------------------
// SVD Line: 1280
// - SFDITEM_FIELD__GPIOC_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT7
//
//
//
// ------------------------------ Register RTree: GPIOC_OTYPER ----------------------------------
// SVD Line: 1240
// SFDITEM_REG__GPIOC_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000804) GPIO port output type register
// ( (unsigned int)((GPIOC_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOC_OTYPER = (GPIOC_OTYPER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
// - SFDITEM_FIELD__GPIOC_OTYPER_OT2
// - SFDITEM_FIELD__GPIOC_OTYPER_OT3
// - SFDITEM_FIELD__GPIOC_OTYPER_OT4
// - SFDITEM_FIELD__GPIOC_OTYPER_OT5
// - SFDITEM_FIELD__GPIOC_OTYPER_OT6
// - SFDITEM_FIELD__GPIOC_OTYPER_OT7
//
//
// -------------------------- Register Item Address: GPIOC_OSPEEDR ------------------------------
// SVD Line: 1287
unsigned int GPIOC_OSPEEDR __AT (0x50000808);
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1292
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 0) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1297
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 2) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1302
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 4) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1307
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 6) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1312
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 8) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1317
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 10) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1322
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 12) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1327
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 14) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOC_OSPEEDR ---------------------------------
// SVD Line: 1287
// SFDITEM_REG__GPIOC_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000808) GPIO port output speed register
// ( (unsigned int)((GPIOC_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED7
//
//
// --------------------------- Register Item Address: GPIOC_PUPDR -------------------------------
// SVD Line: 1334
unsigned int GPIOC_PUPDR __AT (0x5000080C);
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1339
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 0) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1344
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 2) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1349
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 4) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1354
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 6) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1359
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 8) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1364
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 10) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1369
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 12) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1374
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 14) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_PUPDR ----------------------------------
// SVD Line: 1334
// SFDITEM_REG__GPIOC_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000080C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOC_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD7
//
//
// ---------------------------- Register Item Address: GPIOC_IDR --------------------------------
// SVD Line: 1381
unsigned int GPIOC_IDR __AT (0x50000810);
// -------------------------------- Field Item: GPIOC_IDR_ID0 -----------------------------------
// SVD Line: 1386
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID1 -----------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__GPIOC_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID2 -----------------------------------
// SVD Line: 1398
// - SFDITEM_FIELD__GPIOC_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID3 -----------------------------------
// SVD Line: 1404
// - SFDITEM_FIELD__GPIOC_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID4 -----------------------------------
// SVD Line: 1410
// - SFDITEM_FIELD__GPIOC_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID5 -----------------------------------
// SVD Line: 1416
// - SFDITEM_FIELD__GPIOC_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID6 -----------------------------------
// SVD Line: 1422
// - SFDITEM_FIELD__GPIOC_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID7 -----------------------------------
// SVD Line: 1428
// - SFDITEM_FIELD__GPIOC_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID7
//
//
//
// -------------------------------- Register RTree: GPIOC_IDR -----------------------------------
// SVD Line: 1381
// SFDITEM_REG__GPIOC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000810) GPIO port input data register
// ( (unsigned int)((GPIOC_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// - SFDITEM_FIELD__GPIOC_IDR_ID1
// - SFDITEM_FIELD__GPIOC_IDR_ID2
// - SFDITEM_FIELD__GPIOC_IDR_ID3
// - SFDITEM_FIELD__GPIOC_IDR_ID4
// - SFDITEM_FIELD__GPIOC_IDR_ID5
// - SFDITEM_FIELD__GPIOC_IDR_ID6
// - SFDITEM_FIELD__GPIOC_IDR_ID7
//
//
// ---------------------------- Register Item Address: GPIOC_ODR --------------------------------
// SVD Line: 1436
unsigned int GPIOC_ODR __AT (0x50000814);
// -------------------------------- Field Item: GPIOC_ODR_OD0 -----------------------------------
// SVD Line: 1441
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD1 -----------------------------------
// SVD Line: 1446
// - SFDITEM_FIELD__GPIOC_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD2 -----------------------------------
// SVD Line: 1451
// - SFDITEM_FIELD__GPIOC_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD3 -----------------------------------
// SVD Line: 1456
// - SFDITEM_FIELD__GPIOC_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD4 -----------------------------------
// SVD Line: 1461
// - SFDITEM_FIELD__GPIOC_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD5 -----------------------------------
// SVD Line: 1466
// - SFDITEM_FIELD__GPIOC_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD6 -----------------------------------
// SVD Line: 1471
// - SFDITEM_FIELD__GPIOC_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD7 -----------------------------------
// SVD Line: 1476
// - SFDITEM_FIELD__GPIOC_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD7
//
//
//
// -------------------------------- Register RTree: GPIOC_ODR -----------------------------------
// SVD Line: 1436
// SFDITEM_REG__GPIOC_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000814) GPIO port output data register
// ( (unsigned int)((GPIOC_ODR >> 0) & 0xFFFFFFFF), ((GPIOC_ODR = (GPIOC_ODR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// - SFDITEM_FIELD__GPIOC_ODR_OD1
// - SFDITEM_FIELD__GPIOC_ODR_OD2
// - SFDITEM_FIELD__GPIOC_ODR_OD3
// - SFDITEM_FIELD__GPIOC_ODR_OD4
// - SFDITEM_FIELD__GPIOC_ODR_OD5
// - SFDITEM_FIELD__GPIOC_ODR_OD6
// - SFDITEM_FIELD__GPIOC_ODR_OD7
//
//
// ---------------------------- Register Item Address: GPIOC_BSRR -------------------------------
// SVD Line: 1483
unsigned int GPIOC_BSRR __AT (0x50000818);
// ------------------------------- Field Item: GPIOC_BSRR_BS0 -----------------------------------
// SVD Line: 1488
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS1 -----------------------------------
// SVD Line: 1493
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS2 -----------------------------------
// SVD Line: 1498
// - SFDITEM_FIELD__GPIOC_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS3 -----------------------------------
// SVD Line: 1503
// - SFDITEM_FIELD__GPIOC_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS4 -----------------------------------
// SVD Line: 1508
// - SFDITEM_FIELD__GPIOC_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS5 -----------------------------------
// SVD Line: 1513
// - SFDITEM_FIELD__GPIOC_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS6 -----------------------------------
// SVD Line: 1518
// - SFDITEM_FIELD__GPIOC_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS7 -----------------------------------
// SVD Line: 1523
// - SFDITEM_FIELD__GPIOC_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR0 -----------------------------------
// SVD Line: 1528
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR1 -----------------------------------
// SVD Line: 1533
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR2 -----------------------------------
// SVD Line: 1538
// - SFDITEM_FIELD__GPIOC_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR3 -----------------------------------
// SVD Line: 1543
// - SFDITEM_FIELD__GPIOC_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR4 -----------------------------------
// SVD Line: 1548
// - SFDITEM_FIELD__GPIOC_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR5 -----------------------------------
// SVD Line: 1553
// - SFDITEM_FIELD__GPIOC_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR6 -----------------------------------
// SVD Line: 1558
// - SFDITEM_FIELD__GPIOC_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR7 -----------------------------------
// SVD Line: 1563
// - SFDITEM_FIELD__GPIOC_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR7
//
//
//
// ------------------------------- Register RTree: GPIOC_BSRR -----------------------------------
// SVD Line: 1483
// SFDITEM_REG__GPIOC_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000818) GPIO port bit set/reset register
// ( (unsigned int)((GPIOC_BSRR >> 0) & 0xFFFFFFFF), ((GPIOC_BSRR = (GPIOC_BSRR & ~(0xFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// - SFDITEM_FIELD__GPIOC_BSRR_BS2
// - SFDITEM_FIELD__GPIOC_BSRR_BS3
// - SFDITEM_FIELD__GPIOC_BSRR_BS4
// - SFDITEM_FIELD__GPIOC_BSRR_BS5
// - SFDITEM_FIELD__GPIOC_BSRR_BS6
// - SFDITEM_FIELD__GPIOC_BSRR_BS7
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
// - SFDITEM_FIELD__GPIOC_BSRR_BR2
// - SFDITEM_FIELD__GPIOC_BSRR_BR3
// - SFDITEM_FIELD__GPIOC_BSRR_BR4
// - SFDITEM_FIELD__GPIOC_BSRR_BR5
// - SFDITEM_FIELD__GPIOC_BSRR_BR6
// - SFDITEM_FIELD__GPIOC_BSRR_BR7
//
//
// ---------------------------- Register Item Address: GPIOC_LCKR -------------------------------
// SVD Line: 1570
unsigned int GPIOC_LCKR __AT (0x5000081C);
// ------------------------------- Field Item: GPIOC_LCKR_LCK0 ----------------------------------
// SVD Line: 1575
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK1 ----------------------------------
// SVD Line: 1580
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK2 ----------------------------------
// SVD Line: 1585
// - SFDITEM_FIELD__GPIOC_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK3 ----------------------------------
// SVD Line: 1590
// - SFDITEM_FIELD__GPIOC_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK4 ----------------------------------
// SVD Line: 1595
// - SFDITEM_FIELD__GPIOC_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK5 ----------------------------------
// SVD Line: 1600
// - SFDITEM_FIELD__GPIOC_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK6 ----------------------------------
// SVD Line: 1605
// - SFDITEM_FIELD__GPIOC_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK7 ----------------------------------
// SVD Line: 1610
// - SFDITEM_FIELD__GPIOC_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCKK ----------------------------------
// SVD Line: 1615
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOC_LCKR -----------------------------------
// SVD Line: 1570
// SFDITEM_REG__GPIOC_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000081C) GPIO port configuration lock register
// ( (unsigned int)((GPIOC_LCKR >> 0) & 0xFFFFFFFF), ((GPIOC_LCKR = (GPIOC_LCKR & ~(0x100FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x100FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// - SFDITEM_FIELD__GPIOC_LCKR_LCK2
// - SFDITEM_FIELD__GPIOC_LCKR_LCK3
// - SFDITEM_FIELD__GPIOC_LCKR_LCK4
// - SFDITEM_FIELD__GPIOC_LCKR_LCK5
// - SFDITEM_FIELD__GPIOC_LCKR_LCK6
// - SFDITEM_FIELD__GPIOC_LCKR_LCK7
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOC_AFRL -------------------------------
// SVD Line: 1622
unsigned int GPIOC_AFRL __AT (0x50000820);
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1627
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 0) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1632
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 4) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1637
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 8) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1642
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 12) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1647
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 16) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1652
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 20) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1657
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 24) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1662
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 28) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_AFRL -----------------------------------
// SVD Line: 1622
// SFDITEM_REG__GPIOC_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000820) GPIO alternate function low register
// ( (unsigned int)((GPIOC_AFRL >> 0) & 0xFFFFFFFF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOC_BRR --------------------------------
// SVD Line: 1669
unsigned int GPIOC_BRR __AT (0x50000828);
// -------------------------------- Field Item: GPIOC_BRR_BR0 -----------------------------------
// SVD Line: 1674
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR1 -----------------------------------
// SVD Line: 1679
// - SFDITEM_FIELD__GPIOC_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR2 -----------------------------------
// SVD Line: 1684
// - SFDITEM_FIELD__GPIOC_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR3 -----------------------------------
// SVD Line: 1689
// - SFDITEM_FIELD__GPIOC_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR4 -----------------------------------
// SVD Line: 1694
// - SFDITEM_FIELD__GPIOC_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR5 -----------------------------------
// SVD Line: 1699
// - SFDITEM_FIELD__GPIOC_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR6 -----------------------------------
// SVD Line: 1704
// - SFDITEM_FIELD__GPIOC_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR7 -----------------------------------
// SVD Line: 1709
// - SFDITEM_FIELD__GPIOC_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR7
//
//
//
// -------------------------------- Register RTree: GPIOC_BRR -----------------------------------
// SVD Line: 1669
// SFDITEM_REG__GPIOC_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000828) port bit reset register
// ( (unsigned int)((GPIOC_BRR >> 0) & 0xFFFFFFFF), ((GPIOC_BRR = (GPIOC_BRR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// - SFDITEM_FIELD__GPIOC_BRR_BR1
// - SFDITEM_FIELD__GPIOC_BRR_BR2
// - SFDITEM_FIELD__GPIOC_BRR_BR3
// - SFDITEM_FIELD__GPIOC_BRR_BR4
// - SFDITEM_FIELD__GPIOC_BRR_BR5
// - SFDITEM_FIELD__GPIOC_BRR_BR6
// - SFDITEM_FIELD__GPIOC_BRR_BR7
//
//
// --------------------------------- Peripheral View: GPIOC -------------------------------------
// SVD Line: 1722
// GPIOC
// GPIOC
// - SFDITEM_REG__GPIOC_MODER
// - SFDITEM_REG__GPIOC_OTYPER
// - SFDITEM_REG__GPIOC_OSPEEDR
// - SFDITEM_REG__GPIOC_PUPDR
// - SFDITEM_REG__GPIOC_IDR
// - SFDITEM_REG__GPIOC_ODR
// - SFDITEM_REG__GPIOC_BSRR
// - SFDITEM_REG__GPIOC_LCKR
// - SFDITEM_REG__GPIOC_AFRL
// - SFDITEM_REG__GPIOC_BRR
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 1737
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 1742
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] RW (@ 0x40003000) Key value
//
// ( (unsigned short)((IWDG_KR >> 0) & 0xFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 1737
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] RW (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 1749
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 1754
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) Prescaler divider
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 1749
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 1761
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 1766
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) Watchdog counter reload value
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 1761
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 1773
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 1778
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 1784
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 1773
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RW (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 1727
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM1_ISR -------------------------------
// SVD Line: 1810
unsigned int LPTIM1_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM1_ISR_ARRM ----------------------------------
// SVD Line: 1815
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM1_ISR )
// ARRM
//
//
//
// ------------------------------ Field Item: LPTIM1_ISR_ARROK ----------------------------------
// SVD Line: 1821
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload match update OK
//
// ( (unsigned int) LPTIM1_ISR )
// ARROK
//
//
//
// ------------------------------- Register RTree: LPTIM1_ISR -----------------------------------
// SVD Line: 1810
// SFDITEM_REG__LPTIM1_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM1_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM1_ICR -------------------------------
// SVD Line: 1829
unsigned int LPTIM1_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM1_ICR_ARRMCF ---------------------------------
// SVD Line: 1834
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] RW (@ 0x40007C04) Autoreload match Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARRMCF
//
//
//
// ----------------------------- Field Item: LPTIM1_ICR_ARROKCF ---------------------------------
// SVD Line: 1839
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] RW (@ 0x40007C04) Autoreload match update OK Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARROKCF
//
//
//
// ------------------------------- Register RTree: LPTIM1_ICR -----------------------------------
// SVD Line: 1829
// SFDITEM_REG__LPTIM1_ICR
// ICR
//
// [Bits 31..0] RW (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM1_ICR >> 0) & 0xFFFFFFFF), ((LPTIM1_ICR = (LPTIM1_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM1_IER -------------------------------
// SVD Line: 1846
unsigned int LPTIM1_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM1_IER_ARRMIE ---------------------------------
// SVD Line: 1851
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload matchInterrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARRMIE
//
//
//
// ----------------------------- Field Item: LPTIM1_IER_ARROKIE ---------------------------------
// SVD Line: 1856
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload match update OK Interrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARROKIE
//
//
//
// ------------------------------- Register RTree: LPTIM1_IER -----------------------------------
// SVD Line: 1846
// SFDITEM_REG__LPTIM1_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM1_IER >> 0) & 0xFFFFFFFF), ((LPTIM1_IER = (LPTIM1_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
//
//
// --------------------------- Register Item Address: LPTIM1_CFGR -------------------------------
// SVD Line: 1863
unsigned int LPTIM1_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM1_CFGR_PRESC ---------------------------------
// SVD Line: 1868
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM1_CFGR >> 9) & 0x7), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM1_CFGR_PRELOAD --------------------------------
// SVD Line: 1873
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM1_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM1_CFGR ----------------------------------
// SVD Line: 1863
// SFDITEM_REG__LPTIM1_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM1_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
//
//
// ---------------------------- Register Item Address: LPTIM1_CR --------------------------------
// SVD Line: 1880
unsigned int LPTIM1_CR __AT (0x40007C10);
// ------------------------------ Field Item: LPTIM1_CR_ENABLE ----------------------------------
// SVD Line: 1885
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM Enable
//
// ( (unsigned int) LPTIM1_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_SNGSTRT ---------------------------------
// SVD Line: 1890
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in single mode
//
// ( (unsigned int) LPTIM1_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_CNTSTRT ---------------------------------
// SVD Line: 1895
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) CNTSTRT
//
// ( (unsigned int) LPTIM1_CR )
// CNTSTRT
//
//
//
// ----------------------------- Field Item: LPTIM1_CR_COUNTRST ---------------------------------
// SVD Line: 1900
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) Reset counter
//
// ( (unsigned int) LPTIM1_CR )
// COUNTRST
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_RSTARE ----------------------------------
// SVD Line: 1905
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM1_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM1_CR -----------------------------------
// SVD Line: 1880
// SFDITEM_REG__LPTIM1_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM1_CR >> 0) & 0xFFFFFFFF), ((LPTIM1_CR = (LPTIM1_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM1_ARR -------------------------------
// SVD Line: 1912
unsigned int LPTIM1_ARR __AT (0x40007C18);
// ------------------------------- Field Item: LPTIM1_ARR_ARR -----------------------------------
// SVD Line: 1917
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM1_ARR >> 0) & 0xFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPTIM1_ARR -----------------------------------
// SVD Line: 1912
// SFDITEM_REG__LPTIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM1_ARR >> 0) & 0xFFFFFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM1_CNT -------------------------------
// SVD Line: 1924
unsigned int LPTIM1_CNT __AT (0x40007C1C);
// ------------------------------- Field Item: LPTIM1_CNT_CNT -----------------------------------
// SVD Line: 1929
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM1_CNT >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: LPTIM1_CNT -----------------------------------
// SVD Line: 1924
// SFDITEM_REG__LPTIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM1_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM1 ------------------------------------
// SVD Line: 1794
// LPTIM1
// LPTIM1
// - SFDITEM_REG__LPTIM1_ISR
// - SFDITEM_REG__LPTIM1_ICR
// - SFDITEM_REG__LPTIM1_IER
// - SFDITEM_REG__LPTIM1_CFGR
// - SFDITEM_REG__LPTIM1_CR
// - SFDITEM_REG__LPTIM1_ARR
// - SFDITEM_REG__LPTIM1_CNT
//
//
// ----------------------------- Register Item Address: PWM_CR1 ---------------------------------
// SVD Line: 1953
unsigned int PWM_CR1 __AT (0x40002800);
// --------------------------------- Field Item: PWM_CR1_CEN ------------------------------------
// SVD Line: 1957
// - SFDITEM_FIELD__PWM_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002800) CEN
//
// ( (unsigned int) PWM_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: PWM_CR1_UDIS ------------------------------------
// SVD Line: 1961
// - SFDITEM_FIELD__PWM_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002800) UDIS
//
// ( (unsigned int) PWM_CR1 )
// UDIS
//
//
//
// --------------------------------- Field Item: PWM_CR1_URS ------------------------------------
// SVD Line: 1965
// - SFDITEM_FIELD__PWM_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002800) URS
//
// ( (unsigned int) PWM_CR1 )
// URS
//
//
//
// --------------------------------- Field Item: PWM_CR1_DIR ------------------------------------
// SVD Line: 1969
// - SFDITEM_FIELD__PWM_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40002800) DIR
//
// ( (unsigned int) PWM_CR1 )
// DIR
//
//
//
// --------------------------------- Field Item: PWM_CR1_CMS ------------------------------------
// SVD Line: 1973
// - SFDITEM_FIELD__PWM_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40002800) CMS
//
// ( (unsigned char)((PWM_CR1 >> 5) & 0x3), ((PWM_CR1 = (PWM_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: PWM_CR1_ARPE ------------------------------------
// SVD Line: 1977
// - SFDITEM_FIELD__PWM_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002800) ARPE
//
// ( (unsigned int) PWM_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: PWM_CR1_LEDEN -----------------------------------
// SVD Line: 1981
// - SFDITEM_FIELD__PWM_CR1_LEDEN
// LEDEN
//
// [Bit 16] RW (@ 0x40002800) LEDEN
//
// ( (unsigned int) PWM_CR1 )
// LEDEN
//
//
//
// ------------------------------- Field Item: PWM_CR1_LEDCEN -----------------------------------
// SVD Line: 1985
// - SFDITEM_FIELD__PWM_CR1_LEDCEN
// LEDCEN
//
// [Bit 17] RW (@ 0x40002800) LEDCEN
//
// ( (unsigned int) PWM_CR1 )
// LEDCEN
//
//
//
// ------------------------------- Field Item: PWM_CR1_LEDWORD ----------------------------------
// SVD Line: 1989
// - SFDITEM_FIELD__PWM_CR1_LEDWORD
// LEDWORD
//
// [Bits 19..18] RW (@ 0x40002800) LEDWORD
//
// ( (unsigned char)((PWM_CR1 >> 18) & 0x3), ((PWM_CR1 = (PWM_CR1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWM_CR1 ------------------------------------
// SVD Line: 1953
// SFDITEM_REG__PWM_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002800) CR1
// ( (unsigned int)((PWM_CR1 >> 0) & 0xFFFFFFFF), ((PWM_CR1 = (PWM_CR1 & ~(0xF00F7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF00F7) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_CR1_CEN
// - SFDITEM_FIELD__PWM_CR1_UDIS
// - SFDITEM_FIELD__PWM_CR1_URS
// - SFDITEM_FIELD__PWM_CR1_DIR
// - SFDITEM_FIELD__PWM_CR1_CMS
// - SFDITEM_FIELD__PWM_CR1_ARPE
// - SFDITEM_FIELD__PWM_CR1_LEDEN
// - SFDITEM_FIELD__PWM_CR1_LEDCEN
// - SFDITEM_FIELD__PWM_CR1_LEDWORD
//
//
// ----------------------------- Register Item Address: PWM_DIER --------------------------------
// SVD Line: 1995
unsigned int PWM_DIER __AT (0x4000280C);
// -------------------------------- Field Item: PWM_DIER_UIE ------------------------------------
// SVD Line: 1999
// - SFDITEM_FIELD__PWM_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000280C) UIE
//
// ( (unsigned int) PWM_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: PWM_DIER_OC1IE -----------------------------------
// SVD Line: 2003
// - SFDITEM_FIELD__PWM_DIER_OC1IE
// OC1IE
//
// [Bit 1] RW (@ 0x4000280C) OC1IE
//
// ( (unsigned int) PWM_DIER )
// OC1IE
//
//
//
// ----------------------------- Field Item: PWM_DIER_LED1_ENDIE --------------------------------
// SVD Line: 2007
// - SFDITEM_FIELD__PWM_DIER_LED1_ENDIE
// LED1_ENDIE
//
// [Bit 16] RW (@ 0x4000280C) LED1_ENDIE
//
// ( (unsigned int) PWM_DIER )
// LED1_ENDIE
//
//
//
// -------------------------------- Register RTree: PWM_DIER ------------------------------------
// SVD Line: 1995
// SFDITEM_REG__PWM_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000280C) DIER
// ( (unsigned int)((PWM_DIER >> 0) & 0xFFFFFFFF), ((PWM_DIER = (PWM_DIER & ~(0x10003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x10003) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_DIER_UIE
// - SFDITEM_FIELD__PWM_DIER_OC1IE
// - SFDITEM_FIELD__PWM_DIER_LED1_ENDIE
//
//
// ------------------------------ Register Item Address: PWM_SR ---------------------------------
// SVD Line: 2013
unsigned int PWM_SR __AT (0x40002810);
// --------------------------------- Field Item: PWM_SR_UIF -------------------------------------
// SVD Line: 2017
// - SFDITEM_FIELD__PWM_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002810) UIF
//
// ( (unsigned int) PWM_SR )
// UIF
//
//
//
// -------------------------------- Field Item: PWM_SR_OC1IF ------------------------------------
// SVD Line: 2021
// - SFDITEM_FIELD__PWM_SR_OC1IF
// OC1IF
//
// [Bit 1] RW (@ 0x40002810) OC1IF
//
// ( (unsigned int) PWM_SR )
// OC1IF
//
//
//
// ------------------------------ Field Item: PWM_SR_LED1_ENDIF ---------------------------------
// SVD Line: 2025
// - SFDITEM_FIELD__PWM_SR_LED1_ENDIF
// LED1_ENDIF
//
// [Bit 16] RW (@ 0x40002810) LED1_ENDIF
//
// ( (unsigned int) PWM_SR )
// LED1_ENDIF
//
//
//
// --------------------------------- Register RTree: PWM_SR -------------------------------------
// SVD Line: 2013
// SFDITEM_REG__PWM_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002810) SR
// ( (unsigned int)((PWM_SR >> 0) & 0xFFFFFFFF), ((PWM_SR = (PWM_SR & ~(0x10003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x10003) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_SR_UIF
// - SFDITEM_FIELD__PWM_SR_OC1IF
// - SFDITEM_FIELD__PWM_SR_LED1_ENDIF
//
//
// ----------------------------- Register Item Address: PWM_EGR ---------------------------------
// SVD Line: 2031
unsigned int PWM_EGR __AT (0x40002814);
// --------------------------------- Field Item: PWM_EGR_UG -------------------------------------
// SVD Line: 2035
// - SFDITEM_FIELD__PWM_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40002814) UG
//
// ( (unsigned int) PWM_EGR )
// UG
//
//
//
// --------------------------------- Register RTree: PWM_EGR ------------------------------------
// SVD Line: 2031
// SFDITEM_REG__PWM_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40002814) EGR
// ( (unsigned int)((PWM_EGR >> 0) & 0xFFFFFFFF), ((PWM_EGR = (PWM_EGR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_EGR_UG
//
//
// ----------------------------- Register Item Address: PWM_CMR ---------------------------------
// SVD Line: 2041
unsigned int PWM_CMR __AT (0x40002818);
// -------------------------------- Field Item: PWM_CMR_OC1M ------------------------------------
// SVD Line: 2045
// - SFDITEM_FIELD__PWM_CMR_OC1M
// OC1M
//
// [Bits 1..0] RW (@ 0x40002818) OC1M
//
// ( (unsigned char)((PWM_CMR >> 0) & 0x3), ((PWM_CMR = (PWM_CMR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: PWM_CMR_OC1PE -----------------------------------
// SVD Line: 2049
// - SFDITEM_FIELD__PWM_CMR_OC1PE
// OC1PE
//
// [Bit 8] RW (@ 0x40002818) OC1PE
//
// ( (unsigned int) PWM_CMR )
// OC1PE
//
//
//
// --------------------------------- Register RTree: PWM_CMR ------------------------------------
// SVD Line: 2041
// SFDITEM_REG__PWM_CMR
// CMR
//
// [Bits 31..0] RW (@ 0x40002818) CMR
// ( (unsigned int)((PWM_CMR >> 0) & 0xFFFFFFFF), ((PWM_CMR = (PWM_CMR & ~(0x103UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x103) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_CMR_OC1M
// - SFDITEM_FIELD__PWM_CMR_OC1PE
//
//
// ----------------------------- Register Item Address: PWM_CER ---------------------------------
// SVD Line: 2055
unsigned int PWM_CER __AT (0x40002820);
// --------------------------------- Field Item: PWM_CER_C1E ------------------------------------
// SVD Line: 2059
// - SFDITEM_FIELD__PWM_CER_C1E
// C1E
//
// [Bit 0] RW (@ 0x40002820) C1E
//
// ( (unsigned int) PWM_CER )
// C1E
//
//
//
// --------------------------------- Field Item: PWM_CER_C1P ------------------------------------
// SVD Line: 2063
// - SFDITEM_FIELD__PWM_CER_C1P
// C1P
//
// [Bit 1] RW (@ 0x40002820) C1P
//
// ( (unsigned int) PWM_CER )
// C1P
//
//
//
// --------------------------------- Register RTree: PWM_CER ------------------------------------
// SVD Line: 2055
// SFDITEM_REG__PWM_CER
// CER
//
// [Bits 31..0] RW (@ 0x40002820) CER
// ( (unsigned int)((PWM_CER >> 0) & 0xFFFFFFFF), ((PWM_CER = (PWM_CER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_CER_C1E
// - SFDITEM_FIELD__PWM_CER_C1P
//
//
// ----------------------------- Register Item Address: PWM_CNT ---------------------------------
// SVD Line: 2069
unsigned int PWM_CNT __AT (0x40002824);
// --------------------------------- Field Item: PWM_CNT_CNT ------------------------------------
// SVD Line: 2073
// - SFDITEM_FIELD__PWM_CNT_CNT
// CNT
//
// [Bits 9..0] RW (@ 0x40002824) CNT
//
// ( (unsigned short)((PWM_CNT >> 0) & 0x3FF), ((PWM_CNT = (PWM_CNT & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWM_CNT ------------------------------------
// SVD Line: 2069
// SFDITEM_REG__PWM_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002824) CNT
// ( (unsigned int)((PWM_CNT >> 0) & 0xFFFFFFFF), ((PWM_CNT = (PWM_CNT & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_CNT_CNT
//
//
// ----------------------------- Register Item Address: PWM_PSC ---------------------------------
// SVD Line: 2079
unsigned int PWM_PSC __AT (0x40002828);
// --------------------------------- Field Item: PWM_PSC_PSC ------------------------------------
// SVD Line: 2083
// - SFDITEM_FIELD__PWM_PSC_PSC
// PSC
//
// [Bits 7..0] RW (@ 0x40002828) PSC
//
// ( (unsigned char)((PWM_PSC >> 0) & 0xFF), ((PWM_PSC = (PWM_PSC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWM_PSC ------------------------------------
// SVD Line: 2079
// SFDITEM_REG__PWM_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002828) PSC
// ( (unsigned int)((PWM_PSC >> 0) & 0xFFFFFFFF), ((PWM_PSC = (PWM_PSC & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_PSC_PSC
//
//
// ----------------------------- Register Item Address: PWM_ARR ---------------------------------
// SVD Line: 2089
unsigned int PWM_ARR __AT (0x4000282C);
// --------------------------------- Field Item: PWM_ARR_ARR ------------------------------------
// SVD Line: 2093
// - SFDITEM_FIELD__PWM_ARR_ARR
// ARR
//
// [Bits 9..0] RW (@ 0x4000282C) ARR
//
// ( (unsigned short)((PWM_ARR >> 0) & 0x3FF), ((PWM_ARR = (PWM_ARR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWM_ARR ------------------------------------
// SVD Line: 2089
// SFDITEM_REG__PWM_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000282C) ARR
// ( (unsigned int)((PWM_ARR >> 0) & 0xFFFFFFFF), ((PWM_ARR = (PWM_ARR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_ARR_ARR
//
//
// ----------------------------- Register Item Address: PWM_CCR1 --------------------------------
// SVD Line: 2099
unsigned int PWM_CCR1 __AT (0x40002834);
// -------------------------------- Field Item: PWM_CCR1_CCR1 -----------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__PWM_CCR1_CCR1
// CCR1
//
// [Bits 9..0] RW (@ 0x40002834) CCR1
//
// ( (unsigned short)((PWM_CCR1 >> 0) & 0x3FF), ((PWM_CCR1 = (PWM_CCR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: PWM_CCR1 ------------------------------------
// SVD Line: 2099
// SFDITEM_REG__PWM_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002834) CCR1
// ( (unsigned int)((PWM_CCR1 >> 0) & 0xFFFFFFFF), ((PWM_CCR1 = (PWM_CCR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_CCR1_CCR1
//
//
// -------------------------- Register Item Address: PWM_LED1_DATA ------------------------------
// SVD Line: 2109
unsigned int PWM_LED1_DATA __AT (0x40002850);
// --------------------------- Field Item: PWM_LED1_DATA_LED1_DATA ------------------------------
// SVD Line: 2113
// - SFDITEM_FIELD__PWM_LED1_DATA_LED1_DATA
// LED1_DATA
//
// [Bits 23..0] RW (@ 0x40002850) LED1_DATA
//
// ( (unsigned int)((PWM_LED1_DATA >> 0) & 0xFFFFFF), ((PWM_LED1_DATA = (PWM_LED1_DATA & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: PWM_LED1_DATA ---------------------------------
// SVD Line: 2109
// SFDITEM_REG__PWM_LED1_DATA
// LED1_DATA
//
// [Bits 31..0] RW (@ 0x40002850) LED1_DATA
// ( (unsigned int)((PWM_LED1_DATA >> 0) & 0xFFFFFFFF), ((PWM_LED1_DATA = (PWM_LED1_DATA & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__PWM_LED1_DATA_LED1_DATA
//
//
// ---------------------------------- Peripheral View: PWM --------------------------------------
// SVD Line: 1939
// PWM
// PWM
// - SFDITEM_REG__PWM_CR1
// - SFDITEM_REG__PWM_DIER
// - SFDITEM_REG__PWM_SR
// - SFDITEM_REG__PWM_EGR
// - SFDITEM_REG__PWM_CMR
// - SFDITEM_REG__PWM_CER
// - SFDITEM_REG__PWM_CNT
// - SFDITEM_REG__PWM_PSC
// - SFDITEM_REG__PWM_ARR
// - SFDITEM_REG__PWM_CCR1
// - SFDITEM_REG__PWM_LED1_DATA
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 2136
unsigned int PWR_CR1 __AT (0x40007000);
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 2141
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) FLS_SLPTIME
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: PWR_CR1_VR_MODE ----------------------------------
// SVD Line: 2145
// - SFDITEM_FIELD__PWR_CR1_VR_MODE
// VR_MODE
//
// [Bits 15..14] RW (@ 0x40007000) VR_MODE
//
// ( (unsigned char)((PWR_CR1 >> 14) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_HSION_CTRL ---------------------------------
// SVD Line: 2149
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
// HSION_CTRL
//
// [Bit 22] RW (@ 0x40007000) HSION_CTRL
//
// ( (unsigned int) PWR_CR1 )
// HSION_CTRL
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 2136
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0x40F000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x40F000) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_VR_MODE
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
//
//
// ----------------------------- Register Item Address: PWR_CR2 ---------------------------------
// SVD Line: 2155
unsigned int PWR_CR2 __AT (0x40007004);
// -------------------------------- Field Item: PWR_CR2_PVDE ------------------------------------
// SVD Line: 2159
// - SFDITEM_FIELD__PWR_CR2_PVDE
// PVDE
//
// [Bit 0] RW (@ 0x40007004) PVDE
//
// ( (unsigned int) PWR_CR2 )
// PVDE
//
//
//
// -------------------------------- Field Item: PWR_CR2_PVDT ------------------------------------
// SVD Line: 2163
// - SFDITEM_FIELD__PWR_CR2_PVDT
// PVDT
//
// [Bits 6..4] RW (@ 0x40007004) PVDT
//
// ( (unsigned char)((PWR_CR2 >> 4) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR2_PVD_OUT_SEL --------------------------------
// SVD Line: 2167
// - SFDITEM_FIELD__PWR_CR2_PVD_OUT_SEL
// PVD_OUT_SEL
//
// [Bit 7] RW (@ 0x40007004) PVD_OUT_SEL
//
// ( (unsigned int) PWR_CR2 )
// PVD_OUT_SEL
//
//
//
// -------------------------------- Field Item: PWR_CR2_FLTEN -----------------------------------
// SVD Line: 2171
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// FLTEN
//
// [Bit 8] RW (@ 0x40007004) FLTEN
//
// ( (unsigned int) PWR_CR2 )
// FLTEN
//
//
//
// ------------------------------ Field Item: PWR_CR2_FLT_TIME ----------------------------------
// SVD Line: 2175
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
// FLT_TIME
//
// [Bits 11..9] RW (@ 0x40007004) FLT_TIME
//
// ( (unsigned char)((PWR_CR2 >> 9) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWR_CR2 ------------------------------------
// SVD Line: 2155
// SFDITEM_REG__PWR_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40007004) CR2
// ( (unsigned int)((PWR_CR2 >> 0) & 0xFFFFFFFF), ((PWR_CR2 = (PWR_CR2 & ~(0xFF1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR2_PVDE
// - SFDITEM_FIELD__PWR_CR2_PVDT
// - SFDITEM_FIELD__PWR_CR2_PVD_OUT_SEL
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
//
//
// ------------------------------ Register Item Address: PWR_SR ---------------------------------
// SVD Line: 2181
unsigned int PWR_SR __AT (0x40007010);
// --------------------------------- Field Item: PWR_SR_PVDO ------------------------------------
// SVD Line: 2185
// - SFDITEM_FIELD__PWR_SR_PVDO
// PVDO
//
// [Bit 11] RO (@ 0x40007010) PVDO
//
// ( (unsigned int) PWR_SR )
// PVDO
//
//
//
// --------------------------------- Register RTree: PWR_SR -------------------------------------
// SVD Line: 2181
// SFDITEM_REG__PWR_SR
// SR
//
// [Bits 31..0] RW (@ 0x40007010) SR
// ( (unsigned int)((PWR_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__PWR_SR_PVDO
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 2121
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
// - SFDITEM_REG__PWR_CR2
// - SFDITEM_REG__PWR_SR
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 2209
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 2214
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI clock enable bit
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 2219
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RO (@ 0x40021000) HSI clock ready logo
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 2225
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI generates the crossover factor when HSISYS clocks
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEON ------------------------------------
// SVD Line: 2230
// - SFDITEM_FIELD__RCC_CR_HSEON
// HSEON
//
// [Bit 18] RW (@ 0x40021000) HSEON
//
// ( (unsigned int) RCC_CR )
// HSEON
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 2209
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0x43900UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x43900) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// - SFDITEM_FIELD__RCC_CR_HSEON
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 2236
unsigned int RCC_ICSCR __AT (0x40021004);
// -------------------------- Field Item: RCC_ICSCR_HSI_ABS_TRIMCR ------------------------------
// SVD Line: 2241
// - SFDITEM_FIELD__RCC_ICSCR_HSI_ABS_TRIMCR
// HSI_ABS_TRIMCR
//
// [Bits 11..0] RW (@ 0x40021004) Clock frequency calibration value
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0xFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: RCC_ICSCR_HSI_TC_TRIMCR ------------------------------
// SVD Line: 2246
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TC_TRIMCR
// HSI_TC_TRIMCR
//
// [Bits 15..12] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 12) & 0xF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 2251
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bit 16] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned int) RCC_ICSCR )
// HSI_FS
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 2256
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 27..19] RW (@ 0x40021004) LSI_TRIM
//
// ( (unsigned short)((RCC_ICSCR >> 19) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 19 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 19 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 2236
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibration register
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFF9FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF9FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_ABS_TRIMCR
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TC_TRIMCR
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 2262
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 2267
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 2272
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 2277
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) The AHB clock HCLK is based on the crossover coefficient of SYSCLK
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 2282
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB clock division factor
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 2287
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 26..24] RW (@ 0x40021008) MCO output clock selection
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 2292
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 30..28] RW (@ 0x40021008) Microprocessor output clock (MCO) divider factor
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 2262
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0x77007F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77007F3F) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 2299
unsigned int RCC_ECSCR __AT (0x40021010);
// ---------------------------- Field Item: RCC_ECSCR_LSE_DRIVER --------------------------------
// SVD Line: 2304
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// LSE_DRIVER
//
// [Bits 17..16] RW (@ 0x40021010) LSE drive capability setting
//
// ( (unsigned char)((RCC_ECSCR >> 16) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_STARTUP -------------------------------
// SVD Line: 2309
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
// LSE_STARTUP
//
// [Bits 21..20] RW (@ 0x40021010) LSE crystal oscillator stabilization time selection
//
// ( (unsigned char)((RCC_ECSCR >> 20) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 2299
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x330000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x330000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 2316
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_LSERDYIE ---------------------------------
// SVD Line: 2326
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// LSERDYIE
//
// [Bit 1] RW (@ 0x40021018) LSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 2331
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 2316
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enable register
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 2338
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 2343
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSERDYF ----------------------------------
// SVD Line: 2349
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// LSERDYF
//
// [Bit 1] RO (@ 0x4002101C) LSE clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 2355
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSECSSF ----------------------------------
// SVD Line: 2361
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
// LSECSSF
//
// [Bit 9] RO (@ 0x4002101C) LSE Clock Security System (CSS) interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSECSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 2338
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RW (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 2369
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 2374
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] WO (@ 0x40021020) The LSI ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSERDYC ----------------------------------
// SVD Line: 2380
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// LSERDYC
//
// [Bit 1] WO (@ 0x40021020) The LSE ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 2386
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] WO (@ 0x40021020) The HSI ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSECSSC ----------------------------------
// SVD Line: 2392
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
// LSECSSC
//
// [Bit 9] WO (@ 0x40021020) The LSE Clock Security System (CSS) interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSECSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 2369
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] RW (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x20BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x20B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 2400
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 2405
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O PortA reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 2410
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O PortB reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOCRST --------------------------------
// SVD Line: 2415
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
// GPIOCRST
//
// [Bit 2] RW (@ 0x40021024) I/O PortC reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOCRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 2400
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 2422
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// ---------------------------- Field Item: RCC_APBRSTR1_UARTRST --------------------------------
// SVD Line: 2427
// - SFDITEM_FIELD__RCC_APBRSTR1_UARTRST
// UARTRST
//
// [Bit 18] RW (@ 0x4002102C) The UART module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// UARTRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 2432
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) The MCU Debug module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 2437
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) The Power interface module is reset.
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_LPTIMRST -------------------------------
// SVD Line: 2442
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
// LPTIMRST
//
// [Bit 31] RW (@ 0x4002102C) LPTIMRST
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPTIMRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 2422
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APB peripheral reset register 1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0x98040000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98040000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_UARTRST
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 2448
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 2453
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) The SYSCFG module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_PWMRST --------------------------------
// SVD Line: 2458
// - SFDITEM_FIELD__RCC_APBRSTR2_PWMRST
// PWMRST
//
// [Bit 9] RW (@ 0x40021030) The PWM module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// PWMRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 2463
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) The TIM1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 2468
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) The TIM14 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_ADCRST --------------------------------
// SVD Line: 2473
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// ADCRST
//
// [Bit 20] RW (@ 0x40021030) The ADC block is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// ADCRST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR2_VREFBUFRST ------------------------------
// SVD Line: 2478
// - SFDITEM_FIELD__RCC_APBRSTR2_VREFBUFRST
// VREFBUFRST
//
// [Bit 26] RW (@ 0x40021030) VREFBUFRST
//
// ( (unsigned int) RCC_APBRSTR2 )
// VREFBUFRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 2448
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register 2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x4108A01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4108A01) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_PWMRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// - SFDITEM_FIELD__RCC_APBRSTR2_VREFBUFRST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 2484
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 2489
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O PortA clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 2494
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O PortB clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOCEN ---------------------------------
// SVD Line: 2499
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
// GPIOCEN
//
// [Bit 2] RW (@ 0x40021034) I/O PortC clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOCEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 2484
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 2506
unsigned int RCC_AHBENR __AT (0x40021038);
// ----------------------------- Field Item: RCC_AHBENR_FLASHEN ---------------------------------
// SVD Line: 2511
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// FLASHEN
//
// [Bit 8] RW (@ 0x40021038) FLASHEN
//
// ( (unsigned int) RCC_AHBENR )
// FLASHEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_SRAMEN ---------------------------------
// SVD Line: 2515
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// SRAMEN
//
// [Bit 9] RW (@ 0x40021038) SRAMEN
//
// ( (unsigned int) RCC_AHBENR )
// SRAMEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 2506
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enable register
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x300UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x300) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 2521
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ----------------------------- Field Item: RCC_APBENR1_UARTEN ---------------------------------
// SVD Line: 2526
// - SFDITEM_FIELD__RCC_APBENR1_UARTEN
// UARTEN
//
// [Bit 18] RW (@ 0x4002103C) The UART module clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// UARTEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 2531
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) MCU Debug module clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 2536
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) The Power interface module clock enables
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_LPTIMEN --------------------------------
// SVD Line: 2541
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
// LPTIMEN
//
// [Bit 31] RW (@ 0x4002103C) LPTIMEN
//
// ( (unsigned int) RCC_APBENR1 )
// LPTIMEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 2521
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register 1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0x98040000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98040000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_UARTEN
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 2547
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 2552
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) The SYSCFG module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_PWMEN ---------------------------------
// SVD Line: 2557
// - SFDITEM_FIELD__RCC_APBENR2_PWMEN
// PWMEN
//
// [Bit 9] RW (@ 0x40021040) The PWM module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// PWMEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 2562
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) The TIM1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 2567
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 module clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_ADCEN ---------------------------------
// SVD Line: 2572
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// ADCEN
//
// [Bit 20] RW (@ 0x40021040) ADC block clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// ADCEN
//
//
//
// ---------------------------- Field Item: RCC_APBENR2_VREFBUFEN -------------------------------
// SVD Line: 2577
// - SFDITEM_FIELD__RCC_APBENR2_VREFBUFEN
// VREFBUFEN
//
// [Bit 26] RW (@ 0x40021040) VREFBUFEN
//
// ( (unsigned int) RCC_APBENR2 )
// VREFBUFEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 2547
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register 2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x4108A01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4108A01) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_PWMEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// - SFDITEM_FIELD__RCC_APBENR2_VREFBUFEN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 2583
unsigned int RCC_CCIPR __AT (0x40021054);
// ------------------------------ Field Item: RCC_CCIPR_PVDSEL ----------------------------------
// SVD Line: 2588
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// PVDSEL
//
// [Bit 7] RW (@ 0x40021054) PVD module clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// PVDSEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_LPTIM1SEL --------------------------------
// SVD Line: 2593
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// LPTIM1SEL
//
// [Bits 19..18] RW (@ 0x40021054) LPTIM1SEL
//
// ( (unsigned char)((RCC_CCIPR >> 18) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 2583
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configuration register
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xC0080UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC0080) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 2599
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_LSEON -----------------------------------
// SVD Line: 2604
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// LSEON
//
// [Bit 0] RW (@ 0x4002105C) LSE OSC enabled
//
// ( (unsigned int) RCC_BDCR )
// LSEON
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSERDY ----------------------------------
// SVD Line: 2609
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// LSERDY
//
// [Bit 1] RW (@ 0x4002105C) LSE OSC ready
//
// ( (unsigned int) RCC_BDCR )
// LSERDY
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSEBYP ----------------------------------
// SVD Line: 2614
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// LSEBYP
//
// [Bit 2] RW (@ 0x4002105C) LSE OSC bypass
//
// ( (unsigned int) RCC_BDCR )
// LSEBYP
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSON ---------------------------------
// SVD Line: 2619
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// LSECSSON
//
// [Bit 5] RW (@ 0x4002105C) LSE CSS enables
//
// ( (unsigned int) RCC_BDCR )
// LSECSSON
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSD ----------------------------------
// SVD Line: 2624
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// LSECSSD
//
// [Bit 6] RW (@ 0x4002105C) LSE CSS (clock security system) detection failed
//
// ( (unsigned int) RCC_BDCR )
// LSECSSD
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCSEL ----------------------------------
// SVD Line: 2629
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
// LSCSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock selection
//
// ( (unsigned int) RCC_BDCR )
// LSCSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 2599
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x2000067UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2000067) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 2636
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 2641
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI OSC enabled
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 2646
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RO (@ 0x40021060) LSI OSC stability flag
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// ---------------------------- Field Item: RCC_CSR_PINRST_FLTDIS -------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// PINRST_FLTDIS
//
// [Bit 8] RW (@ 0x40021060) NRST filtering is prohibited
//
// ( (unsigned int) RCC_CSR )
// PINRST_FLTDIS
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Clear the reset flag
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 2662
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RO (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 2668
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RO (@ 0x40021060) External NRST pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PORRSTF ----------------------------------
// SVD Line: 2674
// - SFDITEM_FIELD__RCC_CSR_PORRSTF
// PORRSTF
//
// [Bit 27] RO (@ 0x40021060) POR reset flag
//
// ( (unsigned int) RCC_CSR )
// PORRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 2680
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RO (@ 0x40021060) Soft reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 2686
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RO (@ 0x40021060) IWDG reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 2636
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x800101UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800101) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PORRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 2194
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 2706
unsigned int SYSCFG_CFGR2 __AT (0x40010018);
// -------------------------- Field Item: SYSCFG_CFGR2_LOCKUP_LOCK ------------------------------
// SVD Line: 2711
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// LOCKUP_LOCK
//
// [Bit 0] RW (@ 0x40010018) Cortex-M0+ LOCKUP bit enable bit
//
// ( (unsigned int) SYSCFG_CFGR2 )
// LOCKUP_LOCK
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR2_PVD_LOCK -------------------------------
// SVD Line: 2716
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVD_LOCK
// PVD_LOCK
//
// [Bit 2] RW (@ 0x40010018) PVD LOCK selection
//
// ( (unsigned int) SYSCFG_CFGR2 )
// PVD_LOCK
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 2706
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010018) SYSCFG configuration register 2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVD_LOCK
//
//
// ------------------------- Register Item Address: SYSCFG_GPIO_ENS -----------------------------
// SVD Line: 2723
unsigned int SYSCFG_GPIO_ENS __AT (0x4001001C);
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PA_ENS -------------------------------
// SVD Line: 2728
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// PA_ENS
//
// [Bits 7..0] RW (@ 0x4001001C) desc PA_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 0) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PB_ENS -------------------------------
// SVD Line: 2733
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// PB_ENS
//
// [Bits 15..8] RW (@ 0x4001001C) desc PB_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 8) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PC_ENS -------------------------------
// SVD Line: 2738
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
// PC_ENS
//
// [Bits 17..16] RW (@ 0x4001001C) desc PC_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 16) & 0x3), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_GPIO_ENS --------------------------------
// SVD Line: 2723
// SFDITEM_REG__SYSCFG_GPIO_ENS
// GPIO_ENS
//
// [Bits 31..0] RW (@ 0x4001001C) desc GPIO_ENS
// ( (unsigned int)((SYSCFG_GPIO_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 2696
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_GPIO_ENS
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 2768
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 2773
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) desc CEN
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 2778
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) desc UDIS
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 2783
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) desc URS
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 2788
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) desc OPM
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 2793
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) desc DIR
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 2798
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) desc CMS
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 2803
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) desc ARPE
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 2808
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) desc CKD
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 2768
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) desc CR1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 2815
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 2820
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) desc CCPC
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 2825
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) desc CCUS
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_MMS ------------------------------------
// SVD Line: 2830
// - SFDITEM_FIELD__TIM1_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40012C04) desc MMS
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 2835
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) desc TI1S
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 2840
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) desc OIS1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 2845
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) desc OIS1N
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 2850
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) desc OIS2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 2855
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) desc OIS2N
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 2860
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) desc OIS3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 2865
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) desc OIS3N
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 2870
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) desc OIS4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 2815
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) desc CR2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7FF5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF5) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_MMS
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 2877
unsigned int TIM1_SMCR __AT (0x40012C08);
// -------------------------------- Field Item: TIM1_SMCR_SMS -----------------------------------
// SVD Line: 2882
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40012C08) desc SMS
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 2887
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) desc OCCS
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_TS ------------------------------------
// SVD Line: 2892
// - SFDITEM_FIELD__TIM1_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40012C08) desc TS
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 2897
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) desc MSM
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 2902
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) desc ETF
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 2907
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) desc ETPS
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 2912
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) desc ECE
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 2917
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) desc ETP
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 2877
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) desc SMCR
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 2924
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 2929
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) desc UIE
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 2934
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) desc CC1IE
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 2939
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) desc CC2IE
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 2944
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) desc CC3IE
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 2949
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) desc CC4IE
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 2954
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) desc COMIE
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 2959
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) desc TIE
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 2964
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) desc BIE
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 2924
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) desc DIER
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 2971
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 2976
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) desc UIF
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 2981
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) desc CC1IF
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 2986
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) desc CC2IF
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 2991
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) desc CC3IF
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 2996
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) desc CC4IF
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 3001
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) desc COMIF
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 3006
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) desc TIF
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 3011
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) desc BIF
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 3016
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) desc CC1OF
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 3021
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) desc CC2OF
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 3026
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) desc CC3OF
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 3031
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) desc CC4OF
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 3036
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40012C10) desc IC1IR
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 3041
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 17] RW (@ 0x40012C10) desc IC2IR
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 3046
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 18] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 3051
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 19] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 3056
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40012C10) desc IC1IF
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 3061
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 21] RW (@ 0x40012C10) desc IC2IF
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 3066
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 22] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 3071
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 23] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 2971
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) desc SR
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0xFF1EFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1EFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 3078
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 3083
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40012C14) desc UG
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 3088
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40012C14) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 3093
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40012C14) desc CC2G
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 3098
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40012C14) desc CC3G
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 3103
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40012C14) desc CC4G
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 3108
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40012C14) desc COMG
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 3113
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40012C14) desc TG
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 3118
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40012C14) desc BG
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 3078
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40012C14) desc EGR
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_OUTPUT ----------------------------
// SVD Line: 3125
unsigned int TIM1_CCMR1_OUTPUT __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 3130
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 0) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 3135
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) desc OC1FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 3140
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) desc OC1PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M -------------------------------
// SVD Line: 3145
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40012C18) desc OC1M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 4) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 3150
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) desc OC1CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 3155
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 8) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 3160
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) desc OC2FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 3165
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) desc OC2PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M -------------------------------
// SVD Line: 3170
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40012C18) desc OC2M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 12) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 3175
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) desc OC2CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_OUTPUT -------------------------------
// SVD Line: 3125
// SFDITEM_REG__TIM1_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:OUTPUT
// ( (unsigned int)((TIM1_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_INPUT ----------------------------
// SVD Line: 3182
unsigned int TIM1_CCMR1_INPUT __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 3188
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 0) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 3193
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40012C18) desc IC1PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 2) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 3198
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) desc IC1F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 4) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 3203
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 8) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 3208
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) desc IC2PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 10) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 3213
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) desc IC2F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 12) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_INPUT --------------------------------
// SVD Line: 3182
// SFDITEM_REG__TIM1_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:INPUT
// ( (unsigned int)((TIM1_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_OUTPUT ----------------------------
// SVD Line: 3220
unsigned int TIM1_CCMR2_OUTPUT __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 3225
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 0) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 3230
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) desc OC3FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 3235
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) desc OC3PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M -------------------------------
// SVD Line: 3240
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x40012C1C) desc OC3M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 4) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 3245
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) desc OC3CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 3250
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 8) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 3255
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) desc OC4FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 3260
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) desc OC4PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M -------------------------------
// SVD Line: 3265
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x40012C1C) desc OC4M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 12) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 3270
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) desc OC4CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_OUTPUT -------------------------------
// SVD Line: 3220
// SFDITEM_REG__TIM1_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:OUTPUT
// ( (unsigned int)((TIM1_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_INPUT ----------------------------
// SVD Line: 3277
unsigned int TIM1_CCMR2_INPUT __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 3283
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 0) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 3288
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) desc IC3PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 2) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 3293
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) desc IC3F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 4) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 3298
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 8) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 3303
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) desc IC4PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 10) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 3308
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) desc IC4F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 12) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_INPUT --------------------------------
// SVD Line: 3277
// SFDITEM_REG__TIM1_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:INPUT
// ( (unsigned int)((TIM1_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 3315
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 3320
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) desc CC1E
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 3325
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) desc CC1P
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 3330
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) desc CC1NE
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 3335
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) desc CC1NP
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 3340
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) desc CC2E
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 3345
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) desc CC2P
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 3350
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) desc CC2NE
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 3355
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) desc CC2NP
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 3360
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) desc CC3E
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 3365
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) desc CC3P
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 3370
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) desc CC3NE
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 3375
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) desc CC3NP
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 3380
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) desc CC4E
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 3385
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) desc CC4P
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 3315
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) desc CCER
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 3392
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 3397
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) desc CNT
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 3392
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) desc CNT
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 3404
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 3409
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) desc PSC
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 3404
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) desc PSC
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 3416
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 3421
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) desc ARR
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 3416
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) desc ARR
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 3428
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 3433
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) desc REP
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 3428
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) desc RCR
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 3440
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 3445
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) desc CCR1
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR1_CCR1_H ----------------------------------
// SVD Line: 3450
// - SFDITEM_FIELD__TIM1_CCR1_CCR1_H
// CCR1_H
//
// [Bits 31..16] RW (@ 0x40012C34) desc CCR1_H
//
// ( (unsigned short)((TIM1_CCR1 >> 16) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 3440
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) desc CCR1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// - SFDITEM_FIELD__TIM1_CCR1_CCR1_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 3457
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 3462
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) desc CCR2
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR2_CCR2_H ----------------------------------
// SVD Line: 3467
// - SFDITEM_FIELD__TIM1_CCR2_CCR2_H
// CCR2_H
//
// [Bits 31..16] RW (@ 0x40012C38) desc CCR2_H
//
// ( (unsigned short)((TIM1_CCR2 >> 16) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 3457
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) desc CCR2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// - SFDITEM_FIELD__TIM1_CCR2_CCR2_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 3474
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 3479
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) desc CCR3
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR3_CCR3_H ----------------------------------
// SVD Line: 3484
// - SFDITEM_FIELD__TIM1_CCR3_CCR3_H
// CCR3_H
//
// [Bits 31..16] RW (@ 0x40012C3C) desc CCR3_H
//
// ( (unsigned short)((TIM1_CCR3 >> 16) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 3474
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) desc CCR3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// - SFDITEM_FIELD__TIM1_CCR3_CCR3_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 3491
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 3496
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) desc CCR4
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 3491
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) desc CCR4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 3503
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 3508
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) desc DTG
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 3513
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) desc LOCK
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 3518
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) desc OSSI
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 3523
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) desc OSSR
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 3528
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) desc BKE
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 3533
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) desc BKP
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 3538
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) desc AOE
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 3543
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) desc MOE
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 3503
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) desc BDTR
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ---------------------------- Register Item Address: TIM1_TISEL -------------------------------
// SVD Line: 3550
unsigned int TIM1_TISEL __AT (0x40012C5C);
// ------------------------------ Field Item: TIM1_TISEL_TI1SEL ---------------------------------
// SVD Line: 3554
// - SFDITEM_FIELD__TIM1_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x40012C5C) desc TI1SEL
//
// ( (unsigned char)((TIM1_TISEL >> 0) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI2SEL ---------------------------------
// SVD Line: 3559
// - SFDITEM_FIELD__TIM1_TISEL_TI2SEL
// TI2SEL
//
// [Bits 11..8] RW (@ 0x40012C5C) desc TI2SEL
//
// ( (unsigned char)((TIM1_TISEL >> 8) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI3SEL ---------------------------------
// SVD Line: 3564
// - SFDITEM_FIELD__TIM1_TISEL_TI3SEL
// TI3SEL
//
// [Bits 19..16] RW (@ 0x40012C5C) desc TI3SEL
//
// ( (unsigned char)((TIM1_TISEL >> 16) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI4SEL ---------------------------------
// SVD Line: 3569
// - SFDITEM_FIELD__TIM1_TISEL_TI4SEL
// TI4SEL
//
// [Bits 27..24] RW (@ 0x40012C5C) desc TI4SEL
//
// ( (unsigned char)((TIM1_TISEL >> 24) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM1_TISEL -----------------------------------
// SVD Line: 3550
// SFDITEM_REG__TIM1_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x40012C5C) TISEL
// ( (unsigned int)((TIM1_TISEL >> 0) & 0xFFFFFFFF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xF0F0F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F0F0F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_TISEL_TI1SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI2SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI3SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI4SEL
//
//
// ----------------------------- Register Item Address: TIM1_AF1 --------------------------------
// SVD Line: 3576
unsigned int TIM1_AF1 __AT (0x40012C60);
// ------------------------------- Field Item: TIM1_AF1_BKINE -----------------------------------
// SVD Line: 3580
// - SFDITEM_FIELD__TIM1_AF1_BKINE
// BKINE
//
// [Bit 0] RW (@ 0x40012C60) desc BKINE
//
// ( (unsigned int) TIM1_AF1 )
// BKINE
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP1E ----------------------------------
// SVD Line: 3585
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1E
// BKCMP1E
//
// [Bit 1] RW (@ 0x40012C60) desc BKCMP1E
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP1E
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP2E ----------------------------------
// SVD Line: 3590
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2E
// BKCMP2E
//
// [Bit 2] RW (@ 0x40012C60) desc BKCMP2E
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP2E
//
//
//
// ------------------------------- Field Item: TIM1_AF1_BKINP -----------------------------------
// SVD Line: 3595
// - SFDITEM_FIELD__TIM1_AF1_BKINP
// BKINP
//
// [Bit 9] RW (@ 0x40012C60) desc BKINP
//
// ( (unsigned int) TIM1_AF1 )
// BKINP
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP1P ----------------------------------
// SVD Line: 3600
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1P
// BKCMP1P
//
// [Bit 10] RW (@ 0x40012C60) desc BKCMP1P
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP1P
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP2P ----------------------------------
// SVD Line: 3605
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2P
// BKCMP2P
//
// [Bit 11] RW (@ 0x40012C60) desc BKCMP2P
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP2P
//
//
//
// ------------------------------- Field Item: TIM1_AF1_ETRSEL ----------------------------------
// SVD Line: 3610
// - SFDITEM_FIELD__TIM1_AF1_ETRSEL
// ETRSEL
//
// [Bits 17..14] RW (@ 0x40012C60) desc ETRSEL
//
// ( (unsigned char)((TIM1_AF1 >> 14) & 0xF), ((TIM1_AF1 = (TIM1_AF1 & ~(0xFUL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_AF1_INTR_SEL ---------------------------------
// SVD Line: 3615
// - SFDITEM_FIELD__TIM1_AF1_INTR_SEL
// INTR_SEL
//
// [Bits 19..18] RW (@ 0x40012C60) desc INTR_SEL
//
// ( (unsigned char)((TIM1_AF1 >> 18) & 0x3), ((TIM1_AF1 = (TIM1_AF1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM1_AF1_PWM_PHS_EN --------------------------------
// SVD Line: 3620
// - SFDITEM_FIELD__TIM1_AF1_PWM_PHS_EN
// PWM_PHS_EN
//
// [Bit 20] RW (@ 0x40012C60) desc PWM_PHS_EN
//
// ( (unsigned int) TIM1_AF1 )
// PWM_PHS_EN
//
//
//
// -------------------------------- Register RTree: TIM1_AF1 ------------------------------------
// SVD Line: 3576
// SFDITEM_REG__TIM1_AF1
// AF1
//
// [Bits 31..0] RW (@ 0x40012C60) AF1
// ( (unsigned int)((TIM1_AF1 >> 0) & 0xFFFFFFFF), ((TIM1_AF1 = (TIM1_AF1 & ~(0x1FCE07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FCE07) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_AF1_BKINE
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1E
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2E
// - SFDITEM_FIELD__TIM1_AF1_BKINP
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1P
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2P
// - SFDITEM_FIELD__TIM1_AF1_ETRSEL
// - SFDITEM_FIELD__TIM1_AF1_INTR_SEL
// - SFDITEM_FIELD__TIM1_AF1_PWM_PHS_EN
//
//
// ----------------------------- Register Item Address: TIM1_AF2 --------------------------------
// SVD Line: 3627
unsigned int TIM1_AF2 __AT (0x40012C64);
// ------------------------------- Field Item: TIM1_AF2_OCRSEL ----------------------------------
// SVD Line: 3631
// - SFDITEM_FIELD__TIM1_AF2_OCRSEL
// OCRSEL
//
// [Bits 18..16] RW (@ 0x40012C64) desc OCRSEL
//
// ( (unsigned char)((TIM1_AF2 >> 16) & 0x7), ((TIM1_AF2 = (TIM1_AF2 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_AF2 ------------------------------------
// SVD Line: 3627
// SFDITEM_REG__TIM1_AF2
// AF2
//
// [Bits 31..0] RW (@ 0x40012C64) AF2
// ( (unsigned int)((TIM1_AF2 >> 0) & 0xFFFFFFFF), ((TIM1_AF2 = (TIM1_AF2 & ~(0x70000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70000) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_AF2_OCRSEL
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 2747
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_OUTPUT
// - SFDITEM_REG__TIM1_CCMR1_INPUT
// - SFDITEM_REG__TIM1_CCMR2_OUTPUT
// - SFDITEM_REG__TIM1_CCMR2_INPUT
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
// - SFDITEM_REG__TIM1_TISEL
// - SFDITEM_REG__TIM1_AF1
// - SFDITEM_REG__TIM1_AF2
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 3655
unsigned int TIM14_CR1 __AT (0x40002400);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 3659
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002400) desc CEN
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 3664
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002400) desc UDIS
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 3669
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002400) desc URS
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_OPM -----------------------------------
// SVD Line: 3674
// - SFDITEM_FIELD__TIM14_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40002400) desc OPM
//
// ( (unsigned int) TIM14_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 3679
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002400) desc ARPE
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 3684
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002400) desc CKD
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 3655
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002400) CR1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_OPM
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 3691
unsigned int TIM14_DIER __AT (0x4000240C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 3695
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000240C) desc UIE
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 3700
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000240C) desc CC1IE
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 3691
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000240C) DIER
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 3707
unsigned int TIM14_SR __AT (0x40002410);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 3711
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002410) desc UIF
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 3716
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002410) desc CC1IF
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 3721
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002410) desc CC1OF
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IR -----------------------------------
// SVD Line: 3726
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40002410) desc IC1IR
//
// ( (unsigned int) TIM14_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IF -----------------------------------
// SVD Line: 3731
// - SFDITEM_FIELD__TIM14_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40002410) desc IC1IF
//
// ( (unsigned int) TIM14_SR )
// IC1IF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 3707
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002410) SR
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x110203UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x110203) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// - SFDITEM_FIELD__TIM14_SR_IC1IF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 3738
unsigned int TIM14_EGR __AT (0x40002414);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 3742
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40002414) desc UG
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 3747
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40002414) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 3738
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40002414) EGR
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_OUTPUT ---------------------------
// SVD Line: 3754
unsigned int TIM14_CCMR1_OUTPUT __AT (0x40002418);
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 3758
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002418) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 0) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 3763
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002418) desc OC1PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M ------------------------------
// SVD Line: 3768
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40002418) desc OC1M
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 4) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_OUTPUT -------------------------------
// SVD Line: 3754
// SFDITEM_REG__TIM14_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40002418) CCMR1_OUTPUT
// ( (unsigned int)((TIM14_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7B) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_INPUT ----------------------------
// SVD Line: 3775
unsigned int TIM14_CCMR1_INPUT __AT (0x40002418);
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 3780
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002418) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 0) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 3785
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002418) desc IC1PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 2) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 3790
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002418) desc IC1F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 4) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_INPUT -------------------------------
// SVD Line: 3775
// SFDITEM_REG__TIM14_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40002418) CCMR1_INPUT
// ( (unsigned int)((TIM14_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 3797
unsigned int TIM14_CCER __AT (0x40002420);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 3801
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002420) desc CC1E
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 3806
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002420) desc CC1P
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 3811
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002420) desc CC1NP
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 3797
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002420) CCER
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 3818
unsigned int TIM14_CNT __AT (0x40002424);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 3822
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002424) desc CNT
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 3818
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002424) CNT
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 3829
unsigned int TIM14_PSC __AT (0x40002428);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 3833
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002428) desc PSC
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 3829
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002428) PSC
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 3840
unsigned int TIM14_ARR __AT (0x4000242C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 3844
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000242C) desc ARR
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 3840
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000242C) ARR
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 3851
unsigned int TIM14_CCR1 __AT (0x40002434);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 3855
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002434) desc CCR1
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 3851
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002434) CCR1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// --------------------------- Register Item Address: TIM14_TISEL -------------------------------
// SVD Line: 3862
unsigned int TIM14_TISEL __AT (0x4000245C);
// ----------------------------- Field Item: TIM14_TISEL_TI1SEL ---------------------------------
// SVD Line: 3866
// - SFDITEM_FIELD__TIM14_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x4000245C) desc TI1SEL
//
// ( (unsigned char)((TIM14_TISEL >> 0) & 0xF), ((TIM14_TISEL = (TIM14_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_TISEL ----------------------------------
// SVD Line: 3862
// SFDITEM_REG__TIM14_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x4000245C) TISEL
// ( (unsigned int)((TIM14_TISEL >> 0) & 0xFFFFFFFF), ((TIM14_TISEL = (TIM14_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_TISEL_TI1SEL
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 3640
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_OUTPUT
// - SFDITEM_REG__TIM14_CCMR1_INPUT
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_TISEL
//
//
// ----------------------------- Register Item Address: UART1_DR --------------------------------
// SVD Line: 3890
unsigned int UART1_DR __AT (0x40004800);
// --------------------------------- Field Item: UART1_DR_DR ------------------------------------
// SVD Line: 3894
// - SFDITEM_FIELD__UART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004800) Receive/send data register
//
// ( (unsigned short)((UART1_DR >> 0) & 0x1FF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_DR ------------------------------------
// SVD Line: 3890
// SFDITEM_REG__UART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004800) DR
// ( (unsigned int)((UART1_DR >> 0) & 0xFFFFFFFF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_DR_DR
//
//
// ---------------------------- Register Item Address: UART1_BRR --------------------------------
// SVD Line: 3901
unsigned int UART1_BRR __AT (0x40004804);
// -------------------------------- Field Item: UART1_BRR_BRR -----------------------------------
// SVD Line: 3905
// - SFDITEM_FIELD__UART1_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40004804) Baud rate register
//
// ( (unsigned short)((UART1_BRR >> 0) & 0xFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_BRR -----------------------------------
// SVD Line: 3901
// SFDITEM_REG__UART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004804) BRR
// ( (unsigned int)((UART1_BRR >> 0) & 0xFFFFFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART1_SR --------------------------------
// SVD Line: 3912
unsigned int UART1_SR __AT (0x40004810);
// -------------------------------- Field Item: UART1_SR_RXNE -----------------------------------
// SVD Line: 3916
// - SFDITEM_FIELD__UART1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40004810) Receive register not empty
//
// ( (unsigned int) UART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART1_SR_ORE ------------------------------------
// SVD Line: 3922
// - SFDITEM_FIELD__UART1_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40004810) Overrun error bit
//
// ( (unsigned int) UART1_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART1_SR_PE ------------------------------------
// SVD Line: 3927
// - SFDITEM_FIELD__UART1_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40004810) Parity Error bit
//
// ( (unsigned int) UART1_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART1_SR_FE ------------------------------------
// SVD Line: 3932
// - SFDITEM_FIELD__UART1_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40004810) Framing Error bit
//
// ( (unsigned int) UART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART1_SR_BRI ------------------------------------
// SVD Line: 3937
// - SFDITEM_FIELD__UART1_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40004810) Break Interrupt bit
//
// ( (unsigned int) UART1_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART1_SR_TDRE -----------------------------------
// SVD Line: 3942
// - SFDITEM_FIELD__UART1_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40004810) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART1_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART1_SR_TXE ------------------------------------
// SVD Line: 3948
// - SFDITEM_FIELD__UART1_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40004810) Transmitter Empty bit
//
// ( (unsigned int) UART1_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART1_SR_ADDR_RCVD ---------------------------------
// SVD Line: 3954
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40004810) Address Received Bit
//
// ( (unsigned int) UART1_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART1_SR_BUSY -----------------------------------
// SVD Line: 3959
// - SFDITEM_FIELD__UART1_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40004810) UART Busy
//
// ( (unsigned int) UART1_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART1_SR_BUSY_ERR ---------------------------------
// SVD Line: 3965
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40004810) Busy Detect Error
//
// ( (unsigned int) UART1_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART1_SR ------------------------------------
// SVD Line: 3912
// SFDITEM_REG__UART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004810) SR
// ( (unsigned int)((UART1_SR >> 0) & 0xFFFFFFFF), ((UART1_SR = (UART1_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_SR_RXNE
// - SFDITEM_FIELD__UART1_SR_ORE
// - SFDITEM_FIELD__UART1_SR_PE
// - SFDITEM_FIELD__UART1_SR_FE
// - SFDITEM_FIELD__UART1_SR_BRI
// - SFDITEM_FIELD__UART1_SR_TDRE
// - SFDITEM_FIELD__UART1_SR_TXE
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART1_SR_BUSY
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART1_CR1 --------------------------------
// SVD Line: 3972
unsigned int UART1_CR1 __AT (0x40004814);
// --------------------------------- Field Item: UART1_CR1_M ------------------------------------
// SVD Line: 3976
// - SFDITEM_FIELD__UART1_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40004814) Data Length Select
//
// ( (unsigned char)((UART1_CR1 >> 0) & 0x3), ((UART1_CR1 = (UART1_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART1_CR1_STOP -----------------------------------
// SVD Line: 3981
// - SFDITEM_FIELD__UART1_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40004814) Number of stop bits
//
// ( (unsigned int) UART1_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART1_CR1_PCE -----------------------------------
// SVD Line: 3986
// - SFDITEM_FIELD__UART1_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40004814) Parity Enable
//
// ( (unsigned int) UART1_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART1_CR1_PS ------------------------------------
// SVD Line: 3991
// - SFDITEM_FIELD__UART1_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40004814) Even Parity Select
//
// ( (unsigned int) UART1_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART1_CR1_SP ------------------------------------
// SVD Line: 3996
// - SFDITEM_FIELD__UART1_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40004814) Stick Parity
//
// ( (unsigned int) UART1_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART1_CR1_SBK -----------------------------------
// SVD Line: 4001
// - SFDITEM_FIELD__UART1_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40004814) Send Break
//
// ( (unsigned int) UART1_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART1_CR1_SWAP -----------------------------------
// SVD Line: 4006
// - SFDITEM_FIELD__UART1_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40004814) TX/RX pin swap
//
// ( (unsigned int) UART1_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART1_CR1_MSBFIRST ---------------------------------
// SVD Line: 4011
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40004814) MSB first mode
//
// ( (unsigned int) UART1_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART1_CR1 -----------------------------------
// SVD Line: 3972
// SFDITEM_REG__UART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40004814) CR1
// ( (unsigned int)((UART1_CR1 >> 0) & 0xFFFFFFFF), ((UART1_CR1 = (UART1_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR1_M
// - SFDITEM_FIELD__UART1_CR1_STOP
// - SFDITEM_FIELD__UART1_CR1_PCE
// - SFDITEM_FIELD__UART1_CR1_PS
// - SFDITEM_FIELD__UART1_CR1_SP
// - SFDITEM_FIELD__UART1_CR1_SBK
// - SFDITEM_FIELD__UART1_CR1_SWAP
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART1_CR2 --------------------------------
// SVD Line: 4018
unsigned int UART1_CR2 __AT (0x40004818);
// ------------------------------ Field Item: UART1_CR2_RXNEIE ----------------------------------
// SVD Line: 4022
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40004818) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART1_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART1_CR2_TDREIE ----------------------------------
// SVD Line: 4027
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40004818) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART1_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART1_CR2_LSIE -----------------------------------
// SVD Line: 4032
// - SFDITEM_FIELD__UART1_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40004818) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART1_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART1_CR2_BUSYERRIE --------------------------------
// SVD Line: 4037
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40004818) Enable Busyerr state interruption
//
// ( (unsigned int) UART1_CR2 )
// BUSYERRIE
//
//
//
// ------------------------------- Field Item: UART1_CR2_TXEIE ----------------------------------
// SVD Line: 4042
// - SFDITEM_FIELD__UART1_CR2_TXEIE
// TXEIE
//
// [Bit 4] RW (@ 0x40004818) Enable tx empty interruption
//
// ( (unsigned int) UART1_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: UART1_CR2 -----------------------------------
// SVD Line: 4018
// SFDITEM_REG__UART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004818) CR2
// ( (unsigned int)((UART1_CR2 >> 0) & 0xFFFFFFFF), ((UART1_CR2 = (UART1_CR2 & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// - SFDITEM_FIELD__UART1_CR2_LSIE
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
// - SFDITEM_FIELD__UART1_CR2_TXEIE
//
//
// ---------------------------- Register Item Address: UART1_CR3 --------------------------------
// SVD Line: 4049
unsigned int UART1_CR3 __AT (0x4000481C);
// -------------------------------- Field Item: UART1_CR3_M_E -----------------------------------
// SVD Line: 4053
// - SFDITEM_FIELD__UART1_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x4000481C) Extension for DLS
//
// ( (unsigned int) UART1_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART1_CR3_ADDR_MATCH --------------------------------
// SVD Line: 4058
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x4000481C) Address Match Mode
//
// ( (unsigned int) UART1_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART1_CR3_SEND_ADDR --------------------------------
// SVD Line: 4063
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x4000481C) Send address control bit
//
// ( (unsigned int) UART1_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART1_CR3_TX_MODE ---------------------------------
// SVD Line: 4068
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x4000481C) Transmit mode control bit
//
// ( (unsigned int) UART1_CR3 )
// TX_MODE
//
//
//
// ------------------------------- Field Item: UART1_CR3_DMAR -----------------------------------
// SVD Line: 4073
// - SFDITEM_FIELD__UART1_CR3_DMAR
// DMAR
//
// [Bit 4] RW (@ 0x4000481C) DMA receive enable
//
// ( (unsigned int) UART1_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: UART1_CR3_DMAT -----------------------------------
// SVD Line: 4078
// - SFDITEM_FIELD__UART1_CR3_DMAT
// DMAT
//
// [Bit 5] RW (@ 0x4000481C) DMA transmit enable
//
// ( (unsigned int) UART1_CR3 )
// DMAT
//
//
//
// --------------------------- Field Item: UART1_CR3_DMA_SOFT_ACK -------------------------------
// SVD Line: 4083
// - SFDITEM_FIELD__UART1_CR3_DMA_SOFT_ACK
// DMA_SOFT_ACK
//
// [Bit 6] RW (@ 0x4000481C) DMA software ack
//
// ( (unsigned int) UART1_CR3 )
// DMA_SOFT_ACK
//
//
//
// -------------------------------- Register RTree: UART1_CR3 -----------------------------------
// SVD Line: 4049
// SFDITEM_REG__UART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x4000481C) CR3
// ( (unsigned int)((UART1_CR3 >> 0) & 0xFFFFFFFF), ((UART1_CR3 = (UART1_CR3 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR3_M_E
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
// - SFDITEM_FIELD__UART1_CR3_DMAR
// - SFDITEM_FIELD__UART1_CR3_DMAT
// - SFDITEM_FIELD__UART1_CR3_DMA_SOFT_ACK
//
//
// ---------------------------- Register Item Address: UART1_RAR --------------------------------
// SVD Line: 4090
unsigned int UART1_RAR __AT (0x40004820);
// -------------------------------- Field Item: UART1_RAR_RAR -----------------------------------
// SVD Line: 4094
// - SFDITEM_FIELD__UART1_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40004820) Receive address matching register
//
// ( (unsigned char)((UART1_RAR >> 0) & 0xFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_RAR -----------------------------------
// SVD Line: 4090
// SFDITEM_REG__UART1_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40004820) RAR
// ( (unsigned int)((UART1_RAR >> 0) & 0xFFFFFFFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART1_TAR --------------------------------
// SVD Line: 4101
unsigned int UART1_TAR __AT (0x40004824);
// -------------------------------- Field Item: UART1_TAR_TAR -----------------------------------
// SVD Line: 4105
// - SFDITEM_FIELD__UART1_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40004824) Transmit address matching register
//
// ( (unsigned char)((UART1_TAR >> 0) & 0xFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_TAR -----------------------------------
// SVD Line: 4101
// SFDITEM_REG__UART1_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40004824) TAR
// ( (unsigned int)((UART1_TAR >> 0) & 0xFFFFFFFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_TAR_TAR
//
//
// ---------------------------- Register Item Address: UART1_BRRF -------------------------------
// SVD Line: 4112
unsigned int UART1_BRRF __AT (0x40004828);
// ------------------------------- Field Item: UART1_BRRF_BRRF ----------------------------------
// SVD Line: 4116
// - SFDITEM_FIELD__UART1_BRRF_BRRF
// BRRF
//
// [Bits 3..0] RW (@ 0x40004828) Baud rate fractional register
//
// ( (unsigned char)((UART1_BRRF >> 0) & 0xF), ((UART1_BRRF = (UART1_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: UART1_BRRF -----------------------------------
// SVD Line: 4112
// SFDITEM_REG__UART1_BRRF
// BRRF
//
// [Bits 31..0] RW (@ 0x40004828) BRRF
// ( (unsigned int)((UART1_BRRF >> 0) & 0xFFFFFFFF), ((UART1_BRRF = (UART1_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_BRRF_BRRF
//
//
// --------------------------------- Peripheral View: UART1 -------------------------------------
// SVD Line: 3875
// UART1
// UART1
// - SFDITEM_REG__UART1_DR
// - SFDITEM_REG__UART1_BRR
// - SFDITEM_REG__UART1_SR
// - SFDITEM_REG__UART1_CR1
// - SFDITEM_REG__UART1_CR2
// - SFDITEM_REG__UART1_CR3
// - SFDITEM_REG__UART1_RAR
// - SFDITEM_REG__UART1_TAR
// - SFDITEM_REG__UART1_BRRF
//
//
// ----------------------------- Register Item Address: VREF_CR ---------------------------------
// SVD Line: 4134
unsigned int VREF_CR __AT (0x40010100);
// --------------------------- Field Item: VREF_CR_VREFBUF_OUT_SEL ------------------------------
// SVD Line: 4138
// - SFDITEM_FIELD__VREF_CR_VREFBUF_OUT_SEL
// VREFBUF_OUT_SEL
//
// [Bits 1..0] RW (@ 0x40010100) VREFBUF_OUT_SEL
//
// ( (unsigned char)((VREF_CR >> 0) & 0x3), ((VREF_CR = (VREF_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: VREF_CR_VREFBUF_EN ---------------------------------
// SVD Line: 4142
// - SFDITEM_FIELD__VREF_CR_VREFBUF_EN
// VREFBUF_EN
//
// [Bit 3] RW (@ 0x40010100) VREFBUF_EN
//
// ( (unsigned int) VREF_CR )
// VREFBUF_EN
//
//
//
// --------------------------------- Register RTree: VREF_CR ------------------------------------
// SVD Line: 4134
// SFDITEM_REG__VREF_CR
// CR
//
// [Bits 31..0] RW (@ 0x40010100) CR
// ( (unsigned int)((VREF_CR >> 0) & 0xFFFFFFFF), ((VREF_CR = (VREF_CR & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__VREF_CR_VREFBUF_OUT_SEL
// - SFDITEM_FIELD__VREF_CR_VREFBUF_EN
//
//
// ---------------------------------- Peripheral View: VREF -------------------------------------
// SVD Line: 4125
// VREF
// VREF
// - SFDITEM_REG__VREF_CR
//
//
// ---------------------------- IRQ Num definition: PY32F001Bxx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// ------------------------- PY32F001Bxx Specific Interrupt Numbers -----------------------------
// PVD_IRQ
// PVD
// PVD global Interrupts
// 16
//
//
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 17
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 18
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 19
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 20
//
//
// EXTI4_7_IRQ
// EXTI4_7
// EXTI Line 4 to 7 Interrupt
// 21
//
//
// ADC_IRQ
// ADC
// ADC Interrupts
// 24
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 25
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 26
//
//
// LPTIM1_IRQ
// LPTIM1
// LPTIM1 global Interrupts
// 27
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupts
// 28
//
//
// PWM_IRQ
// PWM
// PWM global Interrupts
// 32
//
//
// UART1_IRQ
// UART1
// UART1 global Interrupts
// 33
//
//
// PY32F001Bxx_IRQTable
// PY32F001Bxx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// PVD_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_7_IRQ
// ADC_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// LPTIM1_IRQ
// TIM14_IRQ
// PWM_IRQ
// UART1_IRQ
//
// ----------------------------------- Menu: PY32F001Bxx ---------------------------------------
// SVD Line: 2
// ----------------------------- Peripheral Menu: 'PY32F001Bxx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// ADC
// ADC
//
//
// DBGMCU
// DBGMCU
//
//
// EXTI
// EXTI
//
//
// FLASH
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOC
//
//
// IWDG
// IWDG
//
//
// LPTIM
// LPTIM1
//
//
// PWM
// PWM
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM14
//
//
// UART
// UART1
//
//
// VREF
// VREF
//
//