Puya Puya PY32F032xx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter 0x40012400 0x0 0x400 registers ADC ADC Interrupt 8 ISR ADC interrupt and status register 0x0 ADRDY [0:0] EOSMP [1:1] EOC [2:2] EOS [3:3] OVR [4:4] JEOC [5:5] JEOS [6:6] AWD [7:7] EOCAL [11:11] IER ADC interrupt enable register 0x4 ADRDYIE [0:0] EOSMPIE [1:1] EOCIE [2:2] EOSIE [3:3] OVRIE [4:4] JEOCIE [5:5] JEOSIE [6:6] AWDIE [7:7] EOCALIE [11:11] CR ADC control register 0x8 ADEN [0:0] ADDIS [1:1] ADSTART [2:2] JADSTART [3:3] ADSTP [4:4] JADSTP [5:5] RSTCAL [27:27] ADCAL [31:31] CFGR 0xC DMAEN [0:0] DMACFG [1:1] RES [4:3] EXTSEL [8:5] EXTEN [11:10] OVRMOD [12:12] CONT [13:13] AUTDLY [14:14] ALIGN [15:15] DISCEN [16:16] DISCNUM [19:17] JDISCEN [20:20] AWDSGL [22:22] AWDEN [23:23] JAWDEN [24:24] JAUTO [25:25] AWDCH [29:26] CFGR2 ADC configuration register 2 0x10 CALNUM [30:28] SMPR1 ADC sampling time register 1 0x14 SMP0 [2:0] SMP1 [5:3] SMP2 [8:6] SMP3 [11:9] SMP4 [14:12] SMP5 [17:15] SMP6 [20:18] SMP7 [23:21] SMP8 [26:24] SMP9 [29:27] SMPR2 0x18 SMP10 [2:0] SMP11 [5:3] SMP12 [8:6] SMP13 [11:9] SMP14 [14:12] TR 0x24 LT [11:0] AWDFILT [14:12] HT [27:16] SQR1 0x30 L [3:0] SQ1 [9:6] SQ2 [15:12] SQ3 [21:18] SQ4 [27:24] SQR2 0x34 SQ5 [3:0] SQ6 [9:6] SQ7 [15:12] SQ8 [21:18] SQ9 [27:24] SQR3 0x38 SQ10 [3:0] SQ11 [9:6] SQ12 [15:12] SQ13 [21:18] SQ14 [27:24] SQR4 0x3C SQ15 [3:0] SQ16 [9:6] DR ADC group regular data register 0x40 RDATA [15:0] read-only JSQR 0x4C JL [1:0] JEXTSEL [5:2] JEXTEN [7:6] JSQ1 [11:8] JSQ2 [17:14] JSQ3 [23:20] JSQ4 [29:26] JDR1 0x80 JDATA [15:0] read-only JDR2 0x84 JDATA [15:0] read-only JDR3 0x88 JDATA [15:0] read-only JDR4 0x8C JDATA [15:0] read-only CALFACT 0xB4 WCALFACT [8:0] FACTSEL [13:9] WRVLD [14:14] RDVLD [15:15] OFFSUC [20:20] CAPSUC [21:21] RCALFACT [31:23] read-only CCR ADC common configuration register 0x308 CKMODE [17:16] PRESC [21:18] VREFEN [22:22] TSEN [23:23] PWR_MODE [27:25] VSENSESEL [28:28] COMP 0x40010200 0x0 0x20 registers COMP1_2 COMP1 and 2 Interrupts 12 CSR1 0x0 COMP1_EN COMP1 enable bit [0:0] INMSEL COMP1 negative input select [4:2] INPSEL COMP1 positive input select [7:5] WINMODE COMP1 window mode enable [11:11] BLANKSEL Comparator 1 blanking signal selection [14:12] POLARITY COMP1 output polarity selection [15:15] HYST COMP1 hysteresis function enable control [16:16] PWRMODE COMP1 power mode selection [18:18] INT_OUT_SEL COMP1 output to TIM/EXTI selection [29:29] COMP1_OUT COMP1 output status [30:30] read-only LOCK COMP1_CSR registerlock [31:31] FR1 0x4 FLTEN1 Comparator 1 digital filter configuration [0:0] FLTCNT1 Comparator 1 sampling filter counter [31:16] CCSR 0x8 VREFCMP_EN VREFCMP voltage divider enable signal [0:0] VCDIV [6:1] SSEL [7:7] CSR2 0x10 COMP2_EN COMP2 enable bit [0:0] INMSEL COMP2 negative input select [4:1] INPSEL COMP2 positive input select [7:5] WINMODE [11:11] BLANKSEL Comparator 2 blanking signal selection [14:12] POLARITY COMP2 output polarity selection [15:15] HYST COMP1 hysteresis function enable control [16:16] PWRMODE COMP2 power mode selection [18:18] INT_OUT_SEL COMP2 output to TIM/EXTI selection [29:29] COMP_OUT COMP2 output status [30:30] read-only LOCK COMP2_CSR register lock [31:31] FR2 0x14 FLTEN2 Comparator 2 digital filtering configuration [0:0] FLTCNT2 Comparator 2 sampling filter counter [31:16] CRC CRC calculation unit 0x40023000 0x0 0x400 registers DR Data register 0x0 DR [31:0] IDR Independent Data register 0x4 IDR [7:0] CR Control register 0x8 write-only RESET [0:0] DBGMCU Debug support 0x40015800 0x0 0x400 registers DBG_IDCODE 0x0 DBG_ID [31:0] read-only CR Debug MCU Configuration Register 0x4 DBG_SLEEP [0:0] DBG_STOP [1:1] DBG_APB_FZ1 0x8 DBG_TIM1_STOP [0:0] DBG_TIM3_STOP [1:1] DBG_RTC_STOP [10:10] DBG_WWDG_STOP [11:11] DBG_IWDG_STOP [12:12] DBG_LPTIM1_STOP [31:31] DBG_APB_FZ2 0xC DBG_TIM14_STOP [15:15] DBG_TIM16_STOP [17:17] DBG_TIM17_STOP [18:18] DMA Direct memory access 0x40020000 0x0 0x400 registers DMA_Channel1 DMA Channel 1 Interrupt 9 DMA_Channel2 DMA Channel 2 Interrupt 10 DMA_Channel3 DMA Channel 3 Interrupt 11 ISR DMA interrupt status register(DMA_ISR) 0x0 TCIF1 Transfer Complete Flag for Channel 1 [0:0] read-only BTCIF1 Block Transfer Complete Flag for Channel 1 [1:1] read-only HBTIF1 Half Block Transfer Complete Flag for Channel 1 [2:2] read-only TEIF1 Transfer Error Flag for Channel 1 [3:3] read-only TCIF2 Transfer Complete Flag for Channel 2 [4:4] read-only BTCIF2 Block Transfer Complete Flag for Channel 2 [5:5] read-only HBTIF2 Half Block Transfer Complete Flag for Channel 2 [6:6] read-only TEIF2 Transfer Error Flag for Channel 2 [7:7] read-only TCIF3 Transfer Complete Flag for Channel 3 [8:8] read-only BTCIF3 Block Transfer Complete Flag for Channel 3 [9:9] read-only HBTIF3 Half Block Transfer Complete Flag for Channel 3 [10:10] read-only TEIF3 Transfer Error Flag for Channel 3 [11:11] read-only IFCR DMA interrupt flag clear register(DMA_IFCR) 0x4 CTCIF1 Transfer Complete Flag Clear for Channel 1 [0:0] CBTCIF1 Block Transfer Complete Flag Clear for Channel 1 [1:1] CHBTIF1 Half Block Transfer Complete Flag Clear for Channel 1 [2:2] CTEIF1 Transfer Error Flag Clear for Channel 1 [3:3] CTCIF2 Transfer Complete Flag Clear for Channel 2 [4:4] CBTCIF2 Block Transfer Complete Flag Clear for Channel 2 [5:5] CHBTIF2 Half Block Transfer Complete Flag Clear for Channel 2 [6:6] CTEIF2 Transfer Error Flag Clear for Channel 2 [7:7] CTCIF3 Transfer Complete Flag Clear for Channel 3 [8:8] CBTCIF3 Block Transfer Complete Flag Clear for Channel 3 [9:9] CHBTIF3 Half Block Transfer Complete Flag Clear for Channel 3 [10:10] CTEIF3 Transfer Error Flag Clear for Channel 3 [11:11] CCR1 DMA channel configuration register(DMA_CCR) 0x8 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR1 DMA channel 1 number of dataregister 0xC NDT Number of Data to Transfer [15:0] CPAR1 DMA channel 1 peripheral addressregister 0x10 PA Peripheral Address [31:0] CMAR1 DMA channel 1 memory addressregister 0x14 MA Memory Address [31:0] CCCFGR1 0x18 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR2 DMA channel configuration register(DMA_CCR) 0x1C EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR2 DMA channel 2 number of dataregister 0x20 NDT Number of Data to Transfer [15:0] CPAR2 DMA channel 2 peripheral addressregister 0x24 PA Peripheral Address [31:0] CMAR2 DMA channel 2 memory addressregister 0x28 MA Memory Address [31:0] CCCFGR2 0x2C NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR3 DMA channel configuration register(DMA_CCR) 0x30 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR3 DMA channel 3 number of dataregister 0x34 NDT Number of Data to Transfer [15:0] CPAR3 DMA channel 3 peripheral addressregister 0x38 PA Peripheral Address [31:0] CMAR3 DMA channel 3 memory addressregister 0x3C MA Memory Address [31:0] CCCFGR3 0x40 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] EXTI External interrupt/eventcontroller 0x40021800 0x0 0x400 registers PVD PVD Interrupt through EXTI Lines 16 1 EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR EXTI rising trigger selectionregister 0x0 RT0 [0:0] RT1 [1:1] RT2 [2:2] RT3 [3:3] RT4 [4:4] RT5 [5:5] RT6 [6:6] RT7 [7:7] RT8 [8:8] RT9 [9:9] RT10 [10:10] RT11 [11:11] RT12 [12:12] RT13 [13:13] RT14 [14:14] RT15 [15:15] RT16 [16:16] RT17 [17:17] RT18 [18:18] FTSR EXTI falling trigger selectionregister 0x4 FT0 [0:0] FT1 [1:1] FT2 [2:2] FT3 [3:3] FT4 [4:4] FT5 [5:5] FT6 [6:6] FT7 [7:7] FT8 [8:8] FT9 [9:9] FT10 [10:10] FT11 [11:11] FT12 [12:12] FT13 [13:13] FT14 [14:14] FT15 [15:15] FT16 [16:16] FT17 [17:17] FT18 [18:18] SWIER EXTI software interrupt eventregister 0x8 SWIE0 [0:0] SWIE1 [1:1] SWIE2 [2:2] SWIE3 [3:3] SWIE4 [4:4] SWIE5 [5:5] SWIE6 [6:6] SWIE7 [7:7] SWIE8 [8:8] SWIE9 [9:9] SWIE10 [10:10] SWIE11 [11:11] SWIE12 [12:12] SWIE13 [13:13] SWIE14 [14:14] SWIE15 [15:15] SWIE16 [16:16] SWIE17 [17:17] SWIE18 [18:18] PR EXTI pendingregister 0xC PR0 [0:0] PR1 [1:1] PR2 [2:2] PR3 [3:3] PR4 [4:4] PR5 [5:5] PR6 [6:6] PR7 [7:7] PR8 [8:8] PR9 [9:9] PR10 [10:10] PR11 [11:11] PR12 [12:12] PR13 [13:13] PR14 [14:14] PR15 [15:15] PR16 [16:16] PR17 [17:17] PR18 [18:18] IOSEL1 0x10 EXTI0SEL [1:0] EXTI1SEL [5:4] EXTI2SEL [9:8] EXTI3SEL [13:12] EXTI4SEL [17:16] EXTI5SEL [21:20] EXTI6SEL [25:24] EXTI7SEL [29:28] IOSEL2 0x14 EXTI8SEL [1:0] EXTI9SEL [5:4] EXTI10SEL [9:8] EXTI11SEL [13:12] EXTI12SEL [17:16] EXTI13SEL [21:20] EXTI14SEL [25:24] EXTI15SEL [29:28] IMR EXTI CPU wakeup with interrupt maskregister 0x18 IM0 [0:0] IM1 [1:1] IM2 [2:2] IM3 [3:3] IM4 [4:4] IM5 [5:5] IM6 [6:6] IM7 [7:7] IM8 [8:8] IM9 [9:9] IM10 [10:10] IM11 [11:11] IM12 [12:12] IM13 [13:13] IM14 [14:14] IM15 [15:15] IM16 [16:16] IM17 [17:17] IM18 [18:18] IM20 [20:20] IM22 [22:22] IM24 [24:24] IM25 [25:25] IM27 [27:27] EMR EXTI CPU wakeup with event maskregister 0x1C EM0 [0:0] EM1 [1:1] EM2 [2:2] EM3 [3:3] EM4 [4:4] EM5 [5:5] EM6 [6:6] EM7 [7:7] EM8 [8:8] EM9 [9:9] EM10 [10:10] EM11 [11:11] EM12 [12:12] EM13 [13:13] EM14 [14:14] EM15 [15:15] EM16 [16:16] EM17 [17:17] EM18 [18:18] EM20 [20:20] EM22 [22:22] EM24 [24:24] EM25 [25:25] EM27 [27:27] FLASH Flash 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR Access control register 0x0 LATENCY Latency [1:0] KEYR Flash key register 0x8 KEY Flash CR key [31:0] write-only OPTKEYR Option byte key register 0xC OPTKEY Flash Option key [31:0] write-only SR Status register 0x10 EOP End of operation [0:0] WRPERR Write protection error [4:4] RDERR Bank pcrop read error [11:11] OPTVERR Option and trimming bits loading validity error [15:15] BSY Bank Busy [16:16] read-only USERLOCK User data lock [28:28] read-only CR Flash control register 0x14 PG Page Program [0:0] PER Page Erase [1:1] MER Bank Mass Erase [2:2] UPG Userdata Program [4:4] UPER Userdata Page Erase [5:5] SER Sector Erase [11:11] OPTSTRT Option bytes Programming Start [17:17] UPGSTRT Userdata Programming Start [18:18] PGSTRT Programming Start [19:19] RDERRIE Bank pcrop read error interrupt enable [22:22] EOPIE End of operation interrupt enable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option bytes loading [27:27] SECPROT Secure protect [28:28] OPTLOCK Option Lock [30:30] LOCK Lock [31:31] OPTR Flash option register 0x20 RDP Read Protection [7:0] NRST_MODE nrst mode [10:10] IWDG_STOP IWDG Stop Count Control [13:13] IWDG_SW IWDG Software Enable [14:14] WWDG_SW WWDG Software Enable [15:15] NBOOT1 nboot1 [17:17] BOOT_LOCK Boot Lock [20:20] BOR_EN BOR enable [21:21] BOR_OPCR BOR Level [24:22] SWD_MODE SWD mode [26:25] WRPR 0x28 BK_WRPX Bank Sector Write Protection [15:0] PCROPR 0x2C PCROPSR Bank pcrop start address [8:0] PCROPER Bank pcrop end address [24:16] SECR 0x30 SEC_SIZE Bank securable seize [8:0] LPCR 0x90 SLEEP_EN Sleep enable [0:0] SLEEP_TIME Sleep time [15:8] LPRUN_ENTERT Low power run mode enter time [18:16] LPRUN_EXITT Low power run mode exit time [22:20] TS0 Flash TS0 register 0x100 TS0 TS0 [6:0] TS1 Flash TS1 register 0x104 TS1 TS1 [6:0] TS2P Flash TS2P register 0x108 TS2P TS2P [6:0] TPS3 Flash TPS3 register 0x10C TPS3 TPS3 [8:0] TS3 Flash TS3 register 0x110 TS3 TS3 [6:0] ERSTPE 0x114 ERSTPE ERSTPE [14:0] PRGTPE Flash PRGTPE register 0x118 PRGTPE PRGTPE [14:0] PRETPE Flash PRETPE register 0x11C PRETPE PRETPE [11:0] TACLK2PW 0x120 TACLK2PW TACLK2PW [3:0] GPIOA General-purpose I/Os 0x50000000 0x0 0x400 registers MODER GPIO port mode register 0x0 MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] MODE2 Port x configuration bits (y = 0..15) [5:4] MODE3 Port x configuration bits (y = 0..15) [7:6] MODE4 Port x configuration bits (y = 0..15) [9:8] MODE5 Port x configuration bits (y = 0..15) [11:10] MODE6 Port x configuration bits (y = 0..15) [13:12] MODE7 Port x configuration bits (y = 0..15) [15:14] MODE8 Port x configuration bits (y = 0..15) [17:16] MODE9 Port x configuration bits (y = 0..15) [19:18] MODE10 Port x configuration bits (y = 0..15) [21:20] MODE11 Port x configuration bits (y = 0..15) [23:22] MODE12 Port x configuration bits (y = 0..15) [25:24] MODE13 Port x configuration bits (y = 0..15) [27:26] MODE14 Port x configuration bits (y = 0..15) [29:28] MODE15 Port x configuration bits (y = 0..15) [31:30] OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OT2 Port x configuration bits (y = 0..15) [2:2] OT3 Port x configuration bits (y = 0..15) [3:3] OT4 Port x configuration bits (y = 0..15) [4:4] OT5 Port x configuration bits (y = 0..15) [5:5] OT6 Port x configuration bits (y = 0..15) [6:6] OT7 Port x configuration bits (y = 0..15) [7:7] OT8 Port x configuration bits (y = 0..15) [8:8] OT9 Port x configuration bits (y = 0..15) [9:9] OT10 Port x configuration bits (y = 0..15) [10:10] OT11 Port x configuration bits (y = 0..15) [11:11] OT12 Port x configuration bits (y = 0..15) [12:12] OT13 Port x configuration bits (y = 0..15) [13:13] OT14 Port x configuration bits (y = 0..15) [14:14] OT15 Port x configuration bits (y = 0..15) [15:15] OSPEEDR GPIO port output speed register 0x8 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] OSPEED2 Port x configuration bits (y = 0..15) [5:4] OSPEED3 Port x configuration bits (y = 0..15) [7:6] OSPEED4 Port x configuration bits (y = 0..15) [9:8] OSPEED5 Port x configuration bits (y = 0..15) [11:10] OSPEED6 Port x configuration bits (y = 0..15) [13:12] OSPEED7 Port x configuration bits (y = 0..15) [15:14] OSPEED8 Port x configuration bits (y = 0..15) [17:16] OSPEED9 Port x configuration bits (y = 0..15) [19:18] OSPEED10 Port x configuration bits (y = 0..15) [21:20] OSPEED11 Port x configuration bits (y = 0..15) [23:22] OSPEED12 Port x configuration bits (y = 0..15) [25:24] OSPEED13 Port x configuration bits (y = 0..15) [27:26] OSPEED14 Port x configuration bits (y = 0..15) [29:28] OSPEED15 Port x configuration bits (y = 0..15) [31:30] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] PUPD2 Port x configuration bits (y = 0..15) [5:4] PUPD3 Port x configuration bits (y = 0..15) [7:6] PUPD4 Port x configuration bits (y = 0..15) [9:8] PUPD5 Port x configuration bits (y = 0..15) [11:10] PUPD6 Port x configuration bits (y = 0..15) [13:12] PUPD7 Port x configuration bits (y = 0..15) [15:14] PUPD8 Port x configuration bits (y = 0..15) [17:16] PUPD9 Port x configuration bits (y = 0..15) [19:18] PUPD10 Port x configuration bits (y = 0..15) [21:20] PUPD11 Port x configuration bits (y = 0..15) [23:22] PUPD12 Port x configuration bits (y = 0..15) [25:24] PUPD13 Port x configuration bits (y = 0..15) [27:26] PUPD14 Port x configuration bits (y = 0..15) [29:28] PUPD15 Port x configuration bits (y = 0..15) [31:30] IDR GPIO port input data register 0x10 ID0 Port input data (y = 0..15) [0:0] read-only ID1 Port input data (y = 0..15) [1:1] read-only ID2 Port input data (y = 0..15) [2:2] read-only ID3 Port input data (y = 0..15) [3:3] read-only ID4 Port input data (y = 0..15) [4:4] read-only ID5 Port input data (y = 0..15) [5:5] read-only ID6 Port input data (y = 0..15) [6:6] read-only ID7 Port input data (y = 0..15) [7:7] read-only ID8 Port input data (y = 0..15) [8:8] read-only ID9 Port input data (y = 0..15) [9:9] read-only ID10 Port input data (y = 0..15) [10:10] read-only ID11 Port input data (y = 0..15) [11:11] read-only ID12 Port input data (y = 0..15) [12:12] read-only ID13 Port input data (y = 0..15) [13:13] read-only ID14 Port input data (y = 0..15) [14:14] read-only ID15 Port input data (y = 0..15) [15:15] read-only ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] OD2 Port output data (y = 0..15) [2:2] OD3 Port output data (y = 0..15) [3:3] OD4 Port output data (y = 0..15) [4:4] OD5 Port output data (y = 0..15) [5:5] OD6 Port output data (y = 0..15) [6:6] OD7 Port output data (y = 0..15) [7:7] OD8 Port output data (y = 0..15) [8:8] OD9 Port output data (y = 0..15) [9:9] OD10 Port output data (y = 0..15) [10:10] OD11 Port output data (y = 0..15) [11:11] OD12 Port output data (y = 0..15) [12:12] OD13 Port output data (y = 0..15) [13:13] OD14 Port output data (y = 0..15) [14:14] OD15 Port output data (y = 0..15) [15:15] BSRR GPIO port bit set/reset register 0x18 BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BS2 Port x set bit y (y= 0..15) [2:2] BS3 Port x set bit y (y= 0..15) [3:3] BS4 Port x set bit y (y= 0..15) [4:4] BS5 Port x set bit y (y= 0..15) [5:5] BS6 Port x set bit y (y= 0..15) [6:6] BS7 Port x set bit y (y= 0..15) [7:7] BS8 Port x set bit y (y= 0..15) [8:8] BS9 Port x set bit y (y= 0..15) [9:9] BS10 Port x set bit y (y= 0..15) [10:10] BS11 Port x set bit y (y= 0..15) [11:11] BS12 Port x set bit y (y= 0..15) [12:12] BS13 Port x set bit y (y= 0..15) [13:13] BS14 Port x set bit y (y= 0..15) [14:14] BS15 Port x set bit y (y= 0..15) [15:15] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] BR2 Port x reset bit y (y = 0..15) [18:18] BR3 Port x reset bit y (y = 0..15) [19:19] BR4 Port x reset bit y (y = 0..15) [20:20] BR5 Port x reset bit y (y = 0..15) [21:21] BR6 Port x reset bit y (y = 0..15) [22:22] BR7 Port x reset bit y (y = 0..15) [23:23] BR8 Port x reset bit y (y = 0..15) [24:24] BR9 Port x reset bit y (y = 0..15) [25:25] BR10 Port x reset bit y (y = 0..15) [26:26] BR11 Port x reset bit y (y = 0..15) [27:27] BR12 Port x reset bit y (y = 0..15) [28:28] BR13 Port x reset bit y (y = 0..15) [29:29] BR14 Port x reset bit y (y = 0..15) [30:30] BR15 Port x reset bit y (y = 0..15) [31:31] LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCK2 Port x lock bit y (y= 0..15) [2:2] LCK3 Port x lock bit y (y= 0..15) [3:3] LCK4 Port x lock bit y (y= 0..15) [4:4] LCK5 Port x lock bit y (y= 0..15) [5:5] LCK6 Port x lock bit y (y= 0..15) [6:6] LCK7 Port x lock bit y (y= 0..15) [7:7] LCK8 Port x lock bit y (y= 0..15) [8:8] LCK9 Port x lock bit y (y= 0..15) [9:9] LCK10 Port x lock bit y (y= 0..15) [10:10] LCK11 Port x lock bit y (y= 0..15) [11:11] LCK12 Port x lock bit y (y= 0..15) [12:12] LCK13 Port x lock bit y (y= 0..15) [13:13] LCK14 Port x lock bit y (y= 0..15) [14:14] LCK15 Port x lock bit y (y= 0..15) [15:15] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port x bit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port x bit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port x bit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port x bit y (y = 0..7) [23:20] AFSEL6 Alternate function selection for port x bit y (y = 0..7) [27:24] AFSEL7 Alternate function selection for port x bit y (y = 0..7) [31:28] AFRH GPIO alternate function highregister 0x24 AFSEL8 Alternate function selection for port x bit y (y = 8..15) [3:0] AFSEL9 Alternate function selection for port x bit y (y = 8..15) [7:4] AFSEL10 Alternate function selection for port x bit y (y = 8..15) [11:8] AFSEL11 Alternate function selection for port x bit y (y = 8..15) [15:12] AFSEL12 Alternate function selection for port x bit y (y = 8..15) [19:16] AFSEL13 Alternate function selection for port x bit y (y = 8..15) [23:20] AFSEL14 Alternate function selection for port x bit y (y = 8..15) [27:24] AFSEL15 Alternate function selection for port x bit y (y = 8..15) [31:28] BRR port bit reset register 0x28 BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] BR8 Port Reset bit [8:8] BR9 Port Reset bit [9:9] BR10 Port Reset bit [10:10] BR11 Port Reset bit [11:11] BR12 Port Reset bit [12:12] BR13 Port Reset bit [13:13] BR14 Port Reset bit [14:14] BR15 Port Reset bit [15:15] GPIOB 0x50000400 GPIOF 0x50001400 I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1_EV I2C1 Event global Interrupt 23 I2C1_ER I2C1 Error global Interrupt 24 CR1 Control register 1 0x0 PE Peripheral enable [0:0] WUPEN Wakeup from Stop mode enable [2:2] ENGC General call enable [6:6] NOSTRETCH Clock stretching disable (Slave mode) [7:7] START Start generation [8:8] STOP Stop generation [9:9] ACK Acknowledge enable [10:10] POS Acknowledge(for data reception) [11:11] SWRST Software reset [15:15] WKUP_DIV PCLK division [17:16] WKUP_CNT Timeout count number [19:18] CR2 Control register 2 0x4 FREQ Peripheral clock frequency [6:0] ITERREN Error interrupt enable [8:8] DMAEN DMA requests enable [11:11] LAST DMA last transfer [12:12] SBIE Start bit (Master mode) interrupt enable [16:16] ADDRIE Address sent (master mode)/matched (slave mode) interrupt enable [17:17] BTFIE Byte transfer finished interrupt enable [18:18] ADD10IE 10-bit header sent (Master mode) interrupt enable [19:19] STOPIE Stop detection (slave mode) interrupt enable [20:20] RXIE Data register not empty (receivers) interrupt enable [22:22] TXIE Data register empty (transmitters) interrupt enable [23:23] OAR1 Own address register 1 0x8 ADD Interface address [9:0] ADDMODE Addressing mode (slave mode) [15:15] OAR2 0xC ENDUAL Dual addressing mode enable [0:0] ADD2 Interface address [7:1] OA2MSK Own Address 2 masks [10:8] DR Data register 0x10 DR 8-bit data register [7:0] SR1 Status register 1 0x14 SB Start bit (Master mode) [0:0] read-only ADDR Address sent (master mode)/matched (slave mode) [1:1] read-only BTF Byte transfer finished [2:2] read-only ADD10 10-bit header sent (Master mode) [3:3] read-only STOPF Stop detection (slave mode) [4:4] read-only RXNE Data register not empty (receivers) [6:6] read-only TXE Data register empty (transmitters) [7:7] read-only BERR Bus error [8:8] ARLO Arbitration lost (master mode) [9:9] AF Acknowledge failure [10:10] OVR Overrun/Underrun [11:11] TIMEOUT Timeout or Tlow error [14:14] SR2 Status register 2 0x18 MSL Master/slave [0:0] read-only BUSY Bus busy [1:1] read-only TRA Transmitter/receiver [2:2] read-only GENCALL General call address (Slave mode) [4:4] read-only DUALF Dual flag (Slave mode) [7:7] read-only SBUSY Slave busy [16:16] read-only CCR Clock control register 0x1C CCR Clock control register in Fm/Sm mode (Master mode) [11:0] FP I2C master mode selection [13:13] DUTY Fm mode duty cycle [14:14] FS I2C master mode selection [15:15] TRISE TRISE register 0x20 TRISE Maximum rise time in Fm+/Fm/Sm mode (Master mode) [6:0] THOLDDATA Data hold time [11:7] THOLDDATA_SEL Data hold time select [12:12] OAR3 0x28 ENTRIPLE Triple addressing mode enable [0:0] ADD3 Interface address [7:1] IWDG Independent watchdog 0x40003000 0x0 0x400 registers KR Key register (IWDG_KR) 0x0 KEY IWDG KEY [15:0] PR Prescaler register (IWDG_PR) 0x4 PR IWDG preload [2:0] RLR Reload register (IWDG_RLR) 0x8 RL IWDG reload [11:0] SR Status register (IWDG_SR) 0xC PVU Watchdog prescaler value update [0:0] read-only RVU Watchdog counter reload value update [1:1] read-only LPTIM Low power timer 0x40007C00 0x0 0x400 registers LPTIM LPTIM global Interrupt 17 ISR Interrupt and Status Register 0x0 ARRM Autoreload match [1:1] read-only ARROK Autoreload register update OK [4:4] read-only ICR Interrupt Clear Register 0x4 ARRMCF Autoreload match clear flag [1:1] ARROKCF Autoreload register update OK clear flag [4:4] IER Interrupt Enable Register 0x8 ARRMIE Autoreload match Interrupt Enable [1:1] ARROKIE Autoreload register update OK Interrupt Enable [4:4] CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR Control Register 0x10 ENABLE LPTIM enable [0:0] SNGSTRT LPTIM start in Single mode [1:1] CNTSTRT Timer start in Continuous mode [2:2] COUNTRST Counter reset [3:3] RSTARE Reset after read enable [4:4] ARR Autoreload Register 0x18 ARR Auto reload value [15:0] CNT Counter Register 0x1C CNT Counter value [15:0] read-only LPUART 0x40008000 0x0 0x40 registers LPUART LPUART global Interrupt 29 CR1 0x0 UE LPUART enabled [0:0] UESM LPUART enabled in Stop mode [1:1] RE Receive enable [2:2] TE Transfer enable [3:3] IDLEIE IDLE interrupt enable [4:4] RXNEIE RXNE interrupt enable [5:5] TCIE End of Transfer interrupt enabled [6:6] TXEIE TXE interrupt enable [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control [10:10] WAKE Receive wake-up mode [11:11] M0 Configure the word length in combination with M1 [12:12] MME Silent mode enabled [13:13] CMIE Character match interrupt enabled [14:14] DEDT The time between the transmit frame stop bit and the invalid DE (driver enable) signal [20:16] DEAT The time between the DE (driver enable) signal validity and the start bit [25:21] M1 The value of {M1,M0} the configurate length [28:28] CR2 0x4 ADDM7 7bit/4bit address detection configuration [4:4] STOP Stop bit configuration [13:12] SWAP TX/RX pin interchangeable [15:15] RXINV The RX pin is active level inverting [16:16] TXINV TX pin active level inverted [17:17] DATAINV Inverse binary data processing [18:18] MSBFIRST MSB first [19:19] TXOE_ALWAYS_ON [20:20] ADD LPUART address [31:24] CR3 0x8 EIE Error interrupts are enabled [0:0] HDSEL Half-duplex selection [3:3] DMAR Enable DMA on reception [6:6] DMAT Enable DMA while transmitting [7:7] RTSE RTS enabled [8:8] CTSE CTS enabled [9:9] CTSIE CTS interrupt enable [10:10] OVRDIS Overrun is prohibited [12:12] DDRE Whether DMA is disabled when receiving an error [13:13] DEM DE mode enabled [14:14] DEP DE polarity selection [15:15] WUS Low-power wake-up options [21:20] WUFIE Low-power wake-up interrupt enable [22:22] BRR 0xC BBR LPUART baud rate [19:0] RQR 0x18 SBKRQ Send an abort request [1:1] MMRQ Silent mode request [2:2] ISR 0x1C PE Parity error [0:0] read-only FE Frame error flag [1:1] read-only NE START bit noise flag [2:2] read-only ORE Overrun error flag [3:3] read-only IDLE idle flag [4:4] read-only RXNE RX register not empty [5:5] read-only TC Transmission completion flag [6:6] read-only TXE TX register empty [7:7] read-only CTSIF CTS interrupt flag [9:9] read-only CTS CTS flag [10:10] read-only BUSY Busy flag [16:16] read-only CMF Address match flag [17:17] read-only SBKF Send abort flag [18:18] read-only RWU Receive Mute mode wake-up flag [19:19] read-only WUF Wake flag from low-power mode [20:20] read-only TEACK Transport enable acknowledgement flag [21:21] read-only REACK Receive the enable acknowledgment flag [22:22] read-only ICR 0x20 PECF Check value error flag reset [0:0] FECF Frame error flag reset [1:1] NECF Clear the START bit noise flag [2:2] ORECF Overrun error flag reset [3:3] IDLECF Clear idle flag [4:4] TCCF Transfer completion flag reset [6:6] CTSCF CTS flag reset [9:9] CMCF Address matching flag reset [17:17] WUCF Low power wake-up flag reset [20:20] RDR 0x24 RDR Receive Data Register [8:0] read-only TDR 0x28 TDR Transmit Data Register [8:0] PRESC 0x2C PRESCALER Input clock prescaler register [3:0] SAMPMOD 0x34 SAMPMOD Tolerance sampling mode register [0:0] OPA Operational amplifier 0x40010300 0x0 0x400 registers OCR1 0x30 OPA1_EXTOEN [0:0] OPA_VBIAS [4:3] OPA1_VMSEL [6:5] OPA1_VBSEL [7:7] OPA1_PGA_GAIN [11:8] CR1 0x34 OPA1EN [5:5] OCR2 0x38 OPA2_EXTOEN [0:0] OPA2_VMSEL [6:5] OPA2_VBSEL [7:7] OPA2_PGA_GAIN [11:8] CR2 0x3C OPA2EN [5:5] PWR Power control 0x40007000 0x0 0x400 registers CR1 Power control register 1 0x0 LPMS [2:0] DBP [8:8] VR_MODE [10:9] FLS_SLPTIME [13:12] MR_VSEL [17:16] LPR_VSEL [19:18] DLPR_VSEL [21:20] FLSSLP_CTRL [24:24] HSION_CTRL [25:25] CR2 Power control register 2 0x4 PVDE [0:0] PVDT [6:4] PVD_OUT_SEL [7:7] FLTEN [8:8] FLT_TIME [11:9] SR Power status register 0x10 MR_RDY [9:9] read-only LPRUN_RUN_SWF [11:11] read-only PVDO [16:16] read-only RCC Reset and clock control 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 4 CR Clock control register 0x0 HSION HSI clock enable bit [8:8] HSIRDY HSI clock ready logo [10:10] read-only HSIDIV HSI generates the crossover factor when HSISYS clocks [13:11] HSEON HSE crystal oscillator enabled [16:16] HSERDY HSE crystal clock ready logo [17:17] read-only HSEBYP HSE shields the crystal oscillator and selects the pin input clock [18:18] HSE_CSSON HSE clock security system enabled [19:19] PLLON PLL clock enable [24:24] PLLRDY PLL clock ready [25:25] read-only PLLDIV PLL div [26:26] ICSCR Internal clock sources calibrationregister 0x4 HSI_ABS_TRIM Clock frequency abs calibration value [11:0] HSI_TC_TRIM Clock frequency tc calibration value [15:12] HSI_FS HSI frequency selection [18:16] LSI_TRIM Internal low-speed clock frequency calibration [27:19] CFGR Clock configuration register 0x8 SW System clock source selection [2:0] SWS System clock source selection [5:3] HPRE The AHB clock HCLK is based on the crossover coefficient of SYSCLK [11:8] PPRE APB clock division factor [14:12] MCOSEL MCO output clock selection [27:24] MCOPRE Microprocessor output clock (MCO) divider factor [31:28] PLLCFGR PLL configuration register 0xC PLLSRC [0:0] PLLMUL [6:2] ECSCR External clock source control register 0x10 HSE_DRV HSE drive capability setting [1:0] HSE_RDYSEL HSE stabilization time selection [3:2] HSE_FILT_EN [4:4] LSE_DRIVER LSE drive capability setting [17:16] LSE_STARTUP LSE crystal oscillator stabilization time selection [21:20] CIER Clock interrupt enableregister 0x18 LSIRDYIE LSI clock ready interrupt enabled [0:0] LSERDYIE LSE clock ready interrupt enabled [1:1] HSIRDYIE HSI clock ready interrupt enabled [3:3] HSERDYIE HSE clock ready interrupt enabled [4:4] PLLRDYIE PLL clock ready interrupt enabled [5:5] CIFR Clock interrupt flag register 0x1C LSIRDYF LSI clock ready interrupt flag [0:0] read-only LSERDYF LSE clock ready interrupt flag [1:1] read-only HSIRDYF HSI clock ready interrupt flag [3:3] read-only HSERDYF HSE clock ready interrupt flag [4:4] read-only PLLRDYF PLL clock ready interrupt flag [5:5] read-only CSSF HSE Clock Security System (CSS) interrupt flag [8:8] read-only LSECSSF LSE Clock Security System (CSS) interrupt flag [9:9] read-only CICR Clock interrupt clear register 0x20 LSIRDYC The LSI ready interrupt flag is cleared [0:0] LSERDYC The LSE ready interrupt flag is cleared [1:1] HSIRDYC The HSI ready interrupt flag is cleared to zero [3:3] HSERDYC The HSE ready interrupt flag is cleared to zero [4:4] PLLRDYC The PLL ready interrupt flag is cleared to zero [5:5] CSSC The HSE Clock Security System (CSS) interrupt flag is cleared to zero [8:8] LSECSSC The LSE Clock Security System (CSS) interrupt flag is cleared [9:9] IOPRSTR GPIO reset register 0x24 GPIOARST I/O PortA reset [0:0] GPIOBRST I/O PortB reset [1:1] GPIOFRST I/O PortF reset [5:5] AHBRSTR AHB peripheral reset register 0x28 DMARST [0:0] CRCRST The CRC module is reset [12:12] APBRSTR1 0x2C TIM3RST The Timer3 module APB is reset [1:1] RTCAPBRST The RTC module APB is reset [10:10] WWDGRST The WWDG module is reset [11:11] SPI2RST [14:14] UART1RST The UART2 module is reset [18:18] LPUART1RST The LPUART1 module is reset [20:20] I2C1RST The I2C1 module is reset [21:21] OPA1RST The OPA1 module is reset [23:23] OPA2RST The OPA2 module is reset [24:24] DBGRST The MCU Debug module is reset [27:27] PWRRST The Power interface module is reset. [28:28] LPTIM1RST [31:31] APBRSTR2 APB peripheral reset register2 0x30 SYSCFGRST The SYSCFG module is reset [0:0] TIM1RST The TIM1 module is reset [11:11] SPI1RST The SPI1 module is reset [12:12] USART1RST [14:14] TIM14RST The TIM14 module is reset [15:15] TIM16RST The TIM16 module is reset [17:17] TIM17RST The TIM17 module is reset [18:18] ADCRST The ADC block is reset [20:20] COMP1RST The COMP1 module is reset [21:21] COMP2RST The COMP2 module is reset [22:22] VREFBUFRST [26:26] IOPENR GPIO clock enable register 0x34 GPIOAEN I/O PortA clock enable [0:0] GPIOBEN I/O PortB clock enable [1:1] GPIOFEN I/O PortF clock enable [5:5] AHBENR AHB peripheral clock enableregister 0x38 DMAEN DMA module clock enabled [0:0] FLASHEN [8:8] SRAMEN [9:9] CRCEN CRC module clock enabled [12:12] APBENR1 APB peripheral clock enable register1 0x3C TIM3EN [1:1] RTCAPBEN The RTC module APB clock is enabled [10:10] WWDGEN [11:11] SPI2EN [14:14] UART1EN The UART1 module clock is enabled [18:18] LPUART1EN [20:20] I2C1EN I2C1 module clock enable [21:21] OPA1EN [23:23] OPA2EN [24:24] DBGEN MCU Debug module clock enable [27:27] PWREN The Power interface module clock enables [28:28] LPTIM1EN [31:31] APBENR2 APB peripheral clock enable register2 0x40 SYSCFGEN The SYSCFG module clock is enabled [0:0] TIM1EN The TIM1 module clock is enabled [11:11] SPI1EN The SPI1 module clock is enabled [12:12] USART1EN [14:14] TIM14EN TIM14 module clock enable [15:15] TIM16EN [17:17] TIM17EN [18:18] ADCEN ADC block clock enabled [20:20] COMP1EN COMP1 module clock enable [21:21] COMP2EN COMP2 module clock enabled [22:22] VREFBUFEN [26:26] CCIPR Peripherals independent clock configurationregister 0x54 TIMCLK_CTRL TIMER PCLK FREQUENCY CONTROL [0:0] PVDSEL [7:7] COMP1SEL COMP1 module clock source selection [8:8] COMP2SEL COMP2 module clock source selection [9:9] LPUART1SEL [12:11] LPTIM1SEL [17:16] TIM1SEL [22:22] TIM17SEL [23:23] ADCSEL [31:30] BDCR RTC domain control register 0x5C LSEON LSE OSC enabled [0:0] LSERDY LSE OSC ready [1:1] LSEBYP LSE OSC bypass [2:2] LSECSSON LSE CSS enables [5:5] LSECSSD LSE CSS (clock security system) detection failed [6:6] RTCSEL RTC clock source selection [9:8] RTC_HSEDIV_SEL The RTC clock source is selected as the division of the HSE clock [11:10] RTCEN RTC clock enabled [15:15] BDRST RTC soft reset [16:16] LSCSEL Low-speed clock selection [25:25] IWDGSEL [30:30] CSR Control/status register 0x60 LSION LSI OSC enabled [0:0] LSIRDY LSI OSC stability flag [1:1] read-only PINRST_FLTDIS NRST filtering is prohibited [8:8] BORRSTF BOR reset flag [9:9] read-only RMVF Clear the reset flag [23:23] OBLRSTF Option byte loader reset flag [25:25] read-only PINRSTF External NRST pin reset flag [26:26] read-only PWRRSTF BOR/POR/PDR reset flag [27:27] read-only SFTRSTF Soft reset flag [28:28] read-only IWDGRSTF IWDG reset flag [29:29] read-only WWDGRSTF [30:30] read-only RTC Real time clock 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 CRH RTC Control Register High 0x0 SECIE Seconds interrupt allowed bits [0:0] ALRIE Alarm interrupt allowed bits [1:1] OWIE Overflow interrupt allow bits [2:2] CRL RTC Control Register Low 0x4 SECF Second flag [0:0] ALRF Alarm flag [1:1] OWF Overflow flag [2:2] RSF Registers synchronized flag [3:3] CNF Configuration flag [4:4] RTOFF RTC operation OFF [5:5] read-only PRLH RTC Prescaler Load Register High 0x8 PRL RTC prescaler reload value high [5:0] PRLL RTC Prescaler Load Register Low 0xC PRL RTC prescaler reload value high [15:0] DIVH RTC Prescaler Divider Register High 0x10 RTC_DIV RTC clock divider [3:0] read-only DIVL RTC Prescaler Divider Register Low 0x14 RTC_DIV RTC clock divider [15:0] read-only CNTH RTC Counter Register High 0x18 RTC_CNT RTC core counter [15:0] CNTL RTC Counter Register Low 0x1C RTC_CNT RTC core counter [15:0] ALRH RTC Alarm Register High 0x20 ALR RTC alarm value [15:0] ALRL RTC Alarm Register Low 0x24 ALR RTC alarm value [15:0] BKP_RTCCR 0x2C CAL Calibration value [6:0] CCO Calibrate the clock output bits [7:7] ASOE Seconds/alarm pulse output enable bit [8:8] ASOS Seconds/alarm pulse output select bits [9:9] SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 control register 1 0x0 CPHA Clock Phase [0:0] CPOL Clock Polarity [1:1] MSTR Master Selection [2:2] BR Baud Rate Control [5:3] SPE SPI Enable [6:6] LSBFIRST Frame Format [7:7] SSI Internal slave select [8:8] SSM Software slave management [9:9] RXONLY Receive only [10:10] DFF Data frame format [11:11] CRCNEXT Transmit CRC next [12:12] CRCEN Hardware CRC calculation enable [13:13] BIDIOE Output enable in bidirectional mode [14:14] BIDIMODE Bidirectional data mode enable [15:15] CR2 control register 2 0x4 RXDMAEN Rx buffer DMA enable [0:0] TXDMAEN Tx buffer DMA enable [1:1] SSOE SS Output Enable [2:2] CLRTXFIFO Clear FIFO [4:4] ERRIE Error Interrupt Enable [5:5] RXNEIE RX buffer Not Empty Interrupt Enable [6:6] TXEIE Tx buffer Empty Interrupt Enable [7:7] FRF [15:15] SR status register 0x8 RXNE Receive buffer Not Empty [0:0] read-only TXE Transmit buffer Empty [1:1] read-only CHSIDE Channel side [2:2] read-only UDR Underrun flag [3:3] read-only CRCERR CRC error flag [4:4] MODF Mode fault [5:5] OVR Overrun flag [6:6] read-only BSY Busy flag [7:7] read-only FRE [8:8] read-only FRLVL FIFO Reception Level [10:9] read-only FTLVL FIFO Transmission Level [12:11] read-only DR data register 0xC DR Data Register [15:0] CRCPR CRC polynomial register 0x10 CRCPOLY CRC polynomial register [15:0] RXCRCR 0x14 RXCRC rcv crc reg [15:0] TXCRCR 0x18 TXCRC tx crc reg [15:0] read-only I2S_CFGR 0x1C CHLEN Channel length (number of bits per audio channel) [0:0] DATLEN Data length to be transferred [2:1] CKPOL Steady state clock polarity [3:3] I2SSTD I2S standard selection [5:4] PCMSYNC PCM frame synchronization [7:7] I2SCFG I2S configuration mode [9:8] I2SE I2S enable [10:10] I2SMOD I2S mode selection [11:11] I2SPR I2S prescaler register 0x20 I2SDIV I2S linear prescaler [7:0] ODD Odd factor for the prescaler [8:8] MCKOE Master clock output enable [9:9] SPI2 0x40003800 SPI2 SPI2 global Interrupt 26 SYSCFG System configuration controller 0x40010000 0x0 0x190 registers CFGR1 SYSCFG configuration register1 0x0 MEM_MODE [1:0] GPIO_AHB_SEL [24:24] CFGR2 SYSCFG configuration register2 0x4 CLL [0:0] PVDL [2:2] CFGR3 SYSCFG configuration register3 0x8 DMA1_MAP [5:0] DMA2_MAP [13:8] DMA3_MAP [21:16] PA_ENS_REG 0x10 PA_ENS [15:0] PB_ENS_REG 0x14 PB_ENS [15:0] PF_ENS_REG 0x18 PF_ENS [15:0] IOCFG 0x1C PA_EIIC [7:0] PB_EIIC [10:8] PF_EIIC [12:11] PB_EHS [15:13] PA_EHS [24:24] PB_PU_EIIC [27:25] IIC1_FILT_EN [30:30] PA_ANA2EN 0x20 PA9_ANA2EN [9:9] PA10_ANA2EN [10:10] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 control register 1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 control register 2 0x4 CCPC [0:0] CCUS [2:2] CCDS [3:3] MMS_L [6:4] TI1S [7:7] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] OIS2N [11:11] OIS3 [12:12] OIS3N [13:13] OIS4 [14:14] OIS5 [16:16] OIS6 [18:18] MMS_H [25:25] SMCR slave mode control register 0x8 SMS_L [2:0] OCCS [3:3] TS_L [6:4] MSM [7:7] ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] SMS_H [16:16] TS_H [21:20] DIER DMA/Interrupt enable register 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] COMDE [13:13] TDE [14:14] SR status register 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] B2IF [8:8] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] SBIF [13:13] CC5IF [16:16] CC6IF [17:17] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR event generation register 0x14 UG [0:0] CC1G [1:1] CC2G [2:2] CC3G [3:3] CC4G [4:4] COMG [5:5] TG [6:6] BG [7:7] CCMR1_OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M_L [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M_L [14:12] OC2CE [15:15] OC1M_H [16:16] OC2M_H [24:24] CCMR1_INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCMR2_OUTPUT 0x1C CC3S [1:0] OC3FE [2:2] OC3PE [3:3] OC3M_L [6:4] OC3CE [7:7] CC4S [9:8] OC4FE [10:10] OC4PE [11:11] OC4M_L [14:12] OC4CE [15:15] OC3M_H [16:16] OC4M_H [24:24] CCMR2_INPUT CCMR2_OUTPUT 0x1C CC3S [1:0] IC3PSC [3:2] IC3F [7:4] CC4S [9:8] IC4PSC [11:10] IC4F [15:12] CCER capture/compare enableregister 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CC4NP [15:15] CC5E [16:16] CC5P [17:17] CC6E [20:20] CC6P [21:21] CNT counter 0x24 CNT [15:0] PSC prescaler 0x28 PSC [15:0] ARR auto-reload register 0x2C ARR [15:0] RCR repetition counter register 0x30 REP [7:0] CCR1 capture/compare register 1 0x34 CCR1 [15:0] CCR1_H [31:16] CCR2 capture/compare register 2 0x38 CCR2 [15:0] CCR2_H [31:16] CCR3 capture/compare register 3 0x3C CCR3 [15:0] CCR3_H [31:16] CCR4 capture/compare register 4 0x40 CCR4 [15:0] BDTR break and dead-time register 0x44 DTG [7:0] LOCK [9:8] OSSI [10:10] OSSR [11:11] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] CCR5 0x48 CCR5 [15:0] CCR6 0x4C CCR6 [15:0] CCMR3 0x50 OC5FE [2:2] OC5PE [3:3] OC5M_L [6:4] OC5CE [7:7] OC6FE [10:10] OC6PE [11:11] OC6M_L [14:12] OC6CE [15:15] OC5M_H [16:16] OC6M_H [24:24] TISEL 0x5C TI1SEL [3:0] TI2SEL [11:8] TI3SEL [19:16] TI4SEL [27:24] AF1 0x60 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] ETRSEL [17:14] INTR_SEL [19:18] PWM_PHS_EN [20:20] AF2 0x64 OCRSEL [18:16] DCR DMA control register 0x3DC DBA [4:0] DBL [12:8] DMAR DMA address for full transfer 0x3E0 DMAB [31:0] TIM3 TIM 0x40000400 0x0 0x3F0 registers TIM3 TIM3 global Interrupt 16 CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 0x4 CCPC [0:0] CCUS [2:2] CCDS [3:3] MMS_L [6:4] TI1S [7:7] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] OIS2N [11:11] OIS3 [12:12] OIS3N [13:13] OIS4 [14:14] OIS5 [16:16] OIS6 [18:18] MMS_H [25:25] SMCR 0x8 SMS_L [2:0] OCCS [3:3] TS_L [6:4] MSM [7:7] ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] SMS_H [16:16] TS_H [21:20] DIER 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] COMDE [13:13] TDE [14:14] SR 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] B2IF [8:8] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] SBIF [13:13] CC5IF [16:16] CC6IF [17:17] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR 0x14 UG [0:0] CC1G [1:1] CC2G [2:2] CC3G [3:3] CC4G [4:4] COMG [5:5] TG [6:6] BG [7:7] CCMR1_OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M_L [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M_L [14:12] OC2CE [15:15] OC1M_H [16:16] OC2M_H [24:24] CCMR1_INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCMR2_OUTPUT 0x1C CC3S [1:0] OC3FE [2:2] OC3PE [3:3] OC3M_L [6:4] OC3CE [7:7] CC4S [9:8] OC4FE [10:10] OC4PE [11:11] OC4M_L [14:12] OC4CE [15:15] OC3M_H [16:16] OC4M_H [24:24] CCMR2_INPUT CCMR2_OUTPUT 0x1C CC3S [1:0] IC3PSC [3:2] IC3F [7:4] CC4S [9:8] IC4PSC [11:10] IC4F [15:12] CCER 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CC4NP [15:15] CC5E [16:16] CC5P [17:17] CC6E [20:20] CC6P [21:21] CNT 0x24 CNT [15:0] PSC 0x28 PSC [15:0] ARR 0x2C ARR [15:0] CCR1 0x34 CCR1 [15:0] CCR2 0x38 CCR2 [15:0] CCR3 0x3C CCR3 [15:0] CCR4 0x40 CCR4 [15:0] TISEL 0x5C TI1SEL [3:0] TI2SEL [11:8] TI3SEL [19:16] TI4SEL [27:24] AF1 0x60 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] ETRSEL [17:14] INTR_SEL [19:18] PWM_PHS_EN [20:20] AF2 0x64 OCRSEL [18:16] DCR 0x3DC DBA [4:0] DBL [12:8] DMAR 0x3E0 DMAB [31:0] TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 TIM14 control register1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] DIER DMA/Interrupt enable register 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] COMDE [13:13] TDE [14:14] SR status register 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] B2IF [8:8] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] SBIF [13:13] CC5IF [16:16] CC6IF [17:17] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR event generation register 0x14 UG [0:0] CC1G [1:1] CC2G [2:2] CC3G [3:3] CC4G [4:4] COMG [5:5] TG [6:6] BG [7:7] CCMR1_OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M_L [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M_L [14:12] OC2CE [15:15] OC1M_H [16:16] OC2M_H [24:24] CCMR1_INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCER capture/compare enableregister 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CC4NP [15:15] CC5E [16:16] CC5P [17:17] CC6E [20:20] CC6P [21:21] CNT counter 0x24 CNT [15:0] PSC prescaler 0x28 PSC [15:0] ARR auto-reload register 0x2C ARR [15:0] CCR1 capture/compare register 1 0x34 CCR1 [15:0] TISEL 0x5C TI1SEL [3:0] TIM16 General purpose timer TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global Interrupt 21 CR1 TIM16 control register1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 control register 2 0x4 CCPC [0:0] CCUS [2:2] CCDS [3:3] MMS_L [6:4] TI1S [7:7] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] OIS2N [11:11] OIS3 [12:12] OIS3N [13:13] OIS4 [14:14] OIS5 [16:16] OIS6 [18:18] MMS_H [25:25] DIER DMA/Interrupt enable register 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] COMDE [13:13] TDE [14:14] SR status register 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] B2IF [8:8] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] SBIF [13:13] CC5IF [16:16] CC6IF [17:17] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR event generation register 0x14 UG [0:0] CC1G [1:1] CC2G [2:2] CC3G [3:3] CC4G [4:4] COMG [5:5] TG [6:6] BG [7:7] CCMR1_OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M_L [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M_L [14:12] OC2CE [15:15] OC1M_H [16:16] OC2M_H [24:24] CCMR1_INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCER capture/compare enableregister 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CC4NP [15:15] CC5E [16:16] CC5P [17:17] CC6E [20:20] CC6P [21:21] CNT counter 0x24 CNT [15:0] PSC prescaler 0x28 PSC [15:0] ARR auto-reload register 0x2C ARR [15:0] RCR repetition counter register 0x30 REP [7:0] CCR1 capture/compare register 1 0x34 CCR1 [15:0] BDTR break and dead-time register 0x44 DTG [7:0] LOCK [9:8] OSSI [10:10] OSSR [11:11] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] TISEL 0x5C TI1SEL [3:0] TI2SEL [11:8] TI3SEL [19:16] TI4SEL [27:24] AF1 0x60 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] DCR DMA control register 0x3DC DBA [4:0] DBL [12:8] DMAR DMA address for full transfer 0x3E0 DMAB [31:0] TIM17 0x40014800 TIM17 TIM17 global Interrupt 22 UART1 UART 0x40004800 0x0 0x30 registers UART1 UART1 global Interrupt 28 DR 0x0 DR Receive/send data register [8:0] BRR 0x4 BRR Baud rate register [15:0] SR 0x10 RXNE Receive register not empty [0:0] read-only ORE Overrun error bit [1:1] PE Parity Error bit [2:2] FE Framing Error bit [3:3] BRI Break Interrupt bit [4:4] TDRE Transmit Holding Register Empty bit [5:5] read-only TXE Transmitter Empty bit [6:6] read-only ADDR_RCVD Address Received Bit [8:8] BUSY UART Busy [9:9] read-only BUSY_ERR Busy Detect Error [10:10] CR1 0x14 M Data Length Select [1:0] STOP Number of stop bits [2:2] PCE Parity Enable [3:3] PS Even Parity Select [4:4] SP Stick Parity [5:5] SBK Send Break [6:6] SWAP TX/RX pin swap [8:8] MSBFIRST MSB first mode [9:9] CR2 0x18 RXNEIE Enable Received Data Available Interrupt [0:0] TDREIE Enable Transmit Holding Register Empty Interrupt [1:1] LSIE Enable Receiver Line Status Interrupt [2:2] BUSYERRIE Enable Busyerr state interruption [3:3] TXEIE Enable tx empty interruption [4:4] CR3 0x1C M_E Extension for DLS [0:0] ADDR_MATCH Address Match Mode [1:1] SEND_ADDR Send address control bit [2:2] TX_MODE Transmit mode control bit [3:3] DMAR DMA receive enable [4:4] DMAT DMA transmit enable [5:5] DMA_SOFT_ACK DMA software ack [6:6] RAR 0x20 RAR Receive address matching register [7:0] TAR 0x24 TAR Transmit address matching register [7:0] BRRF 0x28 BRRF Baud rate fractional register [3:0] USART1 Universal synchronous asynchronous receivertransmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR Status register 0x0 PE Parity error [0:0] read-only FE Framing error [1:1] read-only NE Noise error flag [2:2] read-only ORE overrun error [3:3] read-only IDLE idle [4:4] read-only RXNE Read data register not empty [5:5] TC Transmission complete [6:6] TXE Transmit data register empty [7:7] read-only LBD LIN break detection flag [8:8] CTS cts flag [9:9] ABRF auto baud rate flag [10:10] read-only ABRE auto baud rateerror [11:11] read-only ABRRQ auto baud rate req [12:12] read-only RTOF rto flag [19:19] TXPE [20:20] RXBUSY [21:21] read-only TXBUSY [22:22] read-only DR Data register 0x4 DR dr [8:0] BRR Baud rate register 0x8 DIV_FRACTION DIV_Fraction [3:0] DIV_MANTISSA DIV_Mantissa [15:4] CR1 Control register 1 0xC SBK Send break [0:0] RWU Receiver wakeup [1:1] RE Receiver enable [2:2] TE Transmitter enable [3:3] IDLEIE IDLE interrupt enable [4:4] RXNEIE RXNE interrupt enable [5:5] TCIE send complete int enable [6:6] TXEIE txe [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control enable [10:10] WAKE Wakeup method [11:11] M word length [12:12] UE uesart enable [13:13] MSBFIRST msbfirst [15:15] SWAP swap [18:18] DATAINV data inverse [27:27] CR2 Control register 2 0x10 ADD mute addr [3:0] LBDL LIN break detection length [5:5] LBDIE lin break enable [6:6] LBCL lbcl [8:8] CPHA cpha [9:9] CPOL cpol [10:10] CLKEN clk en [11:11] STOP stop bit [13:12] LINEN lin enable [14:14] RTOEN Receiver timeout enable [25:25] CR3 Control register 3 0x14 EIE error int enable [0:0] HDSEL hdsel [3:3] DMAR dma rx enable [6:6] DMAT dma tx enable [7:7] RTSE rts enable [8:8] CTSE cts enable [9:9] CTSIE cts int enable [10:10] OVER8 oversampling [11:11] ABREN autobaud enable [12:12] ABRMOD auto baud mod [14:13] RTOIE rto int enable [29:29] TXLSEIE tx register empty int enable [31:31] RTOR 0x1C RTO receive timeout [23:0] WWDG Window watchdog 0x40002C00 0x0 0x400 registers WWDG Window WatchDog Interrupt 0 CR Control register (WWDG_CR) 0x0 T wwdg counter bit [6:0] WDGA WWDG Activation [7:7] CFR Configuration register(WWDG_CFR) 0x4 W window value bit [6:0] WDGTB time base bit [8:7] EWI Early wakeup interrupt [9:9] SR Status register (WWDG_SR) 0x8 EWIF Early wakeup interrupt flag [0:0]