Puya Puya PY32F020Bxx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupts 12 ISR ADC interrupt and status register 0x0 EOSMP ADC group regular end of sampling flag [1:1] EOC ADC group regular end of unitary conversion flag [2:2] EOSEQ ADC group regular end of sequence conversions flag [3:3] OVR ADC group regular overrun flag [4:4] AWD ADC analog watchdog flag [7:7] IER ADC interrupt enable register 0x4 EOSMPIE ADC group regular end of sampling interrupt [1:1] EOCIE ADC group regular end of unitary conversion interrupt [2:2] EOSEQIE ADC group regular end of sequence conversions interrupt [3:3] OVRIE ADC group regular overrun interrupt [4:4] AWDIE ADC analog watchdog interrupt [7:7] CR ADC control register 0x8 ADEN enabl adc [0:0] ADDIS addis conversion [1:1] ADSTART start conversion [2:2] ADSTP stop conversion [4:4] ADCAL calibration enable [31:31] CFGR1 ADC configuration register 1 0xC SCANDIR sequence direction [2:2] RESSEL conversion ressel select [4:3] read-only ALIGN align mode [5:5] EXTSEL tigle select [8:6] EXTEN trigle mode select [11:10] OVRMOD over mode [12:12] CONT continul mode [13:13] WAIT wait mode [14:14] DISCEN discent mode [16:16] AWDSGL awd single mode [22:22] AWDEN awd enable [23:23] AWDCH awd channels [29:26] SMP 0x14 SMP sample time [2:0] TR ADC analog watchdog 1 threshold register 0x20 LT watch dog values of low [11:0] HT watch dog values of high [27:16] CHSEL 0x28 CHSEL0 Channel-0 selection [0:0] CHSEL1 Channel-1 selection [1:1] CHSEL2 Channel-2 selection [2:2] CHSEL3 Channel-3 selection [3:3] CHSEL4 Channel-4 selection [4:4] CHSEL5 Channel-5 selection [5:5] CHSEL6 Channel-6 selection [6:6] CHSEL7 Channel-7 selection [7:7] CHSEL8 Channel-8 selection [8:8] CHSEL9 Channel-9 selection [9:9] CHSEL10 Channel-10 selection [10:10] CHSEL11 Channel-11 selection [11:11] CHSEL12 Channel-12 selection [12:12] DR ADC group regular data register 0x40 DATA conversion data [15:0] read-only CCSR ADC calibration configuration and status register 0x44 CALSEL calibration mode select [11:11] CALSMP calibration sample time [13:12] CALSET calibration value of set [15:15] OFFSUC offset line calibration success [29:29] CAPSUC capu calibration success [30:30] CALON calibration status [31:31] read-only CALRR1 ADC calibration result register 1 0x48 CALC8OUT CALC8OUT [7:0] read-only CALC9OUT CALC9OUT [15:8] read-only CALC10OUT CALC10OUT [23:16] read-only CALC11OUT CALC11OUT [31:24] read-only CALRR2 ADC calibration result register 2 0x4C CALC4OUT CALC4OUT [7:0] read-only CALC5OUT CALC5OUT [15:8] read-only CALC6OUT CALC6OUT [23:16] read-only CALC7OUT CALC7OUT [31:24] read-only CALRR3 ADC calibration result register 3 0x50 CALBOUT CALBOUT [11:0] read-only CALC2OUT CALC2OUT [20:16] read-only CALC3OUT CALC3OUT [28:24] read-only CALFIR1 ADC calibration factor input register 1 0x54 CALC8IO CALC8IO [7:0] CALC9IO CALC9IO [15:8] CALC10IO CALC10IO [23:16] CALC11IO CALC11IO [31:24] CALFIR2 ADC calibration factor input register 2 0x58 CALC4IO CALC4IO [7:0] CALC5IO CALC5IO [15:8] CALC6IO CALC6IO [23:16] CALC7IO CALC7IO [31:24] CALFIR3 ADC calibration factor input register 2 0x5C CALBIO CALBIO [11:0] CALC2IO CALC2IO [20:16] CALC3IO CALC3IO [28:24] CAL_TEST 0x60 CAL_TEST calibration test values [2:0] DEBUG_SEL debug mode select output of sigs [5:3] CCR ADC common configuration register 0x308 VREF_BUFFERE VerfBuffer enable [5:5] VERFBUFF_SEL VREFBUF output voltage select [7:6] VREFEN reference voltage enable [22:22] TSEN ts line enable [23:23] COMP1 Comparator 1 COMP 0x40010200 0x0 0x10 registers ADC_COMP ADC and COMP Interrupts 12 CSR COMP control and status register 0x0 COMP1_EN COMP1 enable bit [0:0] INMSEL COMP1 negative input select [7:6] INPSEL COMP1 positive input select [9:8] WINMODE COMP1 window mode enable [11:11] POLARITY COMP1 output polarity selection [15:15] PWRMODE COMP1 power mode selection [18:18] COMP_VCDIV COMP1, COMP2 partial voltage selection [25:20] COMP_VCDIV_EN VREFCMP voltage divider enable signal [26:26] COMP_VCSEL VREFCMP reference source selection [27:27] TIM_EXTI_OUT_SEL COMP1 output to TIM/EXTI selection [29:29] COMP_OUT COMP1 output status [30:30] read-only FR Comparator Filter register 0x4 FLTEN1 Comparator 1 digital filter configuration [0:0] FLTCNT1 Comparator 1 sampling filter counter [31:16] COMP2 Comparator2 COMP 0x40010210 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt 12 CSR COMP control and status register 0x0 COMP2_EN COMP2 enable bit [0:0] INMSEL COMP2 negative input select [7:6] INPSEL COMP2 positive input select [9:8] POLARITY COMP2 output polarity selection [15:15] PWRMODE COMP2 power mode selection [18:18] TIM_EXTI_OUT_SEL COMP2 output to TIM/EXTI selection [29:29] COMP_OUT COMP2 output status [30:30] read-only FR Comparator Filter register 0x4 FLTEN2 Comparator 2 digital filtering configuration [0:0] FLTCNT2 Comparator 2 sampling filter counter [31:16] CRC CRC calculation unit 0x40023000 0x0 0x400 registers DR Data register 0x0 DR Data register bits [31:0] IDR Independent Data register 0x4 IDR General-purpose 8-bit data register bits [7:0] CR Control register 0x8 RESET Reset the CRC module [0:0] write-only DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 read-only REV_ID REV_ID [31:0] CR CR Debug MCU Configuration Register 0x4 DBG_SLEEP Debug Sleep Mode [0:0] DBG_STOP Debug Stop Mode [1:1] APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 DBG_RTC_STOP Debug RTC stopped whenCore is halted [10:10] DBG_IWDG_STOP Debug Independent Wachdog stopped whenCore is halted [12:12] APB_FZ2 APB_FZ2 APB Freeze Register2 0xC DBG_TIMER1_STOP Debug Timer 1 stopped when Core ishalted [11:11] DBG_TIM14_STOP Debug TIM 14 stopped whenCore is halted [15:15] EXTI External interrupt/event controller 0x40021800 0x0 0x400 registers EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR EXTI rising trigger selection register 0x0 RT0 Rising trigger event configuration bit of Configurable Event input [0:0] RT1 Rising trigger event configuration bit of Configurable Event input [1:1] RT2 Rising trigger event configuration bit of Configurable Event input [2:2] RT3 Rising trigger event configuration bit of Configurable Event input [3:3] RT4 Rising trigger event configuration bit of Configurable Event input [4:4] RT5 Rising trigger event configuration bit of Configurable Event input [5:5] RT6 Rising trigger event configuration bit of Configurable Event input [6:6] RT7 Rising trigger event configuration bit of Configurable Event input [7:7] RT8 Rising trigger event configuration bit of Configurable Event input [8:8] RT9 Rising trigger event configuration bit of Configurable Event input [9:9] RT10 Rising trigger event configuration bit of Configurable Event input [10:10] RT11 Rising trigger event configuration bit of Configurable Event input [11:11] RT12 Rising trigger event configuration bit of Configurable Event input [12:12] RT13 Rising trigger event configuration bit of Configurable Event input [13:13] RT14 Rising trigger event configuration bit of Configurable Event input [14:14] RT15 Rising trigger event configuration bit of Configurable Event input [15:15] RT17 Rising trigger event configuration bit of Configurable Event input [17:17] RT18 Rising trigger event configuration bit of Configurable Event input [18:18] FTSR EXTI falling trigger selection register 0x4 FT0 Falling trigger event configuration bit of Configurable Event input [0:0] FT1 Falling trigger event configuration bit of Configurable Event input [1:1] FT2 Falling trigger event configuration bit of Configurable Event input [2:2] FT3 Falling trigger event configuration bit of Configurable Event input [3:3] FT4 Falling trigger event configuration bit of Configurable Event input [4:4] FT5 Falling trigger event configuration bit of Configurable Event input [5:5] FT6 Falling trigger event configuration bit of Configurable Event input [6:6] FT7 Falling trigger event configuration bit of Configurable Event input [7:7] FT8 Falling trigger event configuration bit of Configurable Event input [8:8] FT9 Falling trigger event configuration bit of Configurable Event input [9:9] FT10 Falling trigger event configuration bit of Configurable Event input [10:10] FT11 Falling trigger event configuration bit of Configurable Event input [11:11] FT12 Falling trigger event configuration bit of Configurable Event input [12:12] FT13 Falling trigger event configuration bit of Configurable Event input [13:13] FT14 Falling trigger event configuration bit of Configurable Event input [14:14] FT15 Falling trigger event configuration bit of Configurable Event input [15:15] FT17 Falling trigger event configuration bit of Configurable Event input [17:17] FT18 Falling trigger event configuration bit of Configurable Event input [18:18] SWIER EXTI software interrupt event register 0x8 SWI0 Configurable exti linex enable of soft trigle [0:0] SWI1 Configurable exti linex enable of soft trigle [1:1] SWI2 Configurable exti linex enable of soft trigle [2:2] SWI3 Configurable exti linex enable of soft trigle [3:3] SWI4 Configurable exti linex enable of soft trigle [4:4] SWI5 Configurable exti linex enable of soft trigle [5:5] SWI6 Configurable exti linex enable of soft trigle [6:6] SWI7 Configurable exti linex enable of soft trigle [7:7] SWI8 Configurable exti linex enable of soft trigle [8:8] SWI9 Configurable exti linex enable of soft trigle [9:9] SWI10 Configurable exti linex enable of soft trigle [10:10] SWI11 Configurable exti linex enable of soft trigle [11:11] SWI12 Configurable exti linex enable of soft trigle [12:12] SWI13 Configurable exti linex enable of soft trigle [13:13] SWI14 Configurable exti linex enable of soft trigle [14:14] SWI15 Configurable exti linex enable of soft trigle [15:15] SWI17 Configurable exti linex enable of soft trigle [17:17] SWI18 Configurable exti linex enable of soft trigle [18:18] PR EXTI pending register 0xC PR0 Pending line of exti [0:0] PR1 Pending line of exti [1:1] PR2 Pending line of exti [2:2] PR3 Pending line of exti [3:3] PR4 Pending line of exti [4:4] PR5 Pending line of exti [5:5] PR6 Pending line of exti [6:6] PR7 Pending line of exti [7:7] PR8 Pending line of exti [8:8] PR9 Pending line of exti [9:9] PR10 Pending line of exti [10:10] PR11 Pending line of exti [11:11] PR12 Pending line of exti [12:12] PR13 Pending line of exti [13:13] PR14 Pending line of exti [14:14] PR15 Pending line of exti [15:15] PR17 Pending line of exti [17:17] PR18 Pending line of exti [18:18] EXTICR1 0x60 EXTI0 GPIO exti line select [1:0] EXTI1 GPIO exti line select [9:8] EXTI2 GPIO exti line select [17:16] EXTI3 GPIO exti line select [25:24] EXTICR2 0x64 EXTI4 GPIO exti line select [1:0] EXTI5 GPIO exti line select [9:8] IMR EXTI CPU wakeup with interrupt mask register 0x80 IM0 EXIT Mask enable [0:0] IM1 EXIT Mask enable [1:1] IM2 EXIT Mask enable [2:2] IM3 EXIT Mask enable [3:3] IM4 EXIT Mask enable [4:4] IM5 EXIT Mask enable [5:5] IM6 EXIT Mask enable [6:6] IM7 EXIT Mask enable [7:7] IM8 EXIT Mask enable [8:8] IM9 EXIT Mask enable [9:9] IM10 EXIT Mask enable [10:10] IM11 EXIT Mask enable [11:11] IM12 EXIT Mask enable [12:12] IM13 EXIT Mask enable [13:13] IM14 EXIT Mask enable [14:14] IM15 EXIT Mask enable [15:15] IM17 EXIT Mask enable [17:17] IM18 EXIT Mask enable [18:18] IM19 EXIT Mask enable [19:19] IM23 EXIT Mask enable [23:23] IM28 EXIT Mask enable [28:28] EMR EXTI CPU wakeup with event mask register 0x84 EM0 EXIT Mask enable [0:0] EM1 EXIT Mask enable [1:1] EM2 EXIT Mask enable [2:2] EM3 EXIT Mask enable [3:3] EM4 EXIT Mask enable [4:4] EM5 EXIT Mask enable [5:5] EM6 EXIT Mask enable [6:6] EM7 EXIT Mask enable [7:7] EM8 EXIT Mask enable [8:8] EM9 EXIT Mask enable [9:9] EM10 EXIT Mask enable [10:10] EM11 EXIT Mask enable [11:11] EM12 EXIT Mask enable [12:12] EM13 EXIT Mask enable [13:13] EM14 EXIT Mask enable [14:14] EM15 EXIT Mask enable [15:15] EM17 EXIT Mask enable [17:17] EM18 EXIT Mask enable [18:18] EM19 EXIT Mask enable [19:19] EM23 EXIT Mask enable [23:23] EM28 EXIT Mask enable [28:28] FLASH 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR 0x0 LATENCY Latency [1:0] KEY 0x8 KEY Flash CR key [31:0] write-only OPTKEY 0xC OPTKEY Flash Option key [31:0] write-only SR 0x10 EOP End of operation [0:0] WRPERR Write protection error [4:4] USRLOCK Userdata Lock [13:13] read-only OPTVERR Option and trimming bits loading validity error [15:15] BSY Busy [16:16] read-only CR 0x14 PG Page Program [0:0] PER Page Erase [1:1] MER Mass Erase [2:2] SER Sector Erase [11:11] OPTSTRT Option bytes Programming Start [17:17] PGSTRT Programming Start [19:19] EOPIE End of operation interrupt enable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option bytes loading [27:27] OPTLOCK Option Lock [30:30] LOCK Lock [31:31] OPTR 0x20 RDP Read Protection [7:0] BOR_EN BOR enable [8:8] BOR_LEV BOR Level [11:9] IWDG_SW IWDG Software Enable [12:12] NRST_MODE Pin n_reset Mode [14:14] IWDG_STOP IWDG Counting enable in Stop Mode [15:15] SDKR 0x24 SDK_STRT SDK Area Start Address [3:0] SDK_END SDK Area End Address [11:8] BTCR 0x28 BOOT_SIZE Load Flash Size [2:0] SWD_MODE SWD Mode [9:8] BOOT0 BOOT0 [14:14] NBOOT1 nBOOT1 [15:15] WRPR 0x2C WRP Write Protection Disable [7:0] STCR 0x90 SLEEP_EN FLASH Sleep Enable [0:0] SLEEP_TIME FLASH Sleep Time Configuration [15:8] TS0 0x100 TS0 TS0 [8:0] TS1 0x104 TS1 TS1 [9:0] TS2P 0x108 TS2P TS2P [8:0] TPS3 0x10C TPS3 TPS3 [11:0] TS3 0x110 TS3 TS3 [8:0] PERTPE 0x114 PERTPE PERTPE [17:0] SMERTPE 0x118 SMERTPE SMERTPE [17:0] PRGTPE 0x11C PRGTPE PRGTPE [15:0] PRETPE 0x120 PRETPE PRETPE [13:0] GPIOA General-purpose I/Os 0x50000000 0x0 0x400 registers MODER GPIO port mode register 0x0 MODE0 Port x configuration I/O pin 0 [1:0] MODE1 Port x configuration I/O pin 1 [3:2] MODE2 Port x configuration I/O pin 2 [5:4] MODE3 Port x configuration I/O pin 3 [7:6] MODE4 Port x configuration I/O pin 4 [9:8] MODE5 Port x configuration I/O pin 5 [11:10] MODE6 Port x configuration I/O pin 6 [13:12] MODE7 Port x configuration I/O pin 7 [15:14] MODE8 Port x configuration I/O pin 8 [17:16] MODE9 Port x configuration I/O pin 9 [19:18] MODE10 Port x configuration I/O pin 10 [21:20] MODE11 Port x configuration I/O pin 11 [23:22] MODE12 Port x configuration I/O pin 12 [25:24] MODE13 Port x configuration I/O pin 13 [27:26] MODE14 Port x configuration I/O pin 14 [29:28] MODE15 Port x configuration I/O pin 15 [31:30] OTYPER GPIO port output type register 0x4 OT0 Port x configuration I/O pin 0 [0:0] OT1 Port x configuration I/O pin 1 [1:1] OT2 Port x configuration I/O pin 2 [2:2] OT3 Port x configuration I/O pin 3 [3:3] OT4 Port x configuration I/O pin 4 [4:4] OT5 Port x configuration I/O pin 5 [5:5] OT6 Port x configuration I/O pin 6 [6:6] OT7 Port x configuration I/O pin 7 [7:7] OT8 Port x configuration I/O pin 8 [8:8] OT9 Port x configuration I/O pin 9 [9:9] OT10 Port x configuration I/O pin 10 [10:10] OT11 Port x configuration I/O pin 11 [11:11] OT12 Port x configuration I/O pin 12 [12:12] OT13 Port x configuration I/O pin 13 [13:13] OT14 Port x configuration I/O pin 14 [14:14] OT15 Port x configuration I/O pin 15 [15:15] OSPEEDR GPIO port output speed register 0x8 OSPEED0 Port x configuration I/O pin 0 [1:0] OSPEED1 Port x configuration I/O pin 1 [3:2] OSPEED2 Port x configuration I/O pin 2 [5:4] OSPEED3 Port x configuration I/O pin 3 [7:6] OSPEED4 Port x configuration I/O pin 4 [9:8] OSPEED5 Port x configuration I/O pin 5 [11:10] OSPEED6 Port x configuration I/O pin 6 [13:12] OSPEED7 Port x configuration I/O pin 7 [15:14] OSPEED8 Port x configuration I/O pin 8 [17:16] OSPEED9 Port x configuration I/O pin 9 [19:18] OSPEED10 Port x configuration I/O pin 10 [21:20] OSPEED11 Port x configuration I/O pin 11 [23:22] OSPEED12 Port x configuration I/O pin 12 [25:24] OSPEED13 Port x configuration I/O pin 13 [27:26] OSPEED14 Port x configuration I/O pin 14 [29:28] OSPEED15 Port x configuration I/O pin 15 [31:30] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 Port x configuration I/O pin 0 [1:0] PUPD1 Port x configuration I/O pin 1 [3:2] PUPD2 Port x configuration I/O pin 2 [5:4] PUPD3 Port x configuration I/O pin 3 [7:6] PUPD4 Port x configuration I/O pin 4 [9:8] PUPD5 Port x configuration I/O pin 5 [11:10] PUPD6 Port x configuration I/O pin 6 [13:12] PUPD7 Port x configuration I/O pin 7 [15:14] PUPD8 Port x configuration I/O pin 8 [17:16] PUPD9 Port x configuration I/O pin 9 [19:18] PUPD10 Port x configuration I/O pin 10 [21:20] PUPD11 Port x configuration I/O pin 11 [23:22] PUPD12 Port x configuration I/O pin 12 [25:24] PUPD13 Port x configuration I/O pin 13 [27:26] PUPD14 Port x configuration I/O pin 14 [29:28] PUPD15 Port x configuration I/O pin 15 [31:30] IDR GPIO port input data register 0x10 ID0 Port x input data I/O pin 0 [0:0] read-only ID1 Port x input data I/O pin 1 [1:1] read-only ID2 Port x input data I/O pin 2 [2:2] read-only ID3 Port x input data I/O pin 3 [3:3] read-only ID4 Port x input data I/O pin 4 [4:4] read-only ID5 Port x input data I/O pin 5 [5:5] read-only ID6 Port x input data I/O pin 6 [6:6] read-only ID7 Port x input data I/O pin 7 [7:7] read-only ID8 Port x input data I/O pin 8 [8:8] read-only ID9 Port x input data I/O pin 9 [9:9] read-only ID10 Port x input data I/O pin 10 [10:10] read-only ID11 Port x input data I/O pin 11 [11:11] read-only ID12 Port x input data I/O pin 12 [12:12] read-only ID13 Port x input data I/O pin 13 [13:13] read-only ID14 Port x input data I/O pin 14 [14:14] read-only ID15 Port x input data I/O pin 15 [15:15] read-only ODR GPIO port output data register 0x14 OD0 Port output data I/O pin 0 [0:0] OD1 Port output data I/O pin 1 [1:1] OD2 Port output data I/O pin 2 [2:2] OD3 Port output data I/O pin 3 [3:3] OD4 Port output data I/O pin 4 [4:4] OD5 Port output data I/O pin 5 [5:5] OD6 Port output data I/O pin 6 [6:6] OD7 Port output data I/O pin 7 [7:7] OD8 Port output data I/O pin 8 [8:8] OD9 Port output data I/O pin 9 [9:9] OD10 Port output data I/O pin 10 [10:10] OD11 Port output data I/O pin 11 [11:11] OD12 Port output data I/O pin 12 [12:12] OD13 Port output data I/O pin 13 [13:13] OD14 Port output data I/O pin 14 [14:14] OD15 Port output data I/O pin 15 [15:15] BSRR GPIO port bit set/reset register 0x18 BS0 Port x set I/O pin 0 [0:0] write-only BS1 Port x set I/O pin 1 [1:1] write-only BS2 Port x set I/O pin 2 [2:2] write-only BS3 Port x set I/O pin 3 [3:3] write-only BS4 Port x set I/O pin 4 [4:4] write-only BS5 Port x set I/O pin 5 [5:5] write-only BS6 Port x set I/O pin 6 [6:6] write-only BS7 Port x set I/O pin 7 [7:7] write-only BS8 Port x set I/O pin 8 [8:8] write-only BS9 Port x set I/O pin 9 [9:9] write-only BS10 Port x set I/O pin 10 [10:10] write-only BS11 Port x set I/O pin 11 [11:11] write-only BS12 Port x set I/O pin 12 [12:12] write-only BS13 Port x set I/O pin 13 [13:13] write-only BS14 Port x set I/O pin 14 [14:14] write-only BS15 Port x set I/O pin 15 [15:15] write-only BR0 Port x reset I/O pin 0 [16:16] write-only BR1 Port x reset I/O pin 1 [17:17] write-only BR2 Port x reset I/O pin 2 [18:18] write-only BR3 Port x reset I/O pin 3 [19:19] write-only BR4 Port x reset I/O pin 4 [20:20] write-only BR5 Port x reset I/O pin 5 [21:21] write-only BR6 Port x reset I/O pin 6 [22:22] write-only BR7 Port x reset I/O pin 7 [23:23] write-only BR8 Port x reset I/O pin 8 [24:24] write-only BR9 Port x reset I/O pin 9 [25:25] write-only BR10 Port x reset I/O pin 10 [26:26] write-only BR11 Port x reset I/O pin 11 [27:27] write-only BR12 Port x reset I/O pin 12 [28:28] write-only BR13 Port x reset I/O pin 13 [29:29] write-only BR14 Port x reset I/O pin 14 [30:30] write-only BR15 Port x reset I/O pin 15 [31:31] write-only LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock I/O pin 0 [0:0] LCK1 Port x lock I/O pin 1 [1:1] LCK2 Port x lock I/O pin 2 [2:2] LCK3 Port x lock I/O pin 3 [3:3] LCK4 Port x lock I/O pin 4 [4:4] LCK5 Port x lock I/O pin 5 [5:5] LCK6 Port x lock I/O pin 6 [6:6] LCK7 Port x lock I/O pin 7 [7:7] LCK8 Port x lock I/O pin 8 [8:8] LCK9 Port x lock I/O pin 9 [9:9] LCK10 Port x lock I/O pin 10 [10:10] LCK11 Port x lock I/O pin 11 [11:11] LCK12 Port x lock I/O pin 12 [12:12] LCK13 Port x lock I/O pin 13 [13:13] LCK14 Port x lock I/O pin 14 [14:14] LCK15 Port x lock I/O pin 15 [15:15] LCKK Lock key [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x I/O pin 0 [2:0] AFSEL1 Alternate function selection for port x I/O pin 1 [6:4] AFSEL2 Alternate function selection for port x I/O pin 2 [10:8] AFSEL3 Alternate function selection for port x I/O pin 4 [14:12] AFSEL4 Alternate function selection for port x I/O pin 4 [18:16] AFSEL5 Alternate function selection for port x I/O pin 5 [22:20] AFSEL6 Alternate function selection for port x I/O pin 6 [26:24] AFSEL7 Alternate function selection for port x I/O pin 7 [30:28] AFRH GPIO alternate function high register 0x24 AFSEL8 Alternate function selection for port x I/O pin 8 [2:0] AFSEL9 Alternate function selection for port x I/O pin 9 [6:4] AFSEL10 Alternate function selection for port x I/O pin 10 [10:8] AFSEL11 Alternate function selection for port x I/O pin 11 [14:12] AFSEL12 Alternate function selection for port x I/O pin 12 [18:16] AFSEL13 Alternate function selection for port x I/O pin 13 [22:20] AFSEL14 Alternate function selection for port x I/O pin 14 [26:24] AFSEL15 Alternate function selection for port x I/O pin 15 [30:28] BRR port bit reset register 0x28 BR0 Port x reset IO pin 0 [0:0] BR1 Port x reset IO pin 1 [1:1] BR2 Port x reset IO pin 2 [2:2] BR3 Port x reset IO pin 3 [3:3] BR4 Port x reset IO pin 4 [4:4] BR5 Port x reset IO pin 5 [5:5] BR6 Port x reset IO pin 6 [6:6] BR7 Port x reset IO pin 7 [7:7] BR8 Port x reset IO pin 8 [8:8] BR9 Port x reset IO pin 9 [9:9] BR10 Port x reset IO pin 10 [10:10] BR11 Port x reset IO pin 11 [11:11] BR12 Port x reset IO pin 12 [12:12] BR13 Port x reset IO pin 13 [13:13] BR14 Port x reset IO pin 14 [14:14] BR15 Port x reset IO pin 15 [15:15] GPIOB General-purpose I/Os 0x50000400 0x0 0x400 registers MODER GPIO port mode register 0x0 MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] MODE2 Port x configuration bits (y = 0..15) [5:4] MODE3 Port x configuration bits (y = 0..15) [7:6] OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OT2 Port x configuration bits (y = 0..15) [2:2] OT3 Port x configuration bits (y = 0..15) [3:3] OSPEEDR GPIO port output speed register 0x8 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] OSPEED2 Port x configuration bits (y = 0..15) [5:4] OSPEED3 Port x configuration bits (y = 0..15) [7:6] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] PUPD2 Port x configuration bits (y = 0..15) [5:4] PUPD3 Port x configuration bits (y = 0..15) [7:6] IDR GPIO port input data register 0x10 ID0 Port input data (y = 0..15) [0:0] read-only ID1 Port input data (y = 0..15) [1:1] read-only ID2 Port input data (y = 0..15) [2:2] read-only ID3 Port input data (y = 0..15) [3:3] read-only ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] OD2 Port output data (y = 0..15) [2:2] OD3 Port output data (y = 0..15) [3:3] BSRR GPIO port bit set/reset register 0x18 BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BS2 Port x set bit y (y= 0..15) [2:2] BS3 Port x set bit y (y= 0..15) [3:3] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] BR2 Port x reset bit y (y = 0..15) [18:18] BR3 Port x reset bit y (y = 0..15) [19:19] LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCK2 Port x lock bit y (y= 0..15) [2:2] LCK3 Port x lock bit y (y= 0..15) [3:3] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port x bit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port x bit y (y = 0..7) [15:12] BRR port bit reset register 0x28 BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] GPIOF 0x50001400 0x0 0x400 registers MODER 0x0 MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] MODE2 Port x configuration bits (y = 0..15) [5:4] MODE3 Port x configuration bits (y = 0..15) [7:6] MODE4 Port x configuration bits (y = 0..15) [9:8] MODE5 Port x configuration bits (y = 0..15) [11:10] OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OT2 Port x configuration bits (y = 0..15) [2:2] OT3 Port x configuration bits (y = 0..15) [3:3] OT4 Port x configuration bits (y = 0..15) [4:4] OT5 Port x configuration bits (y = 0..15) [5:5] OSPEEDR GPIO port output speed register 0x8 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] OSPEED2 Port x configuration bits (y = 0..15) [5:4] OSPEED3 Port x configuration bits (y = 0..15) [7:6] OSPEED4 Port x configuration bits (y = 0..15) [9:8] OSPEED5 Port x configuration bits (y = 0..15) [11:10] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] PUPD2 Port x configuration bits (y = 0..15) [5:4] PUPD3 Port x configuration bits (y = 0..15) [7:6] PUPD4 Port x configuration bits (y = 0..15) [9:8] PUPD5 Port x configuration bits (y = 0..15) [11:10] IDR GPIO port input data register 0x10 ID0 Port input data (y = 0..15) [0:0] read-only ID1 Port input data (y = 0..15) [1:1] read-only ID2 Port input data (y = 0..15) [2:2] read-only ID3 Port input data (y = 0..15) [3:3] read-only ID4 Port input data (y = 0..15) [4:4] read-only ID5 Port input data (y = 0..15) [5:5] read-only ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] OD2 Port output data (y = 0..15) [2:2] OD3 Port output data (y = 0..15) [3:3] OD4 Port output data (y = 0..15) [4:4] OD5 Port output data (y = 0..15) [5:5] BSRR GPIO port bit set/reset register 0x18 BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BS2 Port x set bit y (y= 0..15) [2:2] BS3 Port x set bit y (y= 0..15) [3:3] BS4 Port x set bit y (y= 0..15) [4:4] BS5 Port x set bit y (y= 0..15) [5:5] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] BR2 Port x reset bit y (y = 0..15) [18:18] BR3 Port x reset bit y (y = 0..15) [19:19] BR4 Port x reset bit y (y = 0..15) [20:20] BR5 Port x reset bit y (y = 0..15) [21:21] LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCK2 Port x lock bit y (y= 0..15) [2:2] LCK3 Port x lock bit y (y= 0..15) [3:3] LCK4 Port x lock bit y (y= 0..15) [4:4] LCK5 Port x lock bit y (y= 0..15) [5:5] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port x bit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port x bit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port x bit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port x bit y (y = 0..7) [23:20] BRR port bit reset register 0x28 BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] I2C Inter integrated circuit 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 Control register 1 0x0 16 PE Peripheral enable [0:0] WUPEN Wakeup from Stop mode enable [2:2] ENGC General call enable [6:6] NOSTRETCH Clock stretching disable (Slave mode) [7:7] START Start generation [8:8] STOP Stop generation [9:9] ACK Acknowledge enable [10:10] POS Acknowledge(for data reception) [11:11] SWRST Software reset [15:15] CR2 Control register 2 0x4 FREQ Peripheral clock frequency [6:0] ITERREN Error interrupt enable [8:8] ITEVTEN Event interrupt enable [9:9] ITBUFEN Buffer interrupt enable [10:10] OAR1 Own address register 1 0x8 ADD Interface address [7:1] DR Data register 0x10 DR 8-bit data register [7:0] SR1 Status register 1 0x14 SB Start bit (Master mode) [0:0] read-only ADDR Address sent (master mode)/matched (slave mode) [1:1] read-only BTF Byte transfer finished [2:2] read-only STOPF Stop detection (slave mode) [4:4] read-only RXNE Data register not empty (receivers) [6:6] read-only TXE Data register empty (transmitters) [7:7] read-only BERR Bus error [8:8] ARLO Arbitration lost (master mode) [9:9] AF Acknowledge failure [10:10] OVR Overrun/Underrun [11:11] TIMEOUT Timeout or Tlow error [14:14] SR2 Status register 2 0x18 MSL Master/slave [0:0] read-only BUSY Bus busy [1:1] read-only TRA Transmitter/receiver [2:2] read-only GENCALL General call address (Slave mode) [4:4] read-only CCR Clock control register 0x1C CCR Clock control register in Fm/Sm mode (Master mode) [11:0] FP I2C master mode selection [13:13] DUTY Fm mode duty cycle [14:14] FS I2C master mode selection [15:15] TRISE TRISE register 0x20 TRISE Maximum rise time in Fm+/Fm/Sm mode (Master mode) [6:0] TDATAHOLD Data hold time [11:7] TDATAHOLD_SEL Data hold time select [12:12] WT Wakeup Time register 0x24 DIV PCLK division [1:0] CNT Timeout count number [3:2] IWDG Independent watchdog 0x40003000 0x0 0x400 registers KR Key register (IWDG_KR) 0x0 KEY Key value [15:0] write-only PR Prescaler register (IWDG_PR) 0x4 PR Prescaler divider [2:0] RLR Reload register (IWDG_RLR) 0x8 RL Watchdog counter reload value [11:0] SR Status register (IWDG_SR) 0xC PVU Watchdog prescaler value update [0:0] read-only RVU Watchdog counter reload value update [1:1] read-only LPTIM1 Low power timer LPTIM1 0x40007C00 0x0 0x400 registers LPTIM1_DAC LPTIM1, DAC global Interrupts 17 ISR ISR Interrupt and Status Register 0x0 read-only ARRM Autoreload match [1:1] ARROK Autoreload match update OK [4:4] ICR ICR Interrupt Clear Register 0x4 write-only ARRMCF Autoreload match Clear Flag [1:1] ARROKCF Autoreload match update OK Clear Flag [4:4] IER IER Interrupt Enable Register 0x8 ARRMIE Autoreload matchInterrupt Enable [1:1] ARROKIE Autoreload match update OK Interrupt Enable [4:4] CFGR CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR CR Control Register 0x10 ENABLE LPTIM Enable [0:0] SNGSTRT LPTIM start in single mode [1:1] CNTSTRT CNTSTRT [2:2] COUNTRST Reset counter [3:3] RSTARE Reset after read enable [4:4] ARR ARR Autoreload Register 0x18 0x1 ARR Auto reload value [15:0] CNT CNT Counter Register 0x1C read-only CNT Counter value [15:0] PWR Power control 0x40007000 0x0 0x400 registers CR1 Power control register 1 0x0 DBP dbg mode protect enable [8:8] FLS_SLPTIME flash sleep time control [13:12] LPR pmu mode control [15:14] SRAM_RETV_CTRL sram retev control [18:17] HSION_CTRL HSION CTRL [19:19] RCC Reset and clock control 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 4 CR Clock control register 0x0 HSION HSI clock enable bit [8:8] HSIRDY HSI clock ready logo [10:10] read-only HSIDIV HSI generates the crossover factor when HSISYS clocks [13:11] HSEON HSE crystal oscillator enabled [16:16] HSERDY HSE crystal clock ready flag [17:17] read-only HSEBYP HSE shields the crystal oscillator and selects the pin input clock [18:18] HSE_CSSON HSE clock security system enabled [19:19] ICSCR Internal clock sources calibration register 0x4 HSI_TRIM Clock frequency calibration value [12:0] HSI_FS HSI frequency selection [15:13] LSI_TRIM Internal low-speed clock frequency calibration [24:16] CFGR Clock configuration register 0x8 SW System clock source selection [2:0] SWS System clock source selection [5:3] HPRE The AHB clock HCLK is based on the crossover coefficient of SYSCLK [11:8] PPRE APB clock division factor [14:12] MCOSEL MCO output clock selection [27:24] MCOPRE Microprocessor output clock (MCO) divider factor [30:28] ECSCR External clock source control register 0x10 HSE_DRV HSE drive capability setting [0:0] HSE_STARTUP HSE stabilization time selection [4:3] LSE_DRIVER LSE drive capability setting [17:16] LSE_STARTUP LSE crystal oscillator stabilization time selection [21:20] CIER Clock interrupt enable register 0x18 LSIRDYIE LSI clock ready interrupt enabled [0:0] LSERDYIE LSE clock ready interrupt enabled [1:1] HSIRDYIE HSI clock ready interrupt enabled [3:3] HSERDYIE HSE clock ready interrupt enabled [4:4] CIFR Clock interrupt flag register 0x1C LSIRDYF LSI clock ready interrupt enabled [0:0] read-only LSERDYF LSE clock ready interrupt enabled [1:1] read-only HSIRDYF HSI clock ready interrupt enabled [3:3] read-only HSERDYF HSE clock ready interrupt enabled [4:4] read-only CSSF HSE Clock Security System (CSS) interrupt flag [8:8] read-only LSECSSF LSE Clock Security System (CSS) interrupt flag [9:9] read-only CICR Clock interrupt clear register 0x20 LSIRDYC The LSI ready interrupt flag is cleared [0:0] write-only LSERDYC The LSE ready interrupt flag is cleared [1:1] write-only HSIRDYC The HSI ready interrupt flag is cleared to zero [3:3] write-only HSERDYC The HSE ready interrupt flag is cleared to zero [4:4] write-only CSSC The HSE Clock Security System (CSS) interrupt flag is cleared to zero [8:8] write-only LSECSSC The LSE Clock Security System (CSS) interrupt flag is cleared [9:9] write-only IOPRSTR GPIO reset register 0x24 GPIOARST I/O PortA reset [0:0] GPIOBRST I/O PortB reset [1:1] GPIOFRST I/O PortF reset [5:5] AHBRSTR AHB peripheral reset register 0x28 CRCRST The CRC module is reset [12:12] APBRSTR1 APB peripheral reset register 1 0x2C RTCAPBRST The RTC module APB is reset [10:10] UART1RST The UART1 module is reset [17:17] UART2RST The UART2 module is reset [18:18] I2C1RST The I2C1 module is reset [21:21] DBGRST The MCU Debug module is reset [27:27] PWRRST The Power interface module is reset. [28:28] APBRSTR2 APB peripheral reset register 2 0x30 SYSCFGRST The SYSCFG module is reset [0:0] TIM1RST The TIM1 module is reset [11:11] SPI1RST The SPI1 module is reset [12:12] UART3RST The UART3 module is reset [13:13] TIM14RST The TIM14 module is reset [15:15] ADCRST The ADC block is reset [20:20] COMP1RST The COMP1 module is reset [21:21] COMP2RST The COMP2 module is reset [22:22] TKRST TK module reset [25:25] IOPENR GPIO clock enable register 0x34 GPIOAEN I/O PortA clock enable [0:0] GPIOBEN I/O PortB clock enable [1:1] GPIOFEN I/O PortF clock enable [5:5] AHBENR AHB peripheral clock enable register 0x38 CRCEN CRC module clock enabled [12:12] APBENR1 APB peripheral clock enable register 1 0x3C RTCAPBEN The RTC module APB clock is enabled [10:10] UART1EN The UART1 module clock is enabled [17:17] UART2EN The UART2 module clock is enabled [18:18] I2C1EN I2C1 module clock enable [21:21] DBGEN MCU Debug module clock enable [27:27] PWREN The Power interface module clock enables [28:28] APBENR2 APB peripheral clock enable register 2 0x40 SYSCFGEN The SYSCFG module clock is enabled [0:0] TIM1EN The TIM1 module clock is enabled [11:11] SPI1EN The SPI1 module clock is enabled [12:12] UART3EN The UART3 module clock is enabled [13:13] TIM14EN TIM14 module clock enable [15:15] ADCEN ADC block clock enabled [20:20] COMP1EN COMP1 module clock enable [21:21] COMP2EN COMP2 module clock enabled [22:22] TKEN TK module clock enabled [25:25] CCIPR Peripherals independent clock configuration register 0x54 TIMCLK_CTRL TIMER PCLK FREQUENCY CONTROL [0:0] COMP1SEL COMP1 module clock source selection [8:8] COMP2SEL COMP2 module clock source selection [9:9] IWDGSEL IWDG internal clock source selection [12:12] ADC_CKMODE ADC clock mode [23:20] BDCR RTC domain control register 0x5C LSEON LSE OSC enabled [0:0] LSERDY LSE OSC ready [1:1] LSEBYP LSE OSC bypass [2:2] LSECSSON LSE CSS enables [5:5] LSECSSD LSE CSS (clock security system) detection failed [6:6] RTCSEL RTC clock source selection [9:8] RTC_HSEDIV_SEL The RTC clock source is selected as the division of the HSE clock [11:10] RTCEN RTC clock enabled [15:15] BDRST RTC soft reset [16:16] LSCSEL Low-speed clock selection [25:25] CSR Control/status register 0x60 LSION LSI OSC enabled [0:0] LSIRDY LSI OSC stability flag [1:1] read-only PINRST_FLTDIS NRST filtering is prohibited [8:8] BORRSTF BOR reset flag [9:9] read-only RMVF Clear the reset flag [23:23] OBLRSTF Option byte loader reset flag [25:25] read-only PINRSTF External NRST pin reset flag [26:26] read-only PORRSTF POR reset flag [27:27] read-only SFTRSTF Soft reset flag [28:28] read-only IWDGRSTF IWDG reset flag [29:29] read-only RTC Real time clock 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 CRH RTC Control Register High 0x0 SECIE Seconds interrupt allowed bits [0:0] ALRIE Alarm interrupt allowed bits [1:1] OWIE Overflow interrupt allow bits [2:2] TK_SECIE TK sec interrupt allowable bits [3:3] TK_ALRIE TK alarm interrupt allowed bits [4:4] TK_OWIE TK overflow interrupt allowable bits [5:5] CRL RTC Control Register Low 0x4 SECF Second flag [0:0] ALRF Alarm flag [1:1] OWF Overflow flag [2:2] RSF Registers synchronized flag [3:3] CNF Configuration flag [4:4] RTOFF RTC operation OFF [5:5] read-only PRLH RTC Prescaler Load Register High 0x8 PRL RTC prescaler reload value high [5:0] write-only PRLL RTC Prescaler Load Register Low 0xC PRL RTC prescaler reload value high [15:0] write-only DIVH RTC Prescaler Divider Register High 0x10 RTC_DIV RTC clock divider [3:0] read-only DIVL RTC Prescaler Divider Register Low 0x14 RTC_DIV RTC clock divider [15:0] read-only CNTH RTC Counter Register High 0x18 RTC_CNT RTC core counter [15:0] CNTL RTC Counter Register Low 0x1C RTC_CNT RTC core counter [15:0] ALRH RTC Alarm Register High 0x20 ALR RTC alarm value [15:0] ALRL RTC Alarm Register Low 0x24 ALR RTC alarm value [15:0] BKP_RTCCR 0x2C CAL Calibration value [6:0] CCO Calibrate the clock output bits [7:7] ASOE Seconds/alarm pulse output enable bit [8:8] ASOS Seconds/alarm pulse output select bits [9:9] SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 0x0 CPHA Clock Phase [0:0] CPOL Clock Polarity [1:1] MSTR Master Selection [2:2] BR Baud Rate Control [5:3] SPE SPI Enable [6:6] LSBFIRST Frame Format [7:7] SSI Internal slave select [8:8] SSM Software slave management [9:9] RXONLY Receive only [10:10] DFF Data frame format [11:11] BIDIOE Output enable in bidirectional mode [14:14] BIDIMODE Bidirectional data mode enable [15:15] CR2 0x4 SSOE SS Output Enable [2:2] CLRTXFIFO Clear FIFO [4:4] ERRIE Error Interrupt Enable [5:5] RXNEIE RX buffer Not Empty Interrupt Enable [6:6] TXEIE Tx buffer Empty Interrupt Enable [7:7] SR 0x8 RXNE Receive buffer Not Empty [0:0] read-only TXE Transmit buffer Empty [1:1] read-only MODF Mode fault [5:5] OVR Overrun flag [6:6] read-only BSY Busy flag [7:7] read-only FRLVL FIFO Reception Level [10:9] read-only FTLVL FIFO Transmission Level [12:11] read-only DR 0xC DR Data Register [15:0] SYSCFG System configuration controller 0x40010000 0x0 0x100 registers CFGR1 SYSCFG configuration register 1 0x0 MEM_MODE Storage Area Mapping Selection [1:0] TIM1_IC1_SRC Timer1 CH1 Input Selection [3:2] ETR_SRC_TIM1 Timer1 ETR Input Selection [9:8] CFGR2 SYSCFG configuration register 2 0x4 LOCKUP_LOCK LOCK_UP as TIM1 Break Enable [0:0] COMP1_BRK_TIM1 COMP1 as TIM1 Break Enable [3:3] COMP2_BRK_TIM1 COMP2 as TIM1 Break Enable [4:4] COMP1_OCREF_CLR_TIM1 COMP1 as TIM1 ocref_clr Enable [9:9] COMP2_OCREF_CLR_TIM1 COMP2 as TIM1 ocref_clr Enable [11:11] PA_ENS 0x10 PA_ENS Pa Noise filter enable [15:0] PB_ENS 0x14 PB_ENS Pb Noise filter enable [3:0] PF_ENS 0x18 PF_ENS Pf Noise filter enable [5:0] IOCFG 0x1C PA_EIIC Pa I2C IO enable [1:0] PF_EIIC Pf I2C IO enable [4:2] PF_PU_IIC Pf I2C Pull-up resistor control enable [7:6] PA_EHS Pa LED IO Conrtol [12:8] PA_IODRVP Pa I2C_VCC Output Drive config [14:13] PA_ENSEG Pa Seg Mode enable [21:16] PB_ENSEG Pb Seg Mode enable [23:22] PA_ANA2EN 0x20 PA_ANA2EN Pa Analog Noise filter enable [15:0] PB_ANA2EN 0x24 PB_ENS Pb Analog Noise filter enable [3:0] PF_ANA2EN 0x28 PF_ANA2EN Pf Analog Noise filter enable [5:0] PA_IORP 0x30 PA0_IORP Pa0 IO pull-up pull-down resistance config [1:0] PA1_IORP Pa1 IO pull-up pull-down resistance config [3:2] PA2_IORP Pa2 IO pull-up pull-down resistance config [5:4] PA3_IORP Pa3 IO pull-up pull-down resistance config [7:6] PA4_IORP Pa4 IO pull-up pull-down resistance config [9:8] PA5_IORP Pa5 IO pull-up pull-down resistance config [11:10] PA6_IORP Pa6 IO pull-up pull-down resistance config [13:12] PA7_IORP Pa7 IO pull-up pull-down resistance config [15:14] PA8_IORP Pa8 IO pull-up pull-down resistance config [17:16] PA9_IORP Pa9 IO pull-up pull-down resistance config [19:18] PA10_IORP Pa10 IO pull-up pull-down resistance config [21:20] PA11_IORP Pa11 IO pull-up pull-down resistance config [23:22] PA12_IORP Pa12 IO pull-up pull-down resistance config [25:24] PA13_IORP Pa13 IO pull-up pull-down resistance config [27:26] PA14_IORP Pa14 IO pull-up pull-down resistance config [29:28] PA15_IORP Pa15 IO pull-up pull-down resistance config [31:30] PB_IORP 0x34 PB0_IORP Pb0 IO pull-up pull-down resistance config [1:0] PB1_IORP Pb1 IO pull-up pull-down resistance config [3:2] PB2_IORP Pb2 IO pull-up pull-down resistance config [5:4] PB3_IORP Pb3 IO pull-up pull-down resistance config [7:6] PF_IORP 0x38 PF0_IORP Pf0 IO pull-up pull-down resistance config [1:0] PF1_IORP Pf1 IO pull-up pull-down resistance config [3:2] PF2_IORP Pf2 IO pull-up pull-down resistance config [5:4] PF3_IORP Pf3 IO pull-up pull-down resistance config [7:6] PF4_IORP Pf4 IO pull-up pull-down resistance config [9:8] PF5_IORP Pf5 IO pull-up pull-down resistance config [11:10] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 0x0 0x3FF CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 0x4 0xF8 CCPC [0:0] CCUS [2:2] MMS [6:4] TI1S [7:7] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] OIS2N [11:11] OIS3 [12:12] OIS3N [13:13] OIS4 [14:14] SMCR 0x8 0xFFF7 SMS [2:0] OCCS [3:3] TS [6:4] MSM [7:7] ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] SMS_3 [16:16] DIER 0xC 0x5F5F UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] SR 0x10 0x1E5F UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] IC1IR [16:16] IC2IR [17:17] IC3IR [18:18] IC4IR [19:19] IC1IF [20:20] IC2IF [21:21] IC3IF [22:22] IC4IF [23:23] EGR 0x14 write-only 0x5F UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G [2:2] write-only CC3G [3:3] write-only CC4G [4:4] write-only COMG [5:5] write-only TG [6:6] write-only BG [7:7] write-only CCMR1_OUTPUT 0x18 0xFFFF CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M [14:12] OC2CE [15:15] OC1M_3 [16:16] OC2M_3 [24:24] CCMR1_INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCMR2_OUTPUT 0x1C 0xFFFF CC3S [1:0] OC3FE [2:2] OC3PE [3:3] OC3M [6:4] OC3CE [7:7] CC4S [9:8] OC4FE [10:10] OC4PE [11:11] OC4M [14:12] OC4CE [15:15] OC3M_3 [16:16] OC4M_3 [24:24] CCMR2_INPUT CCMR2_OUTPUT 0x1C 0xFFFF CC3S [1:0] IC3PSC [3:2] IC3F [7:4] CC4S [9:8] IC4PSC [11:10] IC4F [15:12] CCER 0x20 0x3333 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CNT 0x24 0xFFFF CNT [15:0] PSC 0x28 0xFFFF PSC [15:0] ARR 0x2C 0xFFFF 0xFFFF ARR [15:0] RCR 0x30 0xFFFF 0xFFFF REP [7:0] CCR1 0x34 0xFFFF CCR1 [15:0] CCR2 0x38 0xFFFF CCR2 [15:0] CCR3 0x3C 0xFFFF CCR3 [15:0] CCR4 0x40 0xFFFF CCR4 [15:0] BDTR 0x44 0xFFFF DTG [7:0] LOCK [9:8] OSSI [10:10] OSSR [11:11] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 0x0 0x3FF CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] ARPE [7:7] CKD [9:8] DIER 0xC 0x5F5F UIE [0:0] CC1IE [1:1] SR 0x10 0x1E5F UIF [0:0] CC1IF [1:1] CC1OF [9:9] EGR 0x14 write-only 0x5F UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CCMR1_OUTPUT 0x18 0xFFFF CC1S [1:0] OC1PE [3:3] OC1M [6:4] CCMR1_INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CCER 0x20 0x3333 CC1E [0:0] CC1P [1:1] CC1NP [3:3] CNT 0x24 0xFFFF CNT [15:0] PSC 0x28 0xFFFF PSC [15:0] ARR 0x2C 0xFFFF 0xFFFF ARR [15:0] CCR1 0x34 0xFFFF CCR1 [15:0] OR 0x50 TI1_RMP [1:0] TK Touch key 0x40003800 0x0 0x400 registers TK TK Interrupt 8 CR1 Control register 1 0x0 EN TK enable [0:0] MODE TK mode select [2:1] EXTCMODEN External CMOD enable [3:3] ICOPA SIDAC source current or sink current select [4:4] COPAMODE Key compensation enable [5:5] COPADATA unsensed key output control [7:6] VCCTKCR VCCTK voltage select [10:8] VCC1CR VCC1 voltage select [13:11] MIDACSTEP MIDAC step select [14:14] SIDACSTEP SIDAC step select [15:15] CFT CMP OUT filter select [18:16] VCCTKEN VCCTK voltage enable [19:19] INTCMODEN Internal CMOD enable [20:20] CMPHYSEN CMP hysteresis enable [21:21] BUFFEREN Discharge buffer enable [22:22] DIV PCLK division(TK_CLK) [26:24] STDIV PCLK division(ST_CLK) [29:27] CR2 Control register 2 0x4 START Sense start [0:0] RSTB Counter reset [1:1] SWCTRL TK_SW control [2:2] CMODCHRG CMOD charge enable [3:3] CMODDISCH CMOD discharge enable [4:4] MIDACEN Main IDAC enable [5:5] SIDACEN Slave IDAC enable [6:6] CMODVTINIT The voltage of CMOD initialization [7:7] PWMM PWM mode select [8:8] CTRLSOURCE Software or hardware select [9:9] LPABNORMAL Lowpower wake up control [10:10] CSA_DISCH_SEL CMOD discharge select in CSA mode [11:11] SHORTSW_NUM Short switch times of hardware mode in CSD mode [13:12] LPEN Lowpower wake up enable [14:14] KVREF Reference voltage select [17:16] KVREF_CSA_TARGET Vref charging target value in CSA mode [19:18] LFSRW LFSR valid bit [23:20] IDACR IDAC Control register 0x8 MIDAC Main IDAC configuration [7:0] SIDAC Slave IDAC configuration [23:16] SIDAC_CSA_TARGET SIDAC target value in CSA mode [31:24] KR Key enable register 0xC KEN Sense function enable [25:0] CSR Channel Select register 0x10 CHS Sense key select [25:0] UCR Unsel Control register 0x14 COPAMODEIO IO compensation enable [25:0] STR1 Stable Time register 1 0x18 SETTIME Voltage building time in CSA mode or short switch time in CSD mode or discharge time in PCI mode [9:0] VTINITTIME CMOD dischsrge time in CSA mode [23:16] STR2 Stable Time register 2 0x1C VREF_MIDAC_TIME VREF or MIDAC stabilization time in CSA mode [4:0] DISCH_CHRG_TIME CMOD discharging or charging time in CSA mode [14:8] SIDACTIME SIDAC stabilization time in CSA mode [20:16] BEFORE_SW_TIME From setting SIDACEN to switching TK_SW time in CSA mode or from clearing CMODDISCH to switching TK_SW time in PCI mode [27:24] CHRG_SIDACEN_TIME From clearing CMODCHRG to setting SIDACEN time in CSA mode [29:28] WR Window register 0x20 WIN Window time [15:0] SDR Switch Divide register 0x24 SWDIV TK_CLK division(TK_SW) [8:0] PRSR Pseudo Random Sequence register 0x28 LFSRP LFSR polynomial [15:0] SEED LFSR seed [31:16] DR Data register 0x2C DATA Sense data [15:0] read-only SR Status register 0x30 SENSEDONE Sense finished [0:0] read-only CMPOUT CMP output [1:1] read-only SHORTSWERR Short switch error of hardware in CSD mode [2:2] read-only IER Interrupt enable register 0x34 EVTINTEN Event interrupt enable [0:0] ERRINTEN Error interrupt enable [1:1] ICR Interrupt clear register 0x38 EVTINTCLR Event interrupt clear [0:0] ERRINTCLR Error interrupt clear [1:1] CDR Compare Data register 0x3C CDATA Compare data in lowpower [15:0] LPDR Lowpower Delta register 0x40 NORMALDELTA Delta1 [9:0] ABNORMALDELTA Delta2 [25:16] LPTR Lowpower Time register 0x44 LPWAIT Wait time in lowpower [6:0] OPR 0x48 OP CMP control [5:0] TR 0x4C TMODE Test mode select [2:0] DBGSEL Debug signal select [19:16] DDR 0x50 SHORTSW_DATA Short switch data in CSD mode [9:0] read-only UART1 Universal asynchronous receiver transmitter UART 0x40004400 0x0 0x400 registers UART1 UART1 global Interrupt 31 DR Data register 0x0 DR Receive/send data register [8:0] BRR Baud rate register 0x4 BRR Baud rate register [15:0] SR Status register 0x10 RXNE Receive register not empty [0:0] read-only ORE Overrun error bit [1:1] PE Parity Error bit [2:2] FE Framing Error bit [3:3] BRI Break Interrupt bit [4:4] TDRE Transmit Holding Register Empty bit [5:5] read-only TXE Transmitter Empty bit [6:6] read-only ADDR_RCVD Address Received Bit [8:8] BUSY UART Busy [9:9] read-only BUSY_ERR Busy Detect Error [10:10] CR1 Control register 1 0x14 M Data Length Select [1:0] STOP Number of stop bits [2:2] PCE Parity Enable [3:3] PS Even Parity Select [4:4] SP Stick Parity [5:5] SBK Send Break [6:6] SWAP TX/RX pin swap [8:8] MSBFIRST MSB first mode [9:9] CR2 Control register 2 0x18 RXNEIE Enable Received Data Available Interrupt [0:0] TDREIE Enable Transmit Holding Register Empty Interrupt [1:1] LSIE Enable Receiver Line Status Interrupt [2:2] BUSYERRIE Enable Busyerr state interruption [3:3] CR3 Control register 3 0x1C M_E Extension for DLS [0:0] ADDR_MATCH Address Match Mode [1:1] SEND_ADDR Send address control bit [2:2] TX_MODE Transmit mode control bit [3:3] RAR 0x20 RAR Receive address matching register [7:0] TAR 0x24 TAR Transmit address matching register [7:0] UART2 0x40014400 UART2 UART2 global Interrupt 30 UART3 0x40013800 UART3 UART3 global Interrupt 29