Puya Puya PY32F003xx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 ISR ISR ADC interrupt and status register 0x0 EOSMP ADC group regular end of samplingflag [1:1] EOC ADC group regular end of unitaryconversion flag [2:2] EOSEQ ADC group regular end of sequenceconversions flag [3:3] OVR ADC group regular overrunflag [4:4] AWD ADC analog watchdog flag [7:7] IER IER ADC interrupt enable register 0x4 EOSMPIE ADC group regular end of samplinginterrupt [1:1] EOCIE ADC group regular end of unitaryconversion interrupt [2:2] EOSEQIE ADC group regular end of sequenceconversions interrupt [3:3] OVRIE ADC group regular overruninterrupt [4:4] AWDIE ADC analog watchdoginterrupt [7:7] CR CR ADC control register 0x8 ADEN ADC enable [0:0] ADSTART ADC group regular conversionstart [2:2] ADSTP ADC group regular conversionstop [4:4] ADCAL ADC group regular conversioncalibration [31:31] CFGR1 CFGR1 ADC configuration register 1 0xC DMAEN ADC DMA transfer enable [0:0] DMACFG ADC DMA transferconfiguration [1:1] SCANDIR Scan sequence direction [2:2] RESSEL ADC data resolution [4:3] ALIGN ADC data alignement [5:5] EXTSEL ADC group regular external triggersource [8:6] EXTEN ADC group regular external triggerpolarity [11:10] OVRMOD ADC group regular overrunconfiguration [12:12] CONT ADC group regular continuous conversionmode [13:13] WAIT Wait conversion mode [14:14] DISCEN ADC group regular sequencerdiscontinuous mode [16:16] AWDSGL ADC analog watchdog monitoring asingle channel or all channels [22:22] AWDEN ADC analog watchdog enable on scopeADC group regular [23:23] AWDCH ADC analog watchdog monitored channelselection [29:26] CFGR2 CFGR2 ADC configuration register 2 0x10 CKMODE ADC clock mode [31:28] SMPR SMPR ADC sampling time register 0x14 SMP Sampling time selection [2:0] TR TR ADC analog watchdog 1 threshold register 0x20 0xFFF0000 LT ADC analog watchdog thresholdlow [11:0] HT ADC analog watchdog thresholdhigh [27:16] CHSELR CHSELR ADC group regular sequencer register 0x28 0xFFF0000 CHSEL0 Channel-0 selection [0:0] CHSEL1 Channel-1 selection [1:1] CHSEL2 Channel-2 selection [2:2] CHSEL3 Channel-3 selection [3:3] CHSEL4 Channel-4 selection [4:4] CHSEL5 Channel-5 selection [5:5] CHSEL6 Channel-6 selection [6:6] CHSEL7 Channel-7 selection [7:7] CHSEL8 Channel-8 selection [8:8] CHSEL9 Channel-9 selection [9:9] CHSEL11 Channel-11 selection [11:11] CHSEL12 Channel-12 selection [12:12] DR DR ADC group regular data register 0x40 read-only DATA ADC group regular conversiondata [15:0] CCSR CCSR ADC calibration configuration and status register 0x44 CALSEL Calibration contents selection [11:11] CALSMP Calibration sample time selection [13:12] CALSET Calibration factor selection [15:15] CALFAIL Calibration fail flag [30:30] CALON Calibration flag [31:31] read-only CALRR1 CALRR1 ADC calibration result register 1 0x48 read-only CALC4OUT C4 result [7:0] CALC5OUT C5 result [15:8] CALBOUT offset result [22:16] CALRR2 CALRR2 ADC calibration result register 2 0x4C read-only CALC0OUT C0 result [7:0] CALC1OUT C1 result [15:8] CALC2OUT C2 result [23:16] CALC3OUT C3 result [31:24] CALFIR1 CALFIR1 ADC calibration factor input register 1 0x50 CALC4IO Calibration C4 factor input [7:0] CALC5IO Calibration C5 factor input [15:8] CALBIO Calibration offset factor input [22:16] CALFIR2 CALFIR2 ADC calibration factor input register 2 0x54 CALC0IO Calibration C0 factor input [7:0] CALC1IO Calibration C1 factor input [15:8] CALC2IO Calibration C2 factor input [23:16] CALC3IO Calibration C3 factor input [31:24] CCR CCR ADC common configuration register 0x308 VREFEN VREFINT enable [22:22] TSEN Temperature sensor enable [23:23] COMP1 Comparator COMP 0x40010200 0x0 0x10 registers CSR CSR COMP control and status register 0x0 COMP_EN COMP enable bit [0:0] SCALER_EN SCALER enable bit [1:1] INMSEL Comparator signal selector forinverting input INM [7:4] INPSEL Comparator signal selector fornon-inverting input [9:8] WINMODE Comparator non-inverting inputselector for window mode [11:11] POLARITY Comparator polarityselector [15:15] HYST Comparator hysteresis enableselector [16:16] PWRMODE Comparator power modeselector [19:18] COMP_OUT Comparator output status [30:30] LOCK CSR register lock [31:31] FR FR Comparator Filterregister 0x4 FLTEN Filter enable bit [0:0] FLTCNT Comparator filter and counter [31:16] COMP2 Comparator COMP 0x40010210 0x0 0x10 registers CSR CSR COMP control and status register 0x0 COMP_EN COMP enable bit [0:0] INMSEL Comparator signal selector forinverting input INM [7:4] INPSEL Comparator signal selector fornon-inverting input [9:8] WINMODE Comparator non-inverting inputselector for window mode [11:11] POLARITY Comparator polarityselector [15:15] PWRMODE Comparator power modeselector [19:18] COMP_OUT Comparator output status [30:30] LOCK CSR register lock [31:31] FR FR Comparator Filterregister 0x4 FLTEN Filter enable bit [0:0] FLTCNT Comparator filter and counter [31:16] CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0xFFFFFFFF DR Data Register [31:0] IDR IDR Independent Data register 0x4 IDR Independent Data register [7:0] CR CR Control register 0x8 write-only RESET Reset bit [0:0] DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 read-only CR CR Debug MCU Configuration Register 0x4 DBG_STOP Debug Stop Mode [1:1] APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 DBG_TIMER3_STOP Debug Timer 3 stopped when Core is halted [1:1] DBG_RTC_STOP Debug RTC stopped when Core is halted [10:10] DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted [11:11] DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted [12:12] DBG_LPTIM_STOP Debug LPTIM stopped when Core is halted [31:31] APB_FZ2 APB_FZ2 APB Freeze Register2 0xC DBG_TIMER1_STOP Debug Timer 1 stopped when Core is halted [11:11] DBG_TIMER14_STOP Debug Timer 14 stopped when Core is halted [15:15] DBG_TIMER16_STOP Debug Timer 16 stopped when Core is halted [17:17] DBG_TIMER17_STOP Debug Timer 17 stopped when Core is halted [18:18] DMA Direct memory access DMA 0x40020000 0x0 0x400 registers DMA_Channel1 DMA Channel 1 Interrupt 9 DMA_Channel2_3 DMA Channel 2 and Channel 3 Interrupt 10 ISR ISR DMA interrupt status register(DMA_ISR) 0x0 read-only GIF1 Channel 1 Global interrupt flag [0:0] TCIF1 Channel 1 Transfer Completeflag [1:1] HTIF1 Channel 1 Half Transfer Completeflag [2:2] TEIF1 Channel 1 Transfer Errorflag [3:3] GIF2 Channel 2 Global interruptflag [4:4] TCIF2 Channel 2 Transfer Completeflag [5:5] HTIF2 Channel 2 Half Transfer Completeflag [6:6] TEIF2 Channel 2 Transfer Errorflag [7:7] GIF3 Channel 3 Global interruptflag [8:8] TCIF3 Channel 3 Transfer Completeflag [9:9] HTIF3 Channel 3 Half Transfer Completeflag [10:10] TEIF3 Channel 3 Transfer Errorflag [11:11] IFCR IFCR DMA interrupt flag clear register(DMA_IFCR) 0x4 write-only CGIF1 Channel 1 Global interruptclear [0:0] CTCIF1 Channel 1 Transfer Completeclear [1:1] CHTIF1 Channel 1 Half Transferclear [2:2] CTEIF1 Channel 1 Transfer Errorclear [3:3] CGIF2 Channel 2 Global interruptclear [4:4] CTCIF2 Channel 2 Transfer Completeclear [5:5] CHTIF2 Channel 2 Half Transferclear [6:6] CTEIF2 Channel 2 Transfer Errorclear [7:7] CGIF3 Channel 3 Global interruptclear [8:8] CTCIF3 Channel 3 Transfer Completeclear [9:9] CHTIF3 Channel 3 Half Transferclear [10:10] CTEIF3 Channel 3 Transfer Errorclear [11:11] CCR1 CCR1 DMA channel configuration register(DMA_CCR) 0x8 EN Channel enable [0:0] TCIE Transfer complete interruptenable [1:1] HTIE Half Transfer interruptenable [2:2] TEIE Transfer error interruptenable [3:3] DIR Data transfer direction [4:4] CIRC Circular mode [5:5] PINC Peripheral increment mode [6:6] MINC Memory increment mode [7:7] PSIZE Peripheral size [9:8] MSIZE Memory size [11:10] PL Channel Priority level [13:12] MEM2MEM Memory to memory mode [14:14] CNDTR1 CNDTR1 DMA channel 1 number of dataregister 0xC NDT Number of data to transfer [15:0] CPAR1 CPAR1 DMA channel 1 peripheral addressregister 0x10 PA Peripheral address [31:0] CMAR1 CMAR1 DMA channel 1 memory addressregister 0x14 MA Memory address [31:0] CCR2 CCR2 DMA channel configuration register(DMA_CCR) 0x1C EN Channel enable [0:0] TCIE Transfer complete interruptenable [1:1] HTIE Half Transfer interruptenable [2:2] TEIE Transfer error interruptenable [3:3] DIR Data transfer direction [4:4] CIRC Circular mode [5:5] PINC Peripheral increment mode [6:6] MINC Memory increment mode [7:7] PSIZE Peripheral size [9:8] MSIZE Memory size [11:10] PL Channel Priority level [13:12] MEM2MEM Memory to memory mode [14:14] CNDTR2 CNDTR2 DMA channel 2 number of dataregister 0x20 NDT Number of data to transfer [15:0] CPAR2 CPAR2 DMA channel 2 peripheral addressregister 0x24 PA Peripheral address [31:0] CMAR2 CMAR2 DMA channel 2 memory addressregister 0x28 MA Memory address [31:0] CCR3 CCR3 DMA channel configuration register(DMA_CCR) 0x30 EN Channel enable [0:0] TCIE Transfer complete interruptenable [1:1] HTIE Half Transfer interruptenable [2:2] TEIE Transfer error interruptenable [3:3] DIR Data transfer direction [4:4] CIRC Circular mode [5:5] PINC Peripheral increment mode [6:6] MINC Memory increment mode [7:7] PSIZE Peripheral size [9:8] MSIZE Memory size [11:10] PL Channel Priority level [13:12] MEM2MEM Memory to memory mode [14:14] CNDTR3 CNDTR3 DMA channel 3 number of dataregister 0x34 NDT Number of data to transfer [15:0] CPAR3 CPAR3 DMA channel 3 peripheral addressregister 0x38 PA Peripheral address [31:0] CMAR3 CMAR3 DMA channel 3 memory addressregister 0x3C MA Memory address [31:0] EXTI External interrupt/eventcontroller EXTI 0x40021800 0x0 0x400 registers PVD PVD Interrupt through EXTI Lines 16 1 EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR RTSR EXTI rising trigger selectionregister 0x0 RT0 Rising trigger event configuration bitof Configurable Event input [0:0] RT1 Rising trigger event configuration bitof Configurable Event input [1:1] RT2 Rising trigger event configuration bitof Configurable Event input [2:2] RT3 Rising trigger event configuration bitof Configurable Event input [3:3] RT4 Rising trigger event configuration bitof Configurable Event input [4:4] RT5 Rising trigger event configuration bitof Configurable Event input [5:5] RT6 Rising trigger event configuration bitof Configurable Event input [6:6] RT7 Rising trigger event configuration bitof Configurable Event input [7:7] RT8 Rising trigger event configuration bitof Configurable Event input [8:8] RT9 Rising trigger event configuration bitof Configurable Event input [9:9] RT10 Rising trigger event configuration bitof Configurable Event input [10:10] RT11 Rising trigger event configuration bitof Configurable Event input [11:11] RT12 Rising trigger event configuration bitof Configurable Event input [12:12] RT13 Rising trigger event configuration bitof Configurable Event input [13:13] RT14 Rising trigger event configuration bitof Configurable Event input [14:14] RT15 Rising trigger event configuration bitof Configurable Event input [15:15] RT16 Rising trigger event configuration bitof Configurable Event input [16:16] RT17 Rising trigger event configuration bitof Configurable Event input [17:17] RT18 Rising trigger event configuration bitof Configurable Event input [18:18] FTSR FTSR EXTI falling trigger selectionregister 0x4 FT0 Falling trigger event configuration bitof Configurable Event input [0:0] FT1 Falling trigger event configuration bitof Configurable Event input [1:1] FT2 Falling trigger event configuration bitof Configurable Event input [2:2] FT3 Falling trigger event configuration bitof Configurable Event input [3:3] FT4 Falling trigger event configuration bitof Configurable Event input [4:4] FT5 Falling trigger event configuration bitof Configurable Event input [5:5] FT6 Falling trigger event configuration bitof Configurable Event input [6:6] FT7 Falling trigger event configuration bitof Configurable Event input [7:7] FT8 Falling trigger event configuration bitof Configurable Event input [8:8] FT9 Falling trigger event configuration bitof Configurable Event input [9:9] FT10 Falling trigger event configuration bitof Configurable Event input [10:10] FT11 Falling trigger event configuration bitof Configurable Event input [11:11] FT12 Falling trigger event configuration bitof Configurable Event input [12:12] FT13 Falling trigger event configuration bitof Configurable Event input [13:13] FT14 Falling trigger event configuration bitof Configurable Event input [14:14] FT15 Falling trigger event configuration bitof Configurable Event input [15:15] FT16 Falling trigger event configuration bitof Configurable Event input [16:16] FT17 Falling trigger event configuration bitof Configurable Event input [17:17] FT18 Falling trigger event configuration bitof Configurable Event input [18:18] SWIER SWIER EXTI software interrupt eventregister 0x8 SWI0 Rising trigger event configuration bitof Configurable Event input [0:0] SWI1 Rising trigger event configuration bitof Configurable Event input [1:1] SWI2 Rising trigger event configuration bitof Configurable Event input [2:2] SWI3 Rising trigger event configuration bitof Configurable Event input [3:3] SWI4 Rising trigger event configuration bitof Configurable Event input [4:4] SWI5 Rising trigger event configuration bitof Configurable Event input [5:5] SWI6 Rising trigger event configuration bitof Configurable Event input [6:6] SWI7 Rising trigger event configuration bitof Configurable Event input [7:7] SWI8 Rising trigger event configuration bitof Configurable Event input [8:8] SWI9 Rising trigger event configuration bitof Configurable Event input [9:9] SWI10 Rising trigger event configuration bitof Configurable Event input [10:10] SWI11 Rising trigger event configuration bitof Configurable Event input [11:11] SWI12 Rising trigger event configuration bitof Configurable Event input [12:12] SWI13 Rising trigger event configuration bitof Configurable Event input [13:13] SWI14 Rising trigger event configuration bitof Configurable Event input [14:14] SWI15 Rising trigger event configuration bitof Configurable Event input [15:15] SWI16 Rising trigger event configuration bitof Configurable Event input [16:16] SWI17 Rising trigger event configuration bitof Configurable Event input [17:17] SWI18 Rising trigger event configuration bitof Configurable Event input [18:18] PR PR EXTI pendingregister 0xC PR0 configurable event inputs x rising edgePending bit. [0:0] PR1 configurable event inputs x rising edgePending bit. [1:1] PR2 configurable event inputs x rising edgePending bit. [2:2] PR3 configurable event inputs x rising edgePending bit. [3:3] PR4 configurable event inputs x rising edgePending bit. [4:4] PR5 configurable event inputs x rising edgePending bit. [5:5] PR6 configurable event inputs x rising edgePending bit. [6:6] PR7 configurable event inputs x rising edgePending bit. [7:7] PR8 configurable event inputs x rising edgePending bit. [8:8] PR9 configurable event inputs x rising edgePending bit. [9:9] PR10 configurable event inputs x rising edgePending bit. [10:10] PR11 configurable event inputs x rising edgePending bit. [11:11] PR12 configurable event inputs x rising edgePending bit. [12:12] PR13 configurable event inputs x rising edgePending bit [13:13] PR14 configurable event inputs x rising edgePending bit. [14:14] PR15 configurable event inputs x rising edgePending bit. [15:15] PR16 configurable event inputs x rising edgePending bit. [16:16] PR17 configurable event inputs x rising edgePending bit. [17:17] PR18 configurable event inputs x rising edgePending bit. [18:18] EXTICR1 EXTICR1 EXTI external interrupt selectionregister 0x60 EXTI0 GPIO port selection [1:0] EXTI1 GPIO port selection [9:8] EXTI2 GPIO port selection [17:16] EXTI3 GPIO port selection [25:24] EXTICR2 EXTICR2 EXTI external interrupt selectionregister 0x64 EXTI4 GPIO port selection [1:0] EXTI5 GPIO port selection [8:8] EXTI6 GPIO port selection [16:16] EXTI7 GPIO port selection [24:24] EXTICR3 EXTICR3 EXTI external interrupt selectionregister 0x68 EXTI8 GPIO port selection [0:0] IMR IMR EXTI CPU wakeup with interrupt maskregister 0x80 0xFFF80000 IM0 CPU wakeup with interrupt mask on eventinput [0:0] IM1 CPU wakeup with interrupt mask on eventinput [1:1] IM2 CPU wakeup with interrupt mask on eventinput [2:2] IM3 CPU wakeup with interrupt mask on eventinput [3:3] IM4 CPU wakeup with interrupt mask on eventinput [4:4] IM5 CPU wakeup with interrupt mask on eventinput [5:5] IM6 CPU wakeup with interrupt mask on eventinput [6:6] IM7 CPU wakeup with interrupt mask on eventinput [7:7] IM8 CPU wakeup with interrupt mask on eventinput [8:8] IM9 CPU wakeup with interrupt mask on eventinput [9:9] IM10 CPU wakeup with interrupt mask on eventinput [10:10] IM11 CPU wakeup with interrupt mask on eventinput [11:11] IM12 CPU wakeup with interrupt mask on eventinput [12:12] IM13 CPU wakeup with interrupt mask on eventinput [13:13] IM14 CPU wakeup with interrupt mask on eventinput [14:14] IM15 CPU wakeup with interrupt mask on eventinput [15:15] IM16 CPU wakeup with interrupt mask on eventinput [16:16] IM17 CPU wakeup with interrupt mask on eventinput [17:17] IM18 CPU wakeup with interrupt mask on eventinput [18:18] IM19 CPU wakeup with interrupt mask on eventinput [19:19] IM29 CPU wakeup with interrupt mask on eventinput [29:29] EMR EMR EXTI CPU wakeup with event maskregister 0x84 EM0 CPU wakeup with event mask on eventinput [0:0] EM1 CPU wakeup with event mask on eventinput [1:1] EM2 CPU wakeup with event mask on eventinput [2:2] EM3 CPU wakeup with event mask on eventinput [3:3] EM4 CPU wakeup with event mask on eventinput [4:4] EM5 CPU wakeup with event mask on eventinput [5:5] EM6 CPU wakeup with event mask on eventinput [6:6] EM7 CPU wakeup with event mask on eventinput [7:7] EM8 CPU wakeup with event mask on eventinput [8:8] EM9 CPU wakeup with event mask on eventinput [9:9] EM10 CPU wakeup with event mask on eventinput [10:10] EM11 CPU wakeup with event mask on eventinput [11:11] EM12 CPU wakeup with event mask on eventinput [12:12] EM13 CPU wakeup with event mask on eventinput [13:13] EM14 CPU wakeup with event mask on eventinput [14:14] EM15 CPU wakeup with event mask on eventinput [15:15] EM16 CPU wakeup with event mask on eventinput [16:16] EM17 CPU wakeup with event mask on eventinput [17:17] EM18 CPU wakeup with event mask on eventinput [18:18] EM19 CPU wakeup with event mask on eventinput [19:19] EM29 CPU wakeup with event mask on eventinput [29:29] FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR ACR Access control register 0x0 0x600 LATENCY Latency [0:0] KEYR KEYR Flash key register 0x8 write-only KEY Flash key [31:0] OPTKEYR OPTKEYR Option byte key register 0xC write-only OPTKEY Option byte key [31:0] SR SR Status register 0x10 EOP End of operation [0:0] WRPERR Write protected error [4:4] OPTVERR Option and Engineering bits loadingvalidity error [15:15] BSY Busy [16:16] CR CR Flash control register 0x14 0xC0000000 PG Programming [0:0] PER Page erase [1:1] MER Mass erase [2:2] SER Sector erase [11:11] OPTSTRT Option byte program start [17:17] PGTSTRT Flash main memory program start [19:19] EOPIE End of operation interruptenable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option byteloading [27:27] OPTLOCK Options Lock [30:30] LOCK FLASH_CR Lock [31:31] OPTR OPTR Flash option register 0x20 0x4F55B0AA RDP Read Protection [7:0] BOREN BOR reset Level [8:8] BORF_LEV These bits contain the VDD supply levelthreshold that activates the reset [11:9] IDWG_SW Independent watchdogselection [12:12] WWDG_SW Window watchdog selection [13:13] NRST_MODE NRST_MODE [14:14] nBOOT1 Boot configuration [15:15] SDKR SDKR Flash SDK address register 0x24 0xFFE0001F SDK_STRT SDK area start address [4:0] SDK_END SDK area end address [12:8] WRPR WRPR Flash WRP addressregister 0x2C 0xFFFF WRP WRP address [15:0] STCR STCR Flash sleep time configregister 0x90 0x6400 SLEEP_EN FLash sleep enable [0:0] SLEEP_TIME FLash sleep time configuration(counter based on HSI_10M) [15:8] TS0 TS0 Flash TS0 register 0x100 0xB4 TS0 FLash TS0 register [7:0] TS1 TS1 Flash TS1 register 0x104 0x1B0 TS1 FLash TS1 register [8:0] TS2P TS2P Flash TS2P register 0x108 0xB4 TS2P FLash TS2P register [7:0] TPS3 TPS3 Flash TPS3 register 0x10C 0x6C0 TPS3 FLash TPS3 register [10:0] TS3 TS3 Flash TS3 register 0x110 0xB4 TS3 FLash TS3 register [7:0] PERTPE PERTPE Flash PERTPE register 0x114 0xEA60 PERTPE FLash PERTPE register [16:0] SMERTPE SMERTPE Flash SMERTPE register 0x118 0xFD20 SMERTPE FLash SMERTPE register [16:0] PRGTPE PRGTPE Flash PRGTPE register 0x11C 0x8CA0 PRGTPE FLash PRGTPE register [15:0] PRETPE PRETPE Flash PRETPE register 0x120 0x12C0 PRETPE FLash PRETPE register [12:0] GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0xEBFFFFFF MODE0 Port x configuration bits (y =0..15) [1:0] MODE1 Port x configuration bits (y =0..15) [3:2] MODE2 Port x configuration bits (y =0..15) [5:4] MODE3 Port x configuration bits (y =0..15) [7:6] MODE4 Port x configuration bits (y =0..15) [9:8] MODE5 Port x configuration bits (y =0..15) [11:10] MODE6 Port x configuration bits (y =0..15) [13:12] MODE7 Port x configuration bits (y =0..15) [15:14] MODE8 Port x configuration bits (y =0..15) [17:16] MODE9 Port x configuration bits (y =0..15) [19:18] MODE10 Port x configuration bits (y =0..15) [21:20] MODE11 Port x configuration bits (y =0..15) [23:22] MODE12 Port x configuration bits (y =0..15) [25:24] MODE13 Port x configuration bits (y =0..15) [27:26] MODE14 Port x configuration bits (y =0..15) [29:28] MODE15 Port x configuration bits (y =0..15) [31:30] OTYPER OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y =0..15) [0:0] OT1 Port x configuration bits (y =0..15) [1:1] OT2 Port x configuration bits (y =0..15) [2:2] OT3 Port x configuration bits (y =0..15) [3:3] OT4 Port x configuration bits (y =0..15) [4:4] OT5 Port x configuration bits (y =0..15) [5:5] OT6 Port x configuration bits (y =0..15) [6:6] OT7 Port x configuration bits (y =0..15) [7:7] OT8 Port x configuration bits (y =0..15) [8:8] OT9 Port x configuration bits (y =0..15) [9:9] OT10 Port x configuration bits (y =0..15) [10:10] OT11 Port x configuration bits (y =0..15) [11:11] OT12 Port x configuration bits (y =0..15) [12:12] OT13 Port x configuration bits (y =0..15) [13:13] OT14 Port x configuration bits (y =0..15) [14:14] OT15 Port x configuration bits (y =0..15) [15:15] OSPEEDR OSPEEDR GPIO port output speedregister 0x8 0xC000000 OSPEED0 Port x configuration bits (y =0..15) [1:0] OSPEED1 Port x configuration bits (y =0..15) [3:2] OSPEED2 Port x configuration bits (y =0..15) [5:4] OSPEED3 Port x configuration bits (y =0..15) [7:6] OSPEED4 Port x configuration bits (y =0..15) [9:8] OSPEED5 Port x configuration bits (y =0..15) [11:10] OSPEED6 Port x configuration bits (y =0..15) [13:12] OSPEED7 Port x configuration bits (y =0..15) [15:14] OSPEED8 Port x configuration bits (y =0..15) [17:16] OSPEED9 Port x configuration bits (y =0..15) [19:18] OSPEED10 Port x configuration bits (y =0..15) [21:20] OSPEED11 Port x configuration bits (y =0..15) [23:22] OSPEED12 Port x configuration bits (y =0..15) [25:24] OSPEED13 Port x configuration bits (y =0..15) [27:26] OSPEED14 Port x configuration bits (y =0..15) [29:28] OSPEED15 Port x configuration bits (y =0..15) [31:30] PUPDR PUPDR GPIO port pull-up/pull-downregister 0xC 0x24000000 PUPD0 Port x configuration bits (y =0..15) [1:0] PUPD1 Port x configuration bits (y =0..15) [3:2] PUPD2 Port x configuration bits (y =0..15) [5:4] PUPD3 Port x configuration bits (y =0..15) [7:6] PUPD4 Port x configuration bits (y =0..15) [9:8] PUPD5 Port x configuration bits (y =0..15) [11:10] PUPD6 Port x configuration bits (y =0..15) [13:12] PUPD7 Port x configuration bits (y =0..15) [15:14] PUPD8 Port x configuration bits (y =0..15) [17:16] PUPD9 Port x configuration bits (y =0..15) [19:18] PUPD10 Port x configuration bits (y =0..15) [21:20] PUPD11 Port x configuration bits (y =0..15) [23:22] PUPD12 Port x configuration bits (y =0..15) [25:24] PUPD13 Port x configuration bits (y =0..15) [27:26] PUPD14 Port x configuration bits (y =0..15) [29:28] PUPD15 Port x configuration bits (y =0..15) [31:30] IDR IDR GPIO port input data register 0x10 read-only ID0 Port input data (y =0..15) [0:0] ID1 Port input data (y =0..15) [1:1] ID2 Port input data (y =0..15) [2:2] ID3 Port input data (y =0..15) [3:3] ID4 Port input data (y =0..15) [4:4] ID5 Port input data (y =0..15) [5:5] ID6 Port input data (y =0..15) [6:6] ID7 Port input data (y =0..15) [7:7] ID8 Port input data (y =0..15) [8:8] ID9 Port input data (y =0..15) [9:9] ID10 Port input data (y =0..15) [10:10] ID11 Port input data (y =0..15) [11:11] ID12 Port input data (y =0..15) [12:12] ID13 Port input data (y =0..15) [13:13] ID14 Port input data (y =0..15) [14:14] ID15 Port input data (y =0..15) [15:15] ODR ODR GPIO port output data register 0x14 OD0 Port output data (y =0..15) [0:0] OD1 Port output data (y =0..15) [1:1] OD2 Port output data (y =0..15) [2:2] OD3 Port output data (y =0..15) [3:3] OD4 Port output data (y =0..15) [4:4] OD5 Port output data (y =0..15) [5:5] OD6 Port output data (y =0..15) [6:6] OD7 Port output data (y =0..15) [7:7] OD8 Port output data (y =0..15) [8:8] OD9 Port output data (y =0..15) [9:9] OD10 Port output data (y =0..15) [10:10] OD11 Port output data (y =0..15) [11:11] OD12 Port output data (y =0..15) [12:12] OD13 Port output data (y =0..15) [13:13] OD14 Port output data (y =0..15) [14:14] OD15 Port output data (y =0..15) [15:15] BSRR BSRR GPIO port bit set/resetregister 0x18 write-only BS0 Port x set bit y (y=0..15) [0:0] BS1 Port x set bit y (y=0..15) [1:1] BS2 Port x set bit y (y=0..15) [2:2] BS3 Port x set bit y (y=0..15) [3:3] BS4 Port x set bit y (y=0..15) [4:4] BS5 Port x set bit y (y=0..15) [5:5] BS6 Port x set bit y (y=0..15) [6:6] BS7 Port x set bit y (y=0..15) [7:7] BS8 Port x set bit y (y=0..15) [8:8] BS9 Port x set bit y (y=0..15) [9:9] BS10 Port x set bit y (y=0..15) [10:10] BS11 Port x set bit y (y=0..15) [11:11] BS12 Port x set bit y (y=0..15) [12:12] BS13 Port x set bit y (y=0..15) [13:13] BS14 Port x set bit y (y=0..15) [14:14] BS15 Port x set bit y (y=0..15) [15:15] BR0 Port x set bit y (y=0..15) [16:16] BR1 Port x reset bit y (y =0..15) [17:17] BR2 Port x reset bit y (y =0..15) [18:18] BR3 Port x reset bit y (y =0..15) [19:19] BR4 Port x reset bit y (y =0..15) [20:20] BR5 Port x reset bit y (y =0..15) [21:21] BR6 Port x reset bit y (y =0..15) [22:22] BR7 Port x reset bit y (y =0..15) [23:23] BR8 Port x reset bit y (y =0..15) [24:24] BR9 Port x reset bit y (y =0..15) [25:25] BR10 Port x reset bit y (y =0..15) [26:26] BR11 Port x reset bit y (y =0..15) [27:27] BR12 Port x reset bit y (y =0..15) [28:28] BR13 Port x reset bit y (y =0..15) [29:29] BR14 Port x reset bit y (y =0..15) [30:30] BR15 Port x reset bit y (y =0..15) [31:31] LCKR LCKR GPIO port configuration lockregister 0x1C LCK0 Port x lock bit y (y=0..15) [0:0] LCK1 Port x lock bit y (y=0..15) [1:1] LCK2 Port x lock bit y (y=0..15) [2:2] LCK3 Port x lock bit y (y=0..15) [3:3] LCK4 Port x lock bit y (y=0..15) [4:4] LCK5 Port x lock bit y (y=0..15) [5:5] LCK6 Port x lock bit y (y=0..15) [6:6] LCK7 Port x lock bit y (y=0..15) [7:7] LCK8 Port x lock bit y (y=0..15) [8:8] LCK9 Port x lock bit y (y=0..15) [9:9] LCK10 Port x lock bit y (y=0..15) [10:10] LCK11 Port x lock bit y (y=0..15) [11:11] LCK12 Port x lock bit y (y=0..15) [12:12] LCK13 Port x lock bit y (y=0..15) [13:13] LCK14 Port x lock bit y (y=0..15) [14:14] LCK15 Port x lock bit y (y=0..15) [15:15] LCKK Port x lock bit y (y=0..15) [16:16] AFRL AFRL GPIO alternate function lowregister 0x20 AFSEL0 Alternate function selection for port xbit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port xbit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port xbit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port xbit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port xbit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port xbit y (y = 0..7) [23:20] AFSEL6 Alternate function selection for port xbit y (y = 0..7) [27:24] AFSEL7 Alternate function selection for port xbit y (y = 0..7) [31:28] AFRH AFRH GPIO alternate function highregister 0x24 AFSEL8 Alternate function selection for port xbit y (y = 8..15) [3:0] AFSEL9 Alternate function selection for port xbit y (y = 8..15) [7:4] AFSEL10 Alternate function selection for port xbit y (y = 8..15) [11:8] AFSEL11 Alternate function selection for port xbit y (y = 8..15) [15:12] AFSEL12 Alternate function selection for port xbit y (y = 8..15) [19:16] AFSEL13 Alternate function selection for port xbit y (y = 8..15) [23:20] AFSEL14 Alternate function selection for port xbit y (y = 8..15) [27:24] AFSEL15 Alternate function selection for port xbit y (y = 8..15) [31:28] BRR BRR port bit reset register 0x28 write-only BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] BR8 Port Reset bit [8:8] BR9 Port Reset bit [9:9] BR10 Port Reset bit [10:10] BR11 Port Reset bit [11:11] BR12 Port Reset bit [12:12] BR13 Port Reset bit [13:13] BR14 Port Reset bit [14:14] BR15 Port Reset bit [15:15] GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0xFFFFFFFF MODE0 Port x configuration bits (y =0..15) [1:0] MODE1 Port x configuration bits (y =0..15) [3:2] MODE2 Port x configuration bits (y =0..15) [5:4] MODE3 Port x configuration bits (y =0..15) [7:6] MODE4 Port x configuration bits (y =0..15) [9:8] MODE5 Port x configuration bits (y =0..15) [11:10] MODE6 Port x configuration bits (y =0..15) [13:12] MODE7 Port x configuration bits (y =0..15) [15:14] MODE8 Port x configuration bits (y =0..15) [17:16] OTYPER OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y =0..15) [0:0] OT1 Port x configuration bits (y =0..15) [1:1] OT2 Port x configuration bits (y =0..15) [2:2] OT3 Port x configuration bits (y =0..15) [3:3] OT4 Port x configuration bits (y =0..15) [4:4] OT5 Port x configuration bits (y =0..15) [5:5] OT6 Port x configuration bits (y =0..15) [6:6] OT7 Port x configuration bits (y =0..15) [7:7] OT8 Port x configuration bits (y =0..15) [8:8] OSPEEDR OSPEEDR GPIO port output speedregister 0x8 OSPEED0 Port x configuration bits (y =0..15) [1:0] OSPEED1 Port x configuration bits (y =0..15) [3:2] OSPEED2 Port x configuration bits (y =0..15) [5:4] OSPEED3 Port x configuration bits (y =0..15) [7:6] OSPEED4 Port x configuration bits (y =0..15) [9:8] OSPEED5 Port x configuration bits (y =0..15) [11:10] OSPEED6 Port x configuration bits (y =0..15) [13:12] OSPEED7 Port x configuration bits (y =0..15) [15:14] OSPEED8 Port x configuration bits (y =0..15) [17:16] PUPDR PUPDR GPIO port pull-up/pull-downregister 0xC PUPD0 Port x configuration bits (y =0..15) [1:0] PUPD1 Port x configuration bits (y =0..15) [3:2] PUPD2 Port x configuration bits (y =0..15) [5:4] PUPD3 Port x configuration bits (y =0..15) [7:6] PUPD4 Port x configuration bits (y =0..15) [9:8] PUPD5 Port x configuration bits (y =0..15) [11:10] PUPD6 Port x configuration bits (y =0..15) [13:12] PUPD7 Port x configuration bits (y =0..15) [15:14] PUPD8 Port x configuration bits (y =0..15) [17:16] IDR IDR GPIO port input data register 0x10 read-only ID0 Port input data (y =0..15) [0:0] ID1 Port input data (y =0..15) [1:1] ID2 Port input data (y =0..15) [2:2] ID3 Port input data (y =0..15) [3:3] ID4 Port input data (y =0..15) [4:4] ID5 Port input data (y =0..15) [5:5] ID6 Port input data (y =0..15) [6:6] ID7 Port input data (y =0..15) [7:7] ID8 Port input data (y =0..15) [8:8] ODR ODR GPIO port output data register 0x14 OD0 Port output data (y =0..15) [0:0] OD1 Port output data (y =0..15) [1:1] OD2 Port output data (y =0..15) [2:2] OD3 Port output data (y =0..15) [3:3] OD4 Port output data (y =0..15) [4:4] OD5 Port output data (y =0..15) [5:5] OD6 Port output data (y =0..15) [6:6] OD7 Port output data (y =0..15) [7:7] OD8 Port output data (y =0..15) [8:8] BSRR BSRR GPIO port bit set/resetregister 0x18 write-only BS0 Port x set bit y (y=0..15) [0:0] BS1 Port x set bit y (y=0..15) [1:1] BS2 Port x set bit y (y=0..15) [2:2] BS3 Port x set bit y (y=0..15) [3:3] BS4 Port x set bit y (y=0..15) [4:4] BS5 Port x set bit y (y=0..15) [5:5] BS6 Port x set bit y (y=0..15) [6:6] BS7 Port x set bit y (y=0..15) [7:7] BS8 Port x set bit y (y=0..15) [8:8] BR0 Port x set bit y (y=0..15) [16:16] BR1 Port x reset bit y (y =0..15) [17:17] BR2 Port x reset bit y (y =0..15) [18:18] BR3 Port x reset bit y (y =0..15) [19:19] BR4 Port x reset bit y (y =0..15) [20:20] BR5 Port x reset bit y (y =0..15) [21:21] BR6 Port x reset bit y (y =0..15) [22:22] BR7 Port x reset bit y (y =0..15) [23:23] BR8 Port x reset bit y (y =0..15) [24:24] LCKR LCKR GPIO port configuration lockregister 0x1C LCK0 Port x lock bit y (y=0..15) [0:0] LCK1 Port x lock bit y (y=0..15) [1:1] LCK2 Port x lock bit y (y=0..15) [2:2] LCK3 Port x lock bit y (y=0..15) [3:3] LCK4 Port x lock bit y (y=0..15) [4:4] LCK5 Port x lock bit y (y=0..15) [5:5] LCK6 Port x lock bit y (y=0..15) [6:6] LCK7 Port x lock bit y (y=0..15) [7:7] LCK8 Port x lock bit y (y=0..15) [8:8] LCKK Port x lock bit y (y=0..15) [16:16] AFRL AFRL GPIO alternate function lowregister 0x20 AFSEL0 Alternate function selection for port xbit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port xbit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port xbit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port xbit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port xbit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port xbit y (y = 0..7) [23:20] AFSEL6 Alternate function selection for port xbit y (y = 0..7) [27:24] AFSEL7 Alternate function selection for port xbit y (y = 0..7) [31:28] AFRH AFRH GPIO alternate function highregister 0x24 AFSEL8 Alternate function selection for port xbit y (y = 8..15) [3:0] AFSEL9 Alternate function selection for port xbit y (y = 8..15) [7:4] AFSEL10 Alternate function selection for port xbit y (y = 8..15) [11:8] AFSEL11 Alternate function selection for port xbit y (y = 8..15) [15:12] AFSEL12 Alternate function selection for port xbit y (y = 8..15) [19:16] AFSEL13 Alternate function selection for port xbit y (y = 8..15) [23:20] AFSEL14 Alternate function selection for port xbit y (y = 8..15) [27:24] AFSEL15 Alternate function selection for port xbit y (y = 8..15) [31:28] BRR BRR port bit reset register 0x28 write-only BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] BR8 Port Reset bit [8:8] GPIOF 0x50001400 I2C Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 CR1 Control register 1 0x0 PE Peripheral enable [0:0] ENPEC PEC enable [5:5] ENGC General call enable [6:6] NOSTRETCH Clock stretching disable (Slave mode) [7:7] START Start generation [8:8] STOP Stop generation [9:9] ACK Acknowledge enable [10:10] POS Acknowledge/PEC Position (for data reception) [11:11] PEC Packet error checking [12:12] SWRST Software reset [15:15] CR2 CR2 Control register 2 0x4 FREQ Peripheral clock frequency [5:0] ITERREN Error interrupt enable [8:8] ITEVTEN Event interrupt enable [9:9] ITBUFEN Buffer interrupt enable [10:10] DMAEN DMA requests enable [11:11] LAST DMA last transfer [12:12] OAR1 OAR1 Own address register 1 0x8 ADD Interface address [7:1] DR DR Data register 0x10 DR 8-bit data register [7:0] SR1 SR1 Status register 1 0x14 SB Start bit (Master mode) [0:0] read-only ADDR Address sent (master mode)/matched (slave mode) [1:1] read-only BTF Byte transfer finished [2:2] read-only STOPF Stop detection (slave mode) [4:4] read-only RxNE Data register not empty (receivers) [6:6] read-only TxE Data register empty (transmitters) [7:7] read-only BERR Bus error [8:8] ARLO Arbitration lost (master mode) [9:9] AF Acknowledge failure [10:10] OVR Overrun/Underrun [11:11] PECERR PEC Error in reception [12:12] SR2 SR2 Status register 2 0x18 read-only MSL Master/slave [0:0] BUSY Bus busy [1:1] TRA Transmitter/receiver [2:2] GENCALL General call address (Slave mode) [4:4] DUALF Dual flag (Slave mode) [7:7] PEC acket error checking register [15:8] CCR CCR Clock control register 0x1C CCR Clock control register in Fast/Standard mode (Master mode) [11:0] DUTY Fast mode duty cycle [14:14] F_S I2C master mode selection [15:15] TRISE TRISE TRISE register 0x20 0x2 TRISE Maximum rise time in Fast/Standard mode (Master mode) [5:0] IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 write-only KEY Key value [15:0] PR PR Prescaler register (IWDG_PR) 0x4 PR Prescaler divider [2:0] RLR RLR Reload register (IWDG_RLR) 0x8 0xFFF RL Watchdog counter reloadvalue [11:0] SR SR Status register (IWDG_SR) 0xC read-only PVU Watchdog prescaler valueupdate [0:0] RVU Watchdog counter reload valueupdate [1:1] WVU Watchdog counter window value update [2:2] WINR WINR Window register (IWDG_SR) 0x10 read-only WIN window counter [11:0] LPTIM Low power timer LPTIM 0x40007C00 0x0 0x400 registers ISR ISR Interrupt and Status Register 0x0 read-only ARRM Autoreload match [1:1] ICR ICR Interrupt Clear Register 0x4 write-only ARRMCF Autoreload match ClearFlag [1:1] IER IER Interrupt Enable Register 0x8 ARRMIE Autoreload match InterruptEnable [1:1] CFGR CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR CR Control Register 0x10 ENABLE LPTIM Enable [0:0] SNGSTRT LPTIM start in single mode [1:1] RSTARE Reset after read enable [4:4] ARR ARR Autoreload Register 0x18 0x1 ARR Auto reload value [15:0] CNT CNT Counter Register 0x1C read-only CNT Counter value [15:0] PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x30000 BIAS_CR MR Bias current [3:0] BIAS_CR_SEL MR Bias current selection [4:4] DBP Disable backup domain writeprotection [8:8] VOS Voltage scaling rangeselection [9:9] MRRDY_TIME Time selection wakeup from LP to VR [11:10] FLS_SLPTIME Flash wait time after wakeup from the stop mode [13:12] LPR Low-power run [14:14] SRAM_RETV SRAM retention voltage control [18:16] HSION_CTRL HSI open time control [19:19] CR2 CR2 Power control register 2 0x4 0x500 PVDE Power voltage detectorenable [0:0] SRCSEL Power voltage detector volatageselection [2:2] PVDT Power voltage detector thresholdselection [6:4] FLTEN Digital filter enable [8:8] FLT_TIME Digital filter time configuration [11:9] SR SR Power status register 0x14 read-only PVDO PVD output [11:11] RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 4 CR CR Clock control register 0x0 0x100 HSION HSI16 clock enable [8:8] HSIKERON HSI16 always enable for peripheralkernels [9:9] HSIRDY HSI16 clock ready flag [10:10] HSIDIV HSI16 clock divisionfactor [13:11] HSEON HSE clock enable [16:16] HSERDY HSE clock ready flag [17:17] HSEBYP HSE crystal oscillatorbypass [18:18] CSSON Clock security systemenable [19:19] ICSCR ICSCR Internal clock sources calibrationregister 0x4 0x10000000 HSI_TRIM HSI clock trimming [12:0] HSI_FS HSI frequency selection [15:13] LSI_TRIM LSI clock trimming [24:16] LSI_STARTUP LSI startup time [27:26] CFGR CFGR Clock configuration register 0x8 SW System clock switch [2:0] SWS System clock switch status [5:3] read-only HPRE AHB prescaler [11:8] PPRE APB prescaler [14:12] MCOSEL Microcontroller clockoutput [26:24] MCOPRE Microcontroller clock outputprescaler [30:28] ECSCR ECSCR External clock source control register 0x10 HSE_FREQ HSE clock freqency selection [3:2] LSE_DRIVER LSE clock driver selection [17:16] CIER CIER Clock interrupt enableregister 0x18 LSIRDYIE LSI ready interrupt enable [0:0] LSERDYIE LSE ready interrupt enable [1:1] HSIRDYIE HSI ready interrupt enable [3:3] HSERDYIE HSE ready interrupt enable [4:4] CIFR CIFR Clock interrupt flag register 0x1C read-only LSIRDYF LSI ready interrupt flag [0:0] LSERDYF LSE ready interrupt flag [1:1] HSIRDYF HSI ready interrupt flag [3:3] HSERDYF HSE ready interrupt flag [4:4] CSSF HSE clock secure system interrupt flag [8:8] LSECSSF LSE clock secure system interrupt flag [9:9] CICR CICR Clock interrupt clear register 0x20 write-only LSIRDYC LSI ready interrupt clear [0:0] LSERDYC LSE ready interrupt clear [1:1] HSIRDYC HSI ready interrupt clear [3:3] HSERDYC HSE ready interrupt clear [4:4] CSSC clock secure system interrupt flag clear [8:8] LSECSSC LSE clock secure system interrupt flag clear [9:9] IOPRSTR IOPRSTR GPIO reset register 0x24 GPIOARST I/O port A reset [0:0] GPIOBRST I/O port B reset [1:1] GPIOFRST I/O port F reset [5:5] AHBRSTR AHBRSTR AHB peripheral reset register 0x28 DMARST DMA reset [0:0] CRCRST CRC reset [12:12] APBRSTR1 APBRSTR1 APB peripheral reset register1 0x2C TIM3RST TIM3 timer reset [1:1] USART2RST USART2 reset [17:17] I2CRST I2C reset [21:21] DBGRST Debug support reset [27:27] PWRRST Power interface reset [28:28] LPTIMRST Low Power Timer reset [31:31] APBRSTR2 APBRSTR2 APB peripheral reset register2 0x30 SYSCFGRST SYSCFG and COMPreset [0:0] TIM1RST TIM1 timer reset [11:11] SPI1RST SPI1 reset [12:12] USART1RST USART1 reset [14:14] TIM14RST TIM14 timer reset [15:15] TIM16RST TIM16 timer reset [17:17] TIM17RST TIM17 timer reset [18:18] ADCRST ADC reset [20:20] COMP1RST COMP1 reset [21:21] COMP2RST COMP2 reset [22:22] IOPENR IOPENR GPIO clock enable register 0x34 GPIOAEN I/O port A clock enable [0:0] GPIOBEN I/O port B clock enable [1:1] GPIOFEN I/O port F clock enable [5:5] AHBENR AHBENR AHB peripheral clock enableregister 0x38 DMAEN DMA clock enable [0:0] FLASHEN Flash memory interface clockenable [8:8] SRAMEN SRAM memory interface clockenable [9:9] CRCEN CRC clock enable [12:12] APBENR1 APBENR1 APB peripheral clock enable register1 0x3C TIM3EN TIM3 timer clock enable [1:1] RTCAPBEN RTC APB clock enable [10:10] WWDGEN WWDG clock enable [11:11] USART2EN USART2 clock enable [17:17] I2CEN I2C clock enable [21:21] DBGEN Debug support clock enable [27:27] PWREN Power interface clockenable [28:28] LPTIMEN LPTIM clock enable [31:31] APBENR2 APBENR2 APB peripheral clock enable register2 0x40 SYSCFGEN SYSCFG, COMP and VREFBUF clockenable [0:0] TIM1EN TIM1 timer clock enable [11:11] SPI1EN SPI1 clock enable [12:12] USART1EN USART1 clock enable [14:14] TIM14EN TIM14 timer clock enable [15:15] TIM16EN TIM16 timer clock enable [17:17] TIM17EN TIM16 timer clock enable [18:18] ADCEN ADC clock enable [20:20] COMP1EN COMP1 clock enable [21:21] COMP2EN COMP2 clock enable [22:22] CCIPR CCIPR Peripherals independent clock configurationregister 0x54 PVDSEL PVD detect clock sourceselection [7:7] COMP1SEL COMP1 clock sourceselection [8:8] COMP2SEL COMP2 clock sourceselection [9:9] LPTIM1SEL LPTIM1 clock sourceselection [19:18] BDCR BDCR RTC domain control register 0x5C LSEON LSE oscillator enable [0:0] LSERDY LSE oscillator ready [1:1] LSEBYP LSE oscillator bypass [2:2] LSECSSON LSE CSS enable [5:5] LSECSSD LSE CSS detect [6:6] RTCSEL RTC clock source selection [9:8] RTCEN RTC clock source enable [15:15] BDRST RTC domain software reset [16:16] LSCOEN Low-speed clock output (LSCO)enable [24:24] LSCOSEL Low-speed clock outputselection [25:25] CSR CSR Control/status register 0x60 LSION LSI oscillator enable [0:0] LSIRDY LSI oscillator ready [1:1] RMVF Remove reset flags [23:23] OBLRSTF Option byte loader resetflag [25:25] PINRSTF Pin reset flag [26:26] PWRRSTF BOR or POR/PDR flag [27:27] SFTRSTF Software reset flag [28:28] IWDGRSTF Independent window watchdog resetflag [29:29] WWDGRSTF Window watchdog reset flag [30:30] RTC Real time clock RTC 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 CRH CRH RTC Control Register High 0x0 SECIE Second interrupt Enable [0:0] ALRIE Alarm interrupt Enable [1:1] OWIE Overflow interrupt Enable [2:2] CRL CRL RTC Control Register Low 0x4 0x20 SECF Second Flag [0:0] ALRF Alarm Flag [1:1] OWF Overflow Flag [2:2] RSF Registers Synchronized Flag [3:3] CNF Configuration Flag [4:4] RTOFF RTC operation OFF [5:5] read-only PRLH PRLH RTC Prescaler Load Register High 0x8 write-only PRLH RTC Prescaler Load Register High [3:0] PRLL PRLL RTC Prescaler Load Register Low 0xC write-only 0x8000 PRLL RTC Prescaler Divider Register Low [15:0] DIVH DIVH RTC Prescaler Divider Register High 0x10 read-only DIVH RTC prescaler divider register high [3:0] DIVL DIVL RTC Prescaler Divider Register Low 0x14 read-only 0x8000 DIVL RTC prescaler divider register Low [15:0] CNTH CNTH RTC Counter Register High 0x18 CNTH RTC counter register high [15:0] CNTL CNTL RTC Counter Register Low 0x1C CNTL RTC counter register Low [15:0] ALRH ALRH RTC Alarm Register High 0x20 write-only 0xFFFF ALRH RTC alarm register high [15:0] ALRL ALRL RTC Alarm Register Low 0x24 write-only 0xFFFF ALRL RTC alarm register low [15:0] RTCCR RTCCR RTC clock calibration 0x2C CAL Calibration value [6:0] CCO Calibration clock output [7:7] ASOE Alarm or second output enable [8:8] ASOS Alarm or second output selection [9:9] SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 CR1 control register 1 0x0 CPHA Clock phase [0:0] CPOL Clock polarity [1:1] MSTR Master selection [2:2] BR Baud rate control [5:3] SPE SPI enable [6:6] LSBFIRST Frame format [7:7] SSI Internal slave selection [8:8] SSM Software slave management [9:9] RXONLY Receive only [10:10] BIDIOE Output enable in bidirectional mode [14:14] BIDIMODE Bidirectional data mode enable [15:15] CR2 CR2 control register 2 0x4 RXDMAEN Rx buffer DMA enable [0:0] TXDMAEN Tx buffer DMA enable [1:1] SSOE SS output enable [2:2] ERRIE Error interrupt enable [5:5] RXNEIE RX buffer not empty interrupt enable [6:6] TXEIE Tx buffer empty interrupt enable [7:7] DS Data length [11:11] FRXTH FIFO reception threshold [12:12] LDMA_RX Last DAM Transmit(RX) [13:13] LDMA_TX Last DAM Transmit(TX) [14:14] SLVFM Slave fast mode enable [15:15] SR SR status register 0x8 0x2 RXNE Receive buffer not empty [0:0] read-only TXE Transmit buffer empty [1:1] read-only MODF Mode fault [5:5] read-only OVR Overrun flag [6:6] read-only BSY Busy flag [7:7] read-only FRLVL FIFO reception level [10:9] read-only FTLVL FIFO transmission level [12:11] read-only DR DR data register 0xC DR Data register [15:0] SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers CFGR1 CFGR1 SYSCFG configuration register1 0x0 MEM_MODE Memory mapping selectionbits [1:0] I2C_PA2_ANF Analog filter enable control driving capabilityactivation bits PA2 [18:18] I2C_PA3_ANF Analog filter enable control driving capabilityactivation bits PA3 [19:19] I2C_PA7_ANF Analog filter enable control driving capabilityactivation bits PA7 [20:20] I2C_PA8_ANF Analog filter enable control driving capabilityactivation bits PA8 [21:21] I2C_PA9_ANF Analog filter enable control driving capabilityactivation bits PA9 [22:22] I2C_PA10_ANF Analog filter enable control driving capabilityactivation bits PA10 [23:23] I2C_PA11_ANF Analog filter enable control driving capabilityactivation bits PA11 [24:24] I2C_PA12_ANF Analog filter enable control driving capabilityactivation bits PA12 [25:25] I2C_PB6_ANF Analog filter enable control driving capabilityactivation bits PB6 [26:26] I2C_PB7_ANF Analog filter enable control driving capabilityactivation bits PB7 [27:27] I2C_PB8_ANF Analog filter enable control driving capabilityactivation bits PB8 [28:28] I2C_PF0_ANF Analog filter enable control driving capabilityactivation bits PF0 [29:29] I2C_PF1_ANF Analog filter enable control driving capabilityactivation bits PF1 [30:30] CFGR2 CFGR2 SYSCFG configuration register2 0x18 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enablebit [0:0] PVD_LOCK PVD lock enable bit [2:2] COMP1_BRK_TIM1 COMP1 is enable to input of TIM1 break [3:3] COMP2_BRK_TIM1 COMP2 is enable to input of TIM1 break [4:4] COMP1_BRK_TIM16 COMP1 is enable to input of TIM16 break [5:5] COMP2_BRK_TIM16 COMP2 is enable to input of TIM16 break [6:6] COMP1_BRK_TIM17 COMP1 is enable to input of TIM17 break [7:7] COMP2_BRK_TIM17 COMP2 is enable to input of TIM17 break [8:8] ETR_SRC_TIM1 TIM1 ETR source selection [10:9] CFGR3 CFGR3 SYSCFG configuration register3 0x1C DMA1_MAP DMA channel1 requeset selection [4:0] DMA2_MAP DMA channel2 requeset selection [12:8] DMA3_MAP DMA channel3 requeset selection [20:16] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 CR1 control register 1 0x0 CEN Counter enable [0:0] UDIS Update disable [1:1] URS Update request source [2:2] OPM One-pulse mode [3:3] DIR Direction [4:4] CMS Center-aligned modeselection [6:5] ARPE Auto-reload preload enable [7:7] CKD Clock division [9:8] CR2 CR2 control register 2 0x4 CCPC Capture/compare preloadedcontrol [0:0] CCUS Capture/compare control updateselection [2:2] CCDS Capture/compare DMAselection [3:3] MMS Master mode selection [6:4] TI1S TI1 selection [7:7] OIS1 Output Idle state 1 [8:8] OIS1N Output Idle state 1 [9:9] OIS2 Output Idle state 2 [10:10] OIS2N Output Idle state 2 [11:11] OIS3 Output Idle state 3 [12:12] OIS3N Output Idle state 3 [13:13] OIS4 Output Idle state 4 [14:14] SMCR SMCR slave mode control register 0x8 SMS Slave mode selection [2:0] OCCS OCREF clear selection bit [3:3] TS Trigger selection [6:4] MSM Master/Slave mode [7:7] ETF External trigger filter [11:8] ETPS External trigger prescaler [13:12] ECE External clock enable [14:14] ETP External trigger polarity [15:15] DIER DIER DMA/Interrupt enable register 0xC UIE Update interrupt enable [0:0] CC1IE Capture/Compare 1 interruptenable [1:1] CC2IE Capture/Compare 2 interruptenable [2:2] CC3IE Capture/Compare 3 interruptenable [3:3] CC4IE Capture/Compare 4 interruptenable [4:4] COMIE COM interrupt enable [5:5] TIE Trigger interrupt enable [6:6] BIE Break interrupt enable [7:7] UDE Update DMA request enable [8:8] CC1DE Capture/Compare 1 DMA requestenable [9:9] CC2DE Capture/Compare 2 DMA requestenable [10:10] CC3DE Capture/Compare 3 DMA requestenable [11:11] CC4DE Capture/Compare 4 DMA requestenable [12:12] COMDE COM DMA request enable [13:13] TDE Trigger DMA request enable [14:14] SR SR status register 0x10 UIF Update interrupt flag [0:0] CC1IF Capture/compare 1 interruptflag [1:1] CC2IF Capture/Compare 2 interruptflag [2:2] CC3IF Capture/Compare 3 interruptflag [3:3] CC4IF Capture/Compare 4 interruptflag [4:4] COMIF COM interrupt flag [5:5] TIF Trigger interrupt flag [6:6] BIF Break interrupt flag [7:7] CC1OF Capture/Compare 1 overcaptureflag [9:9] CC2OF Capture/compare 2 overcaptureflag [10:10] CC3OF Capture/Compare 3 overcaptureflag [11:11] CC4OF Capture/Compare 4 overcaptureflag [12:12] EGR EGR event generation register 0x14 write-only UG Update generation [0:0] CC1G Capture/compare 1generation [1:1] CC2G Capture/compare 2generation [2:2] CC3G Capture/compare 3generation [3:3] CC4G Capture/compare 4generation [4:4] COMG Capture/Compare control updategeneration [5:5] TG Trigger generation [6:6] BG Break generation [7:7] CCMR1_Output CCMR1_Output capture/compare mode register (outputmode) 0x18 CC1S Capture/Compare 1selection [1:0] OC1FE Output Compare 1 fastenable [2:2] OC1PE Output Compare 1 preloadenable [3:3] OC1M Output Compare 1 mode [6:4] OC1CE Output Compare 1 clearenable [7:7] CC2S Capture/Compare 2selection [9:8] OC2FE Output Compare 2 fastenable [10:10] OC2PE Output Compare 2 preloadenable [11:11] OC2M Output Compare 2 mode [14:12] OC2CE Output Compare 2 clearenable [15:15] CCMR1_Input CCMR1_Input capture/compare mode register 1 (inputmode) CCMR1_Output 0x18 CC1S Capture/Compare 1selection [1:0] ICPSC Input capture 1 prescaler [3:2] IC1F Input capture 1 filter [7:4] CC2S Capture/Compare 2selection [9:8] IC2PSC Input capture 2 prescaler [11:10] IC2F Input capture 2 filter [15:12] CCMR2_Output CCMR2_Output capture/compare mode register (outputmode) 0x1C CC3S Capture/Compare 3selection [1:0] OC3FE Output compare 3 fastenable [2:2] OC3PE Output compare 3 preloadenable [3:3] OC3M Output compare 3 mode [6:4] OC3CE Output compare 3 clearenable [7:7] CC4S Capture/Compare 4selection [9:8] OC4FE Output compare 4 fastenable [10:10] OC4PE Output compare 4 preloadenable [11:11] OC4M Output compare 4 mode [14:12] OC4CE Output compare 4 clearenable [15:15] CCMR2_Input CCMR2_Input capture/compare mode register 2 (inputmode) CCMR2_Output 0x1C CC3S Capture/compare 3selection [1:0] IC3PSC Input capture 3 prescaler [3:2] IC3F Input capture 3 filter [7:4] CC4S Capture/Compare 4selection [9:8] IC4PSC Input capture 4 prescaler [11:10] IC4F Input capture 4 filter [15:12] CCER CCER capture/compare enableregister 0x20 CC1E Capture/Compare 1 outputenable [0:0] CC1P Capture/Compare 1 outputPolarity [1:1] CC1NE Capture/Compare 1 complementary outputenable [2:2] CC1NP Capture/Compare 1 outputPolarity [3:3] CC2E Capture/Compare 2 outputenable [4:4] CC2P Capture/Compare 2 outputPolarity [5:5] CC2NE Capture/Compare 2 complementary outputenable [6:6] CC2NP Capture/Compare 2 outputPolarity [7:7] CC3E Capture/Compare 3 outputenable [8:8] CC3P Capture/Compare 3 outputPolarity [9:9] CC3NE Capture/Compare 3 complementary outputenable [10:10] CC3NP Capture/Compare 3 outputPolarity [11:11] CC4E Capture/Compare 4 outputenable [12:12] CC4P Capture/Compare 3 outputPolarity [13:13] CNT CNT counter 0x24 CNT counter value [15:0] PSC PSC prescaler 0x28 PSC Prescaler value [15:0] ARR ARR auto-reload register 0x2C ARR Auto-reload value [15:0] RCR RCR repetition counter register 0x30 REP Repetition counter value [7:0] CCR1 CCR1 capture/compare register 1 0x34 CCR1 Capture/Compare 1 value [15:0] CCR2 CCR2 capture/compare register 2 0x38 CCR2 Capture/Compare 2 value [15:0] CCR3 CCR3 capture/compare register 3 0x3C CCR3 Capture/Compare value [15:0] CCR4 CCR4 capture/compare register 4 0x40 CCR4 Capture/Compare value [15:0] BDTR BDTR break and dead-time register 0x44 DTG Dead-time generator setup [7:0] LOCK Lock configuration [9:8] OSSI Off-state selection for Idlemode [10:10] OSSR Off-state selection for Runmode [11:11] BKE Break enable [12:12] BKP Break polarity [13:13] AOE Automatic output enable [14:14] MOE Main output enable [15:15] DCR DCR DMA control register 0x48 DBA DMA base address [4:0] DBL DMA burst length [12:8] DMAR DMAR DMA address for full transfer 0x4C DMAB DMA register for burstaccesses [15:0] TIM3 General purpose timer TIM 0x40000400 0x0 0x400 registers TIM3 TIM3 global Interrupt 16 CR1 CR1 control register 1 0x0 CEN Counter enable [0:0] UDIS Update disable [1:1] URS Update request source [2:2] OPM One-pulse mode [3:3] DIR Direction [4:4] CMS Center-aligned modeselection [6:5] ARPE Auto-reload preload enable [7:7] CKD Clock division [9:8] CR2 CR2 control register 2 0x4 CCDS Capture/compare DMAselection [3:3] MMS Master mode selection [6:4] TI1S TI1 selection [7:7] SMCR SMCR slave mode control register 0x8 SMS Slave mode selection [2:0] OCCS OCREF Clear Selection [3:3] TS Trigger selection [6:4] MSM Master/Slave mode [7:7] DIER DIER DMA/Interrupt enable register 0xC UIE Update interrupt enable [0:0] CC1IE Capture/Compare 1 interruptenable [1:1] CC2IE Capture/Compare 2 interruptenable [2:2] CC3IE Capture/Compare 3 interruptenable [3:3] CC4IE Capture/Compare 4 interruptenable [4:4] TIE Trigger interrupt enable [6:6] UDE Update DMA request enable [8:8] CC1DE Capture/Compare 1 DMA requestenable [9:9] CC2DE Capture/Compare 2 DMA requestenable [10:10] CC3DE Capture/Compare 3 DMA requestenable [11:11] CC4DE Capture/Compare 4 DMA requestenable [12:12] TDE Trigger DMA request enable [14:14] SR SR status register 0x10 UIF Update interrupt flag [0:0] CC1IF Capture/compare 1 interruptflag [1:1] CC2IF Capture/Compare 2 interruptflag [2:2] CC3IF Capture/Compare 3 interruptflag [3:3] CC4IF Capture/Compare 4 interruptflag [4:4] TIF Trigger interrupt flag [6:6] CC1OF Capture/Compare 1 overcaptureflag [9:9] CC2OF Capture/compare 2 overcaptureflag [10:10] CC3OF Capture/Compare 3 overcaptureflag [11:11] CC4OF Capture/Compare 4 overcaptureflag [12:12] EGR EGR event generation register 0x14 write-only UG Update generation [0:0] CC1G Capture/compare 1generation [1:1] CC2G Capture/compare 2generation [2:2] CC3G Capture/compare 3generation [3:3] CC4G Capture/compare 4generation [4:4] TG Trigger generation [6:6] CCMR1_Output CCMR1_Output capture/compare mode register 1 (outputmode) 0x18 CC1S Capture/Compare 1selection [1:0] OC1FE Output compare 1 fastenable [2:2] OC1PE Output compare 1 preloadenable [3:3] OC1M Output compare 1 mode [6:4] OC1CE Output compare 1 clearenable [7:7] CC2S Capture/Compare 2selection [9:8] OC2FE Output compare 2 fastenable [10:10] OC2PE Output compare 2 preloadenable [11:11] OC2M Output compare 2 mode [14:12] OC2CE Output compare 2 clearenable [15:15] CCMR1_Input CCMR1_Input capture/compare mode register 1 (inputmode) CCMR1_Output 0x18 CC1S Capture/Compare 1selection [1:0] IC1PSC Input capture 1 prescaler [3:2] IC1F Input capture 1 filter [7:4] CC2S Capture/compare 2selection [9:8] IC2PSC Input capture 2 prescaler [11:10] IC2F Input capture 2 filter [15:12] CCMR2_Output CCMR2_Output capture/compare mode register 2 (outputmode) 0x1C CC3S Capture/Compare 3selection [1:0] OC3FE Output compare 3 fastenable [2:2] OC3PE Output compare 3 preloadenable [3:3] OC3M Output compare 3 mode [6:4] OC3CE Output compare 3 clearenable [7:7] CC4S Capture/Compare 4selection [9:8] OC4FE Output compare 4 fastenable [10:10] OC4PE Output compare 4 preloadenable [11:11] OC4M Output compare 4 mode [14:12] OC4CE Output compare 4 clearenable [15:15] CCMR2_Input CCMR2_Input capture/compare mode register 2 (inputmode) CCMR2_Output 0x1C CC3S Capture/Compare 3selection [1:0] IC3PSC Input capture 3 prescaler [3:2] IC3F Input capture 3 filter [7:4] CC4S Capture/Compare 4selection [9:8] IC4PSC Input capture 4 prescaler [11:10] IC4F Input capture 4 filter [15:12] CCER CCER capture/compare enableregister 0x20 CC1E Capture/Compare 1 outputenable [0:0] CC1P Capture/Compare 1 outputPolarity [1:1] CC1NP Capture/Compare 1 outputPolarity [3:3] CC2E Capture/Compare 2 outputenable [4:4] CC2P Capture/Compare 2 outputPolarity [5:5] CC2NP Capture/Compare 2 outputPolarity [7:7] CC3E Capture/Compare 3 outputenable [8:8] CC3P Capture/Compare 3 outputPolarity [9:9] CC3NP Capture/Compare 3 outputPolarity [11:11] CC4E Capture/Compare 4 outputenable [12:12] CC4P Capture/Compare 4 outputPolarity [13:13] CC4NP Capture/Compare 4 outputPolarity [15:15] CNT CNT counter 0x24 CNT counter value [15:0] PSC PSC prescaler 0x28 PSC Prescaler value [15:0] ARR ARR auto-reload register 0x2C ARR Auto-reload value [15:0] CCR1 CCR1 capture/compare register 1 0x34 CCR1 Capture/Compare 1 value [15:0] CCR2 CCR2 capture/compare register 2 0x38 CCR2 Capture/Compare 2 value [15:0] CCR3 CCR3 capture/compare register 3 0x3C CCR3 Capture/Compare value [15:0] CCR4 CCR4 capture/compare register 4 0x40 CCR4 Capture/Compare value [15:0] DCR DCR DMA control register 0x48 DBA DMA base address [4:0] DBL DMA burst length [12:8] DMAR DMAR DMA address for full transfer 0x4C DMAB DMA register for burstaccesses [31:0] TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 CR1 TIM14 control register1 0x0 CEN Counter enable [0:0] UDIS Update disable [1:1] URS Update request source [2:2] ARPE Auto-reload preload enable [7:7] CKD Prescaler factor [9:8] DIER DIER DMA/Interrupt enable register 0xC UIE Update interrupt enable [0:0] CC1IE Compare/ [1:1] SR SR status register 0x10 UIF Update interrupt flag [0:0] CC1IF Compare/capture 1 interrupt flag [1:1] CC1OF Compare/capture 1 flag [9:9] EGR EGR event generation register 0x14 write-only UG Update generation [0:0] CC1G Compare/capture1 event [1:1] CCMR1_Output CCMR1_Output capture/compare mode register (outputmode) 0x18 CC1S Capture/Compare 1selection [1:0] OC1FE Output Compare 1 fastenable [2:2] OC1PE Output Compare 1 preloadenable [3:3] OC1M Output Compare 1 mode [6:4] CCMR1_Input CCMR1_Input capture/compare mode register 1 (inputmode) CCMR1_Output 0x18 CC1S Capture/Compare 1selection [1:0] IC1PSC Input capture 1 prescaler [3:2] IC1F Input capture 1 filter [7:4] CCER CCER capture/compare enableregister 0x20 CC1E Capture/Compare 1 outputenable [0:0] CC1P Capture/Compare 1 outputPolarity [1:1] CC1NP Capture/Compare 1 outputPolarity [3:3] CNT CNT counter 0x24 CNT counter value [15:0] PSC PSC prescaler 0x28 PSC Prescaler value [15:0] ARR ARR auto-reload register 0x2C ARR Auto-reload value [15:0] CCR1 CCR1 capture/compare register 1 0x34 CCR1 Capture/Compare 1 value [15:0] OR OR Option register 0x50 TI1_RMP TIM14 channel1 input remap [1:0] TIM16 General purpose timer TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global Interrupt 21 CR1 CR1 TIM16 control register1 0x0 CEN Counter enable [0:0] UDIS Update disable [1:1] URS Update request source [2:2] OPM One pulse mode [3:3] ARPE Auto-reload preload enable [7:7] CKD Prescaler factor [9:8] CR2 CR2 control register 2 0x4 CCPC Capture/compare preloadedcontrol [0:0] CCDS Capture/compare DMAselection [3:3] OIS1 Output Idle state 1 [8:8] OIS1N Output Idle state 1 [9:9] DIER DIER DMA/Interrupt enable register 0xC UIE Update interrupt enable [0:0] CC1IE Capture/Compare 1 interrupt enable [1:1] COMIE Com interrupt enable [5:5] BIE Break interrupt enable [7:7] UDE Update DMA request enable [8:8] CC1DE Compare/capture DMA requeset enable [9:9] SR SR status register 0x10 UIF Update interrupt flag [0:0] CC1IF Capture/Compare 1 interrupt flag [1:1] COMIF Com interrupt flag [5:5] BIF Break interrupt flag [7:7] CC1OF Update interrupt flag [9:9] EGR EGR event generation register 0x14 write-only UG Update generation [0:0] CC1G Capture/Compare 1 generation [1:1] COMG COM evnet generation [5:5] BG Break event generation [7:7] CCMR1_Output CCMR1_Output capture/compare mode register (outputmode) 0x18 CC1S Capture/Compare 1selection [1:0] OC1FE Output Compare 1 fastenable [2:2] OC1PE Output Compare 1 preloadenable [3:3] OC1M Output Compare 1 mode [6:4] CCMR1_Input CCMR1_Input capture/compare mode register 1 (inputmode) CCMR1_Output 0x18 CC1S Capture/Compare 1selection [1:0] IC1PSC Input capture 1 prescaler [3:2] IC1F Input capture 1 filter [7:4] CCER CCER capture/compare enableregister 0x20 CC1E Capture/Compare 1 outputenable [0:0] CC1P Capture/Compare 1 outputPolarity [1:1] CC1NE Capture/Compare 1 complementary outputenable [2:2] CC1NP Capture/Compare 1 outputPolarity [3:3] CNT CNT counter 0x24 CNT counter value [15:0] PSC PSC prescaler 0x28 PSC Prescaler value [15:0] ARR ARR auto-reload register 0x2C ARR Auto-reload value [15:0] RCR RCR repetition counter register 0x30 REP Repetition counter value [7:0] CCR1 CCR1 capture/compare register 1 0x34 CCR1 Capture/Compare 1 value [15:0] BDTR BDTR break and dead-time register 0x44 DTG Dead-time generator setup [7:0] LOCK Lock configuration [9:8] OSSI Off-state selection for Idlemode [10:10] OSSR Off-state selection for Runmode [11:11] BKE Break enable [12:12] BKP Break polarity [13:13] AOE Automatic output enable [14:14] MOE Main output enable [15:15] DCR DCR DMA control register 0x48 DBA DMA base address [4:0] DBL DMA burst length [12:8] DMAR DMAR DMA address for full transfer 0x4C DMAB DMA register for burstaccesses [31:0] TIM17 0x40014800 TIM17 TIM17 global Interrupt 22 USART1 Universal synchronous asynchronous receivertransmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR SR Status register 0x0 0xC0 PE Parity error [0:0] read-only FE Framing error [1:1] read-only NE Noise error flag [2:2] read-only ORE Overrun error [3:3] read-only IDLE IDLE line detected [4:4] read-only RXNE Read data register notempty [5:5] TC Transmission complete [6:6] TXE Transmit data registerempty [7:7] read-only CTS CTS flag [9:9] ABRF Automate baudrate detection flag [10:10] read-only ABRE Automate baudrate detection error flag [11:11] read-only ABRRQ Automate baudrate detection requeset [12:12] write-only DR DR Data register 0x4 DR Data value [8:0] BRR BRR Baud rate register 0x8 DIV_Fraction fraction of USARTDIV [3:0] DIV_Mantissa mantissa of USARTDIV [15:4] CR1 CR1 Control register 1 0xC SBK Send break [0:0] RWU Receiver wakeup [1:1] RE Receiver enable [2:2] TE Transmitter enable [3:3] IDLEIE IDLE interrupt enable [4:4] RXNEIE RXNE interrupt enable [5:5] TCIE Transmission complete interruptenable [6:6] TXEIE TXE interrupt enable [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control enable [10:10] WAKE Wakeup method [11:11] M Word length [12:12] UE USART enable [13:13] CR2 CR2 Control register 2 0x10 ADD Address of the USART node [3:0] LBCL Last bit clock pulse [8:8] CPHA Clock phase [9:9] CPOL Clock polarity [10:10] CLKEN Clock enable [11:11] STOP STOP bits [13:12] CR3 CR3 Control register 3 0x14 EIE Error interrupt enable [0:0] IREN IrDA mode enable [1:1] IRLP IrDA low-power [2:2] HDSEL Half-duplex selection [3:3] DMAR DMA enable receiver [6:6] DMAT DMA enable transmitter [7:7] RTSE RTS enable [8:8] CTSE CTS enable [9:9] CTSIE CTS interrupt enable [10:10] OVER8 Oversampling mode [11:11] ABREN Auto baudrate enable [12:12] ABRMOD Auto baudrate mode [14:13] USART2 0x40004400 USART2 USART2 global Interrupt 28 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window WatchDog Interrupt 0 CR CR Control register (WWDG_CR) 0x0 0x7F T 7-bit counter (MSB to LSB) [6:0] WDGA Activation bit [7:7] CFR CFR Configuration register(WWDG_CFR) 0x4 0x7F W 7-bit window value [6:0] WDGTB Timer Base [8:7] EWI Early Wakeup Interrupt [9:9] SR SR Status register (WWDG_SR) 0x8 EWIF Early Wakeup Interrupt flag [0:0]