Puya Puya PY32F002Xxx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupts 12 ISR ISR ADC interrupt and status register 0x0 EOSMP ADC group regular end of sampling flag [1:1] EOC ADC group regular end of unitary conversion flag [2:2] EOSEQ ADC group regular end of sequence conversions flag [3:3] OVR ADC group regular overrun flag [4:4] AWD ADC analog watchdog flag [7:7] IER IER ADC interrupt enable register 0x4 EOSMPIE ADC group regular end of sampling interrupt [1:1] EOCIE ADC group regular end of unitary conversion interrupt [2:2] EOSEQIE ADC group regular end of sequence conversions interrupt [3:3] OVRIE ADC group regular overrun interrupt [4:4] AWDIE ADC analog watchdog interrupt [7:7] CR CR ADC control register 0x8 ADEN ADC enable [0:0] ADDIS ADC enable [1:1] ADSTART ADC group regular conversion start [2:2] ADSTP ADC group regular conversion stop [4:4] VREF_BUFFERE desc VREF_BUFFERE [5:5] VERBUFF_SEL desc VERBUFF_SEL [7:6] ADCAL ADC group regular conversion calibration [31:31] CFGR1 CFGR1 ADC configuration register 1 0xC SCANDIR Scan sequence direction [2:2] RESSEL ADC data resolution [4:3] ALIGN ADC data alignement [5:5] EXTSEL ADC group regular external trigger source [8:6] EXTEN ADC group regular external trigger polarity [11:10] OVRMOD ADC group regular overrun configuration [12:12] CONT ADC group regular continuous conversion mode [13:13] WAIT Wait conversion mode [14:14] DISCEN ADC group regular sequencer discontinuous mode [16:16] AWDSGL ADC analog watchdog monitoring a single channel or all channels [22:22] AWDEN ADC analog watchdog enable on scope ADC group regular [23:23] AWDCH ADC analog watchdog monitored channel selection [29:26] CFGR2 CFGR2 ADC configuration register 2 0x10 CKMODE ADC clock mode [31:28] SMPR SMPR ADC sampling time register 0x14 SMP Sampling time selection [2:0] TR TR ADC analog watchdog 1 threshold register 0x20 0xFFF0000 LT ADC analog watchdog threshold low [11:0] HT ADC analog watchdog threshold high [27:16] CHSELR CHSELR ADC group regular sequencer register 0x28 0xFFF0000 CHSEL0 Channel-0 selection [0:0] CHSEL1 Channel-1 selection [1:1] CHSEL2 Channel-2 selection [2:2] CHSEL3 Channel-3 selection [3:3] CHSEL4 Channel-4 selection [4:4] CHSEL5 Channel-5 selection [5:5] CHSEL6 Channel-6 selection [6:6] CHSEL7 Channel-7 selection [7:7] CHSEL8 Channel-8 selection [8:8] CHSEL9 Channel-9 selection [9:9] DR DR ADC group regular data register 0x40 read-only DATA ADC group regular conversion data [15:0] CCSR CCSR ADC calibration configuration and status register 0x44 CALSEL Calibration contents selection [11:11] CALSMP Calibration sample time selection [13:12] CALBYP desc CALBYP [14:14] CALSET Calibration factor selection [15:15] OFFSUC desc OFFSUC [29:29] CALSUC desc CALSUC [30:30] CALON Calibration flag [31:31] read-only CCR CCR ADC common configuration register 0x308 VREFEN VREFINT enable [22:22] TSEN Temperature sensor enable [23:23] COMP1 Comparator 1 COMP 0x40010200 0x0 0x10 registers ADC_COMP ADC and COMP Interrupts 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] INNSEL desc INNSEL [5:5] WINMODE Comparator non-inverting input selector for window mode [11:11] POLARITY Comparator polarity selector [15:15] VCDIV VCDIV [25:22] VCDIV_EN VCDIV_EN [26:26] VCSEL VCSEL [27:27] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN1 Filter enable bit [0:0] FLTCNT1 Comparator filter and counter [31:16] COMP2 Comparator2 COMP 0x40010210 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] INMSEL Comparator signal selector for inverting input INM [5:5] INPSEL Comparator signal selector for non-inverting input [9:9] POLARITY Comparator polarity selector [15:15] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN2 Filter enable bit [0:0] FLTCNT2 Comparator filter and counter [31:16] CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0xFFFFFFFF DR Data Register [31:0] IDR IDR Independent Data register 0x4 IDR Independent Data register [7:0] CR CR Control register 0x8 write-only RESET Reset bit [0:0] DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 read-only REV_ID REV_ID [31:0] CR CR Debug MCU Configuration Register 0x4 DBG_STOP Debug Stop Mode [1:1] APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 DBG_LPTIM_STOP Debug LPTIM stopped when Core ishalted [31:31] APB_FZ2 APB_FZ2 APB Freeze Register2 0xC DBG_TIMER1_STOP Debug Timer 1 stopped when Core ishalted [11:11] DBG_TIM14_STOP Debug TIM 14 stopped whenCore is halted [15:15] EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR RTSR EXTI rising trigger selection register 0x0 RT0 Rising trigger event configuration bit of Configurable Event input [0:0] RT1 Rising trigger event configuration bit of Configurable Event input [1:1] RT2 Rising trigger event configuration bit of Configurable Event input [2:2] RT3 Rising trigger event configuration bit of Configurable Event input [3:3] RT4 Rising trigger event configuration bit of Configurable Event input [4:4] RT5 Rising trigger event configuration bit of Configurable Event input [5:5] RT6 Rising trigger event configuration bit of Configurable Event input [6:6] RT7 Rising trigger event configuration bit of Configurable Event input [7:7] RT17 Rising trigger event configuration bit of Configurable Event input [17:17] RT18 Rising trigger event configuration bit of Configurable Event input [18:18] FTSR FTSR EXTI falling trigger selection register 0x4 FT0 Falling trigger event configuration bit of Configurable Event input [0:0] FT1 Falling trigger event configuration bit of Configurable Event input [1:1] FT2 Falling trigger event configuration bit of Configurable Event input [2:2] FT3 Falling trigger event configuration bit of Configurable Event input [3:3] FT4 Falling trigger event configuration bit of Configurable Event input [4:4] FT5 Falling trigger event configuration bit of Configurable Event input [5:5] FT6 Falling trigger event configuration bit of Configurable Event input [6:6] FT7 Falling trigger event configuration bit of Configurable Event input [7:7] FT17 Falling trigger event configuration bit of Configurable Event input [17:17] FT18 Falling trigger event configuration bit of Configurable Event input [18:18] SWIER SWIER EXTI software interrupt event register 0x8 SWI0 Rising trigger event configuration bit of Configurable Event input [0:0] SWI1 Rising trigger event configuration bit of Configurable Event input [1:1] SWI2 Rising trigger event configuration bit of Configurable Event input [2:2] SWI3 Rising trigger event configuration bit of Configurable Event input [3:3] SWI4 Rising trigger event configuration bit of Configurable Event input [4:4] SWI5 Rising trigger event configuration bit of Configurable Event input [5:5] SWI6 Rising trigger event configuration bit of Configurable Event input [6:6] SWI7 Rising trigger event configuration bit of Configurable Event input [7:7] SWI17 Rising trigger event configuration bit of Configurable Event input [17:17] SWI18 Rising trigger event configuration bit of Configurable Event input [18:18] PR PR EXTI pending register 0xC PR0 configurable event inputs x rising edge Pending bit. [0:0] PR1 configurable event inputs x rising edge Pending bit. [1:1] PR2 configurable event inputs x rising edge Pending bit. [2:2] PR3 configurable event inputs x rising edge Pending bit. [3:3] PR4 configurable event inputs x rising edge Pending bit. [4:4] PR5 configurable event inputs x rising edge Pending bit. [5:5] PR6 configurable event inputs x rising edge Pending bit. [6:6] PR7 configurable event inputs x rising edge Pending bit. [7:7] PR17 configurable event inputs x rising edge Pending bit. [17:17] PR18 configurable event inputs x rising edge Pending bit. [18:18] EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 EXTI0 GPIO port selection [1:0] EXTI1 GPIO port selection [9:8] EXTI2 GPIO port selection [17:16] EXTI3 GPIO port selection [25:24] EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 EXTI4 GPIO port selection [1:0] EXTI5 GPIO port selection [8:8] EXTI6 GPIO port selection [16:16] EXTI7 GPIO port selection [24:24] IMR IMR EXTI CPU wakeup with interrupt mask register 0x80 0xFFF80000 IM0 CPU wakeup with interrupt mask on event input [0:0] IM1 CPU wakeup with interrupt mask on event input [1:1] IM2 CPU wakeup with interrupt mask on event input [2:2] IM3 CPU wakeup with interrupt mask on event input [3:3] IM4 CPU wakeup with interrupt mask on event input [4:4] IM5 CPU wakeup with interrupt mask on event input [5:5] IM6 CPU wakeup with interrupt mask on event input [6:6] IM7 CPU wakeup with interrupt mask on event input [7:7] IM17 CPU wakeup with interrupt mask on event input [17:17] IM18 CPU wakeup with interrupt mask on event input [18:18] IM29 CPU wakeup with interrupt mask on event input [29:29] EMR EMR EXTI CPU wakeup with event mask register 0x84 EM0 CPU wakeup with event mask on event input [0:0] EM1 CPU wakeup with event mask on event input [1:1] EM2 CPU wakeup with event mask on event input [2:2] EM3 CPU wakeup with event mask on event input [3:3] EM4 CPU wakeup with event mask on event input [4:4] EM5 CPU wakeup with event mask on event input [5:5] EM6 CPU wakeup with event mask on event input [6:6] EM7 CPU wakeup with event mask on event input [7:7] EM17 CPU wakeup with event mask on event input [17:17] EM18 CPU wakeup with event mask on event input [18:18] EM29 CPU wakeup with event mask on event input [29:29] FLASH Flash Flash 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR ACR Access control register 0x0 0x600 LATENCY Latency [0:0] KEYR KEYR Flash key register 0x8 write-only KEY Flash key [31:0] OPTKEYR OPTKEYR Option byte key register 0xC write-only OPTKEY Option byte key [31:0] SR SR Status register 0x10 EOP End of operation [0:0] WRPERR Write protected error [4:4] OPTVERR Option and Engineering bits loading validity error [15:15] BSY Busy [16:16] CR CR Flash control register 0x14 0xC0000000 PG Programming [0:0] PER Page erase [1:1] MER Mass erase [2:2] SER Sector erase [11:11] OPTSTRT Option byte program start [17:17] PGSTRT Flash main memory program start [19:19] EOPIE End of operation interrupt enable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option byte loading [27:27] OPTLOCK Options Lock [30:30] LOCK FLASH_CR Lock [31:31] OPTR OPTR Flash option register 0x20 0x4F55B0AA BOREN BOR reset Level [8:8] BORF_LEV These bits contain the VDD supply level threshold that activates the reset [11:9] IWDG_SW Independent watchdog selection [12:12] SWD_MODE SWD_MODE [13:13] NRST_MODE NRST_MODE [14:14] SDKR SDKR Flash SDK address register 0x24 0xFFE0001F SDK_STRT SDK area start address [3:0] SDK_END SDK area end address [11:8] BTCR BTCR FLASH boot control register 0x28 BOOT_SIZE desc BOOT_SIZE [2:0] BOOT0 desc BOOT0 [14:14] NBOOT1 desc NBOOT1 [15:15] WRPR WRPR Flash WRP address register 0x2C 0xFFFF WRP WRP address [5:0] STCR STCR Flash sleep time config register 0x90 0x6400 SLEEP_EN FLash sleep enable [0:0] SLEEP_TIME FLash sleep time configuration(counter based on HSI_10M) [15:8] TS0 TS0 Flash TS0 register 0x100 0xB4 TS0 FLash TS0 register [8:0] TS1 TS1 Flash TS1 register 0x104 0x1B0 TS1 FLash TS1 register [9:0] TS2P TS2P Flash TS2P register 0x108 0xB4 TS2P FLash TS2P register [8:0] TPS3 TPS3 Flash TPS3 register 0x10C 0x6C0 TPS3 FLash TPS3 register [11:0] TS3 TS3 Flash TS3 register 0x110 0xB4 TS3 FLash TS3 register [8:0] PERTPE PERTPE Flash PERTPE register 0x114 0x14820 PERTPE FLash PERTPE register [17:0] SMERTPE SMERTPE Flash SMERTPE register 0x118 0x14820 SMERTPE FLash SMERTPE register [17:0] PRGTPE PRGTPE Flash PRGTPE register 0x11C 0x5DC0 PRGTPE FLash PRGTPE register [15:0] PRETPE PRETPE Flash PRETPE register 0x120 0x12C0 PRETPE FLash PRETPE register [13:0] GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0xEBFFFFFF MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] MODE2 Port x configuration bits (y = 0..15) [5:4] MODE3 Port x configuration bits (y = 0..15) [7:6] MODE4 Port x configuration bits (y = 0..15) [9:8] MODE5 Port x configuration bits (y = 0..15) [11:10] MODE6 Port x configuration bits (y = 0..15) [13:12] MODE7 Port x configuration bits (y = 0..15) [15:14] OTYPER OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OT2 Port x configuration bits (y = 0..15) [2:2] OT3 Port x configuration bits (y = 0..15) [3:3] OT4 Port x configuration bits (y = 0..15) [4:4] OT5 Port x configuration bits (y = 0..15) [5:5] OT6 Port x configuration bits (y = 0..15) [6:6] OT7 Port x configuration bits (y = 0..15) [7:7] OSPEEDR OSPEEDR GPIO port output speed register 0x8 0xC000000 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] OSPEED2 Port x configuration bits (y = 0..15) [5:4] OSPEED3 Port x configuration bits (y = 0..15) [7:6] OSPEED4 Port x configuration bits (y = 0..15) [9:8] OSPEED5 Port x configuration bits (y = 0..15) [11:10] OSPEED6 Port x configuration bits (y = 0..15) [13:12] OSPEED7 Port x configuration bits (y = 0..15) [15:14] PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x24000000 PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] PUPD2 Port x configuration bits (y = 0..15) [5:4] PUPD3 Port x configuration bits (y = 0..15) [7:6] PUPD4 Port x configuration bits (y = 0..15) [9:8] PUPD5 Port x configuration bits (y = 0..15) [11:10] PUPD6 Port x configuration bits (y = 0..15) [13:12] PUPD7 Port x configuration bits (y = 0..15) [15:14] IDR IDR GPIO port input data register 0x10 read-only ID0 Port input data (y = 0..15) [0:0] ID1 Port input data (y = 0..15) [1:1] ID2 Port input data (y = 0..15) [2:2] ID3 Port input data (y = 0..15) [3:3] ID4 Port input data (y = 0..15) [4:4] ID5 Port input data (y = 0..15) [5:5] ID6 Port input data (y = 0..15) [6:6] ID7 Port input data (y = 0..15) [7:7] ODR ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] OD2 Port output data (y = 0..15) [2:2] OD3 Port output data (y = 0..15) [3:3] OD4 Port output data (y = 0..15) [4:4] OD5 Port output data (y = 0..15) [5:5] OD6 Port output data (y = 0..15) [6:6] OD7 Port output data (y = 0..15) [7:7] BSRR BSRR GPIO port bit set/reset register 0x18 write-only BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BS2 Port x set bit y (y= 0..15) [2:2] BS3 Port x set bit y (y= 0..15) [3:3] BS4 Port x set bit y (y= 0..15) [4:4] BS5 Port x set bit y (y= 0..15) [5:5] BS6 Port x set bit y (y= 0..15) [6:6] BS7 Port x set bit y (y= 0..15) [7:7] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] BR2 Port x reset bit y (y = 0..15) [18:18] BR3 Port x reset bit y (y = 0..15) [19:19] BR4 Port x reset bit y (y = 0..15) [20:20] BR5 Port x reset bit y (y = 0..15) [21:21] BR6 Port x reset bit y (y = 0..15) [22:22] BR7 Port x reset bit y (y = 0..15) [23:23] LCKR LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCK2 Port x lock bit y (y= 0..15) [2:2] LCK3 Port x lock bit y (y= 0..15) [3:3] LCK4 Port x lock bit y (y= 0..15) [4:4] LCK5 Port x lock bit y (y= 0..15) [5:5] LCK6 Port x lock bit y (y= 0..15) [6:6] LCK7 Port x lock bit y (y= 0..15) [7:7] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] AFSEL2 Alternate function selection for port x bit y (y = 0..7) [11:8] AFSEL3 Alternate function selection for port x bit y (y = 0..7) [15:12] AFSEL4 Alternate function selection for port x bit y (y = 0..7) [19:16] AFSEL5 Alternate function selection for port x bit y (y = 0..7) [23:20] AFSEL6 Alternate function selection for port x bit y (y = 0..7) [27:24] AFSEL7 Alternate function selection for port x bit y (y = 0..7) [31:28] BRR BRR port bit reset register 0x28 write-only BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] BR2 Port Reset bit [2:2] BR3 Port Reset bit [3:3] BR4 Port Reset bit [4:4] BR5 Port Reset bit [5:5] BR6 Port Reset bit [6:6] BR7 Port Reset bit [7:7] GPIOB 0x50000400 GPIOC General-purpose I/Os GPIO 0x50000800 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0xEBFFFFFF MODE0 Port x configuration bits (y = 0..15) [1:0] MODE1 Port x configuration bits (y = 0..15) [3:2] OTYPER OTYPER GPIO port output type register 0x4 OT0 Port x configuration bits (y = 0..15) [0:0] OT1 Port x configuration bits (y = 0..15) [1:1] OSPEEDR OSPEEDR GPIO port output speed register 0x8 0xC000000 OSPEED0 Port x configuration bits (y = 0..15) [1:0] OSPEED1 Port x configuration bits (y = 0..15) [3:2] PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x24000000 PUPD0 Port x configuration bits (y = 0..15) [1:0] PUPD1 Port x configuration bits (y = 0..15) [3:2] IDR IDR GPIO port input data register 0x10 read-only ID0 Port input data (y = 0..15) [0:0] ID1 Port input data (y = 0..15) [1:1] ODR ODR GPIO port output data register 0x14 OD0 Port output data (y = 0..15) [0:0] OD1 Port output data (y = 0..15) [1:1] BSRR BSRR GPIO port bit set/reset register 0x18 write-only BS0 Port x set bit y (y= 0..15) [0:0] BS1 Port x set bit y (y= 0..15) [1:1] BR0 Port x set bit y (y= 0..15) [16:16] BR1 Port x reset bit y (y = 0..15) [17:17] LCKR LCKR GPIO port configuration lock register 0x1C LCK0 Port x lock bit y (y= 0..15) [0:0] LCK1 Port x lock bit y (y= 0..15) [1:1] LCKK Port x lock bit y (y= 0..15) [16:16] AFRL AFRL GPIO alternate function low register 0x20 AFSEL0 Alternate function selection for port x bit y (y = 0..7) [3:0] AFSEL1 Alternate function selection for port x bit y (y = 0..7) [7:4] BRR BRR port bit reset register 0x28 write-only BR0 Port Reset bit [0:0] BR1 Port Reset bit [1:1] I2C Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 CR1 Control register 1 0x0 PE Peripheral enable [0:0] ENGC General call enable [6:6] NOSTRETCH Clock stretching disable (Slavemode) [7:7] START Start generation [8:8] STOP Stop generation [9:9] ACK Acknowledge enable [10:10] POS Acknowledge/PEC Position (for datareception) [11:11] SWRST Software reset [15:15] CR2 CR2 Control register 2 0x4 FREQ Peripheral clock frequency [5:0] ITERREN Error interrupt enable [8:8] ITEVTEN Event interrupt enable [9:9] ITBUFEN Buffer interrupt enable [10:10] OAR1 OAR1 Own address register 1 0x8 ADD Interface address [7:1] DR DR Data register 0x10 DR 8-bit data register [7:0] SR1 SR1 Status register 1 0x14 SB Start bit (Master mode) [0:0] read-only ADDR Address sent (master mode)/matched(slave mode) [1:1] read-only BTF Byte transfer finished [2:2] read-only STOPF Stop detection (slavemode) [4:4] read-only RxNE Data register not empty(receivers) [6:6] read-only TxE Data register empty(transmitters) [7:7] read-only BERR Bus error [8:8] ARLO Arbitration lost (mastermode) [9:9] AF Acknowledge failure [10:10] OVR Overrun/Underrun [11:11] SR2 SR2 Status register 2 0x18 read-only MSL Master/slave [0:0] BUSY Bus busy [1:1] TRA Transmitter/receiver [2:2] GENCALL General call address (Slavemode) [4:4] CCR CCR Clock control register 0x1C CCR Clock control register in Fast/Standardmode (Master mode) [11:0] DUTY Fast mode duty cycle [14:14] F_S I2C master mode selection [15:15] TRISE TRISE TRISE register 0x20 0x2 TRISE Maximum rise time in Fast/Standard mode(Master mode) [5:0] IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 write-only KEY Key value [15:0] PR PR Prescaler register (IWDG_PR) 0x4 PR Prescaler divider [2:0] RLR RLR Reload register (IWDG_RLR) 0x8 0xFFF RL Watchdog counter reload value [11:0] SR SR Status register (IWDG_SR) 0xC read-only PVU Watchdog prescaler value update [0:0] RVU Watchdog counter reload value update [1:1] LPTIM1 Low power timer LPTIM1 0x40007C00 0x0 0x400 registers LPTIM1_DAC LPTIM1, DAC global Interrupts 17 ISR ISR Interrupt and Status Register 0x0 read-only ARRM Autoreload match [1:1] ARROK Autoreload match update OK [4:4] ICR ICR Interrupt Clear Register 0x4 write-only ARRMCF Autoreload match Clear Flag [1:1] ARROKCF Autoreload match update OK Clear Flag [4:4] IER IER Interrupt Enable Register 0x8 ARRMIE Autoreload matchInterrupt Enable [1:1] ARROKIE Autoreload match update OK Interrupt Enable [4:4] CFGR CFGR Configuration Register 0xC PRESC Clock prescaler [11:9] PRELOAD Registers update mode [22:22] CR CR Control Register 0x10 ENABLE LPTIM Enable [0:0] SNGSTRT LPTIM start in single mode [1:1] CNTSTRT CNTSTRT [2:2] COUNTRST Reset counter [3:3] RSTARE Reset after read enable [4:4] ARR ARR Autoreload Register 0x18 0x1 ARR Auto reload value [15:0] CNT CNT Counter Register 0x1C read-only CNT Counter value [15:0] PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x30000 BIAS_CR MR Bias current [3:0] BIAS_CR_SEL MR Bias current selection [4:4] DBP Disable backup domain write protection [7:7] VOS Voltage scaling range selection [9:8] MRRDY_TIME Time selection wakeup from LP to VR [11:10] FLS_SLPTIME Flash wait time after wakeup from the stop mode [13:12] LPR Low-power run [15:14] SRAM_RETV SRAM retention voltage control [18:16] HSION_CTRL HSI open time control [19:19] CR2 CR2 Power control register 2 0x4 0x500 FLTEN Digital filter enable [8:8] FLT_TIME Digital filter time configuration [11:9] RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC RCC global Interrupt 4 CR CR Clock control register 0x0 0x100 HSION HSI16 clock enable [8:8] HSIRDY HSI16 clock ready flag [10:10] HSIDIV HSI16 clock division factor [13:11] HSEEN [18:18] ICSCR ICSCR Internal clock sources calibration register 0x4 0x10000000 HSI_TRIM HSI clock trimming [12:0] HSI_FS HSI frequency selection [15:13] LSI_TRIM LSI clock trimming [24:16] LSI_STARTUP LSI startup time [27:26] CFGR CFGR Clock configuration register 0x8 SW System clock switch [2:0] SWS System clock switch status [5:3] read-only HPRE AHB prescaler [11:8] PPRE APB prescaler [14:12] MCOSEL Microcontroller clock output [26:24] MCOPRE Microcontroller clock output prescaler [30:28] ECSCR ECSCR External clock source control register 0x10 LSE_DRIVER desc LSE_DRIVER [17:16] LSE_STARTUP desc LSE_STARTUP [21:20] CIER CIER Clock interrupt enable register 0x18 LSIRDYIE LSI ready interrupt enable [0:0] LSERDYIE LSE ready interrupt enable [1:1] HSIRDYIE HSI ready interrupt enable [3:3] CIFR CIFR Clock interrupt flag register 0x1C read-only LSIRDYF LSI ready interrupt flag [0:0] LSERDYF LSE ready interrupt flag [2:2] HSIRDYF HSI ready interrupt flag [3:3] LSECSSF LSE clock secure system interrupt flag [9:9] CICR CICR Clock interrupt clear register 0x20 write-only LSIRDYC LSI ready interrupt clear [0:0] LSERDYC LSE ready interrupt clear [1:1] HSIRDYC HSI ready interrupt clear [3:3] LSECSSC LSE clock secure system interrupt flag clear [9:9] IOPRSTR IOPRSTR GPIO reset register 0x24 GPIOARST I/O port A reset [0:0] GPIOBRST I/O port B reset [1:1] GPIOCRST I/O port C reset [2:2] AHBRSTR AHBRSTR AHB peripheral reset register 0x28 FLASHRST FLASH reset [8:8] CRCRST CRC reset [12:12] APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C I2CRST I2C reset [21:21] DBGRST Debug support reset [27:27] PWRRST Power interface reset [28:28] LPTIMRST Low Power Timer reset [31:31] APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 SYSCFGRST SYSCFG and COMP reset [0:0] TIM1RST TIM1 timer reset [11:11] SPI1RST SPI1 reset [12:12] USART1RST USART1 reset [14:14] TIM14RST TIM14 reset [15:15] ADCRST ADC reset [20:20] COMP1RST COMP1 reset [21:21] COMP2RST COMP2 reset [22:22] IOPENR IOPENR GPIO clock enable register 0x34 GPIOAEN I/O port A clock enable [0:0] GPIOBEN I/O port B clock enable [1:1] GPIOCEN I/O port C clock enable [2:2] AHBENR AHBENR AHB peripheral clock enable register 0x38 FLASHEN Flash memory interface clock enable [8:8] SRAMEN SRAM memory interface clock enable [9:9] CRCEN CRC clock enable [12:12] APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C I2CEN I2C clock enable [21:21] DBGEN Debug support clock enable [27:27] PWREN Power interface clock enable [28:28] LPTIMEN LPTIM clock enable [31:31] APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable [0:0] TIM1EN TIM1 timer clock enable [11:11] SPI1EN SPI1 clock enable [12:12] USART1EN USART1 clock enable [14:14] TIM14EN TIM14 clock enable [15:15] ADCEN ADC clock enable [20:20] COMP1EN COMP1 clock enable [21:21] COMP2EN COMP2 clock enable [22:22] CCIPR CCIPR Peripherals independent clock configuration register 0x54 COMP1SEL COMP1 clock source selection [10:10] COMP2SEL COMP2 clock source selection [11:11] LPTIM1SEL LPTIM1 clock source selection [19:18] BDCR BDCR RTC domain control register 0x5C LSEON LSE oscillator enable [0:0] LSERDY LSE oscillator ready [1:1] LSEBYP LSE oscillator bypass [2:2] LSECSSON LSE CSS enable [5:5] LSECSSD LSE CSS detect [6:6] LSCOEN Low-speed clock output (LSCO) enable [24:24] LSCOSEL Low-speed clock output selection [25:25] CSR CSR Control/status register 0x60 LSION LSI oscillator enable [0:0] LSIRDY LSI oscillator ready [1:1] PINRST_FLTDIS desc PINRST_FLTDIS [8:8] RMVF Remove reset flags [23:23] OBLRSTF Option byte loader reset flag [25:25] PINRSTF Pin reset flag [26:26] PWRRSTF BOR or POR/PDR flag [27:27] SFTRSTF Software reset flag [28:28] IWDGRSTF Independent window watchdog reset flag [29:29] SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 desc CR1 0x0 CPHA desc CPHA [0:0] CPOL desc CPOL [1:1] MSTR desc MSTR [2:2] BR desc BR [5:3] SPE desc SPE [6:6] LSBFIRST desc LSBFIRST [7:7] SSI desc SSI [8:8] SSM desc SSM [9:9] RXONLY desc RXONLY [10:10] DDF desc DDF [11:11] BIDIOE desc BIDIOE [14:14] BIDIMODE desc BIDIMODE [15:15] CR2 desc CR2 0x4 SSOE desc SSOE [2:2] ERRIE desc ERRIE [5:5] RXNEIE desc RXNEIE [6:6] TXEIE desc TXEIE [7:7] DS desc DS [11:11] SLVFM desc SLVFM [15:15] SR desc SR 0x8 0x2 RXNE desc RXNE [0:0] read-only TXE desc TXE [1:1] read-only MODF desc MODF [5:5] read-only OVR desc OVR [6:6] read-only BSY desc BSY [7:7] read-only FRLVL desc FRLVL [10:9] read-only FTLVL desc FTLVL [12:11] read-only DR desc DR 0xC DR desc DR [15:0] SYSCFG System configuration controller SYSCFG 0x40010000 0x0 0x30 registers CFGR1 CFGR1 SYSCFG configuration register 1 0x0 MEM_MODE Memory mapping selection bits [1:0] I2C_PA2_FMP desc I2C_PA2_FMP [16:16] I2C_PB3_FMP desc I2C_PB3_FMP [17:17] I2C_PB4_FMP desc I2C_PB4_FMP [18:18] I2C_PB6_FMP desc I2C_PB6_FMP [19:19] CFGR2 CFGR2 SYSCFG configuration register 2 0x18 LOCKUP_LOCK Cortex-M0+ LOCKUP bit enable bit [0:0] ETR_SRC_TIM1 TIM1 ETR source selection [10:9] GPIO_ENS desc GPIO_ENS 0x1C PA_ENS desc PA_ENS [7:0] PB_ENS desc PB_ENS [15:8] PC_ENS desc PC_ENS [17:16] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCPC desc CCPC [0:0] CCUS desc CCUS [2:2] MMS desc MMS [6:4] TI1S desc TI1S [7:7] OIS1 desc OIS1 [8:8] OIS1N desc OIS1N [9:9] OIS2 desc OIS2 [10:10] OIS2N desc OIS2N [11:11] OIS3 desc OIS3 [12:12] OIS3N desc OIS3N [13:13] OIS4 desc OIS4 [14:14] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] OCCS desc OCCS [3:3] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] COMIE desc COMIE [5:5] TIE desc TIE [6:6] BIE desc BIE [7:7] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only COMG desc COMG [5:5] write-only TG desc TG [6:6] write-only BG desc BG [7:7] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] OC3FE desc OC3FE [2:2] OC3PE desc OC3PE [3:3] OC3M desc OC3M [6:4] OC3CE desc OC3CE [7:7] CC4S desc CC4S [9:8] OC4FE desc OC4FE [10:10] OC4PE desc OC4PE [11:11] OC4M desc OC4M [14:12] OC4CE desc OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 0xFFFF CC3S desc CC3S [1:0] IC3PSC desc IC3PSC [3:2] IC3F desc IC3F [7:4] CC4S desc CC4S [9:8] IC4PSC desc IC4PSC [11:10] IC4F desc IC4F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NE desc CC1NE [2:2] CC1NP desc CC1NP [3:3] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC2NE desc CC2NE [6:6] CC2NP desc CC2NP [7:7] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC3NE desc CC3NE [10:10] CC3NP desc CC3NP [11:11] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] RCR desc RCR 0x30 0xFFFF 0xFFFF REP desc REP [7:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] CCR3 desc CCR3 0x3C 0xFFFF CCR3 desc CCR3 [15:0] CCR4 desc CCR4 0x40 0xFFFF CCR4 desc CCR4 [15:0] BDTR desc BDTR 0x44 0xFFFF DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] ARPE desc ARPE [7:7] CKD desc CKD [9:8] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC1OF desc CC1OF [9:9] IC1IR desc IC1IR [16:16] IC1IF desc IC1IF [20:20] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC1NP desc CC1NP [3:3] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] OR desc OR 0x50 TI1_RMP desc TI1_RMP [1:0] USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR SR Status register 0x0 0xC0 PE Parity error [0:0] read-only FE Framing error [1:1] read-only NE Noise error flag [2:2] read-only ORE Overrun error [3:3] read-only IDLE IDLE line detected [4:4] read-only RXNE Read data register not empty [5:5] TC Transmission complete [6:6] TXE Transmit data register empty [7:7] read-only CTS CTS flag [9:9] ABRF Automate baudrate detection flag [10:10] read-only ABRE Automate baudrate detection error flag [11:11] read-only ABRRQ Automate baudrate detection requeset [12:12] write-only DR DR Data register 0x4 DR Data value [8:0] BRR BRR Baud rate register 0x8 DIV_Fraction fraction of USARTDIV [3:0] DIV_Mantissa mantissa of USARTDIV [15:4] CR1 CR1 Control register 1 0xC RWU Receiver wakeup [1:1] RE Receiver enable [2:2] TE Transmitter enable [3:3] IDLEIE IDLE interrupt enable [4:4] RXNEIE RXNE interrupt enable [5:5] TCIE Transmission complete interrupt enable [6:6] TXEIE TXE interrupt enable [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control enable [10:10] WAKE Wakeup method [11:11] M Word length [12:12] UE USART enable [13:13] CR2 CR2 Control register 2 0x10 ADD Address of the USART node [3:0] LBCL Last bit clock pulse [8:8] CPHA Clock phase [9:9] CPOL Clock polarity [10:10] CLKEN Clock enable [11:11] STOP STOP bits [13:12] CR3 CR3 Control register 3 0x14 EIE Error interrupt enable [0:0] HDSEL Half-duplex selection [3:3] RTSE RTS enable [8:8] CTSE CTS enable [9:9] CTSIE CTS interrupt enable [10:10] OVER8 Oversampling mode [11:11] ABREN Auto baudrate enable [12:12] ABRMOD Auto baudrate mode [14:13]