Puya https://www.puyasemi.com/uploadfiles/ PY32F0xx_DFP Puya PY32F0 Series Device Support ADD PY32F020B . Update PY32F002X,add comp1/2 . Remove PY32F001B. Update PY32F005/032 interrupt and DbgMCUcfg. Update PY32F072E/040E/071E. upadte PY32F001B/F005/F032/F090/F092 Algorithm. upadte PY32F001B Algorithm. update PY32F090/F092 Interrupt and DbgMCUcfg. add PY32F006 svd. add PY32F001B svd. update PY32F031 DbgMCU. add PY32F005 svd. add PY32F002C svd. add PY32F0033 svd. add PY32F005 svd. add PY32F002C svd. update PY32F032 svd. update PY32F002C svd. Add PY32F090/092 series. Add PY32F002Z series. update PY32F040/071/072 series. Add OLD PY32F0xx FLM Files. Add PY32F001C series. Add PY32F040EPxB series. Add PY32F002C series. Add more series. Add more series. Fix some issues. Add more series. Add more series. First Release version of PY32F0 Device Family Pack. Puya Device Support PY32F0 The PY32F0 mainstream microcontrollers are based on high-performance Arm Cortex-M0+ 32-bit RISC core. The chip provides sleep and stop low-power operating modes to meet different low-power applications. Offering a high level of integration, they are suitable for a variety of application scenarios, such as controllers, handheld devices, PC peripherals, games and GPS platforms, industrial applications, etc. // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x4002103C, Read32(0x4002103C) | 0x08000000); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior __var DbgMCU_CR = 0x00000002; // DBGMCU_CR: DBG_STOP, DBG_STANDBY __var DbgMCU_APB_Fz1 = 0x00000000; // DGBMCU_APB_FZ1: All Peripherals Operate as in Normal Mode __var DbgMCU_APB_Fz2 = 0x00000000; // DGBMCU_APB_FZ2: All Peripherals Operate as in Normal Mode // Replication of Standard Functionality Write32(0xE000EDF0, 0xA05F0001); // Enable Core Debug via DHCSR // Device Specific Debug Setup Write32(0x40021040, Read32(0x40021040) | 0x00000400); // Set RCC_APBENR1.DBGEN Write32(0x40015804, DbgMCU_CR); // DBGMCU_CR: Configure MCU Debug Write32(0x40015808, DbgMCU_APB_Fz1); // DBGMCU_APB_FZ1: Configure APB Peripheral Freeze1 Behavior Write32(0x4001580C, DbgMCU_APB_Fz2); // DBGMCU_APB_FZ2: Configure APB Peripheral Freeze2 Behavior Puya PYF0 Series Devices Puya PY32F0 Series devices and CMSIS Puya PY32F001Cx4 Devices Puya PY32F001C Devices Puya PY32F002Ax5 Devices Puya PY32F002A Devices Puya PY32F002Bx5 Devices Puya PY32F002B Devices Puya PY32F002Cx5 Devices Puya PY32F002Cx6 Devices Puya PY32F002C Devices Puya PY32F002Xx2 Devices Puya PY32F002Xx4 Devices Puya PY32F002Xx5 Devices Puya PY32F002X Devices Puya PY32F002Zx4 Devices Puya PY32F002Z Devices Puya PY32F003x4 Devices Puya PY32F003x6 Devices Puya PY32F003x7 Devices Puya PY32F003x8 Devices Puya PY32F003 Devices Puya PY32F005x6 Devices Puya PY32F005 Devices Puya PY32F006x8 Devices Puya PY32F006 Devices Puya PY32F020Bx6 Devices Puya PY32F020B Devices Puya PY32F021x8 Devices Puya PY32F021 Devices Puya PY32F030x4 Devices Puya PY32F030x6 Devices Puya PY32F030x7 Devices Puya PY32F030x8 Devices Puya PY32F030 Devices Puya PY32F031x4 Devices Puya PY32F031x6 Devices Puya PY32F031x7 Devices Puya PY32F031x8 Devices Puya PY32F031 Devices Puya PY32F032x8 Devices Puya PY32F032 Devices Puya PY32F033x8 Devices Puya PY32F033 Devices Puya PY32F040x6 Devices Puya PY32F040x8 Devices Puya PY32F040x9 Devices Puya PY32F040xB Devices Puya PY32F040 Devices Puya PY32F040Cx6 Devices Puya PY32F040Cx8 Devices Puya PY32F040Cx9 Devices Puya PY32F040CxB Devices Puya PY32F040Ex6 Devices Puya PY32F040Ex8 Devices Puya PY32F040Ex9 Devices Puya PY32F040ExB Devices Puya PY32F040EPxB Devices Puya PY32F040E Devices Puya PY32F071x6 Devices Puya PY32F071x8 Devices Puya PY32F071x9 Devices Puya PY32F071xB Devices Puya PY32F071 Devices Puya PY32F071Cx6 Devices Puya PY32F071Cx8 Devices Puya PY32F071Cx9 Devices Puya PY32F071CxB Devices Puya PY32F071Ex6 Devices Puya PY32F071Ex8 Devices Puya PY32F071Ex9 Devices Puya PY32F071ExB Devices Puya PY32F071E Devices Puya PY32F072x6 Devices Puya PY32F072x8 Devices Puya PY32F072x9 Devices Puya PY32F072xB Devices Puya PY32F072 Devices Puya PY32F072Cx6 Devices Puya PY32F072Cx8 Devices Puya PY32F072Cx9 Devices Puya PY32F072CxB Devices Puya PY32F072Ex6 Devices Puya PY32F072Ex8 Devices Puya PY32F072Ex9 Devices Puya PY32F072ExB Devices Puya PY32F072E Devices Puya PY32F090xB Devices Puya PY32F090xC Devices Puya PY32F090 Devices Puya PY32F092xC Devices Puya PY32F092 Devices Puya PY32F001C Devices and ARMCC Compiler Puya PY32F001C Devices and CMSIS-CORE Puya PY32F002A Devices and ARMCC Compiler Puya PY32F002A Devices and CMSIS-CORE Puya PY32F002B Devices and ARMCC Compiler Puya PY32F002B Devices and CMSIS-CORE Puya PY32F002C Devices and ARMCC Compiler Puya PY32F002C Devices and CMSIS-CORE Puya PY32F002X Devices and ARMCC Compiler Puya PY32F002X Devices and CMSIS-CORE Puya PY32F002Z Devices and ARMCC Compiler Puya PY32F002Z Devices and CMSIS-CORE Puya PY32F003 Devices and ARMCC Compiler Puya PY32F003 Devices and CMSIS-CORE Puya PY32F005 Devices and ARMCC Compiler Puya PY32F005 Devices and CMSIS-CORE Puya PY32F006 Devices and ARMCC Compiler Puya PY32F006 Devices and CMSIS-CORE Puya PY32F020B Devices and ARMCC Compiler Puya PY32F020B Series Devices and CMSIS-CORE Puya PY32F021 Devices and ARMCC Compiler Puya PY32F021 Series Devices and CMSIS-CORE Puya PY32F030 Devices and ARMCC Compiler Puya PY32F030 Series Devices and CMSIS-CORE Puya PY32F031 Devices and ARMCC Compiler Puya PY32F031 Devices and CMSIS-CORE Puya PY32F032 Devices and ARMCC Compiler Puya PY32F032 Devices and CMSIS-CORE Puya PY32F033 Devices and ARMCC Compiler Puya PY32F033 Devices and CMSIS-CORE Puya PY32F040 Devices and ARMCC Compiler Puya PY32F040 Devices and CMSIS-CORE Puya PY32F040E Devices and ARMCC Compiler Puya PY32F040E Devices and CMSIS-CORE Puya PY32F071 Devices and ARMCC Compiler Puya PY32F071 Devices and CMSIS-CORE Puya PY32F071E Devices and ARMCC Compiler Puya PY32F071E Devices and CMSIS-CORE Puya PY32F072 Devices and ARMCC Compiler Puya PY32F072 Devices and CMSIS-CORE Puya PY32F072E Devices and ARMCC Compiler Puya PY32F072E Devices and CMSIS-CORE Puya PY32F090 Devices and ARMCC Compiler Puya PY32F090 Devices and CMSIS-CORE Puya PY32F092 Devices and ARMCC Compiler Puya PY32F092 Devices and CMSIS-CORE System Startup for Puya PY32F0 Series