Puya Puya PY32F092xx PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x0 0xFFFFFFFF ADC Analog to Digital Converter 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 ISR 0x0 ADRDY [0:0] EOSMP [1:1] EOC [2:2] EOS [3:3] OVR [4:4] JEOC [5:5] JEOS [6:6] AWD [7:7] EOCAL [11:11] IER 0x4 ADRDYIE [0:0] EOSMPIE [1:1] EOCIE [2:2] EOSIE [3:3] OVRIE [4:4] JEOCIE [5:5] JEOSIE [6:6] AWD1IE [7:7] EOCALIE [11:11] CR 0x8 ADEN [0:0] ADDIS [1:1] ADSTART [2:2] JADSTART [3:3] ADSTP [4:4] JADSTP [5:5] RSTCAL [27:27] ADCAL [31:31] CFGR 0xC DMAEN [0:0] DMACFG [1:1] RES [4:3] EXTSEL [8:5] EXTEN [11:10] OVRMOD [12:12] CONT [13:13] AUTDLY [14:14] ALIGN [15:15] DISCEN [16:16] DISCNUM [19:17] JDISCEN [20:20] AWDSGL [22:22] AWDEN [23:23] JAWDEN [24:24] JAUTO [25:25] AWDCH [30:26] CFGR2 0x10 ROVSE [0:0] JOVSE [1:1] OVSR [4:2] OVSS [8:5] TROVS [9:9] ROVSM [10:10] GCOMP [16:16] CALNUM [30:28] SMPR1 desc SMPR1 0x14 SMP0 [2:0] SMP1 [5:3] SMP2 [8:6] SMP3 [11:9] SMP4 [14:12] SMP5 [17:15] SMP6 [20:18] SMP7 [23:21] SMP8 [26:24] SMP9 [29:27] SMPR2 desc SMPR2 0x18 SMP10 [2:0] SMP11 [5:3] SMP12 [8:6] SMP13 [11:9] SMP14 [14:12] SMP15 [17:15] SMP16 [20:18] SMP17 [23:21] SMP18 [26:24] SMP19 [29:27] SMPR3 desc SMPR2 0x1C SMP20 [2:0] SMP21 [5:3] SMP22 [8:6] SMP23 [11:9] SMP24 [14:12] SMP25 [17:15] SMP26 [20:18] SMP27 [23:21] SMP28 [26:24] SMP29 [29:27] SMPR4 0x20 SMP30 [2:0] SMP31 [5:3] SMP32 [8:6] TR 0x24 LT [11:0] HT [27:16] SQR1 desc SQR1 0x30 L [3:0] SQ1 [11:6] SQ2 [17:12] SQ3 [23:18] SQ4 [29:24] SQR2 desc SQR2 0x34 SQ5 [5:0] SQ6 [11:6] SQ7 [17:12] SQ8 [23:18] SQ9 [29:24] SQR3 desc SQR3 0x38 SQ10 [5:0] SQ11 [11:6] SQ12 [17:12] SQ13 [23:18] SQ14 [29:24] SQR4 0x3C SQ15 [5:0] SQ16 [11:6] DR desc DR 0x40 RDATA [15:0] read-only JSQR desc JSQR 0x4C JL [1:0] JEXTSEL [5:2] JEXTEN [7:6] JSQ1 [13:8] JSQ2 [19:14] JSQ3 [25:20] JSQ4 [31:26] OFR1 0x60 OFFSET [11:0] OFFSETPOS [23:23] SATEN [24:24] OFFSET_CH [30:25] OFFSET_EN [31:31] OFR2 0x64 OFFSET [11:0] OFFSETPOS [23:23] SATEN [24:24] OFFSET_CH [30:25] OFFSET_EN [31:31] OFR3 0x68 OFFSET [11:0] OFFSETPOS [23:23] SATEN [24:24] OFFSET_CH [30:25] OFFSET_EN [31:31] OFR4 0x6C OFFSET [11:0] OFFSETPOS [23:23] SATEN [24:24] OFFSET_CH [30:25] OFFSET_EN [31:31] JDR1 desc JDR1 0x80 JDATA [15:0] read-only JDR2 desc JDR2 0x84 JDATA [15:0] read-only JDR3 desc JDR3 0x88 JDATA [15:0] read-only JDR4 desc JDR4 0x8C JDATA [15:0] read-only CALFACT 0xB4 OFFSUC [20:20] CAPSUC [21:21] GCOMP 0xC0 GCOMPCOEFF [13:0] CCR 0x308 CKMODE [17:16] PRESC [21:18] VREFENT_EN [22:22] TSEN [23:23] PWR_MODE [27:25] VSENSESEL [28:28] DIFF_EN [29:29] ADC_DBGSEL [31:30] BKP_TAMP 0x4000B000 0x0 0x180 registers TAMP_CR1 0x0 TAMP1EN TAMP enable [0:0] ITAMP1EN TAMPER pin interrupt enable [16:16] TAMP_CR2 0x4 TAMP1NOER TAMP not erase enable [0:0] TAMP1MSK TAMP enable [16:16] TAMP1TRG TAMPER pin interrupt enable [24:24] TAMP_FLTCR 0xC TAMPFREQ [2:0] RAMPFLT [4:3] TAMP_IER 0x2C TAMP1IE [0:0] ITAMP1IE [16:16] TAMP_SR 0x30 TAMP1IF [0:0] read-only ITAMP1F [16:16] read-only TAMP_MISR 0x34 TAMP1MF [0:0] read-only ITAMP1MF [16:16] read-only TAMP_SCR 0x3C CTAMP1F [0:0] write-only CITAMP1F [16:16] write-only TAMP_BKP0R 0x100 BKP bakeup data word0 [31:0] TAMP_BKP1R 0x104 BKP bakeup data word1 [31:0] TAMP_BKP2R 0x108 BKP bakeup data word2 [31:0] TAMP_BKP3R 0x10C BKP bakeup data word3 [31:0] TAMP_BKP4R 0x110 BKP bakeup data word4 [31:0] TAMP_BKP5R 0x114 BKP bakeup data word5 [31:0] TAMP_BKP6R 0x118 BKP bakeup data word6 [31:0] TAMP_BKP7R 0x11C BKP bakeup data word7 [31:0] COMP1 Comparator 1 COMP 0x40010200 0x0 0x8 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 COMP1_EN COMP enable bit [0:0] INMSEL Comparator signal selector for inverting input INM [4:2] INPSEL Comparator signal selector for non-inverting input [7:5] WINMODE Comparator non-inverting input selector for window mode [11:11] POLARITY Comparator polarity selector [15:15] HYST Comparator hysteresis enable selector [16:16] PWRMODE Comparator power mode selector [18:18] INT_OUT_SEL Comparator internal digital output control [29:29] COMP_OUT Comparator output status [30:30] LOCK Comparator CSR register lock [31:31] FR FR Comparator Filter register 0x4 FLTEN1 Filter enable bit [0:0] FLTCNT1 Comparator filter and counter [31:16] COMP2 Comparator2 COMP 0x40010210 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 EN COMP enable bit [0:0] HYST Comparator hysteresis enable selector [1:1] INMSEL Comparator signal selector for inverting input INM [5:2] INPSEL Comparator signal selector for non-inverting input [9:6] WINMODE Comparator non-inverting input selector for window mode [11:11] POLARITY Comparator polarity selector [15:15] PWRMODE Comparator power mode selector [19:18] COMP_OUT Comparator output status [30:30] FR FR Comparator Filter register 0x4 FLTEN2 Filter enable bit [0:0] FLTCNT2 Comparator filter and counter [31:16] COMP_COMMON Comparator COMP 0x40010208 0x0 0x4 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CCSR CCSR COMP control and status register 0x0 VREFCMP_EN VREFCMP enable bit [0:0] VCDIV COMP1,COMP2 voltage divider selection [6:1] SSEL VREFCMP Voltage Source Selection [7:7] CRC CRC calculation unit 0x40023000 0x0 0x400 registers DR Data register 0x0 DR CRC data [31:0] IDR Independent Data register 0x4 IDR CRC independent data [31:0] CR Control register 0x8 RESET CRC software reset [0:0] write-only POLYSIZE Polynomial size [4:3] REV_IN Reverse input data [6:5] REV_OUT Reverse output data [7:7] INIT 0x10 INIT initial value [31:0] POL 0x14 POL polynomial [31:0] DAC desc DAC 0x40007400 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR1 0x0 EN [0:0] BOFF [1:1] TEN [2:2] TSEL [5:3] WAVE [7:6] MAMP [11:8] DMAEN [12:12] DMAUDRIE [13:13] DACCEN [14:14] BUF_CAL [15:15] CR2 0x4 SWTRIG [0:0] write-only VREFSEL [1:1] INTEREN [2:2] DHR12R 0x8 DACDHR [11:0] DHR12L 0xC DACDHR [15:4] DHR8R 0x10 DACDHR [7:0] DOR 0x2C DACDOR [11:0] SR desc SR 0x34 DMAUDR [13:13] CALR 0x38 DAC_OS_TRIMCR_VCC [5:0] DAC_OS_TRIMCR_VREFBUF [11:6] DAC_DOUT [12:12] read-only DAC_CR [21:16] read-only DBG 0x40015800 0x0 0x10 registers IDCODE 0x0 REV_ID [31:0] read-only CR 0x4 DBG_SLEEP [0:0] DBG_STOP [1:1] DBG_STDBY [2:2] APB_FZ1 0x8 DBG_TIM2_STOP [0:0] DBG_TIM3_STOP [1:1] DBG_TIM6_STOP [4:4] DBG_TIM7_STOP [5:5] DBG_RTC_STOP [10:10] DBG_WWDG_STOP [11:11] DBG_IWDG_STOP [12:12] DBG_CAN_STOP [19:19] DBG_I2C1_STOP [21:21] DBG_I2C2_STOP [22:22] DBG_LPTIM2_STOP [30:30] DBG_LPTIM1_STOP [31:31] APB_FZ2 0xC DBG_TIM1_STOP [11:11] DBG_TIM15_STOP [16:16] DBG_TIM16_STOP [17:17] DBG_TIM17_STOP [18:18] DBG_PWM_STOP [19:19] DMA Direct memory access 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel 1 Interrupt 9 DMA1_Channel2_3 DMA1 Channel 2 and Channel 3 Interrupt 10 DMA1_Channel4_5_6_7 DMA1 Channel 4, 5, 6, 7 Interrupts 11 ISR desc ISR 0x0 TCIF1 Transfer Complete Flag for Channel 1 [0:0] read-only BTCIF1 Block Transfer Complete Flag for Channel 1 [1:1] read-only HBTIF1 Half Block Transfer Complete Flag for Channel 1 [2:2] read-only TEIF1 Transfer Error Flag for Channel 1 [3:3] read-only TCIF2 Transfer Complete Flag for Channel 2 [4:4] read-only BTCIF2 Block Transfer Complete Flag for Channel 2 [5:5] read-only HBTIF2 Half Block Transfer Complete Flag for Channel 2 [6:6] read-only TEIF2 Transfer Error Flag for Channel 2 [7:7] read-only TCIF3 Transfer Complete Flag for Channel 3 [8:8] read-only BTCIF3 Block Transfer Complete Flag for Channel 3 [9:9] read-only HBTIF3 Half Block Transfer Complete Flag for Channel 3 [10:10] read-only TEIF3 Transfer Error Flag for Channel 3 [11:11] read-only TCIF4 Transfer Complete Flag for Channel 4 [12:12] read-only BTCIF4 Block Transfer Complete Flag for Channel 4 [13:13] read-only HBTIF4 Half Block Transfer Complete Flag for Channel 4 [14:14] read-only TEIF4 Transfer Error Flag for Channel 4 [15:15] read-only TCIF5 Transfer Complete Flag for Channel 5 [16:16] read-only BTCIF5 Block Transfer Complete Flag for Channel 5 [17:17] read-only HBTIF5 Half Block Transfer Complete Flag for Channel 5 [18:18] read-only TEIF5 Transfer Error Flag for Channel 5 [19:19] read-only TCIF6 Transfer Complete Flag for Channel 6 [20:20] read-only BTCIF6 Block Transfer Complete Flag for Channel 6 [21:21] read-only HBTIF6 Half Block Transfer Complete Flag for Channel 6 [22:22] read-only TEIF6 Transfer Error Flag for Channel 6 [23:23] read-only TCIF7 Transfer Complete Flag for Channel 7 [24:24] read-only BTCIF7 Block Transfer Complete Flag for Channel 7 [25:25] read-only HBTIF7 Half Block Transfer Complete Flag for Channel 7 [26:26] read-only TEIF7 Transfer Error Flag for Channel 7 [27:27] read-only IFCR desc IFCR 0x4 CTCIF1 Transfer Complete Flag Clear for Channel 1 [0:0] write-only CBTCIF1 Block Transfer Complete Flag Clear for Channel 1 [1:1] write-only CHBTIF1 Half Block Transfer Complete Flag Clear for Channel 1 [2:2] write-only CTEIF1 Transfer Error Flag Clear for Channel 1 [3:3] write-only CTCIF2 Transfer Complete Flag Clear for Channel 2 [4:4] write-only CBTCIF2 Block Transfer Complete Flag Clear for Channel 2 [5:5] write-only CHBTIF2 Half Block Transfer Complete Flag Clear for Channel 2 [6:6] write-only CTEIF2 Transfer Error Flag Clear for Channel 2 [7:7] write-only CTCIF3 Transfer Complete Flag Clear for Channel 3 [8:8] write-only CBTCIF3 Block Transfer Complete Flag Clear for Channel 3 [9:9] write-only CHBTIF3 Half Block Transfer Complete Flag Clear for Channel 3 [10:10] write-only CTEIF3 Transfer Error Flag Clear for Channel 3 [11:11] write-only CTCIF4 Transfer Complete Flag Clear for Channel 4 [12:12] write-only CBTCIF4 Block Transfer Complete Flag Clear for Channel 4 [13:13] write-only CHBTIF4 Half Block Transfer Complete Flag Clear for Channel 4 [14:14] write-only CTEIF4 Transfer Error Flag Clear for Channel 4 [15:15] write-only CTCIF5 Transfer Complete Flag Clear for Channel 5 [16:16] write-only CBTCIF5 Block Transfer Complete Flag Clear for Channel 5 [17:17] write-only CHBTIF5 Half Block Transfer Complete Flag Clear for Channel 5 [18:18] write-only CTEIF5 Transfer Error Flag Clear for Channel 5 [19:19] write-only CTCIF6 Transfer Complete Flag Clear for Channel 6 [20:20] write-only CBTCIF6 Block Transfer Complete Flag Clear for Channel 6 [21:21] write-only CHBTIF6 Half Block Transfer Complete Flag Clear for Channel 6 [22:22] write-only CTEIF6 Transfer Error Flag Clear for Channel 6 [23:23] write-only CTCIF7 Transfer Complete Flag Clear for Channel 7 [24:24] write-only CBTCIF7 Block Transfer Complete Flag Clear for Channel 7 [25:25] write-only CHBTIF7 Half Block Transfer Complete Flag Clear for Channel 7 [26:26] write-only CTEIF7 Transfer Error Flag Clear for Channel 7 [27:27] write-only CCR1 desc CCR1 0x8 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR1 desc CNDTR1 0xC NDT Number of Data to Transfer [15:0] CPAR1 desc CPAR1 0x10 PA Peripheral Address [31:0] CMAR1 desc CMAR1 0x14 MA Memory Address [31:0] CCCFGR1 0x18 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR2 desc CCR2 0x1C EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR2 desc CNDTR2 0x20 NDT Number of Data to Transfer [15:0] CPAR2 desc CPAR2 0x24 PA Peripheral Address [31:0] CMAR2 desc CMAR2 0x28 MA Memory Address [31:0] CCCFGR2 0x2C NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR3 desc CCR3 0x30 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR3 desc CNDTR3 0x34 NDT Number of Data to Transfer [15:0] CPAR3 desc CPAR3 0x38 PA Peripheral Address [31:0] CMAR3 desc CMAR3 0x3C MA Memory Address [31:0] CCCFGR3 0x40 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR4 0x44 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR4 0x48 NDT Number of Data to Transfer [15:0] CPAR4 0x4C PA Peripheral Address [31:0] CMAR4 0x50 MA Memory Address [31:0] CCCFGR4 0x54 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR5 0x58 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR5 0x5C NDT Number of Data to Transfer [15:0] CPAR5 0x60 PA Peripheral Address [31:0] CMAR5 0x64 MA Memory Address [31:0] CCCFGR5 0x68 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR6 0x6C EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR6 0x70 NDT Number of Data to Transfer [15:0] CPAR6 0x74 PA Peripheral Address [31:0] CMAR6 0x78 MA Memory Address [31:0] CCCFGR6 0x7C NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] CCR7 0x80 EN Channel Enable [0:0] TCIE Transfer Complete Interrupt Enable [1:1] BTCIE Block Transfer Complete Interrupt Enable [2:2] HBTIE Half Block Transfer Complete Interrupt Enable [3:3] TEIE Transfer Error Interrupt Enable [4:4] DIR Data Transfer Direction [5:5] CIRC Circular Mode [6:6] TRANST Transfer Type [7:7] PINC Peripheral Increment Mode [9:8] MINC Memory Increment Mode [11:10] PSIZE Peripheral Size [13:12] MSIZE Memory Size [15:14] PL Priority Level [18:16] MEM2MEM Memory-to-memory Mode [19:19] PNORLD Peripheral No Reload [20:20] MNORLD Memory No Reload [21:21] BTCSUSP Suspend in Block Transfer Complete Interrupt [22:22] M2MARB Memory-to-memory Mode Arbitration [23:23] CNDTR7 0x84 NDT Number of Data to Transfer [15:0] CPAR7 0x88 PA Peripheral Address [31:0] CMAR7 0x8C MA Memory Address [31:0] CCCFGR7 0x90 NBT Number of Block to Loop Transfer [7:0] NDTL Number of Data to Transfer Last Loop [31:16] EXTI External interrupt/event controller 0x40010400 0x0 0x400 registers PVD PVD Interrupt through EXTI Lines 16 1 EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR EXTI rising trigger selection register 0x0 RT0 [0:0] RT1 [1:1] RT2 [2:2] RT3 [3:3] RT4 [4:4] RT5 [5:5] RT6 [6:6] RT7 [7:7] RT8 [8:8] RT9 [9:9] RT10 [10:10] RT11 [11:11] RT12 [12:12] RT13 [13:13] RT14 [14:14] RT15 [15:15] RT16 [16:16] RT17 [17:17] RT18 [18:18] RT19 [19:19] FTSR EXTI falling trigger selection register 0x4 FT0 [0:0] FT1 [1:1] FT2 [2:2] FT3 [3:3] FT4 [4:4] FT5 [5:5] FT6 [6:6] FT7 [7:7] FT8 [8:8] FT9 [9:9] FT10 [10:10] FT11 [11:11] FT12 [12:12] FT13 [13:13] FT14 [14:14] FT15 [15:15] FT16 [16:16] FT17 [17:17] FT18 [18:18] FT19 [19:19] SWIER EXTI software interrupt event register 0x8 SWIE0 [0:0] SWIE1 [1:1] SWIE2 [2:2] SWIE3 [3:3] SWIE4 [4:4] SWIE5 [5:5] SWIE6 [6:6] SWIE7 [7:7] SWIE8 [8:8] SWIE9 [9:9] SWIE10 [10:10] SWIE11 [11:11] SWIE12 [12:12] SWIE13 [13:13] SWIE14 [14:14] SWIE15 [15:15] SWIE16 [16:16] SWIE17 [17:17] SWIE18 [18:18] SWIE19 [19:19] PR EXTI pending register 0xC PR0 [0:0] PR1 [1:1] PR2 [2:2] PR3 [3:3] PR4 [4:4] PR5 [5:5] PR6 [6:6] PR7 [7:7] PR8 [8:8] PR9 [9:9] PR10 [10:10] PR11 [11:11] PR12 [12:12] PR13 [13:13] PR14 [14:14] PR15 [15:15] PR16 [16:16] PR17 [17:17] PR18 [18:18] PR19 [19:19] IOSEL1 0x10 EXTI0SEL [1:0] EXTI1SEL [5:4] EXTI2SEL [9:8] EXTI3SEL [13:12] EXTI4SEL [17:16] EXTI5SEL [21:20] EXTI6SEL [25:24] EXTI7SEL [29:28] IOSEL2 0x14 EXTI8SEL [1:0] EXTI9SEL [5:4] EXTI10SEL [9:8] EXTI11SEL [13:12] EXTI12SEL [17:16] EXTI13SEL [21:20] EXTI14SEL [25:24] EXTI15SEL [29:28] IMR EXTI CPU wakeup with interrupt mask register 0x18 IM0 [0:0] IM1 [1:1] IM2 [2:2] IM3 [3:3] IM4 [4:4] IM5 [5:5] IM6 [6:6] IM7 [7:7] IM8 [8:8] IM9 [9:9] IM10 [10:10] IM11 [11:11] IM12 [12:12] IM13 [13:13] IM14 [14:14] IM15 [15:15] IM16 [16:16] IM17 [17:17] IM18 [18:18] IM19 [19:19] IM20 [20:20] IM21 [21:21] IM22 [22:22] IM23 [23:23] IM24 [24:24] IM25 [25:25] IM26 [26:26] IM27 [27:27] IM28 [28:28] IM29 [29:29] EMR EXTI CPU wakeup with event mask register 0x1C EM0 [0:0] EM1 [1:1] EM2 [2:2] EM3 [3:3] EM4 [4:4] EM5 [5:5] EM6 [6:6] EM7 [7:7] EM8 [8:8] EM9 [9:9] EM10 [10:10] EM11 [11:11] EM12 [12:12] EM13 [13:13] EM14 [14:14] EM15 [15:15] EM16 [16:16] EM17 [17:17] EM18 [18:18] EM19 [19:19] EM20 [20:20] EM21 [21:21] EM22 [22:22] EM23 [23:23] EM24 [24:24] EM25 [25:25] EM26 [26:26] EM27 [27:27] EM28 [28:28] EM29 [29:29] FDCAN 0x40006400 0x0 0x100 registers ENDN 0x4 ETV Endian Register [31:0] read-only DBTP 0xC DSJW Data (Re)Synchronization Jump Width [3:0] DTSEG2 Data time segment after sample point [7:4] DTSEG1 Data time segment before sample point [12:8] DBRP Data Bit Rate Prescaler [20:16] TDC Transmitter Delay Compensation [23:23] TEST 0x10 LBCK Loop Back Mode [4:4] TX Control of Transmit Pin [6:5] RX Receive Pin [7:7] TXBNP Tx Buffer Number Prepared [12:8] PVAL Prepared Valid [13:13] TXBNS Tx Buffer Number Started [20:16] SVAL Started Valid [21:21] RWD 0x14 WDC Watchdog Configuration [7:0] WDV Watchdog Value [15:8] CCCR 0x18 INIT Initialization [0:0] CCE Configuration Change Enable [1:1] ASM Restricted Operation Mode [2:2] CSA Clock Stop Acknowledge [3:3] CSR Clock Stop Request [4:4] MON Bus Monitoring Mode [5:5] DAR Disable Automatic Retransmission [6:6] TEST Test Mode Enable [7:7] FDOE FD Operation Enable [8:8] BRSE Bit Rate Switch Enable [9:9] WMM Wide Message Marker [11:11] PXHD Protocol Exception Handling Disable [12:12] EFBI Edge Filtering during Bus Integration [13:13] TXP Transmit Pause [14:14] NISO Non ISO Operation [15:15] NBTP 0x1C NTSEG2 Nominal Time segment after sample point [6:0] NTSEG1 Nominal Time segment before sample point [15:8] NBRP Nominal Bit Rate Prescaler [24:16] NSJW Nominal (Re)Synchronization Jump Width [31:25] TSCC 0x20 TSS Timestamp Select [1:0] read-only TCP Timestamp Counter Prescaler [19:16] TSCV 0x24 TSC Timestamp Counter [15:0] TOCC 0x28 ETOC Enable Timeout Counter [0:0] TOS Timeout Select [2:1] TOP Timeout Period [31:16] TOCV 0x2C TOC Timeout Counter [15:0] ECR 0x40 TEC Transmit Error Counter [7:0] read-only REC Receive Error Counter [14:8] read-only RP Receive Error Passive [15:15] read-only CEL CAN Error Logging [23:16] read-only PSR 0x44 LEC Last Error Code [2:0] read-only ACT Activity [4:3] read-only EP Error Passive [5:5] read-only EW Warning Status [6:6] read-only BO Bus_Off Status [7:7] read-only DLEC Data Phase Last Error Code [10:8] read-only RESI ESI flag of last received CAN FD Message [11:11] read-only RBRS BRS flag of last received CAN FD Message [12:12] read-only RFDF Received a CAN FD Message [13:13] read-only PXE Protocol Exception Event [14:14] read-only TDCV Transmitter Delay Compensation Value [22:16] read-only TDCR 0x48 TDCF Transmitter Delay Compensation Filter Window Length [6:0] TDCO Transmitter Delay Compensation SSP Offset [14:8] IR 0x50 RF0N Rx FIFO 0 New Message [0:0] RF0W Rx FIFO 0 Watermark Reached [1:1] RF0F Rx FIFO 0 Full [2:2] RF0L Rx FIFO 0 Message Lost [3:3] RF1N Rx FIFO 1 New Message [4:4] RF1W Rx FIFO 1 Watermark Reached [5:5] RF1F Rx FIFO 1 Full [6:6] RF1L Rx FIFO 1 Message Lost [7:7] HPM High Priority Message [8:8] TC Transmission Completed [9:9] TCF Transmission Cancellation Finished [10:10] TFE Tx FIFO Empty [11:11] TEFN Tx Event FIFO New Entry [12:12] TEFW Tx Event FIFO Watermark Reached [13:13] TEFF Tx Event FIFO Full [14:14] TEFL Tx Event FIFO Element Lost [15:15] TSW Timestamp Wraparound [16:16] MRAF Message RAM Access Failure [17:17] TOO Timeout Occurred [18:18] DRX Message stored to Dedicated Rx Buffer [19:19] BEC Bit Error Corrected [20:20] BEU Bit Error Uncorrected [21:21] ELO Error Logging Overflow [22:22] EP Error Passive [23:23] EW Warning Status [24:24] BO Bus_Off Status [25:25] WDI Watchdog Interrupt [26:26] PEA Protocol Error in Arbitration Phase [27:27] PED Protocol Error in Data Phase (Data Bit Time is used) [28:28] ARA Access to Reserved Address [29:29] IE 0x54 RF0NE Rx FIFO 1 New Message Interrupt Enable [0:0] RF0WE Rx FIFO 1 Watermark Reached Interrupt Enable [1:1] RF0FE Rx FIFO 1 Full Interrupt Enable [2:2] RF0LE Rx FIFO 1 Message Lost Interrupt Enable [3:3] RF1NE Rx FIFO 2 New Message Interrupt Enable [4:4] RF1WE Rx FIFO 2 Watermark Reached Interrupt Enable [5:5] RF1FE Rx FIFO 2 Full Interrupt Enable [6:6] RF1LE Rx FIFO 2 Message Lost Interrupt Enable [7:7] HPME High Priority Message Interrupt Enable [8:8] TCE Transmission Completed Interrupt Enable [9:9] TCFE Transmission Cancellation Finished Interrupt Enable [10:10] TFEE Tx FIFO Empty Interrupt Enable [11:11] TEFNE Tx Event FIFO New Entry Interrupt Enable [12:12] TEFWE Tx Event FIFO Watermark Reached Interrupt Enable [13:13] TEFFE Tx Event FIFO Full Interrupt Enable [14:14] TEFLE Tx Event FIFO Event Lost Interrupt Enable [15:15] TSWE Timestamp Wraparound Interrupt Enable [16:16] MRAFE Message RAM Access Failure Interrupt Enable [17:17] TOOE Timeout Occurred Interrupt Enable [18:18] DRXE Message stored to Dedicated Rx Buffer Interrupt Enable [19:19] BECE Bit Error Corrected Interrupt Enable [20:20] BEUE Bit Error Uncorrected Interrupt Enable [21:21] ELOE Error Logging Overflow Interrupt Enable [22:22] EPE Error Passive Interrupt Enable [23:23] EWE Warning Status Interrupt Enable [24:24] BOE Bus_Off Status Interrupt Enable [25:25] WDIE Watchdog Interrupt Enable [26:26] PEAE Protocol Error in Arbitration Phase Enable [27:27] PEDE Protocol Error in Data Phase Enable [28:28] ARAE Access to Reserved Address Enable [29:29] ILS 0x58 RF0NL Rx FIFO 1 New Message Interrupt Line [0:0] RF0WL Rx FIFO 1 Watermark Reached Interrupt Line [1:1] RF0FL Rx FIFO 1 Full Interrupt Line [2:2] RF0LL Rx FIFO 1 Message Lost Interrupt Line [3:3] RF1NL Rx FIFO 2 New Message Interrupt Line [4:4] RF1WL Rx FIFO 2 Watermark Reached Interrupt Line [5:5] RF1FL Rx FIFO 2 Full Interrupt Line [6:6] RF1LL Rx FIFO 2 Message Lost Interrupt Line [7:7] HPML High Priority Message Interrupt Line [8:8] TCL Transmission Completed Interrupt Line [9:9] TCFL Transmission Cancellation Finished Interrupt Line [10:10] TFEL Tx FIFO Empty Interrupt Line [11:11] TEFNL Tx Event FIFO New Entry Interrupt Line [12:12] TEFWL Tx Event FIFO Watermark Reached Interrupt Line [13:13] TEFFL Tx Event FIFO Full Interrupt Line [14:14] TEFLL Tx Event FIFO Event Lost Interrupt Line [15:15] TSWL Timestamp Wraparound Interrupt Line [16:16] MRAFL Message RAM Access Failure Interrupt Line [17:17] TOOL Timeout Occurred Interrupt Line [18:18] DRXL Message stored to Dedicated Rx Buffer Interrupt Line [19:19] BECL Bit Error Corrected Interrupt Line [20:20] BEUL Bit Error Uncorrected Interrupt Line [21:21] ELOL Error Logging Overflow Interrupt Line [22:22] EPL Error Passive Interrupt Line [23:23] EWL Warning Status Interrupt Line [24:24] BOL Bus_Off Status Interrupt Line [25:25] WDIL Watchdog Interrupt Line [26:26] PEAL Protocol Error in Arbitration Phase Line [27:27] PEDL Protocol Error in Data Phase Line [28:28] ARAL Access to Reserved Address Line [29:29] ILE 0x5C EINT0 Enable Interrupt Line 0 [0:0] EINT1 Enable Interrupt Line 1 [1:1] GFC 0x80 RRFE Reject Remote Frames Extended [0:0] RRFS Reject Remote Frames Standard [1:1] ANFE Accept Non-matching Frames Extended [3:2] ANFS Accept Non-matching Frames Standard [5:4] SIDFC 0x84 FLSSA Filter List Standard Start Address [15:2] LSS List Size Standard [23:16] XIDFC 0x88 FLESA Filter List Extended Start Address [15:2] LSE List Size Extended [22:16] XIDAM 0x90 EIDM Extended ID Mask [28:0] HPMS 0x94 BIDX Buffer Index [5:0] read-only MSI Message Storage Indicator [7:6] read-only FIDX Filter Index [14:8] read-only FLST Filter List [15:15] read-only NDAT1 0x98 ND0 New Data0 [0:0] ND1 New Data1 [1:1] ND2 New Data2 [2:2] ND3 New Data3 [3:3] ND4 New Data4 [4:4] ND5 New Data5 [5:5] ND6 New Data6 [6:6] ND7 New Data7 [7:7] ND8 New Data8 [8:8] ND9 New Data9 [9:9] ND10 New Data10 [10:10] ND11 New Data11 [11:11] ND12 New Data12 [12:12] ND13 New Data13 [13:13] ND14 New Data14 [14:14] ND15 New Data15 [15:15] ND16 New Data16 [16:16] ND17 New Data17 [17:17] ND18 New Data18 [18:18] ND19 New Data19 [19:19] ND20 New Data20 [20:20] ND21 New Data21 [21:21] ND22 New Data22 [22:22] ND23 New Data23 [23:23] ND24 New Data24 [24:24] ND25 New Data25 [25:25] ND26 New Data26 [26:26] ND27 New Data27 [27:27] ND28 New Data28 [28:28] ND29 New Data29 [29:29] ND30 New Data30 [30:30] ND31 New Data31 [31:31] NDAT2 0x9C ND32 New Data32 [0:0] ND33 New Data33 [1:1] ND34 New Data34 [2:2] ND35 New Data35 [3:3] ND36 New Data36 [4:4] ND37 New Data37 [5:5] ND38 New Data38 [6:6] ND39 New Data39 [7:7] ND40 New Data40 [8:8] ND41 New Data41 [9:9] ND42 New Data42 [10:10] ND43 New Data43 [11:11] ND44 New Data44 [12:12] ND45 New Data45 [13:13] ND46 New Data46 [14:14] ND47 New Data47 [15:15] ND48 New Data48 [16:16] ND49 New Data49 [17:17] ND50 New Data50 [18:18] ND51 New Data51 [19:19] ND52 New Data52 [20:20] ND53 New Data53 [21:21] ND54 New Data54 [22:22] ND55 New Data55 [23:23] ND56 New Data56 [24:24] ND57 New Data57 [25:25] ND58 New Data58 [26:26] ND59 New Data59 [27:27] ND60 New Data60 [28:28] ND61 New Data61 [29:29] ND62 New Data62 [30:30] ND63 New Data63 [31:31] RXF0C 0xA0 F0SA Rx FIFO 0 Start Address [15:2] F0S Rx FIFO 0 Size [22:16] F0WM Rx FIFO 0 Watermark [30:24] F0OM FIFO 0 Operation Mode [31:31] RXF0S 0xA4 F0FL Rx FIFO 0 Fill Level [6:0] read-only F0GI Rx FIFO 0 Get Index [13:8] read-only F0PI Rx FIFO 0 Put Index [21:16] read-only F0F Rx FIFO 0 Full [24:24] read-only RF0L Rx FIFO 0 Message Lost [25:25] read-only RXF0A 0xA8 F0AI Rx FIFO 0 Acknowledge Index [5:0] RXBC 0xAC RBSA Rx Buffer Start Address [15:2] RXF1C 0xB0 F1SA Rx FIFO 1 Start Address [15:2] F1S Rx FIFO 1 Size [22:16] F1WM Rx FIFO 1 Watermark [30:24] F1OM FIFO 1 Operation Mode [31:31] RXF1S 0xB4 F1FL Rx FIFO 1 Fill Level [6:0] read-only F1GI Rx FIFO 1 Get Index [13:8] read-only F1PI Rx FIFO 1 Put Index [21:16] read-only F1F Rx FIFO 1 Full [24:24] read-only RF1L Rx FIFO 1 Message Lost [25:25] read-only DMS Debug Message Status [31:30] read-only RXF1A 0xB8 F1AI Rx FIFO 1 Acknowledge Index [5:0] RXESC 0xBC F0DS Rx FIFO 0 Data Field Size [2:0] F1DS Rx FIFO 1 Data Field Size [6:4] RBDS Rx Buffer Data Field Size [10:8] TXBC 0xC0 TBSA Tx Buffers Start Address [15:2] NDTB Number of Dedicated Transmit Buffers [21:16] TFQS Transmit FIFO/Queue Size [29:24] TFQM Tx FIFO/Queue Mode [30:30] TXFQS 0xC4 TFFL Tx FIFO Free Level [5:0] read-only TFGI Tx FIFO Get Index [12:8] read-only TFQPI Tx FIFO/Queue Put Index [20:16] read-only TFQF Tx FIFO/Queue Full [21:21] read-only TXESC 0xC8 TBDS Tx Buffer Data Field Size [2:0] TXBRP 0xCC TRP0 Transmission Request Pending [0:0] read-only TRP1 Transmission Request Pending [1:1] read-only TRP2 Transmission Request Pending [2:2] read-only TRP3 Transmission Request Pending [3:3] read-only TRP4 Transmission Request Pending [4:4] read-only TRP5 Transmission Request Pending [5:5] read-only TRP6 Transmission Request Pending [6:6] read-only TRP7 Transmission Request Pending [7:7] read-only TRP8 Transmission Request Pending [8:8] read-only TRP9 Transmission Request Pending [9:9] read-only TRP10 Transmission Request Pending [10:10] read-only TRP11 Transmission Request Pending [11:11] read-only TRP12 Transmission Request Pending [12:12] read-only TRP13 Transmission Request Pending [13:13] read-only TRP14 Transmission Request Pending [14:14] read-only TRP15 Transmission Request Pending [15:15] read-only TRP16 Transmission Request Pending [16:16] read-only TRP17 Transmission Request Pending [17:17] read-only TRP18 Transmission Request Pending [18:18] read-only TRP19 Transmission Request Pending [19:19] read-only TRP20 Transmission Request Pending [20:20] read-only TRP21 Transmission Request Pending [21:21] read-only TRP22 Transmission Request Pending [22:22] read-only TRP23 Transmission Request Pending [23:23] read-only TRP24 Transmission Request Pending [24:24] read-only TRP25 Transmission Request Pending [25:25] read-only TRP26 Transmission Request Pending [26:26] read-only TRP27 Transmission Request Pending [27:27] read-only TRP28 Transmission Request Pending [28:28] read-only TRP29 Transmission Request Pending [29:29] read-only TRP30 Transmission Request Pending [30:30] read-only TRP31 Transmission Request Pending [31:31] read-only TXBAR 0xD0 AR0 Add Request [0:0] AR1 Add Request [1:1] AR2 Add Request [2:2] AR3 Add Request [3:3] AR4 Add Request [4:4] AR5 Add Request [5:5] AR6 Add Request [6:6] AR7 Add Request [7:7] AR8 Add Request [8:8] AR9 Add Request [9:9] AR10 Add Request [10:10] AR11 Add Request [11:11] AR12 Add Request [12:12] AR13 Add Request [13:13] AR14 Add Request [14:14] AR15 Add Request [15:15] AR16 Add Request [16:16] AR17 Add Request [17:17] AR18 Add Request [18:18] AR19 Add Request [19:19] AR20 Add Request [20:20] AR21 Add Request [21:21] AR22 Add Request [22:22] AR23 Add Request [23:23] AR24 Add Request [24:24] AR25 Add Request [25:25] AR26 Add Request [26:26] AR27 Add Request [27:27] AR28 Add Request [28:28] AR29 Add Request [29:29] AR30 Add Request [30:30] AR31 Add Request [31:31] TXBCR 0xD4 CR0 Cancellation Request [0:0] CR1 Cancellation Request [1:1] CR2 Cancellation Request [2:2] CR3 Cancellation Request [3:3] CR4 Cancellation Request [4:4] CR5 Cancellation Request [5:5] CR6 Cancellation Request [6:6] CR7 Cancellation Request [7:7] CR8 Cancellation Request [8:8] CR9 Cancellation Request [9:9] CR10 Cancellation Request [10:10] CR11 Cancellation Request [11:11] CR12 Cancellation Request [12:12] CR13 Cancellation Request [13:13] CR14 Cancellation Request [14:14] CR15 Cancellation Request [15:15] CR16 Cancellation Request [16:16] CR17 Cancellation Request [17:17] CR18 Cancellation Request [18:18] CR19 Cancellation Request [19:19] CR20 Cancellation Request [20:20] CR21 Cancellation Request [21:21] CR22 Cancellation Request [22:22] CR23 Cancellation Request [23:23] CR24 Cancellation Request [24:24] CR25 Cancellation Request [25:25] CR26 Cancellation Request [26:26] CR27 Cancellation Request [27:27] CR28 Cancellation Request [28:28] CR29 Cancellation Request [29:29] CR30 Cancellation Request [30:30] CR31 Cancellation Request [31:31] TXBTO 0xD8 TO0 Transmission Occurred [0:0] read-only TO1 Transmission Occurred [1:1] read-only TO2 Transmission Occurred [2:2] read-only TO3 Transmission Occurred [3:3] read-only TO4 Transmission Occurred [4:4] read-only TO5 Transmission Occurred [5:5] read-only TO6 Transmission Occurred [6:6] read-only TO7 Transmission Occurred [7:7] read-only TO8 Transmission Occurred [8:8] read-only TO9 Transmission Occurred [9:9] read-only TO10 Transmission Occurred [10:10] read-only TO11 Transmission Occurred [11:11] read-only TO12 Transmission Occurred [12:12] read-only TO13 Transmission Occurred [13:13] read-only TO14 Transmission Occurred [14:14] read-only TO15 Transmission Occurred [15:15] read-only TO16 Transmission Occurred [16:16] read-only TO17 Transmission Occurred [17:17] read-only TO18 Transmission Occurred [18:18] read-only TO19 Transmission Occurred [19:19] read-only TO20 Transmission Occurred [20:20] read-only TO21 Transmission Occurred [21:21] read-only TO22 Transmission Occurred [22:22] read-only TO23 Transmission Occurred [23:23] read-only TO24 Transmission Occurred [24:24] read-only TO25 Transmission Occurred [25:25] read-only TO26 Transmission Occurred [26:26] read-only TO27 Transmission Occurred [27:27] read-only TO28 Transmission Occurred [28:28] read-only TO29 Transmission Occurred [29:29] read-only TO30 Transmission Occurred [30:30] read-only TO31 Transmission Occurred [31:31] read-only TXBCF 0xDC CF0 Cancellation Finished [0:0] read-only CF1 Cancellation Finished [1:1] read-only CF2 Cancellation Finished [2:2] read-only CF3 Cancellation Finished [3:3] read-only CF4 Cancellation Finished [4:4] read-only CF5 Cancellation Finished [5:5] read-only CF6 Cancellation Finished [6:6] read-only CF7 Cancellation Finished [7:7] read-only CF8 Cancellation Finished [8:8] read-only CF9 Cancellation Finished [9:9] read-only CF10 Cancellation Finished [10:10] read-only CF11 Cancellation Finished [11:11] read-only CF12 Cancellation Finished [12:12] read-only CF13 Cancellation Finished [13:13] read-only CF14 Cancellation Finished [14:14] read-only CF15 Cancellation Finished [15:15] read-only CF16 Cancellation Finished [16:16] read-only CF17 Cancellation Finished [17:17] read-only CF18 Cancellation Finished [18:18] read-only CF19 Cancellation Finished [19:19] read-only CF20 Cancellation Finished [20:20] read-only CF21 Cancellation Finished [21:21] read-only CF22 Cancellation Finished [22:22] read-only CF23 Cancellation Finished [23:23] read-only CF24 Cancellation Finished [24:24] read-only CF25 Cancellation Finished [25:25] read-only CF26 Cancellation Finished [26:26] read-only CF27 Cancellation Finished [27:27] read-only CF28 Cancellation Finished [28:28] read-only CF29 Cancellation Finished [29:29] read-only CF30 Cancellation Finished [30:30] read-only CF31 Cancellation Finished [31:31] read-only TXBTIE 0xE0 TIE0 Transmission Interrupt Enable [0:0] TIE1 Transmission Interrupt Enable [1:1] TIE2 Transmission Interrupt Enable [2:2] TIE3 Transmission Interrupt Enable [3:3] TIE4 Transmission Interrupt Enable [4:4] TIE5 Transmission Interrupt Enable [5:5] TIE6 Transmission Interrupt Enable [6:6] TIE7 Transmission Interrupt Enable [7:7] TIE8 Transmission Interrupt Enable [8:8] TIE9 Transmission Interrupt Enable [9:9] TIE10 Transmission Interrupt Enable [10:10] TIE11 Transmission Interrupt Enable [11:11] TIE12 Transmission Interrupt Enable [12:12] TIE13 Transmission Interrupt Enable [13:13] TIE14 Transmission Interrupt Enable [14:14] TIE15 Transmission Interrupt Enable [15:15] TIE16 Transmission Interrupt Enable [16:16] TIE17 Transmission Interrupt Enable [17:17] TIE18 Transmission Interrupt Enable [18:18] TIE19 Transmission Interrupt Enable [19:19] TIE20 Transmission Interrupt Enable [20:20] TIE21 Transmission Interrupt Enable [21:21] TIE22 Transmission Interrupt Enable [22:22] TIE23 Transmission Interrupt Enable [23:23] TIE24 Transmission Interrupt Enable [24:24] TIE25 Transmission Interrupt Enable [25:25] TIE26 Transmission Interrupt Enable [26:26] TIE27 Transmission Interrupt Enable [27:27] TIE28 Transmission Interrupt Enable [28:28] TIE29 Transmission Interrupt Enable [29:29] TIE30 Transmission Interrupt Enable [30:30] TIE31 Transmission Interrupt Enable [31:31] TXBCIE 0xE4 CFIE0 Cancellation Finished Interrupt Enable [0:0] CFIE1 Cancellation Finished Interrupt Enable [1:1] CFIE2 Cancellation Finished Interrupt Enable [2:2] CFIE3 Cancellation Finished Interrupt Enable [3:3] CFIE4 Cancellation Finished Interrupt Enable [4:4] CFIE5 Cancellation Finished Interrupt Enable [5:5] CFIE6 Cancellation Finished Interrupt Enable [6:6] CFIE7 Cancellation Finished Interrupt Enable [7:7] CFIE8 Cancellation Finished Interrupt Enable [8:8] CFIE9 Cancellation Finished Interrupt Enable [9:9] CFIE10 Cancellation Finished Interrupt Enable [10:10] CFIE11 Cancellation Finished Interrupt Enable [11:11] CFIE12 Cancellation Finished Interrupt Enable [12:12] CFIE13 Cancellation Finished Interrupt Enable [13:13] CFIE14 Cancellation Finished Interrupt Enable [14:14] CFIE15 Cancellation Finished Interrupt Enable [15:15] CFIE16 Cancellation Finished Interrupt Enable [16:16] CFIE17 Cancellation Finished Interrupt Enable [17:17] CFIE18 Cancellation Finished Interrupt Enable [18:18] CFIE19 Cancellation Finished Interrupt Enable [19:19] CFIE20 Cancellation Finished Interrupt Enable [20:20] CFIE21 Cancellation Finished Interrupt Enable [21:21] CFIE22 Cancellation Finished Interrupt Enable [22:22] CFIE23 Cancellation Finished Interrupt Enable [23:23] CFIE24 Cancellation Finished Interrupt Enable [24:24] CFIE25 Cancellation Finished Interrupt Enable [25:25] CFIE26 Cancellation Finished Interrupt Enable [26:26] CFIE27 Cancellation Finished Interrupt Enable [27:27] CFIE28 Cancellation Finished Interrupt Enable [28:28] CFIE29 Cancellation Finished Interrupt Enable [29:29] CFIE30 Cancellation Finished Interrupt Enable [30:30] CFIE31 Cancellation Finished Interrupt Enable [31:31] TXEFC 0xF0 EFSA Event FIFO Start Address [15:2] EFS Event FIFO Size [21:16] EFWM Event FIFO Watermark [29:24] TXEFS 0xF4 EFFL Event FIFO Fill Level [5:0] read-only EFGI Event FIFO Get Index [12:8] read-only EFPI Event FIFO Put Index [20:16] read-only EFF Event FIFO Full [24:24] read-only TEFL Tx Event FIFO Element Lost [25:25] read-only TXEFA 0xF8 EFAI Event FIFO Acknowledge Index [4:0] FLASH desc FLASH 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR desc ACR 0x0 LATENCY Latency [1:0] PRFTEN Prefect enable [8:8] ICEN Instruction cache enable [9:9] DCEN Data cache enable [10:10] KEYR desc KEYR 0x8 KEY Flash CR key [31:0] write-only OPTKEYR desc OPTKEYR 0xC OPTKEY Flash Option key [31:0] write-only SR desc SR 0x10 EOP End of operation [0:0] WRPERR Write protection error [4:4] RDERR0 Bank0 pcrop read error [11:11] RDERR1 Bank1 pcrop read error [12:12] USRLOCK Userdata Lock [13:13] read-only OPTVERR Option and trimming bits loading validity error [15:15] BSY0 Bank0 Busy [16:16] read-only BSY1 Bank1 Busy [17:17] read-only CR desc CR 0x14 PG Page Program [0:0] PER Page Erase [1:1] MER0 Bank 0 Mass Erase [2:2] MER1 Bank 1 Mass Erase [3:3] UPG Userdata Program [4:4] UPER Userdata Page Erase [5:5] SER Sector Erase [11:11] OPTSTRT Option bytes Programming Start [17:17] UPGSTRT Userdata Programming Start [18:18] PGSTRT Programming Start [19:19] RDERR0IE Bank0 pcrop read error interrupt enable [22:22] RDERR1IE Bank1 pcrop read error interrupt enable [23:23] EOPIE End of operation interrupt enable [24:24] ERRIE Error interrupt enable [25:25] OBL_LAUNCH Force the option bytes loading [27:27] OPTLOCK Option Lock [30:30] LOCK Lock [31:31] ECCR 0x18 ADDR_ECC ECC fail address [16:0] read-only BK_ECC ECC fail bank [21:21] read-only SYSF_ECC System Flash ECC fail [22:22] read-only ECCCIE ECC correction interrupt enable [24:24] ECCC ECC correction [30:30] ECCD ECC detection [31:31] OPTR desc OPTR 0x20 RDP Read Protection [7:0] NRST_STANDBY nrst standby [8:8] NRST_STOP nrst stop [9:9] IWDG_STDBY IWDG Standy Count Control [10:10] IWDG_STOP IWDG Stop Count Control [11:11] IWDG_SW IWDG Software Enable [12:12] WWDG_SW WWDG Software Enable [13:13] NRST_MODE nrst mode [14:14] NBOOT1 nboot1 [15:15] BOR_EN BOR enable [16:16] BOR_LEV BOR Level [19:17] SRAM_PE sram parity enable [20:20] SWD_MODE SWD mode [22:21] BFB Boot Flash Bank [23:23] BOOT_LOCK Boot Lock [24:24] ECC_EN ECC enable [25:25] WRPR desc WRPR 0x28 BK0_WRPX Bank0 Sector Write Protection [15:0] BK1_WRPX Bank1 Sector Write Protection [31:16] PCROPR0 0x30 PCROP0SR Bank0 pcrop start address [8:0] PCROP0ER Bank0 pcrop end address [24:16] PCROPR1 0x34 PCROP1SR Bank1 pcrop start address [8:0] PCROP1ER Bank1 pcrop end address [24:16] LPCR 0x90 SLEEP_EN Sleep enable [0:0] SLEEP_TIME Sleep time [15:8] LPRUN_ENTERT Low power run mode enter time [18:16] LPRUN_EXITT Low power run mode exit time [22:20] TS0 desc TS0 0x100 TS0 TS0 [8:0] TS1 desc TS1 0x104 TS1 TS1 [10:0] TS2P desc TS2P 0x108 TS2P TS2P [8:0] TPS3 desc TPS3 0x10C TPS3 TPS3 [12:0] TS3 desc TS3 0x110 TS3 TS3 [8:0] PERTPE desc PERTPE 0x114 PERTPE PERTPE [17:0] SMERTPE desc SMERTPE 0x118 SMERTPE SMERTPE [17:0] PRGTPE desc PRGTPE 0x11C PRGTPE PRGTPE [15:0] PRETPE desc PRETPE 0x120 PRETPE PRETPE [13:0] TACLK2PW 0x124 TACLK2PW TACLK2PW [7:0] GPIOA General-purpose I/Os 0x50000000 0x0 0x400 registers MODER GPIO port mode register 0x0 MODER0 GPIOA0 MODE [1:0] MODER1 GPIOA1 MODE [3:2] MODER2 GPIOA2 MODE [5:4] MODER3 GPIOA3 MODE [7:6] MODER4 GPIOA4 MODE [9:8] MODER5 GPIOA5 MODE [11:10] MODER6 GPIOA6 MODE [13:12] MODER7 GPIOA7 MODE [15:14] MODER8 GPIOA8 MODE [17:16] MODER9 GPIOA9 MODE [19:18] MODER10 GPIOA10 MODE [21:20] MODER11 GPIOA11 MODE [23:22] MODER12 GPIOA12 MODE [25:24] MODER13 GPIOA13 MODE [27:26] MODER14 GPIOA14 MODE [29:28] MODER15 GPIOA15 MODE [31:30] OTYPER GPIO port output type register 0x4 OT0 GPIOA0 Output type [0:0] OT1 GPIOA1 Output type [1:1] OT2 GPIOA2 Output type [2:2] OT3 GPIOA3 Output type [3:3] OT4 GPIOA4 Output type [4:4] OT5 GPIOA5 Output type [5:5] OT6 GPIOA6 Output type [6:6] OT7 GPIOA7 Output type [7:7] OT8 GPIOA8 Output type [8:8] OT9 GPIOA9 Output type [9:9] OT10 GPIOA10 Output type [10:10] OT11 GPIOA11 Output type [11:11] OT12 GPIOA12 Output type [12:12] OT13 GPIOA13 Output type [13:13] OT14 GPIOA14 Output type [14:14] OT15 GPIOA15 Output type [15:15] OSPDDER 0x8 OSPEED0 GPIOA0 output speed [1:0] OSPEED1 GPIOA1 output speed [3:2] OSPEED2 GPIOA2 output speed [5:4] OSPEED3 GPIOA3 output speed [7:6] OSPEED4 GPIOA4 output speed [9:8] OSPEED5 GPIOA5 output speed [11:10] OSPEED6 GPIOA6 output speed [13:12] OSPEED7 GPIOA7 output speed [15:14] OSPEED8 GPIOA8 output speed [17:16] OSPEED9 GPIOA9 output speed [19:18] OSPEED10 GPIOA10 output speed [21:20] OSPEED11 GPIOA11 output speed [23:22] OSPEED12 GPIOA12 output speed [25:24] OSPEED13 GPIOA13 output speed [27:26] OSPEED14 GPIOA14 output speed [29:28] OSPEED15 GPIOA15 output speed [31:30] PUPDR GPIO port pull-up/pull-down register 0xC PUPD0 GPIOA0 pull up/pull down [1:0] PUPD1 GPIOA1 pull up/pull down [3:2] PUPD2 GPIOA2 pull up/pull down [5:4] PUPD3 GPIOA3 pull up/pull down [7:6] PUPD4 GPIOA4 pull up/pull down [9:8] PUPD5 GPIOA5 pull up/pull down [11:10] PUPD6 GPIOA6 pull up/pull down [13:12] PUPD7 GPIOA7 pull up/pull down [15:14] PUPD8 GPIOA8 pull up/pull down [17:16] PUPD9 GPIOA9 pull up/pull down [19:18] PUPD10 GPIOA10 pull up/pull down [21:20] PUPD11 GPIOA11 pull up/pull down [23:22] PUPD12 GPIOA12 pull up/pull down [25:24] PUPD13 GPIOA13 pull up/pull down [27:26] PUPD14 GPIOA14 pull up/pull down [29:28] PUPD15 GPIOA15 pull up/pull down [31:30] IDR GPIO port input data register 0x10 ID0 GPIOA0 input data [0:0] read-only ID1 GPIOA1 input data [1:1] read-only ID2 GPIOA2 input data [2:2] read-only ID3 GPIOA3 input data [3:3] read-only ID4 GPIOA4 input data [4:4] read-only ID5 GPIOA5 input data [5:5] read-only ID6 GPIOA6 input data [6:6] read-only ID7 GPIOA7 input data [7:7] read-only ID8 GPIOA8 input data [8:8] read-only ID9 GPIOA9 input data [9:9] read-only ID10 GPIOA10 input data [10:10] read-only ID11 GPIOA11 input data [11:11] read-only ID12 GPIOA12 input data [12:12] read-only ID13 GPIOA13 input data [13:13] read-only ID14 GPIOA14 input data [14:14] read-only ID15 GPIOA15 input data [15:15] read-only ODR GPIO port output data register 0x14 OD0 GPIOA0 output data [0:0] OD1 GPIOA1 output data [1:1] OD2 GPIOA2 output data [2:2] OD3 GPIOA3 output data [3:3] OD4 GPIOA4 output data [4:4] OD5 GPIOA5 output data [5:5] OD6 GPIOA6 output data [6:6] OD7 GPIOA7 output data [7:7] OD8 GPIOA8 output data [8:8] OD9 GPIOA9 output data [9:9] OD10 GPIOA10 output data [10:10] OD11 GPIOA11 output data [11:11] OD12 GPIOA12 output data [12:12] OD13 GPIOA13 output data [13:13] OD14 GPIOA14 output data [14:14] OD15 GPIOA15 output data [15:15] BSRR GPIO port bit set/reset register 0x18 BS0 GPIOA0 output set [0:0] write-only BS1 GPIOA1 output set [1:1] write-only BS2 GPIOA2 output set [2:2] write-only BS3 GPIOA3 output set [3:3] write-only BS4 GPIOA4 output set [4:4] write-only BS5 GPIOA5 output set [5:5] write-only BS6 GPIOA6 output set [6:6] write-only BS7 GPIOA7 output set [7:7] write-only BS8 GPIOA8 output set [8:8] write-only BS9 GPIOA9 output set [9:9] write-only BS10 GPIOA10 output set [10:10] write-only BS11 GPIOA11 output set [11:11] write-only BS12 GPIOA12 output set [12:12] write-only BS13 GPIOA13 output set [13:13] write-only BS14 GPIOA14 output set [14:14] write-only BS15 GPIOA15 output set [15:15] write-only BR0 GPIOA0 outut reset [16:16] write-only BR1 GPIOA1 outut reset [17:17] write-only BR2 GPIOA2 outut reset [18:18] write-only BR3 GPIOA3 outut reset [19:19] write-only BR4 GPIOA4 outut reset [20:20] write-only BR5 GPIOA5 outut reset [21:21] write-only BR6 GPIOA6 outut reset [22:22] write-only BR7 GPIOA7 outut reset [23:23] write-only BR8 GPIOA8 outut reset [24:24] write-only BR9 GPIOA9 outut reset [25:25] write-only BR10 GPIOA10 outut reset [26:26] write-only BR11 GPIOA11 outut reset [27:27] write-only BR12 GPIOA12 outut reset [28:28] write-only BR13 GPIOA13 outut reset [29:29] write-only BR14 GPIOA14 outut reset [30:30] write-only BR15 GPIOA15 outut reset [31:31] write-only LCKR GPIO port configuration lock register 0x1C LCK0 GPIOA lock(bit0) [0:0] LCK1 GPIOA lock(bit1) [1:1] LCK2 GPIOA lock(bit2) [2:2] LCK3 GPIOA lock(bit3) [3:3] LCK4 GPIOA lock(bit4) [4:4] LCK5 GPIOA lock(bit5) [5:5] LCK6 GPIOA lock(bit6) [6:6] LCK7 GPIOA lock(bit7) [7:7] LCK8 GPIOA lock(bit8) [8:8] LCK9 GPIOA lock(bit9) [9:9] LCK10 GPIOA lock(bit10) [10:10] LCK11 GPIOA lock(bit11) [11:11] LCK12 GPIOA lock(bit12) [12:12] LCK13 GPIOA lock(bit13) [13:13] LCK14 GPIOA lock(bit14) [14:14] LCK15 GPIOA lock(bit15) [15:15] LCKK GPIOA lock key [16:16] AFRL GPIO alternate function low register 0x20 AFSEL0 GPIOA0 AF select [3:0] AFSEL1 GPIOA1 AF select [7:4] AFSEL2 GPIOA2 AF select [11:8] AFSEL3 GPIOA3 AF select [15:12] AFSEL4 GPIOA4 AF select [19:16] AFSEL5 GPIOA5 AF select [23:20] AFSEL6 GPIOA6 AF select [27:24] AFSEL7 GPIOA7 AF select [31:28] AFRH GPIO alternate function high register 0x24 AFSEL8 GPIOA8 AF select [3:0] AFSEL9 GPIOA9 AF select [7:4] AFSEL10 GPIOA10 AF select [11:8] AFSEL11 GPIOA11 AF select [15:12] AFSEL12 GPIOA12 AF select [19:16] AFSEL13 GPIOA13 AF select [23:20] AFSEL14 GPIOA14 AF select [27:24] AFSEL15 GPIOA15 AF select [31:28] BRR port bit reset register 0x28 BR0 GPIOA 0 output pin reset [0:0] write-only BR1 GPIOA 1 output pin reset [1:1] write-only BR2 GPIOA 2 output pin reset [2:2] write-only BR3 GPIOA 3 output pin reset [3:3] write-only BR4 GPIOA 4 output pin reset [4:4] write-only BR5 GPIOA 5 output pin reset [5:5] write-only BR6 GPIOA 6 output pin reset [6:6] write-only BR7 GPIOA 7 output pin reset [7:7] write-only BR8 GPIOA 8 output pin reset [8:8] write-only BR9 GPIOA 9 output pin reset [9:9] write-only BR10 GPIOA 10 output pin reset [10:10] write-only BR11 GPIOA 11 output pin reset [11:11] write-only BR12 GPIOA 12 output pin reset [12:12] write-only BR13 GPIOA 13 output pin reset [13:13] write-only BR14 GPIOA 14 output pin reset [14:14] write-only BR15 GPIOA 15 output pin reset [15:15] write-only GPIOB General-purpose I/Os 0x50000400 0x0 0x30 registers MODER 0x0 MODER0 GPIOB0 MODE [1:0] MODER1 GPIOB1 MODE [3:2] MODER2 GPIOB2 MODE [5:4] MODER3 GPIOB3 MODE [7:6] MODER4 GPIOB4 MODE [9:8] MODER5 GPIOB5 MODE [11:10] MODER6 GPIOB6 MODE [13:12] MODER7 GPIOB7 MODE [15:14] MODER8 GPIOB8 MODE [17:16] MODER9 GPIOB9 MODE [19:18] MODER10 GPIOB10 MODE [21:20] MODER11 GPIOB11 MODE [23:22] MODER12 GPIOB12 MODE [25:24] MODER13 GPIOB13 MODE [27:26] MODER14 GPIOB14 MODE [29:28] MODER15 GPIOB15 MODE [31:30] OTYPER 0x4 OT0 GPIOB0 Output type [0:0] OT1 GPIOB1 Output type [1:1] OT2 GPIOB2 Output type [2:2] OT3 GPIOB3 Output type [3:3] OT4 GPIOB4 Output type [4:4] OT5 GPIOB5 Output type [5:5] OT6 GPIOB6 Output type [6:6] OT7 GPIOB7 Output type [7:7] OT8 GPIOB8 Output type [8:8] OT9 GPIOB9 Output type [9:9] OT10 GPIOB10 Output type [10:10] OT11 GPIOB11 Output type [11:11] OT12 GPIOB12 Output type [12:12] OT13 GPIOB13 Output type [13:13] OT14 GPIOB14 Output type [14:14] OT15 GPIOB15 Output type [15:15] OSPDDER 0x8 OSPEED0 GPIOB0 output speed [1:0] OSPEED1 GPIOB1 output speed [3:2] OSPEED2 GPIOB2 output speed [5:4] OSPEED3 GPIOB3 output speed [7:6] OSPEED4 GPIOB4 output speed [9:8] OSPEED5 GPIOB5 output speed [11:10] OSPEED6 GPIOB6 output speed [13:12] OSPEED7 GPIOB7 output speed [15:14] OSPEED8 GPIOB8 output speed [17:16] OSPEED9 GPIOB9 output speed [19:18] OSPEED10 GPIOB10 output speed [21:20] OSPEED11 GPIOB11 output speed [23:22] OSPEED12 GPIOB12 output speed [25:24] OSPEED13 GPIOB13 output speed [27:26] OSPEED14 GPIOB14 output speed [29:28] OSPEED15 GPIOB15 output speed [31:30] PUPDR 0xC PUPD0 GPIOB0 pull up/pull down [1:0] PUPD1 GPIOB1 pull up/pull down [3:2] PUPD2 GPIOB2 pull up/pull down [5:4] PUPD3 GPIOB3 pull up/pull down [7:6] PUPD4 GPIOB4 pull up/pull down [9:8] PUPD5 GPIOB5 pull up/pull down [11:10] PUPD6 GPIOB6 pull up/pull down [13:12] PUPD7 GPIOB7 pull up/pull down [15:14] PUPD8 GPIOB8 pull up/pull down [17:16] PUPD9 GPIOB9 pull up/pull down [19:18] PUPD10 GPIOB10 pull up/pull down [21:20] PUPD11 GPIOB11 pull up/pull down [23:22] PUPD12 GPIOB12 pull up/pull down [25:24] PUPD13 GPIOB13 pull up/pull down [27:26] PUPD14 GPIOB14 pull up/pull down [29:28] PUPD15 GPIOB15 pull up/pull down [31:30] IDR 0x10 ID0 GPIOB0 input data [0:0] read-only ID1 GPIOB1 input data [1:1] read-only ID2 GPIOB2 input data [2:2] read-only ID3 GPIOB3 input data [3:3] read-only ID4 GPIOB4 input data [4:4] read-only ID5 GPIOB5 input data [5:5] read-only ID6 GPIOB6 input data [6:6] read-only ID7 GPIOB7 input data [7:7] read-only ID8 GPIOB8 input data [8:8] read-only ID9 GPIOB9 input data [9:9] read-only ID10 GPIOB10 input data [10:10] read-only ID11 GPIOB11 input data [11:11] read-only ID12 GPIOB12 input data [12:12] read-only ID13 GPIOB13 input data [13:13] read-only ID14 GPIOB14 input data [14:14] read-only ID15 GPIOB15 input data [15:15] read-only ODR 0x14 OD0 GPIOB0 output data [0:0] OD1 GPIOB1 output data [1:1] OD2 GPIOB2 output data [2:2] OD3 GPIOB3 output data [3:3] OD4 GPIOB4 output data [4:4] OD5 GPIOB5 output data [5:5] OD6 GPIOB6 output data [6:6] OD7 GPIOB7 output data [7:7] OD8 GPIOB8 output data [8:8] OD9 GPIOB9 output data [9:9] OD10 GPIOB10 output data [10:10] OD11 GPIOB11 output data [11:11] OD12 GPIOB12 output data [12:12] OD13 GPIOB13 output data [13:13] OD14 GPIOB14 output data [14:14] OD15 GPIOB15 output data [15:15] BSRR 0x18 BS0 GPIOB0 output set [0:0] write-only BS1 GPIOB1 output set [1:1] write-only BS2 GPIOB2 output set [2:2] write-only BS3 GPIOB3 output set [3:3] write-only BS4 GPIOB4 output set [4:4] write-only BS5 GPIOB5 output set [5:5] write-only BS6 GPIOB6 output set [6:6] write-only BS7 GPIOB7 output set [7:7] write-only BS8 GPIOB8 output set [8:8] write-only BS9 GPIOB9 output set [9:9] write-only BS10 GPIOB10 output set [10:10] write-only BS11 GPIOB11 output set [11:11] write-only BS12 GPIOB12 output set [12:12] write-only BS13 GPIOB13 output set [13:13] write-only BS14 GPIOB14 output set [14:14] write-only BS15 GPIOB15 output set [15:15] write-only BR0 GPIOB0 outut reset [16:16] write-only BR1 GPIOB1 outut reset [17:17] write-only BR2 GPIOB2 outut reset [18:18] write-only BR3 GPIOB3 outut reset [19:19] write-only BR4 GPIOB4 outut reset [20:20] write-only BR5 GPIOB5 outut reset [21:21] write-only BR6 GPIOB6 outut reset [22:22] write-only BR7 GPIOB7 outut reset [23:23] write-only BR8 GPIOB8 outut reset [24:24] write-only BR9 GPIOB9 outut reset [25:25] write-only BR10 GPIOB10 outut reset [26:26] write-only BR11 GPIOB11 outut reset [27:27] write-only BR12 GPIOB12 outut reset [28:28] write-only BR13 GPIOB13 outut reset [29:29] write-only BR14 GPIOB14 outut reset [30:30] write-only BR15 GPIOB15 outut reset [31:31] write-only LCKR 0x1C LCK0 GPIOB lock(bit0) [0:0] LCK1 GPIOB lock(bit1) [1:1] LCK2 GPIOB lock(bit2) [2:2] LCK3 GPIOB lock(bit3) [3:3] LCK4 GPIOB lock(bit4) [4:4] LCK5 GPIOB lock(bit5) [5:5] LCK6 GPIOB lock(bit6) [6:6] LCK7 GPIOB lock(bit7) [7:7] LCK8 GPIOB lock(bit8) [8:8] LCK9 GPIOB lock(bit9) [9:9] LCK10 GPIOB lock(bit10) [10:10] LCK11 GPIOB lock(bit11) [11:11] LCK12 GPIOB lock(bit12) [12:12] LCK13 GPIOB lock(bit13) [13:13] LCK14 GPIOB lock(bit14) [14:14] LCK15 GPIOB lock(bit15) [15:15] LCKK GPIOB lock key [16:16] AFRL 0x20 AFSEL0 GPIOB0 AF select [3:0] AFSEL1 GPIOB1 AF select [7:4] AFSEL2 GPIOB2 AF select [11:8] AFSEL3 GPIOB3 AF select [15:12] AFSEL4 GPIOB4 AF select [19:16] AFSEL5 GPIOB5 AF select [23:20] AFSEL6 GPIOB6 AF select [27:24] AFSEL7 GPIOB7 AF select [31:28] AFRH 0x24 AFSEL8 GPIOB8 AF select [3:0] AFSEL9 GPIOB9 AF select [7:4] AFSEL10 GPIOB10 AF select [11:8] AFSEL11 GPIOB11 AF select [15:12] AFSEL12 GPIOB12 AF select [19:16] AFSEL13 GPIOB13 AF select [23:20] AFSEL14 GPIOB14 AF select [27:24] AFSEL15 GPIOB15 AF select [31:28] BRR 0x28 BR0 GPIOB 0 output pin reset [0:0] write-only BR1 GPIOB 1 output pin reset [1:1] write-only BR2 GPIOB 2 output pin reset [2:2] write-only BR3 GPIOB 3 output pin reset [3:3] write-only BR4 GPIOB 4 output pin reset [4:4] write-only BR5 GPIOB 5 output pin reset [5:5] write-only BR6 GPIOB 6 output pin reset [6:6] write-only BR7 GPIOB 7 output pin reset [7:7] write-only BR8 GPIOB 8 output pin reset [8:8] write-only BR9 GPIOB 9 output pin reset [9:9] write-only BR10 GPIOB 10 output pin reset [10:10] write-only BR11 GPIOB 11 output pin reset [11:11] write-only BR12 GPIOB 12 output pin reset [12:12] write-only BR13 GPIOB 13 output pin reset [13:13] write-only BR14 GPIOB 14 output pin reset [14:14] write-only BR15 GPIOB 15 output pin reset [15:15] write-only GPIOC General-purpose I/Os 0x50000800 0x0 0x30 registers MODER 0x0 MODER0 GPIOC0 MODE [1:0] MODER1 GPIOC1 MODE [3:2] MODER2 GPIOC2 MODE [5:4] MODER3 GPIOC3 MODE [7:6] MODER4 GPIOC4 MODE [9:8] MODER5 GPIOC5 MODE [11:10] MODER6 GPIOC6 MODE [13:12] MODER7 GPIOC7 MODE [15:14] MODER8 GPIOC8 MODE [17:16] MODER9 GPIOC9 MODE [19:18] MODER10 GPIOC10 MODE [21:20] MODER11 GPIOC11 MODE [23:22] MODER12 GPIOC12 MODE [25:24] MODER13 GPIOC13 MODE [27:26] MODER14 GPIOC14 MODE [29:28] MODER15 GPIOC15 MODE [31:30] OTYPER 0x4 OT0 GPIOC0 Output type [0:0] OT1 GPIOC1 Output type [1:1] OT2 GPIOC2 Output type [2:2] OT3 GPIOC3 Output type [3:3] OT4 GPIOC4 Output type [4:4] OT5 GPIOC5 Output type [5:5] OT6 GPIOC6 Output type [6:6] OT7 GPIOC7 Output type [7:7] OT8 GPIOC8 Output type [8:8] OT9 GPIOC9 Output type [9:9] OT10 GPIOC10 Output type [10:10] OT11 GPIOC11 Output type [11:11] OT12 GPIOC12 Output type [12:12] OT13 GPIOC13 Output type [13:13] OT14 GPIOC14 Output type [14:14] OT15 GPIOC15 Output type [15:15] OSPDDER 0x8 OSPEED0 GPIOC0 output speed [1:0] OSPEED1 GPIOC1 output speed [3:2] OSPEED2 GPIOC2 output speed [5:4] OSPEED3 GPIOC3 output speed [7:6] OSPEED4 GPIOC4 output speed [9:8] OSPEED5 GPIOC5 output speed [11:10] OSPEED6 GPIOC6 output speed [13:12] OSPEED7 GPIOC7 output speed [15:14] OSPEED8 GPIOC8 output speed [17:16] OSPEED9 GPIOC9 output speed [19:18] OSPEED10 GPIOC10 output speed [21:20] OSPEED11 GPIOC11 output speed [23:22] OSPEED12 GPIOC12 output speed [25:24] OSPEED13 GPIOC13 output speed [27:26] OSPEED14 GPIOC14 output speed [29:28] OSPEED15 GPIOC15 output speed [31:30] PUPDR 0xC PUPD0 GPIOC0 pull up/pull down [1:0] PUPD1 GPIOC1 pull up/pull down [3:2] PUPD2 GPIOC2 pull up/pull down [5:4] PUPD3 GPIOC3 pull up/pull down [7:6] PUPD4 GPIOC4 pull up/pull down [9:8] PUPD5 GPIOC5 pull up/pull down [11:10] PUPD6 GPIOC6 pull up/pull down [13:12] PUPD7 GPIOC7 pull up/pull down [15:14] PUPD8 GPIOC8 pull up/pull down [17:16] PUPD9 GPIOC9 pull up/pull down [19:18] PUPD10 GPIOC10 pull up/pull down [21:20] PUPD11 GPIOC11 pull up/pull down [23:22] PUPD12 GPIOC12 pull up/pull down [25:24] PUPD13 GPIOC13 pull up/pull down [27:26] PUPD14 GPIOC14 pull up/pull down [29:28] PUPD15 GPIOC15 pull up/pull down [31:30] IDR 0x10 ID0 GPIOC0 input data [0:0] read-only ID1 GPIOC1 input data [1:1] read-only ID2 GPIOC2 input data [2:2] read-only ID3 GPIOC3 input data [3:3] read-only ID4 GPIOC4 input data [4:4] read-only ID5 GPIOC5 input data [5:5] read-only ID6 GPIOC6 input data [6:6] read-only ID7 GPIOC7 input data [7:7] read-only ID8 GPIOC8 input data [8:8] read-only ID9 GPIOC9 input data [9:9] read-only ID10 GPIOC10 input data [10:10] read-only ID11 GPIOC11 input data [11:11] read-only ID12 GPIOC12 input data [12:12] read-only ID13 GPIOC13 input data [13:13] read-only ID14 GPIOC14 input data [14:14] read-only ID15 GPIOC15 input data [15:15] read-only ODR 0x14 OD0 GPIOC0 output data [0:0] OD1 GPIOC1 output data [1:1] OD2 GPIOC2 output data [2:2] OD3 GPIOC3 output data [3:3] OD4 GPIOC4 output data [4:4] OD5 GPIOC5 output data [5:5] OD6 GPIOC6 output data [6:6] OD7 GPIOC7 output data [7:7] OD8 GPIOC8 output data [8:8] OD9 GPIOC9 output data [9:9] OD10 GPIOC10 output data [10:10] OD11 GPIOC11 output data [11:11] OD12 GPIOC12 output data [12:12] OD13 GPIOC13 output data [13:13] OD14 GPIOC14 output data [14:14] OD15 GPIOC15 output data [15:15] BSRR 0x18 BS0 GPIOC0 output set [0:0] write-only BS1 GPIOC1 output set [1:1] write-only BS2 GPIOC2 output set [2:2] write-only BS3 GPIOC3 output set [3:3] write-only BS4 GPIOC4 output set [4:4] write-only BS5 GPIOC5 output set [5:5] write-only BS6 GPIOC6 output set [6:6] write-only BS7 GPIOC7 output set [7:7] write-only BS8 GPIOC8 output set [8:8] write-only BS9 GPIOC9 output set [9:9] write-only BS10 GPIOC10 output set [10:10] write-only BS11 GPIOC11 output set [11:11] write-only BS12 GPIOC12 output set [12:12] write-only BS13 GPIOC13 output set [13:13] write-only BS14 GPIOC14 output set [14:14] write-only BS15 GPIOC15 output set [15:15] write-only BR0 GPIOC0 outut reset [16:16] write-only BR1 GPIOC1 outut reset [17:17] write-only BR2 GPIOC2 outut reset [18:18] write-only BR3 GPIOC3 outut reset [19:19] write-only BR4 GPIOC4 outut reset [20:20] write-only BR5 GPIOC5 outut reset [21:21] write-only BR6 GPIOC6 outut reset [22:22] write-only BR7 GPIOC7 outut reset [23:23] write-only BR8 GPIOC8 outut reset [24:24] write-only BR9 GPIOC9 outut reset [25:25] write-only BR10 GPIOC10 outut reset [26:26] write-only BR11 GPIOC11 outut reset [27:27] write-only BR12 GPIOC12 outut reset [28:28] write-only BR13 GPIOC13 outut reset [29:29] write-only BR14 GPIOC14 outut reset [30:30] write-only BR15 GPIOC15 outut reset [31:31] write-only LCKR 0x1C LCK0 GPIOC lock(bit0) [0:0] LCK1 GPIOC lock(bit1) [1:1] LCK2 GPIOC lock(bit2) [2:2] LCK3 GPIOC lock(bit3) [3:3] LCK4 GPIOC lock(bit4) [4:4] LCK5 GPIOC lock(bit5) [5:5] LCK6 GPIOC lock(bit6) [6:6] LCK7 GPIOC lock(bit7) [7:7] LCK8 GPIOC lock(bit8) [8:8] LCK9 GPIOC lock(bit9) [9:9] LCK10 GPIOC lock(bit10) [10:10] LCK11 GPIOC lock(bit11) [11:11] LCK12 GPIOC lock(bit12) [12:12] LCK13 GPIOC lock(bit13) [13:13] LCK14 GPIOC lock(bit14) [14:14] LCK15 GPIOC lock(bit15) [15:15] LCKK GPIOC lock key [16:16] AFRL 0x20 AFSEL0 GPIOC0 AF select [3:0] AFSEL1 GPIOC1 AF select [7:4] AFSEL2 GPIOC2 AF select [11:8] AFSEL3 GPIOC3 AF select [15:12] AFSEL4 GPIOC4 AF select [19:16] AFSEL5 GPIOC5 AF select [23:20] AFSEL6 GPIOC6 AF select [27:24] AFSEL7 GPIOC7 AF select [31:28] AFRH 0x24 AFSEL8 GPIOC8 AF select [3:0] AFSEL9 GPIOC9 AF select [7:4] AFSEL10 GPIOC10 AF select [11:8] AFSEL11 GPIOC11 AF select [15:12] AFSEL12 GPIOC12 AF select [19:16] AFSEL13 GPIOC13 AF select [23:20] AFSEL14 GPIOC14 AF select [27:24] AFSEL15 GPIOC15 AF select [31:28] BRR 0x28 BR0 GPIOC 0 output pin reset [0:0] write-only BR1 GPIOC 1 output pin reset [1:1] write-only BR2 GPIOC 2 output pin reset [2:2] write-only BR3 GPIOC 3 output pin reset [3:3] write-only BR4 GPIOC 4 output pin reset [4:4] write-only BR5 GPIOC 5 output pin reset [5:5] write-only BR6 GPIOC 6 output pin reset [6:6] write-only BR7 GPIOC 7 output pin reset [7:7] write-only BR8 GPIOC 8 output pin reset [8:8] write-only BR9 GPIOC 9 output pin reset [9:9] write-only BR10 GPIOC 10 output pin reset [10:10] write-only BR11 GPIOC 11 output pin reset [11:11] write-only BR12 GPIOC 12 output pin reset [12:12] write-only BR13 GPIOC 13 output pin reset [13:13] write-only BR14 GPIOC 14 output pin reset [14:14] write-only BR15 GPIOC 15 output pin reset [15:15] write-only GPIOD 0x50000C00 0x0 0x30 registers MODER 0x0 MODER0 GPIOD0 MODE [1:0] MODER1 GPIOD1 MODE [3:2] MODER2 GPIOD2 MODE [5:4] MODER3 GPIOD3 MODE [7:6] MODER4 GPIOD4 MODE [9:8] MODER5 GPIOD5 MODE [11:10] MODER6 GPIOD6 MODE [13:12] MODER7 GPIOD7 MODE [15:14] MODER8 GPIOD8 MODE [17:16] MODER9 GPIOD9 MODE [19:18] MODER10 GPIOD10 MODE [21:20] MODER11 GPIOD11 MODE [23:22] MODER12 GPIOD12 MODE [25:24] MODER13 GPIOD13 MODE [27:26] MODER14 GPIOD14 MODE [29:28] MODER15 GPIOD15 MODE [31:30] OTYPER 0x4 OT0 GPIOD0 Output type [0:0] OT1 GPIOD1 Output type [1:1] OT2 GPIOD2 Output type [2:2] OT3 GPIOD3 Output type [3:3] OT4 GPIOD4 Output type [4:4] OT5 GPIOD5 Output type [5:5] OT6 GPIOD6 Output type [6:6] OT7 GPIOD7 Output type [7:7] OT8 GPIOD8 Output type [8:8] OT9 GPIOD9 Output type [9:9] OT10 GPIOD10 Output type [10:10] OT11 GPIOD11 Output type [11:11] OT12 GPIOD12 Output type [12:12] OT13 GPIOD13 Output type [13:13] OT14 GPIOD14 Output type [14:14] OT15 GPIOD15 Output type [15:15] OSPDDER 0x8 OSPEED0 GPIOD0 output speed [1:0] OSPEED1 GPIOD1 output speed [3:2] OSPEED2 GPIOD2 output speed [5:4] OSPEED3 GPIOD3 output speed [7:6] OSPEED4 GPIOD4 output speed [9:8] OSPEED5 GPIOD5 output speed [11:10] OSPEED6 GPIOD6 output speed [13:12] OSPEED7 GPIOD7 output speed [15:14] OSPEED8 GPIOD8 output speed [17:16] OSPEED9 GPIOD9 output speed [19:18] OSPEED10 GPIOD10 output speed [21:20] OSPEED11 GPIOD11 output speed [23:22] OSPEED12 GPIOD12 output speed [25:24] OSPEED13 GPIOD13 output speed [27:26] OSPEED14 GPIOD14 output speed [29:28] OSPEED15 GPIOD15 output speed [31:30] PUPDR 0xC PUPD0 GPIOD0 pull up/pull down [1:0] PUPD1 GPIOD1 pull up/pull down [3:2] PUPD2 GPIOD2 pull up/pull down [5:4] PUPD3 GPIOD3 pull up/pull down [7:6] PUPD4 GPIOD4 pull up/pull down [9:8] PUPD5 GPIOD5 pull up/pull down [11:10] PUPD6 GPIOD6 pull up/pull down [13:12] PUPD7 GPIOD7 pull up/pull down [15:14] PUPD8 GPIOD8 pull up/pull down [17:16] PUPD9 GPIOD9 pull up/pull down [19:18] PUPD10 GPIOD10 pull up/pull down [21:20] PUPD11 GPIOD11 pull up/pull down [23:22] PUPD12 GPIOD12 pull up/pull down [25:24] PUPD13 GPIOD13 pull up/pull down [27:26] PUPD14 GPIOD14 pull up/pull down [29:28] PUPD15 GPIOD15 pull up/pull down [31:30] IDR 0x10 ID0 GPIOD0 input data [0:0] read-only ID1 GPIOD1 input data [1:1] read-only ID2 GPIOD2 input data [2:2] read-only ID3 GPIOD3 input data [3:3] read-only ID4 GPIOD4 input data [4:4] read-only ID5 GPIOD5 input data [5:5] read-only ID6 GPIOD6 input data [6:6] read-only ID7 GPIOD7 input data [7:7] read-only ID8 GPIOD8 input data [8:8] read-only ID9 GPIOD9 input data [9:9] read-only ID10 GPIOD10 input data [10:10] read-only ID11 GPIOD11 input data [11:11] read-only ID12 GPIOD12 input data [12:12] read-only ID13 GPIOD13 input data [13:13] read-only ID14 GPIOD14 input data [14:14] read-only ID15 GPIOD15 input data [15:15] read-only ODR 0x14 OD0 GPIOD0 output data [0:0] OD1 GPIOD1 output data [1:1] OD2 GPIOD2 output data [2:2] OD3 GPIOD3 output data [3:3] OD4 GPIOD4 output data [4:4] OD5 GPIOD5 output data [5:5] OD6 GPIOD6 output data [6:6] OD7 GPIOD7 output data [7:7] OD8 GPIOD8 output data [8:8] OD9 GPIOD9 output data [9:9] OD10 GPIOD10 output data [10:10] OD11 GPIOD11 output data [11:11] OD12 GPIOD12 output data [12:12] OD13 GPIOD13 output data [13:13] OD14 GPIOD14 output data [14:14] OD15 GPIOD15 output data [15:15] BSRR 0x18 BS0 GPIOD0 output set [0:0] write-only BS1 GPIOD1 output set [1:1] write-only BS2 GPIOD2 output set [2:2] write-only BS3 GPIOD3 output set [3:3] write-only BS4 GPIOD4 output set [4:4] write-only BS5 GPIOD5 output set [5:5] write-only BS6 GPIOD6 output set [6:6] write-only BS7 GPIOD7 output set [7:7] write-only BS8 GPIOD8 output set [8:8] write-only BS9 GPIOD9 output set [9:9] write-only BS10 GPIOD10 output set [10:10] write-only BS11 GPIOD11 output set [11:11] write-only BS12 GPIOD12 output set [12:12] write-only BS13 GPIOD13 output set [13:13] write-only BS14 GPIOD14 output set [14:14] write-only BS15 GPIOD15 output set [15:15] write-only BR0 GPIOD0 outut reset [16:16] write-only BR1 GPIOD1 outut reset [17:17] write-only BR2 GPIOD2 outut reset [18:18] write-only BR3 GPIOD3 outut reset [19:19] write-only BR4 GPIOD4 outut reset [20:20] write-only BR5 GPIOD5 outut reset [21:21] write-only BR6 GPIOD6 outut reset [22:22] write-only BR7 GPIOD7 outut reset [23:23] write-only BR8 GPIOD8 outut reset [24:24] write-only BR9 GPIOD9 outut reset [25:25] write-only BR10 GPIOD10 outut reset [26:26] write-only BR11 GPIOD11 outut reset [27:27] write-only BR12 GPIOD12 outut reset [28:28] write-only BR13 GPIOD13 outut reset [29:29] write-only BR14 GPIOD14 outut reset [30:30] write-only BR15 GPIOD15 outut reset [31:31] write-only LCKR 0x1C LCK0 GPIOD lock(bit0) [0:0] LCK1 GPIOD lock(bit1) [1:1] LCK2 GPIOD lock(bit2) [2:2] LCK3 GPIOD lock(bit3) [3:3] LCK4 GPIOD lock(bit4) [4:4] LCK5 GPIOD lock(bit5) [5:5] LCK6 GPIOD lock(bit6) [6:6] LCK7 GPIOD lock(bit7) [7:7] LCK8 GPIOD lock(bit8) [8:8] LCK9 GPIOD lock(bit9) [9:9] LCK10 GPIOD lock(bit10) [10:10] LCK11 GPIOD lock(bit11) [11:11] LCK12 GPIOD lock(bit12) [12:12] LCK13 GPIOD lock(bit13) [13:13] LCK14 GPIOD lock(bit14) [14:14] LCK15 GPIOD lock(bit15) [15:15] LCKK GPIOD lock key [16:16] AFRL 0x20 AFSEL0 GPIOD0 AF select [3:0] AFSEL1 GPIOD1 AF select [7:4] AFSEL2 GPIOD2 AF select [11:8] AFSEL3 GPIOD3 AF select [15:12] AFSEL4 GPIOD4 AF select [19:16] AFSEL5 GPIOD5 AF select [23:20] AFSEL6 GPIOD6 AF select [27:24] AFSEL7 GPIOD7 AF select [31:28] AFRH 0x24 AFSEL8 GPIOD8 AF select [3:0] AFSEL9 GPIOD9 AF select [7:4] AFSEL10 GPIOD10 AF select [11:8] AFSEL11 GPIOD11 AF select [15:12] AFSEL12 GPIOD12 AF select [19:16] AFSEL13 GPIOD13 AF select [23:20] AFSEL14 GPIOD14 AF select [27:24] AFSEL15 GPIOD15 AF select [31:28] BRR 0x28 BR0 GPIOD 0 output pin reset [0:0] write-only BR1 GPIOD 1 output pin reset [1:1] write-only BR2 GPIOD 2 output pin reset [2:2] write-only BR3 GPIOD 3 output pin reset [3:3] write-only BR4 GPIOD 4 output pin reset [4:4] write-only BR5 GPIOD 5 output pin reset [5:5] write-only BR6 GPIOD 6 output pin reset [6:6] write-only BR7 GPIOD 7 output pin reset [7:7] write-only BR8 GPIOD 8 output pin reset [8:8] write-only BR9 GPIOD 9 output pin reset [9:9] write-only BR10 GPIOD 10 output pin reset [10:10] write-only BR11 GPIOD 11 output pin reset [11:11] write-only BR12 GPIOD 12 output pin reset [12:12] write-only BR13 GPIOD 13 output pin reset [13:13] write-only BR14 GPIOD 14 output pin reset [14:14] write-only BR15 GPIOD 15 output pin reset [15:15] write-only I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 desc CR1 0x0 PE Peripheral enable [0:0] SMBUS SMBus mode [1:1] WUPEN Wakeup from Stop mode enable [2:2] SMBTYPE SMBus type [3:3] ENARP ARP enable [4:4] ENPEC PEC enable [5:5] ENGC General call enable [6:6] NOSTRETCH Clock stretching disable (Slave mode) [7:7] START Start generation [8:8] STOP Stop generation [9:9] ACK Acknowledge enable [10:10] POS Acknowledge(for data reception) [11:11] PEC Packet error checking [12:12] ALERT SMBus alert [13:13] SWRST Software reset [15:15] WKUP_DIV PCLK division [17:16] WKUP_CNT Timeout count number [19:18] CR2 desc CR2 0x4 FREQ Peripheral clock frequency [6:0] ITERREN Error interrupt enable [8:8] ITEVTEN Event interrupt enable [9:9] ITBUFEN Buffer interrupt enable [10:10] DMAEN DMA requests enable [11:11] LAST DMA last transfer [12:12] OAR1 desc OAR1 0x8 ADD Interface address [9:0] ADDMODE Addressing mode (slave mode) [15:15] OAR2 desc OAR2 0xC ENDUAL Dual addressing mode enable [0:0] ADD2 Interface address [7:1] OA2MSK Own Address 2 masks [10:8] DR desc DR 0x10 DR 8-bit data register [7:0] SR1 desc SR1 0x14 SB Start bit (Master mode) [0:0] read-only ADDR Address sent (master mode)/matched (slave mode) [1:1] read-only BTF Byte transfer finished [2:2] read-only ADD10 10-bit header sent (Master mode) [3:3] read-only STOPF Stop detection (slave mode) [4:4] read-only RXNE Data register not empty (receivers) [6:6] read-only TXE Data register empty (transmitters) [7:7] read-only BERR Bus error [8:8] ARLO Arbitration lost (master mode) [9:9] AF Acknowledge failure [10:10] OVR Overrun/Underrun [11:11] PECERR PEC Error in reception [12:12] TIMEOUT Timeout or Tlow error [14:14] SMBALERT SMBus alert [15:15] SR2 desc SR2 0x18 MSL Master/slave [0:0] read-only BUSY Bus busy [1:1] read-only TRA Transmitter/receiver [2:2] read-only GENCALL General call address (Slave mode) [4:4] read-only SMBDEFAULT SMBus device default address (Slave mode) [5:5] read-only SMBHOST SMBus host header (Slave mode) [6:6] read-only DUALF Dual flag (Slave mode) [7:7] read-only PEC Packet error checking register [15:8] read-only CCR desc CCR 0x1C CCR Clock control register in Fm/Sm mode (Master mode) [11:0] FP I2C master mode selection [13:13] DUTY Fm mode duty cycle [14:14] FS I2C master mode selection [15:15] TRISE desc TRISE 0x20 TRISE Maximum rise time in Fm+/Fm/Sm mode (Master mode) [6:0] THOLDDATA Data hold time [11:7] THOLDDATA_SEL Data hold time select [12:12] TIMEOUTR 0x24 TIMEOUTA Bus Timeout A [11:0] TIDLE Idle clock timeout detection [12:12] TIMEOUTEN Clock timeout enable [15:15] TIMEOUTB Bus timeout B [27:16] TEXTEN Extended clock timeout enable [31:31] I2C2 desc I2C 0x40005800 I2C2 I2C2 Event Interrupt 24 IWDG Independent watchdog 0x40003000 0x0 0x400 registers KR Key register (IWDG_KR) 0x0 KEY IWDG KEY [15:0] write-only PR Prescaler register (IWDG_PR) 0x4 PR IWDG preload [2:0] RLR Reload register (IWDG_RLR) 0x8 RL IWDG reload [11:0] SR Status register (IWDG_SR) 0xC PVU Watchdog prescaler value update [0:0] read-only RVU Watchdog counter reload value update [1:1] read-only IVU Watchdog Interrupt value update [3:3] read-only IF Watchdog interrupt status [4:4] read-only ICNTR 0x10 ICNTR Watchdog prescaler value update [11:0] ICR 0x14 IER Watchdog Interrupt enable [0:0] ICR Watchdog interrupt status clear [1:1] write-only LCD LCD CONTROLLER 0x40002400 0x0 0x400 registers LCD_CANINT1 LCD/CANINT1 global Interrupt 8 CR 0x0 EN [0:0] LCDCLK [2:1] BIAS [5:4] DUTY [8:6] BSEL [10:9] CONTRAST [15:12] VSEL [16:16] VCP_SEL [19:17] FCCTL [23:21] DEAD [26:24] CP_FRQ [29:27] CP_ST [31:30] CSR 0x4 BLINKCNT [5:0] BLINKEN [6:6] SWCAP_DRV_NUM [9:7] MODE [10:10] DMAEN [11:11] BKFIE [12:12] UDDIE [14:14] UDR [15:15] BKF [16:16] read-only SOF [17:17] read-only UDD [18:18] read-only ENS [19:19] read-only INTCLR INTCLR 0x8 BKFC [16:16] write-only SOFC [17:17] write-only UDDC [18:18] write-only POEN0 POEN0 0xC SX [31:0] POEN1 POEN1 0x10 SX [3:0] SXCY [7:4] CX [11:8] RAM0 des RAM0 0x14 DX [31:0] RAM1 des RAM1 0x18 DX [31:0] RAM2 des RAM2 0x1C DX [31:0] RAM3 des RAM3 0x20 DX [31:0] RAM4 des RAM4 0x24 DX [31:0] RAM5 des RAM5 0x28 DX [31:0] RAM6 des RAM6 0x2C DX [31:0] RAM7 des RAM7 0x30 DX [31:0] RAM8 des RAM8 0x34 DX [7:0] RAM9 des RAM9 0x38 DX [7:0] RAM10 des RAM10 0x3C DX [7:0] RAM11 des RAM11 0x40 DX [7:0] RAM12 des RAM12 0x44 DX [7:0] RAM13 des RAM13 0x48 DX [7:0] RAM14 des RAM14 0x4C DX [7:0] RAM15 des RAM15 0x50 DX [7:0] LPTIM1 Low power timer LPTIM 0x40007C00 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 ISR Interrupt and Status Register 0x0 CMPM Compare match [0:0] read-only ARRM Autoreload match [1:1] read-only EXTTRIG External trigger edge event [2:2] read-only CMPOK Compare register update OK [3:3] read-only ARROK Autoreload register update OK [4:4] read-only UP Counter direction change down to up [5:5] read-only DOWN Counter direction change up to down [6:6] read-only ICR Interrupt Clear Register 0x4 CMPMCF Compare match clear flag [0:0] write-only ARRMCF Autoreload match clear flag [1:1] write-only EXTTRIGCF External trigger valid edge clear flag [2:2] write-only CMPOKCF Compare register update OK clear flag [3:3] write-only ARROKCF Autoreload register update OK clear flag [4:4] write-only UPCF Direction change to UP clear flag [5:5] write-only DOWNCF Direction change to down clear flag [6:6] write-only IER Interrupt Enable Register 0x8 CMPMIE Compare match Interrupt Enable [0:0] ARRMIE Autoreload match Interrupt Enable [1:1] EXTTRIGIE External trigger valid edge Interrupt Enable [2:2] CMPOKIE Compare register update OK Interrupt Enable [3:3] ARROKIE Autoreload register update OK Interrupt Enable [4:4] UPIE Direction change to UP Interrupt Enable [5:5] DOWNIE Direction change to down Interrupt Enable [6:6] CFGR Configuration Register 0xC CKSEL Clock selector [0:0] CKPOL Clock Polarity [2:1] CKFLT Configurable digital filter for external clock [4:3] TRGFLT Configurable digital filter for trigger [7:6] PRESC Clock prescaler [11:9] TRIGSEL Trigger selector [15:13] TRIGEN Trigger enable and polarity [18:17] TIMOUT Timeout enable [19:19] WAVE Waveform shape [20:20] WAVPOL Waveform shape polarity [21:21] PRELOAD Registers update mode [22:22] ENC Encoder mode enable [24:24] CR Control Register 0x10 ENABLE LPTIM enable [0:0] SNGSTRT LPTIM start in Single mode [1:1] CNTSTRT Timer start in Continuous mode [2:2] COUNTRST Counter reset [3:3] RSTARE Reset after read enable [4:4] CMP 0x14 CMP Compare value [31:0] ARR Autoreload Register 0x18 ARR Auto reload value [31:0] CNT Counter Register 0x1C CNT Counter value [31:0] read-only OR 0x20 IN1_L LPTimer input 1 remap extension [0:0] IN2L LPTimer input 1 remap extension [1:1] IN1_H LPTimer input 3 remap extension [3:2] IN2_H LPTimer input 2 remap extension [5:4] LPTIM2 0x40009400 LPUART1 LPUART 0x40008000 0x0 0x40 registers UART1_LPUART1 UART1/LPUART1 global Interrupt 29 CR1 0x0 UE LPUART enabled [0:0] UESM LPUART enabled in Stop mode [1:1] RE Receive enable [2:2] TE Transfer enable [3:3] IDLEIE IDLE interrupt enable [4:4] EXNEIE Receive register untempered enable [5:5] TCIE End of Transfer interrupt enabled [6:6] TXEIE Transmit Register Empty Break Enable [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control [10:10] WAKE Receive wake-up mode [11:11] M0 Configure the word length in combination with M1 [12:12] MME Silent mode enabled [13:13] CMIE Character match interrupt enabled [14:14] DEDT The time between the transmit frame stop bit and the invalid DE (driver enable) signal [20:16] DEAT The time between the DE (driver enable) signal validity and the start bit [25:21] M1 The value of {M1,M0} the configurate length [28:28] CR2 0x4 ADDM7 7bit/4bit address detection configuration [4:4] STOP Stop bit configuration [13:12] SWAP TX/RX pin interchangeable [15:15] RXINV The RX pin is active level inverting [16:16] TXINV TX pin active level inverted [17:17] DATAINV Inverse binary data processing [18:18] MSBFIRST MSB first [19:19] TXOE_ALWAYS_ON [20:20] ADD LPUART address [31:24] CR3 0x8 EIE Error interrupts are enabled [0:0] HDSEL Half-duplex selection [3:3] DMAR Enable DMA on reception [6:6] DMAT Enable DMA while transmitting [7:7] RTSE RTS enabled [8:8] CTSE CTS enabled [9:9] CTSIE CTS interrupt enable [10:10] OVRDIS Overrun is prohibited [12:12] DDRE Whether DMA is disabled when receiving an error [13:13] DEM DE mode enabled [14:14] DEP DE polarity selection [15:15] WUS Low-power wake-up options [21:20] WUFIE Low-power wake-up interrupt enable [22:22] BRR 0xC BBR LPUART baud rate [19:0] LPWKUP_BRR 0x10 LPWKUP_BBR LPUART lpwkup baud rate [19:0] HW_BRR_UPEN LPUART wkup brr update enable [20:20] RQR 0x18 SBKRQ Send an abort request [1:1] write-only MMRQ Silent mode request [2:2] write-only ISR 0x1C PE Parity error [0:0] read-only FE Frame error flag [1:1] read-only NE START bit noise flag [2:2] read-only ORE Overrun error flag [3:3] read-only IDLE idle flag [4:4] read-only RXNE RX register not empty [5:5] read-only TC Transmission completion flag [6:6] read-only TXE TX register empty [7:7] read-only CTSIF CTS interrupt flag [9:9] read-only CTS CTS flag [10:10] read-only BUSY Busy flag [16:16] read-only CMF Address match flag [17:17] read-only SBKF Send abort flag [18:18] read-only RWU Receive Mute mode wake-up flag [19:19] read-only WUF Wake flag from low-power mode [20:20] read-only TEACK Transport enable acknowledgement flag [21:21] read-only REACK Receive the enable acknowledgment flag [22:22] read-only ICR 0x20 PECF Check value error flag reset [0:0] write-only FECF Frame error flag reset [1:1] write-only NECF Clear the START bit noise flag [2:2] write-only ORECF Overrun error flag reset [3:3] write-only IDLECF Clear idle flag [4:4] write-only TCCF Transfer completion flag reset [6:6] write-only CTSCF CTS flag reset [9:9] write-only CMCF Address matching flag reset [17:17] write-only WUCF Low power wake-up flag reset [20:20] write-only RDR 0x24 RDR Receive Data Register [8:0] read-only TDR 0x28 TDR Transmit Data Register [8:0] PRESC 0x2C PRESCALER Input clock prescaler register [3:0] DBG 0x30 DBGSEL debug select [1:0] OFFSET_ADD offset add [31:24] LPUART2 0x40009800 UART2_LPUART2 UART2/LPUART2 global Interrupt 30 OPA des OPA 0x40010300 0x0 0x100 registers OCR 0x30 OPA_EXTOEN [0:0] OPA_EXTOSEL [2:1] CR 0x34 OPA_VINPSEL [0:0] OPA_VINMSEL [2:2] OPAEN [5:5] TMR 0x40 OPA_TM [0:0] PWM 0x40014C00 0x0 0x50 registers PWM_CANINT PWM/CANINT global Interrupt 19 CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 0x4 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] ETRSEL [15:13] SMCR 0x8 ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] DIER 0xC UIE [0:0] OC1IE [1:1] OC2IE [2:2] OC3IE [3:3] OC4IE [4:4] BIE [7:7] UDE [8:8] OC1DE [9:9] OC2DE [10:10] OC3DE [11:11] OC4DE [12:12] SR 0x10 UIF [0:0] OC1IF [1:1] OC2IF [2:2] OC3IF [3:3] OC4IF [4:4] BIF [7:7] CCR1OK [9:9] CCR2OK [10:10] CCR3OK [11:11] CCR4OK [12:12] CNTOK [13:13] PSCOK [14:14] ARROK [15:15] EGR 0x14 UG [0:0] write-only CMR 0x18 OC1M [1:0] OC2M [3:2] OC3M [5:4] OC4M [7:6] OC1PE [8:8] OC2PE [9:9] OC3PE [10:10] OC4PE [11:11] CER 0x20 C1E [0:0] C1P [1:1] C1NE [2:2] C1NP [3:3] C2E [4:4] C2P [5:5] C2NE [6:6] C2NP [7:7] C3E [8:8] C3P [9:9] C4E [12:12] C4P [13:13] CNT 0x24 CNT [15:0] PSC 0x28 PSC [15:0] ARR 0x2C ARR [15:0] CCR1 0x34 CCR1 [15:0] CCR2 0x38 CCR2 [15:0] CCR3 0x3C CCR3 [15:0] CCR4 0x40 CCR4 [15:0] BDTR 0x44 DTG [7:0] LOCK [9:8] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] DCR 0x48 DBA [4:0] DBL [12:8] DMAR 0x4C DMAB [31:0] PWR Power control 0x40007000 0x0 0x400 registers CR1 Power control register 1 0x0 LPMS [2:0] DBP [8:8] VR_MODE [10:9] FLS_SLPTIME [13:12] MR_VSEL [17:16] LPR_VSEL [19:18] DLPR_VSEL [21:20] FLSSLP_CTRL [24:24] HSION_CTRL [25:25] STDBY_MRRDY_WAIT [27:26] CR2 Power control register 2 0x4 PVDE [0:0] PVDT [6:4] PVD_OUT_SEL [7:7] FLTEN [8:8] FLT_TIME [11:9] CR3 0x8 EWUP0 [0:0] EWUP1 [1:1] EWUP2 [2:2] EWUP3 [3:3] EWUP4 [4:4] EWUP5 [5:5] EWUP6 [6:6] EWUP7 [7:7] LD_EN [8:8] APC [9:9] SRAM1PDSTD [10:10] CR4 0xC WP0 [1:0] WP1 [3:2] WP2 [5:4] WP3 [7:6] WP4 [9:8] WP5 [11:10] WP6 [13:12] WP7 [15:14] SR Power status register 0x10 WUF0 [0:0] read-only WUF1 [1:1] read-only WUF2 [2:2] read-only WUF3 [3:3] read-only WUF4 [4:4] read-only WUF5 [5:5] read-only WUF6 [6:6] read-only WUF7 [7:7] read-only SBF [8:8] read-only MR_RDY [9:9] read-only MR_VOS_RDY [10:10] read-only LPRUN_RUN_SWF [11:11] read-only IWDGRST_WUF [12:12] read-only PINRST_WUF [13:13] read-only VCC_PORF [14:14] read-only PVDO [16:16] read-only SCR 0x14 CWUF0 [0:0] write-only CWUF1 [1:1] write-only CWUF2 [2:2] write-only CWUF3 [3:3] write-only CWUF4 [4:4] write-only CWUF5 [5:5] write-only CWUF6 [6:6] write-only CWUF7 [7:7] write-only CSBF [8:8] write-only CIWDGRSTWUF [12:12] write-only CPINRSTWUF [13:13] write-only CVCCPORF [14:14] write-only PUCRA 0x20 PU0 [0:0] PU1 [1:1] PU2 [2:2] PU3 [3:3] PU4 [4:4] PU5 [5:5] PU6 [6:6] PU7 [7:7] PU8 [8:8] PU9 [9:9] PU10 [10:10] PU11 [11:11] PU12 [12:12] PU13 [13:13] PU14 [14:14] PU15 [15:15] PDCRA 0x24 PD0 [0:0] PD1 [1:1] PD2 [2:2] PD3 [3:3] PD4 [4:4] PD5 [5:5] PD6 [6:6] PD7 [7:7] PD8 [8:8] PD9 [9:9] PD10 [10:10] PD11 [11:11] PD12 [12:12] PD13 [13:13] PD14 [14:14] PD15 [15:15] PUCRB 0x28 PU0 [0:0] PU1 [1:1] PU2 [2:2] PU3 [3:3] PU4 [4:4] PU5 [5:5] PU6 [6:6] PU7 [7:7] PU8 [8:8] PU9 [9:9] PU10 [10:10] PU11 [11:11] PU12 [12:12] PU13 [13:13] PU14 [14:14] PU15 [15:15] PDCRB 0x2C PD0 [0:0] PD1 [1:1] PD2 [2:2] PD3 [3:3] PD4 [4:4] PD5 [5:5] PD6 [6:6] PD7 [7:7] PD8 [8:8] PD9 [9:9] PD10 [10:10] PD11 [11:11] PD12 [12:12] PD13 [13:13] PD14 [14:14] PD15 [15:15] PUCRC 0x30 PU0 [0:0] PU1 [1:1] PU2 [2:2] PU3 [3:3] PU4 [4:4] PU5 [5:5] PU6 [6:6] PU7 [7:7] PU8 [8:8] PU9 [9:9] PU10 [10:10] PU11 [11:11] PU12 [12:12] PU13 [13:13] PU14 [14:14] PU15 [15:15] PDCRC 0x34 PD0 [0:0] PD1 [1:1] PD2 [2:2] PD3 [3:3] PD4 [4:4] PD5 [5:5] PD6 [6:6] PD7 [7:7] PD8 [8:8] PD9 [9:9] PD10 [10:10] PD11 [11:11] PD12 [12:12] PD13 [13:13] PD14 [14:14] PD15 [15:15] PUCRD 0x38 PU0 [0:0] PU1 [1:1] PU2 [2:2] PU3 [3:3] PU4 [4:4] PU5 [5:5] PU6 [6:6] PU7 [7:7] PU8 [8:8] PU9 [9:9] PU10 [10:10] PU11 [11:11] PU12 [12:12] PU13 [13:13] PU14 [14:14] PU15 [15:15] PDCRD 0x3C PD0 [0:0] PD1 [1:1] PD2 [2:2] PD3 [3:3] PD4 [4:4] PD5 [5:5] PD6 [6:6] PD7 [7:7] PD8 [8:8] PD9 [9:9] PD10 [10:10] PD11 [11:11] PD12 [12:12] PD13 [13:13] PD14 [14:14] PD15 [15:15] RCC Reset and clock control 0x40021000 0x0 0x400 registers RCC RCC global Interrupts 4 CR Clock control register 0x0 MSIDIV [2:0] HSIKERON [6:6] MSION [7:7] HSION [8:8] MSIRDY [9:9] read-only HSIRDY [10:10] read-only HSIDIV [13:11] HSEON [16:16] HSERDY [17:17] read-only HSEBYP [18:18] HSE_CSSON [19:19] PLLON [24:24] PLLRDY [25:25] read-only ICSCR Internal clock sources calibration register 0x4 HSI_TRIMCR [12:0] HSI_FS_OP [15:13] CFGR Clock configuration register 0x8 SW [2:0] SWS [5:3] HPRE [11:8] PPRE [14:12] MCOSEL [27:24] MCOPRE [31:28] PLLCFGR PLL configuration register 0xC PLLSRC [0:0] PLLMUL [6:2] ECSCR External clock source control register 0x10 HSE_DRV [1:0] HSE_RDYSEL [3:2] HSE_FILT_EN [4:4] CIER Clock interrupt enable register 0x18 LSIRDYIE [0:0] LSERDYIE [1:1] MSIRDYIE [2:2] HSIRDYIE [3:3] HSERDYIE [4:4] PLLRDYIE [5:5] CIFR Clock interrupt flag register 0x1C LSIRDYF [0:0] read-only LSERDYF [1:1] read-only HSIRDYF [3:3] read-only HSERDYF [4:4] read-only PLLRDYF [5:5] read-only CSSF [8:8] read-only LSECSSF [9:9] read-only CICR Clock interrupt clear register 0x20 LSIRDYC [0:0] write-only LSERDYC [1:1] write-only HSIRDYC [3:3] write-only HSERDYC [4:4] write-only PLLRDYC [5:5] write-only CSSC [8:8] write-only LSECSSC [9:9] write-only IOPRSTR GPIO reset register 0x24 GPIOARST [0:0] GPIOBRST [1:1] GPIOCRST [2:2] GPIODRST [3:3] AHBRSTR AHB peripheral reset register 0x28 DMARST [0:0] CRCRST [12:12] APBRSTR1 APB peripheral reset register 1 0x2C TIM2RST [0:0] TIM3RST [1:1] TIM6RST [4:4] TIM7RST [5:5] PWMRST [6:6] WWDGRST [11:11] SPI2RST [14:14] LPUART2RST [16:16] USART2RST [17:17] UART1RST [18:18] UART2RST [19:19] LPUART1RST [20:20] I2C1RST [21:21] I2C2RST [22:22] OPARST [23:23] CANRST [25:25] DBGRST [27:27] PWRRST [28:28] DACRST [29:29] LPTIM2RST [30:30] LPTIM1RST [31:31] APBRSTR2 APB peripheral reset register 2 0x30 SYSCFGRST [0:0] TIM1RST [11:11] SPI1RST [12:12] USART1RST [14:14] TIM15RST [16:16] TIM16RST [17:17] TIM17RST [18:18] ADCRST [20:20] COMP1RST [21:21] COMP2RST [22:22] LCDRST [24:24] TKRST [25:25] VREFBUFRST [26:26] IOPENR GPIO clock enable register 0x34 GPIOAEN [0:0] GPIOBEN [1:1] GPIOCEN [2:2] GPIODEN [3:3] AHBENR AHB peripheral clock enable register 0x38 DMAEN [0:0] FLASHEN [8:8] SRAMEN [9:9] CRCEN [12:12] APBENR1 APB peripheral clock enable register 1 0x3C TIM2EN [0:0] TIM3EN [1:1] TIM6EN [4:4] TIM7EN [5:5] PWMEN [6:6] WWDGEN [11:11] SPI2EN [14:14] LPUART2EN [16:16] USART2EN [17:17] UART1EN [18:18] UART2EN [19:19] LPUART1EN [20:20] I2C1EN [21:21] I2C2EN [22:22] OPAEN [23:23] CANEN [25:25] DBGEN [27:27] PWREN [28:28] DACEN [29:29] LPTIM2EN [30:30] LPTIM1EN [31:31] APBENR2 APB peripheral clock enable register 2 0x40 SYSCFGEN [0:0] TIM1EN [11:11] SPI1EN [12:12] USART1EN [14:14] TIM15EN [16:16] TIM16EN [17:17] TIM17EN [18:18] ADCEN [20:20] COMP1EN [21:21] COMP2EN [22:22] COMP3EN [23:23] LCDEN [24:24] TKEN [25:25] VREFBUFEN [26:26] CCIPR Peripherals independent clock configuration register 0x54 TIMCLKCTRL [0:0] CANSEL [6:5] PVDSEL [7:7] COMP1SEL [8:8] COMP2SEL [9:9] COMP3SEL [10:10] LPUART1SEL [12:11] LPUART2SEL [14:13] LPTIM1SEL [17:16] LPTIM2SEL [19:18] PWMSEL [21:21] ADCSEL [31:30] BDCR RTC domain control register 0x5C LSERDY [1:1] read-only LSEBYP [2:2] LSEDRV [4:3] LSECSSON [5:5] LSECSSD [6:6] read-only RTCSEL [9:8] LSEEN [13:10] LSCSEL [14:14] RTCEN [15:15] BDRST [16:16] LSI_TRIMCR [25:17] LSION [26:26] LSIRDY [27:27] read-only LSE_RDYSEL [29:28] IWDGSEL [30:30] CSR Control/status register 0x60 NRST_FLTDIS [8:8] RMVF [23:23] OBLRSTF [25:25] read-only PINRSTF [26:26] read-only PWRRSTF [27:27] read-only SFTRSTF [28:28] read-only IWDGRSTF [29:29] read-only WWDGRSTF [30:30] read-only LPWRRSTF [31:31] read-only RTC desc RTC 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 TR 0x0 SU [3:0] ST [6:4] MNU [11:8] MNT [14:12] HU [19:16] HT [21:20] PM [22:22] DR 0x4 DU [3:0] DT [5:4] MU [11:8] MT [12:12] WDU [15:13] YU [19:16] YT [23:20] SSR 0x8 SS [15:0] read-only ICSR 0xC ALRAWF [0:0] read-only ALRBWF [1:1] read-only WUTWF [2:2] read-only SHPF [3:3] read-only INITS [4:4] read-only RSF [5:5] INITF [6:6] read-only INIT [7:7] RECALPF [16:16] read-only PRER 0x10 PREDIV_S [14:0] PREDIV_A [22:16] WUTR 0x14 WUT [15:0] CR 0x18 WUCKSEL [2:0] TSEDGE [3:3] REFCKON [4:4] BYPSHAD [5:5] FMT [6:6] ALRAE [8:8] ALRBE [9:9] WUTE [10:10] TSE [11:11] ALRAIE [12:12] ALRBIE [13:13] WUTIE [14:14] TSIE [15:15] ADD1H [16:16] write-only SUB1H [17:17] write-only BKP [18:18] COSEL [19:19] POL [20:20] OSEL [22:21] COE [23:23] ITSE [24:24] TAMPTS [25:25] TAMPOE [26:26] TAMPALRM_PU [29:29] TAMPALRM_TYPE [30:30] WPR 0x24 KEY [7:0] CALR 0x28 CALM [8:0] CALW16 [13:13] CALW8 [14:14] CALP [15:15] SHIFTR 0x2C SUBFS [14:0] write-only ADD1S [31:31] write-only TSTR 0x30 SU [3:0] read-only ST [6:4] read-only MNU [11:8] read-only MNT [14:12] read-only HU [19:16] read-only HT [21:20] read-only PM [22:22] read-only TSDR 0x34 DU [3:0] read-only DT [5:4] read-only MU [11:8] read-only MT [12:12] read-only WDU [15:13] read-only TSSSR 0x38 SS [15:0] read-only ALRMAR 0x40 SU [3:0] ST [6:4] MSK1 [7:7] MNU [11:8] MNT [14:12] MSK2 [15:15] HU [19:16] HT [21:20] PM [22:22] MSK3 [23:23] DU [27:24] DT [29:28] WDSEL [30:30] MSK4 [31:31] ALRMASSR 0x44 SS [14:0] MASKSS [27:24] ALRMBR 0x48 SU [3:0] ST [6:4] MSK1 [7:7] MNU [11:8] MNT [14:12] MSK2 [15:15] HU [19:16] HT [21:20] PM [22:22] MSK3 [23:23] DU [27:24] DT [29:28] WDSEL [30:30] MSK4 [31:31] ALRMBSSR 0x4C SS [14:0] MASKSS [27:24] SR 0x50 ALRAF [0:0] read-only ALRBF [1:1] read-only WUTF [2:2] read-only TSF [3:3] read-only TSOVF [4:4] read-only ITSF [5:5] read-only MISR 0x54 ALRAMF [0:0] read-only ALRBMF [1:1] read-only WUTMF [2:2] read-only TSMF [3:3] read-only TSOVMF [4:4] read-only ITSMF [5:5] read-only SCR 0x5C CALRAF [0:0] write-only CALRBF [1:1] write-only CWUTF [2:2] write-only CTSF [3:3] write-only CTSOVF [4:4] write-only CITSF [5:5] write-only SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 desc CR1 0x0 CPHA Clock Phase [0:0] CPOL Clock Polarity [1:1] MSTR Master Selection [2:2] BR Baud Rate Control [5:3] SPE SPI Enable [6:6] LSBFIRST Frame Format [7:7] SSI Internal slave select [8:8] SSM Software slave management [9:9] RXONLY Receive only [10:10] DFF Data frame format [11:11] CRCEN Hardware CRC calculation enable [13:13] BIDIOE Output enable in bidirectional mode [14:14] BIDIMODE Bidirectional data mode enable [15:15] CR2 desc CR2 0x4 RXDMAEN Rx buffer DMA enable [0:0] TXDMAEN Tx buffer DMA enable [1:1] SSOE SS Output Enable [2:2] CLRTXFIFO Clear FIFO [4:4] ERRIE Error Interrupt Enable [5:5] RXNEIE RX buffer Not Empty Interrupt Enable [6:6] TXEIE Tx buffer Empty Interrupt Enable [7:7] FRXTH [12:12] FRF [15:15] SR desc SR 0x8 RXNE Receive buffer Not Empty [0:0] read-only TXE Transmit buffer Empty [1:1] read-only CHSIDE Channel side [2:2] read-only UDR Underrun flag [3:3] read-only CRCERR CRC error flag [4:4] MODF Mode fault [5:5] OVR Overrun flag [6:6] read-only BSY Busy flag [7:7] read-only FRE [8:8] read-only FRLVL FIFO Reception Level [10:9] read-only FTLVL FIFO Transmission Level [12:11] read-only DR desc DR 0xC DR Data Register [15:0] CRCPR desc CRCPR 0x10 CRCPOLY CRC polynomial register [15:0] RXCRCR desc RXCRCR 0x14 RXCRC rcv crc reg [15:0] read-only TXCRCR desc TXCRCR 0x18 TXCRC tx crc reg [15:0] read-only I2S_CFGR 0x1C CHLEN Channel length (number of bits per audio channel [0:0] DATLEN Data length to be transferred [2:1] CKPOL Steady state clock polarity [3:3] I2SSTD I2S standard selection [5:4] PCMSYNC PCM frame synchronization [7:7] I2SCFG I2S configuration mode [9:8] I2SE I2S enable [10:10] I2SMOD I2S mode selection [11:11] I2SPR desc I2SPR 0x20 I2SDIV I2S linear prescaler [7:0] ODD Odd factor for the prescaler [8:8] MCKOE Master clock output enable [9:9] SPI2 0x40003800 SPI2 SPI2 global Interrupt 26 SYSCFG desc SYSCFG 0x40010000 0x0 0x200 registers CFGR1 desc CFGR1 0x0 MEM_MODE [1:0] TK_LP_TRIG [9:8] RTC_TRIG_TKSEL [11:10] LPTIM1_TRIG_TKEN [12:12] LPTIM2_TRIG_TKEN [13:13] GPIO_AHB_SEL [24:24] CFGR2 desc CFGR2 0x4 CLL [0:0] SPL [1:1] PVDL [2:2] ECCL [3:3] CFGR3 desc CFGR3 0x8 DMA1_MAP [5:0] DMA2_MAP [13:8] DMA3_MAP [21:16] DMA4_MAP [29:24] PA_ENS_REG 0x20 PA_ENS [15:0] PB_ENS_REG 0x24 PB_ENS [15:0] PC_ENS_REG 0x28 PC_ENS [15:0] PD_ENS_REG 0x2C PD_ENS [13:0] IOCFG 0x38 PA_EIIC [3:0] PB_EIIC [13:8] PD_EIIC_10 [14:14] PD_EIIC_11 [15:15] PC_EIIC [24:16] PD_EIIC [29:26] PD_PU_IIC [31:30] LEDCFG 0x3C SEGIS_EN [3:0] PB_EHS [15:8] PB_ENSEG [29:16] PC_ENSEG [31:30] PA_ANA2EN 0x40 PA_ANA2EN [15:0] PB_ANA2EN 0x44 PB_ANA2EN [15:0] PC_ANA2EN 0x48 PC_ANA2EN [15:0] PD_ANA2EN 0x4C PD_ANA2EN [13:0] SCSR 0x70 PERR_RSTEN [0:0] SPF [8:8] SWPR 0x74 SRAM_P0WP [0:0] SRAM_P1WP [1:1] SRAM_P2WP [2:2] SRAM_P3WP [3:3] SRAM_P4WP [4:4] SRAM_P5WP [5:5] SRAM_P6WP [6:6] SRAM_P7WP [7:7] SRAM_P8WP [8:8] SRAM_P9WP [9:9] SRAM_P10WP [10:10] SRAM_P11WP [11:11] SRAM_P12WP [12:12] SRAM_P13WP [13:13] SRAM_P14WP [14:14] SRAM_P15WP [15:15] SRAM_P16WP [16:16] SRAM_P17WP [17:17] SRAM_P18WP [18:18] SRAM_P19WP [19:19] SRAM_P20WP [20:20] SRAM_P21WP [21:21] SRAM_P22WP [22:22] SRAM_P23WP [23:23] SRAM_P24WP [24:24] SRAM_P25WP [25:25] SRAM_P26WP [26:26] SRAM_P27WP [27:27] SRAM_P28WP [28:28] SRAM_P29WP [29:29] SRAM_P30WP [30:30] SRAM_P31WP [31:31] TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 desc CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 desc CR2 0x4 CCPC [0:0] CCUS [2:2] CCDS [3:3] MMS_L [6:4] TI1S [7:7] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] OIS2N [11:11] OIS3 [12:12] OIS3N [13:13] OIS4 [14:14] MMS_H [25:25] SMCR desc SMCR 0x8 SMS_L [2:0] OCCS [3:3] TS_L [6:4] MSM [7:7] ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] SMS_H [16:16] TS_H [21:20] DIER desc DIER 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] COMIE [5:5] TIE [6:6] BIE [7:7] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] COMDE [13:13] TDE [14:14] SR desc SR 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] COMIF [5:5] TIF [6:6] BIF [7:7] B2IF [8:8] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] SBIF [13:13] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR desc EGR 0x14 UG [0:0] read-only CC1G [1:1] read-only CC2G [2:2] read-only CC3G [3:3] read-only CC4G [4:4] read-only COMG [5:5] read-only TG [6:6] read-only BG [7:7] read-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M_L [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M_L [14:12] OC2CE [15:15] OC1M_H [16:16] OC2M_H [24:24] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C CC3S [1:0] OC3FE [2:2] OC3PE [3:3] OC3M_L [6:4] OC3CE [7:7] CC4S [9:8] OC4FE [10:10] OC4PE [11:11] OC4M_L [14:12] OC4CE [15:15] OC3M_H [16:16] OC4M_H [24:24] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C CC3S [1:0] IC3PSC [3:2] IC3F [7:4] CC4S [9:8] IC4PSC [11:10] IC4F [15:12] TIMXCCER 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NE [6:6] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NE [10:10] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CNT desc CNT 0x24 CNT [15:0] PSC desc PSC 0x28 PSC [15:0] ARR desc ARR 0x2C ARR [15:0] RCR desc RCR 0x30 REP [7:0] CCR1 desc CCR1 0x34 CCR1 [15:0] CCR2 desc CCR2 0x38 CCR2 [15:0] CCR3 desc CCR3 0x3C CCR3 [15:0] CCR4 desc CCR4 0x40 CCR4 [15:0] BDTR desc BDTR 0x44 DTG [7:0] LOCK [9:8] OSSI [10:10] OSSR [11:11] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] TISEL 0x5C TI1SEL [3:0] TI2SEL [11:8] TI3SEL [19:16] TI4SEL [27:24] AF1 0x60 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] ETRSEL [17:14] AF2 0x64 OCRSEL [18:16] DCR desc DCR 0x3DC DBA [4:0] DBL [12:8] DMAR desc DMAR 0x3E0 DMAB [31:0] TIM2 desc TIM TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global Interrupt 15 CR1 desc CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] DIR [4:4] CMS [6:5] ARPE [7:7] CKD [9:8] CR2 desc CR2 0x4 CCDS [3:3] MMS_L [6:4] TI1S [7:7] MMS_H [25:25] SMCR desc SMCR 0x8 SMS [2:0] OCCS [3:3] TS_L [6:4] MSM [7:7] ETF [11:8] ETPS [13:12] ECE [14:14] ETP [15:15] TS_H [21:20] DIER desc DIER 0xC UIE [0:0] CC1IE [1:1] CC2IE [2:2] CC3IE [3:3] CC4IE [4:4] TIE [6:6] UDE [8:8] CC1DE [9:9] CC2DE [10:10] CC3DE [11:11] CC4DE [12:12] TDE [14:14] SR desc SR 0x10 UIF [0:0] CC1IF [1:1] CC2IF [2:2] CC3IF [3:3] CC4IF [4:4] TIF [6:6] CC1OF [9:9] CC2OF [10:10] CC3OF [11:11] CC4OF [12:12] IC1IR [18:18] IC2IR [19:19] IC3IR [24:24] IC4IR [25:25] IC1IF [26:26] IC2IF [27:27] IC3IF [28:28] IC4IF [29:29] EGR desc EGR 0x14 UG [0:0] read-only CC1G [1:1] read-only CC2G [2:2] read-only CC3G [3:3] read-only CC4G [4:4] read-only TG [6:6] read-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M [6:4] OC1CE [7:7] CC2S [9:8] OC2FE [10:10] OC2PE [11:11] OC2M [14:12] OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C CC3S [1:0] OC3FE [2:2] OC3PE [3:3] OC3M [6:4] OC3CE [7:7] CC4S [9:8] OC4FE [10:10] OC4PE [11:11] OC4M [14:12] OC4CE [15:15] CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C CC3S [1:0] IC3PSC [3:2] IC3F [7:4] CC4S [9:8] IC4PSC [11:10] IC4F [15:12] CCER desc CCER 0x20 CC1E [0:0] CC1P [1:1] CC1NP [3:3] CC2E [4:4] CC2P [5:5] CC2NP [7:7] CC3E [8:8] CC3P [9:9] CC3NP [11:11] CC4E [12:12] CC4P [13:13] CC4NP [15:15] CNT desc CNT 0x24 CNT [31:0] PSC desc PSC 0x28 PSC [15:0] ARR desc ARR 0x2C ARR [31:0] CCR1 desc CCR1 0x34 CCR1 [31:0] CCR2 desc CCR2 0x38 CCR2 [31:0] CCR3 desc CCR3 0x3C CCR3 [31:0] CCR4 desc CCR4 0x40 CCR4 [31:0] TISEL 0x5C TI1SEL [3:0] TI2SEL [11:8] TI3SEL [19:16] TI4SEL [27:24] AF1 0x60 ETRSEL [17:14] AF2 0x64 OCRSEL [18:16] TIMXDCR 0x3DC DBA [4:0] DBL [12:8] DMAR desc DMAR 0x3E0 DMAB [31:0] TIM3 General purpose timer 0x40000400 TIM3 TIM3 global Interrupt 16 TIM6 desc TIM TIM 0x40001000 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR1 desc CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] ARPE [7:7] DIER desc DIER 0xC UIE [0:0] UDE [8:8] SR desc SR 0x10 UIF [0:0] EGR desc EGR 0x14 UG [0:0] read-only CNT desc CNT 0x24 CNT [31:0] PSC desc PSC 0x28 PSC [15:0] ARR desc ARR 0x2C ARR [31:0] read-only TIM7 desc TIM 0x40001400 TIM7_LPTIM2 TIM7/LPTIM2 global Interrupt 18 TIM14 General purpose timer TIM 0x40002000 0x0 0x400 registers CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] TIF desc TIF [6:6] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] OR desc OR 0x50 TI1_RMP desc TI1_RMP [1:0] TIM15 0x40014000 0x0 0x400 registers TIM15 TIM15 global Interrupt 20 CR1 desc CR1 0x0 0x3FF CEN desc CEN [0:0] UDIS desc UDIS [1:1] URS desc URS [2:2] OPM desc OPM [3:3] DIR desc DIR [4:4] CMS desc CMS [6:5] ARPE desc ARPE [7:7] CKD desc CKD [9:8] CR2 desc CR2 0x4 0xF8 CCDS desc CCDS [3:3] MMS desc MMS [6:4] TI1S desc TI1S [7:7] SMCR desc SMCR 0x8 0xFFF7 SMS desc SMS [2:0] TS desc TS [6:4] MSM desc MSM [7:7] ETF desc ETF [11:8] ETPS desc ETPS [13:12] ECE desc ECE [14:14] ETP desc ETP [15:15] DIER desc DIER 0xC 0x5F5F UIE desc UIE [0:0] CC1IE desc CC1IE [1:1] CC2IE desc CC2IE [2:2] CC3IE desc CC3IE [3:3] CC4IE desc CC4IE [4:4] TIE desc TIE [6:6] UDE desc UDE [8:8] CC1DE desc CC1DE [9:9] CC2DE desc CC2DE [10:10] CC3DE desc CC3DE [11:11] CC4DE desc CC4DE [12:12] TDE desc TDE [14:14] SR desc SR 0x10 0x1E5F UIF desc UIF [0:0] CC1IF desc CC1IF [1:1] CC2IF desc CC2IF [2:2] CC3IF desc CC3IF [3:3] CC4IF desc CC4IF [4:4] COMIF desc COMIF [5:5] TIF desc TIF [6:6] BIF desc BIF [7:7] CC1OF desc CC1OF [9:9] CC2OF desc CC2OF [10:10] CC3OF desc CC3OF [11:11] CC4OF desc CC4OF [12:12] IC1IR desc IC1IR [16:16] IC2IR desc IC2IR [17:17] IC3IR desc IC3IR [18:18] IC4IR desc IC3IR [19:19] IC1IF desc IC1IF [20:20] IC2IF desc IC2IF [21:21] IC3IF desc IC3IF [22:22] IC4IF desc IC3IF [23:23] EGR desc EGR 0x14 write-only 0x5F UG desc UG [0:0] write-only CC1G Capture/Compare 1 Generation [1:1] write-only CC2G desc CC2G [2:2] write-only CC3G desc CC3G [3:3] write-only CC4G desc CC4G [4:4] write-only TG desc TG [6:6] write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] OC1FE desc OC1FE [2:2] OC1PE desc OC1PE [3:3] OC1M desc OC1M [6:4] OC1CE desc OC1CE [7:7] CC2S desc CC2S [9:8] OC2FE desc OC2FE [10:10] OC2PE desc OC2PE [11:11] OC2M desc OC2M [14:12] OC2CE desc OC2CE [15:15] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 0xFFFF CC1S desc CC1S [1:0] IC1PSC desc IC1PSC [3:2] IC1F desc IC1F [7:4] CC2S desc CC2S [9:8] IC2PSC desc IC2PSC [11:10] IC2F desc IC2F [15:12] CCER desc CCER 0x20 0x3333 CC1E desc CC1E [0:0] CC1P desc CC1P [1:1] CC2E desc CC2E [4:4] CC2P desc CC2P [5:5] CC3E desc CC3E [8:8] CC3P desc CC3P [9:9] CC4E desc CC4E [12:12] CC4P desc CC4P [13:13] CNT desc CNT 0x24 0xFFFF CNT desc CNT [15:0] PSC desc PSC 0x28 0xFFFF PSC desc PSC [15:0] ARR desc ARR 0x2C 0xFFFF 0xFFFF ARR desc ARR [15:0] RCR desc RCR 0x30 0xFFFF 0xFFFF REP desc REP [7:0] CCR1 desc CCR1 0x34 0xFFFF CCR1 desc CCR1 [15:0] CCR2 desc CCR2 0x38 0xFFFF CCR2 desc CCR2 [15:0] BDTR desc BDTR 0x44 0xFFFF DTG desc DTG [7:0] LOCK desc LOCK [9:8] OSSI desc OSSI [10:10] OSSR desc OSSR [11:11] BKE desc BKE [12:12] BKP desc BKP [13:13] AOE desc AOE [14:14] MOE desc MOE [15:15] DCR desc DCR 0x48 0x1F1F DBA desc DBA [4:0] DBL desc DBL [12:8] DMAR desc DMAR 0x4C 0xFFFF DMAB desc DMAB [15:0] TIM16 General purpose timer TIM 0x40014400 0x0 0x400 registers TIM16 TIM16 global Interrupt 21 CR1 desc CR1 0x0 CEN [0:0] UDIS [1:1] URS [2:2] OPM [3:3] ARPE [7:7] CKD [9:8] CR2 desc CR2 0x4 CCPC [0:0] CCDS [3:3] MMS [6:4] OIS1 [8:8] OIS1N [9:9] OIS2 [10:10] DIER desc DIER 0xC UIE [0:0] CC1IE [1:1] COMIE [5:5] BIE [7:7] UDE [8:8] CC1DE [9:9] SR desc SR 0x10 UIF [0:0] CC1IF [1:1] COMIF [5:5] BIF [7:7] CC1OF [9:9] IC1IR [16:16] IC1IF [20:20] EGR desc EGR 0x14 UG [0:0] read-only CC1G [1:1] read-only COMG [5:5] read-only BG [7:7] read-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 CC1S [1:0] OC1FE [2:2] OC1PE [3:3] OC1M [6:4] OC1CE [7:7] CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 CC1S [1:0] IC1PSC [3:2] IC1F [7:4] CC2S [9:8] IC2PSC [11:10] IC2F [15:12] CCER desc CCER 0x20 CC1E [0:0] CC1P [1:1] CC1NE [2:2] CC1NP [3:3] CNT desc CNT 0x24 CNT [15:0] PSC desc PSC 0x28 PSC [15:0] ARR desc ARR 0x2C ARR [15:0] RCR desc RCR 0x30 REP [7:0] CCR1 desc CCR1 0x34 CCR1 [15:0] BDTR desc BDTR 0x44 DTG [7:0] LOCK [9:8] OSSI [10:10] OSSR [11:11] BKE [12:12] BKP [13:13] AOE [14:14] MOE [15:15] TISEL 0x5C TI1SEL [3:0] AF1 0x60 BKINE [0:0] BKCMP1E [1:1] BKCMP2E [2:2] BKINP [9:9] BKCMP1P [10:10] BKCMP2P [11:11] TIMXDCR 0x3DC DBA [4:0] DBL [12:8] DMAR desc DMAR 0x3E0 DMAB [31:0] TIM17 0x40014800 TIM17 TIM17 global Interrupt 22 TK 0x40012800 0x0 0x110 registers CR1 0x0 EN [0:0] EXTCMODEN [3:3] ICOPA [4:4] COPAMODE [5:5] COPADATA [7:6] VCC1SEL [13:11] MIDACSTEP [14:14] SIDACSTEP [15:15] CFT [18:16] INTCMODEN [20:20] CMPHYSEN Comparetor Hysteresis Enable [21:21] BUFFEREN Buffer Enable [22:22] DIV TK_CLK Division [26:24] STDIV ST_CLK Division [30:27] INTEREN Internal Enable [31:31] CR2 0x4 START [0:0] RSTB [1:1] SWCTRL [2:2] CMODCHRG [3:3] CMODISCH [4:4] MIDACEN [5:5] SIDACEN [6:6] PWMM [8:8] CTRLSOURCE [9:9] LPABNORMAL [10:10] SHORTSW_NUM [13:12] LPEN [14:14] KVREF [17:16] LFSRW [23:20] CMODCOPA [29:29] CMODCS [30:30] CMODEN [31:31] IDACR 0x8 MIDAC [7:0] SIDAC [23:16] KR 0xC KEN [31:0] CSR 0x10 CHS [31:0] UCR 0x14 COPAMODEIO [31:0] STR 0x18 SETTIME [9:0] WR 0x20 WIN [15:0] SDR 0x24 SWDIV [8:0] PRSR 0x28 LFSRP [15:0] SEED [31:16] DR 0x2C DATA [15:0] read-only SR 0x30 SENSEDONE [0:0] read-only CMPOUT [1:1] read-only SHORTSWERR [2:2] read-only IER 0x34 EVTINTEN [0:0] ERRINTEN [1:1] ICR 0x38 EVTINTCLR [0:0] ERRINTCLR [1:1] CDR 0x3C CDATA [15:0] LPDR 0x40 NORMALDELTA [9:0] ABNORMALDELTA [25:16] LPTR 0x44 LPWAIT [6:0] OPR 0x48 OP [5:0] TR 0x100 TMODE [2:0] DBGSEL [19:16] DDR 0x104 SHORTSW_DATA [9:0] read-only UART1 UART 0x40004800 0x0 0x30 registers UART1_LPUART1 UART1/LPUART1 global Interrupt 29 DR 0x0 DR Receive/send data register [8:0] BRR 0x4 BRR Baud rate register [15:0] SR 0x10 RXNE Receive register not empty [0:0] read-only ORE Overrun error bit [1:1] PE Parity Error bit [2:2] FE Framing Error bit [3:3] BRI Break Interrupt bit [4:4] TDRE Transmit Holding Register Empty bit [5:5] read-only TXE Transmitter Empty bit [6:6] read-only ADDR_RCVD Address Received Bit [8:8] BUSY UART Busy [9:9] read-only BUSY_ERR Busy Detect Error [10:10] CR1 0x14 M Data Length Select [1:0] STOP Number of stop bits [2:2] PCE Parity Enable [3:3] PS Even Parity Select [4:4] SP Stick Parity [5:5] SBK Send Break [6:6] SWAP TX/RX pin swap [8:8] MSBFIRST MSB first mode [9:9] CR2 0x18 RXNEIE Enable Received Data Available Interrupt [0:0] TDREIE Enable Transmit Holding Register Empty Interrupt [1:1] LSIE Enable Receiver Line Status Interrupt [2:2] BUSYERRIE Enable Busyerr state interruption [3:3] TXEIE Enable tx empty interruption [4:4] CR3 0x1C M_E Extension for DLS [0:0] ADDR_MATCH Address Match Mode [1:1] SEND_ADDR Send address control bit [2:2] TX_MODE Transmit mode control bit [3:3] DMAR DMA receive enable [4:4] DMAT DMA transmit enable [5:5] DMA_SOFT_ACK DMA software ack [6:6] RAR 0x20 RAR Receive address matching register [7:0] TAR 0x24 TAR Transmit address matching register [7:0] BRRF 0x28 BRRF Baud rate fractional register [3:0] UART2 0x40004C00 UART2_LPUART2 UART2/LPUART2 global Interrupt 30 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR desc SR 0x0 PE Parity error [0:0] read-only FE Framing error [1:1] read-only NE Noise error flag [2:2] read-only ORE overrun error [3:3] read-only IDLE idle [4:4] read-only RXNE Read data register not empty [5:5] read-only TC Transmission complete [6:6] read-only TXE Transmit data register empty [7:7] read-only LBD LIN break detection flag [8:8] CTS cts flag [9:9] ABRF auto baud rate flag [10:10] read-only ABRE auto baud rateerror [11:11] read-only ABRQ auto baud rate req [12:12] read-only EOBF end of block flag [18:18] RTOF rto flag [19:19] TXPE [20:20] RXBUSY [21:21] read-only TXBUSY [22:22] read-only WAIT_RPT [23:23] read-only TXLSEF [31:31] read-only DR desc DR 0x4 DR dr [8:0] BRR desc BRR 0x8 DIV_FRACTION DIV_Fraction [3:0] DIV_MANTISSA DIV_Mantissa [15:4] CR1 desc CR1 0xC SBK Send break [0:0] RWU Receiver wakeup [1:1] RE Receiver enable [2:2] TE Transmitter enable [3:3] IDLEIE IDLE interrupt enable [4:4] RXNEIE RXNE interrupt enable [5:5] TCIE send complete int enable [6:6] TXEIE txe [7:7] PEIE PE interrupt enable [8:8] PS Parity selection [9:9] PCE Parity control enable [10:10] WAKE Wakeup method [11:11] M word length [12:12] UE uesart enable [13:13] MSBFIRST msbfirst [15:15] SWAP swap [18:18] DATAINV data inverse [27:27] CR2 desc CR2 0x10 ADD mute addr [3:0] LBDL LIN break detection length [5:5] LBDIE lin break enable [6:6] LBCL lbcl [8:8] CPHA cpha [9:9] CPOL cpol [10:10] CLKEN clk en [11:11] STOP stop bit [13:12] LINEN lin enable [14:14] RTOEN Receiver timeout enable [25:25] ERSW error select width [27:26] REP_T repeat times [28:28] TREPEN tx repeat enable [29:29] RREPEN [30:30] CR3 desc CR3 0x14 EIE error int enable [0:0] IREN iren enable [1:1] IRLP idra lowpower [2:2] HDSEL hdsel [3:3] NACK scen nack enable [4:4] SCEN scen enable [5:5] DMAR dma rx enable [6:6] DMAT dma tx enable [7:7] RTSE rts enable [8:8] CTSE cts enable [9:9] CTSIE cts int enable [10:10] OVER8 oversampling [11:11] ABREN autobaud enable [12:12] ABRMOD auto baud mod [14:13] RTOIE rto int enable [29:29] EOBIE eob int enable [30:30] TXLSEIE tx register empty int enable [31:31] GTPR desc GTPR 0x18 PSC Prescaler value [7:0] GT Guard time value [15:8] RTOR 0x1C RTO receive timeout [23:0] BLEN blocken length [31:24] USART2 0x40004400 USART2 USART2 global Interrupt 28 VREFBUF 0x40010800 0x0 0x10 registers CR 0x0 VREFBUF_OUT_SEL [2:0] VREFBUF_EN [3:3] WWDG Window watchdog 0x40002C00 0x0 0x400 registers WWDG Window WatchDog Interrupt 0 CR Control register (WWDG_CR) 0x0 T WWDG counter [6:0] WDGA WWDG Activation [7:7] CFR Configuration register (WWDG_CFR) 0x4 W window value [6:0] WDGTB Time base [8:7] EWI Early wakeup interrupt [9:9] SR Status register (WWDG_SR) 0x8 16 EWIF Early wakeup interrupt flag [0:0]