/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F033xx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:15:01 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F033xx.svd',
* last modified on Wed Mar 25 15:16:00 2026
*/
// ----------------------------- Register Item Address: ADC_ISR ---------------------------------
// SVD Line: 40
unsigned int ADC_ISR __AT (0x40012400);
// -------------------------------- Field Item: ADC_ISR_ADRDY -----------------------------------
// SVD Line: 45
// - SFDITEM_FIELD__ADC_ISR_ADRDY
// ADRDY
//
// [Bit 0] RW (@ 0x40012400) ADRDY
//
// ( (unsigned int) ADC_ISR )
// ADRDY
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOSMP -----------------------------------
// SVD Line: 49
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// EOSMP
//
// [Bit 1] RW (@ 0x40012400) EOSMP
//
// ( (unsigned int) ADC_ISR )
// EOSMP
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOC ------------------------------------
// SVD Line: 53
// - SFDITEM_FIELD__ADC_ISR_EOC
// EOC
//
// [Bit 2] RW (@ 0x40012400) EOC
//
// ( (unsigned int) ADC_ISR )
// EOC
//
//
//
// --------------------------------- Field Item: ADC_ISR_EOS ------------------------------------
// SVD Line: 57
// - SFDITEM_FIELD__ADC_ISR_EOS
// EOS
//
// [Bit 3] RW (@ 0x40012400) EOS
//
// ( (unsigned int) ADC_ISR )
// EOS
//
//
//
// --------------------------------- Field Item: ADC_ISR_OVR ------------------------------------
// SVD Line: 61
// - SFDITEM_FIELD__ADC_ISR_OVR
// OVR
//
// [Bit 4] RW (@ 0x40012400) OVR
//
// ( (unsigned int) ADC_ISR )
// OVR
//
//
//
// -------------------------------- Field Item: ADC_ISR_JEOC ------------------------------------
// SVD Line: 65
// - SFDITEM_FIELD__ADC_ISR_JEOC
// JEOC
//
// [Bit 5] RW (@ 0x40012400) JEOC
//
// ( (unsigned int) ADC_ISR )
// JEOC
//
//
//
// -------------------------------- Field Item: ADC_ISR_JEOS ------------------------------------
// SVD Line: 69
// - SFDITEM_FIELD__ADC_ISR_JEOS
// JEOS
//
// [Bit 6] RW (@ 0x40012400) JEOS
//
// ( (unsigned int) ADC_ISR )
// JEOS
//
//
//
// --------------------------------- Field Item: ADC_ISR_AWD ------------------------------------
// SVD Line: 73
// - SFDITEM_FIELD__ADC_ISR_AWD
// AWD
//
// [Bit 7] RW (@ 0x40012400) AWD
//
// ( (unsigned int) ADC_ISR )
// AWD
//
//
//
// -------------------------------- Field Item: ADC_ISR_EOCAL -----------------------------------
// SVD Line: 77
// - SFDITEM_FIELD__ADC_ISR_EOCAL
// EOCAL
//
// [Bit 11] RW (@ 0x40012400) EOCAL
//
// ( (unsigned int) ADC_ISR )
// EOCAL
//
//
//
// --------------------------------- Register RTree: ADC_ISR ------------------------------------
// SVD Line: 40
// SFDITEM_REG__ADC_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40012400) ADC interrupt and status register
// ( (unsigned int)((ADC_ISR >> 0) & 0xFFFFFFFF), ((ADC_ISR = (ADC_ISR & ~(0x8FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8FF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_ISR_ADRDY
// - SFDITEM_FIELD__ADC_ISR_EOSMP
// - SFDITEM_FIELD__ADC_ISR_EOC
// - SFDITEM_FIELD__ADC_ISR_EOS
// - SFDITEM_FIELD__ADC_ISR_OVR
// - SFDITEM_FIELD__ADC_ISR_JEOC
// - SFDITEM_FIELD__ADC_ISR_JEOS
// - SFDITEM_FIELD__ADC_ISR_AWD
// - SFDITEM_FIELD__ADC_ISR_EOCAL
//
//
// ----------------------------- Register Item Address: ADC_IER ---------------------------------
// SVD Line: 83
unsigned int ADC_IER __AT (0x40012404);
// ------------------------------- Field Item: ADC_IER_ADRDYIE ----------------------------------
// SVD Line: 88
// - SFDITEM_FIELD__ADC_IER_ADRDYIE
// ADRDYIE
//
// [Bit 0] RW (@ 0x40012404) ADRDYIE
//
// ( (unsigned int) ADC_IER )
// ADRDYIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOSMPIE ----------------------------------
// SVD Line: 92
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// EOSMPIE
//
// [Bit 1] RW (@ 0x40012404) EOSMPIE
//
// ( (unsigned int) ADC_IER )
// EOSMPIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOCIE -----------------------------------
// SVD Line: 96
// - SFDITEM_FIELD__ADC_IER_EOCIE
// EOCIE
//
// [Bit 2] RW (@ 0x40012404) EOCIE
//
// ( (unsigned int) ADC_IER )
// EOCIE
//
//
//
// -------------------------------- Field Item: ADC_IER_EOSIE -----------------------------------
// SVD Line: 100
// - SFDITEM_FIELD__ADC_IER_EOSIE
// EOSIE
//
// [Bit 3] RW (@ 0x40012404) EOSIE
//
// ( (unsigned int) ADC_IER )
// EOSIE
//
//
//
// -------------------------------- Field Item: ADC_IER_OVRIE -----------------------------------
// SVD Line: 104
// - SFDITEM_FIELD__ADC_IER_OVRIE
// OVRIE
//
// [Bit 4] RW (@ 0x40012404) OVRIE
//
// ( (unsigned int) ADC_IER )
// OVRIE
//
//
//
// ------------------------------- Field Item: ADC_IER_JEOCIE -----------------------------------
// SVD Line: 108
// - SFDITEM_FIELD__ADC_IER_JEOCIE
// JEOCIE
//
// [Bit 5] RW (@ 0x40012404) JEOCIE
//
// ( (unsigned int) ADC_IER )
// JEOCIE
//
//
//
// ------------------------------- Field Item: ADC_IER_JEOSIE -----------------------------------
// SVD Line: 112
// - SFDITEM_FIELD__ADC_IER_JEOSIE
// JEOSIE
//
// [Bit 6] RW (@ 0x40012404) JEOSIE
//
// ( (unsigned int) ADC_IER )
// JEOSIE
//
//
//
// -------------------------------- Field Item: ADC_IER_AWDIE -----------------------------------
// SVD Line: 116
// - SFDITEM_FIELD__ADC_IER_AWDIE
// AWDIE
//
// [Bit 7] RW (@ 0x40012404) AWDIE
//
// ( (unsigned int) ADC_IER )
// AWDIE
//
//
//
// ------------------------------- Field Item: ADC_IER_EOCALIE ----------------------------------
// SVD Line: 120
// - SFDITEM_FIELD__ADC_IER_EOCALIE
// EOCALIE
//
// [Bit 11] RW (@ 0x40012404) EOCALIE
//
// ( (unsigned int) ADC_IER )
// EOCALIE
//
//
//
// --------------------------------- Register RTree: ADC_IER ------------------------------------
// SVD Line: 83
// SFDITEM_REG__ADC_IER
// IER
//
// [Bits 31..0] RW (@ 0x40012404) ADC interrupt enable register
// ( (unsigned int)((ADC_IER >> 0) & 0xFFFFFFFF), ((ADC_IER = (ADC_IER & ~(0x8FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8FF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_IER_ADRDYIE
// - SFDITEM_FIELD__ADC_IER_EOSMPIE
// - SFDITEM_FIELD__ADC_IER_EOCIE
// - SFDITEM_FIELD__ADC_IER_EOSIE
// - SFDITEM_FIELD__ADC_IER_OVRIE
// - SFDITEM_FIELD__ADC_IER_JEOCIE
// - SFDITEM_FIELD__ADC_IER_JEOSIE
// - SFDITEM_FIELD__ADC_IER_AWDIE
// - SFDITEM_FIELD__ADC_IER_EOCALIE
//
//
// ------------------------------ Register Item Address: ADC_CR ---------------------------------
// SVD Line: 126
unsigned int ADC_CR __AT (0x40012408);
// --------------------------------- Field Item: ADC_CR_ADEN ------------------------------------
// SVD Line: 131
// - SFDITEM_FIELD__ADC_CR_ADEN
// ADEN
//
// [Bit 0] RW (@ 0x40012408) ADEN
//
// ( (unsigned int) ADC_CR )
// ADEN
//
//
//
// -------------------------------- Field Item: ADC_CR_ADDIS ------------------------------------
// SVD Line: 135
// - SFDITEM_FIELD__ADC_CR_ADDIS
// ADDIS
//
// [Bit 1] RW (@ 0x40012408) ADDIS
//
// ( (unsigned int) ADC_CR )
// ADDIS
//
//
//
// ------------------------------- Field Item: ADC_CR_ADSTART -----------------------------------
// SVD Line: 139
// - SFDITEM_FIELD__ADC_CR_ADSTART
// ADSTART
//
// [Bit 2] RW (@ 0x40012408) ADSTART
//
// ( (unsigned int) ADC_CR )
// ADSTART
//
//
//
// ------------------------------- Field Item: ADC_CR_JADSTART ----------------------------------
// SVD Line: 143
// - SFDITEM_FIELD__ADC_CR_JADSTART
// JADSTART
//
// [Bit 3] RW (@ 0x40012408) JADSTART
//
// ( (unsigned int) ADC_CR )
// JADSTART
//
//
//
// -------------------------------- Field Item: ADC_CR_ADSTP ------------------------------------
// SVD Line: 147
// - SFDITEM_FIELD__ADC_CR_ADSTP
// ADSTP
//
// [Bit 4] RW (@ 0x40012408) ADSTP
//
// ( (unsigned int) ADC_CR )
// ADSTP
//
//
//
// -------------------------------- Field Item: ADC_CR_JADSTP -----------------------------------
// SVD Line: 151
// - SFDITEM_FIELD__ADC_CR_JADSTP
// JADSTP
//
// [Bit 5] RW (@ 0x40012408) JADSTP
//
// ( (unsigned int) ADC_CR )
// JADSTP
//
//
//
// -------------------------------- Field Item: ADC_CR_RSTCAL -----------------------------------
// SVD Line: 155
// - SFDITEM_FIELD__ADC_CR_RSTCAL
// RSTCAL
//
// [Bit 27] RW (@ 0x40012408) RSTCAL
//
// ( (unsigned int) ADC_CR )
// RSTCAL
//
//
//
// -------------------------------- Field Item: ADC_CR_ADCAL ------------------------------------
// SVD Line: 159
// - SFDITEM_FIELD__ADC_CR_ADCAL
// ADCAL
//
// [Bit 31] RW (@ 0x40012408) ADCAL
//
// ( (unsigned int) ADC_CR )
// ADCAL
//
//
//
// --------------------------------- Register RTree: ADC_CR -------------------------------------
// SVD Line: 126
// SFDITEM_REG__ADC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40012408) ADC control register
// ( (unsigned int)((ADC_CR >> 0) & 0xFFFFFFFF), ((ADC_CR = (ADC_CR & ~(0x8800003FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8800003F) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CR_ADEN
// - SFDITEM_FIELD__ADC_CR_ADDIS
// - SFDITEM_FIELD__ADC_CR_ADSTART
// - SFDITEM_FIELD__ADC_CR_JADSTART
// - SFDITEM_FIELD__ADC_CR_ADSTP
// - SFDITEM_FIELD__ADC_CR_JADSTP
// - SFDITEM_FIELD__ADC_CR_RSTCAL
// - SFDITEM_FIELD__ADC_CR_ADCAL
//
//
// ----------------------------- Register Item Address: ADC_CFGR --------------------------------
// SVD Line: 165
unsigned int ADC_CFGR __AT (0x4001240C);
// ------------------------------- Field Item: ADC_CFGR_DMAEN -----------------------------------
// SVD Line: 169
// - SFDITEM_FIELD__ADC_CFGR_DMAEN
// DMAEN
//
// [Bit 0] RW (@ 0x4001240C) DMAEN
//
// ( (unsigned int) ADC_CFGR )
// DMAEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR_DMACFG ----------------------------------
// SVD Line: 173
// - SFDITEM_FIELD__ADC_CFGR_DMACFG
// DMACFG
//
// [Bit 1] RW (@ 0x4001240C) DMACFG
//
// ( (unsigned int) ADC_CFGR )
// DMACFG
//
//
//
// -------------------------------- Field Item: ADC_CFGR_RES ------------------------------------
// SVD Line: 177
// - SFDITEM_FIELD__ADC_CFGR_RES
// RES
//
// [Bits 4..3] RW (@ 0x4001240C) RES
//
// ( (unsigned char)((ADC_CFGR >> 3) & 0x3), ((ADC_CFGR = (ADC_CFGR & ~(0x3UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR_EXTSEL ----------------------------------
// SVD Line: 181
// - SFDITEM_FIELD__ADC_CFGR_EXTSEL
// EXTSEL
//
// [Bits 8..5] RW (@ 0x4001240C) EXTSEL
//
// ( (unsigned char)((ADC_CFGR >> 5) & 0xF), ((ADC_CFGR = (ADC_CFGR & ~(0xFUL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 5 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR_EXTEN -----------------------------------
// SVD Line: 185
// - SFDITEM_FIELD__ADC_CFGR_EXTEN
// EXTEN
//
// [Bits 11..10] RW (@ 0x4001240C) EXTEN
//
// ( (unsigned char)((ADC_CFGR >> 10) & 0x3), ((ADC_CFGR = (ADC_CFGR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CFGR_OVRMOD ----------------------------------
// SVD Line: 189
// - SFDITEM_FIELD__ADC_CFGR_OVRMOD
// OVRMOD
//
// [Bit 12] RW (@ 0x4001240C) OVRMOD
//
// ( (unsigned int) ADC_CFGR )
// OVRMOD
//
//
//
// -------------------------------- Field Item: ADC_CFGR_CONT -----------------------------------
// SVD Line: 193
// - SFDITEM_FIELD__ADC_CFGR_CONT
// CONT
//
// [Bit 13] RW (@ 0x4001240C) CONT
//
// ( (unsigned int) ADC_CFGR )
// CONT
//
//
//
// ------------------------------- Field Item: ADC_CFGR_AUTDLY ----------------------------------
// SVD Line: 197
// - SFDITEM_FIELD__ADC_CFGR_AUTDLY
// AUTDLY
//
// [Bit 14] RW (@ 0x4001240C) AUTDLY
//
// ( (unsigned int) ADC_CFGR )
// AUTDLY
//
//
//
// ------------------------------- Field Item: ADC_CFGR_ALIGN -----------------------------------
// SVD Line: 201
// - SFDITEM_FIELD__ADC_CFGR_ALIGN
// ALIGN
//
// [Bit 15] RW (@ 0x4001240C) ALIGN
//
// ( (unsigned int) ADC_CFGR )
// ALIGN
//
//
//
// ------------------------------- Field Item: ADC_CFGR_DISCEN ----------------------------------
// SVD Line: 205
// - SFDITEM_FIELD__ADC_CFGR_DISCEN
// DISCEN
//
// [Bit 16] RW (@ 0x4001240C) DISCEN
//
// ( (unsigned int) ADC_CFGR )
// DISCEN
//
//
//
// ------------------------------ Field Item: ADC_CFGR_DISCNUM ----------------------------------
// SVD Line: 209
// - SFDITEM_FIELD__ADC_CFGR_DISCNUM
// DISCNUM
//
// [Bits 19..17] RW (@ 0x4001240C) DISCNUM
//
// ( (unsigned char)((ADC_CFGR >> 17) & 0x7), ((ADC_CFGR = (ADC_CFGR & ~(0x7UL << 17 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 17 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CFGR_JDISCEN ----------------------------------
// SVD Line: 213
// - SFDITEM_FIELD__ADC_CFGR_JDISCEN
// JDISCEN
//
// [Bit 20] RW (@ 0x4001240C) JDISCEN
//
// ( (unsigned int) ADC_CFGR )
// JDISCEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR_AWDSGL ----------------------------------
// SVD Line: 217
// - SFDITEM_FIELD__ADC_CFGR_AWDSGL
// AWDSGL
//
// [Bit 22] RW (@ 0x4001240C) AWDSGL
//
// ( (unsigned int) ADC_CFGR )
// AWDSGL
//
//
//
// ------------------------------- Field Item: ADC_CFGR_AWDEN -----------------------------------
// SVD Line: 221
// - SFDITEM_FIELD__ADC_CFGR_AWDEN
// AWDEN
//
// [Bit 23] RW (@ 0x4001240C) AWDEN
//
// ( (unsigned int) ADC_CFGR )
// AWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR_JAWDEN ----------------------------------
// SVD Line: 225
// - SFDITEM_FIELD__ADC_CFGR_JAWDEN
// JAWDEN
//
// [Bit 24] RW (@ 0x4001240C) JAWDEN
//
// ( (unsigned int) ADC_CFGR )
// JAWDEN
//
//
//
// ------------------------------- Field Item: ADC_CFGR_JAUTO -----------------------------------
// SVD Line: 229
// - SFDITEM_FIELD__ADC_CFGR_JAUTO
// JAUTO
//
// [Bit 25] RW (@ 0x4001240C) JAUTO
//
// ( (unsigned int) ADC_CFGR )
// JAUTO
//
//
//
// ------------------------------- Field Item: ADC_CFGR_AWDCH -----------------------------------
// SVD Line: 233
// - SFDITEM_FIELD__ADC_CFGR_AWDCH
// AWDCH
//
// [Bits 29..26] RW (@ 0x4001240C) AWDCH
//
// ( (unsigned char)((ADC_CFGR >> 26) & 0xF), ((ADC_CFGR = (ADC_CFGR & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR ------------------------------------
// SVD Line: 165
// SFDITEM_REG__ADC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x4001240C) CFGR
// ( (unsigned int)((ADC_CFGR >> 0) & 0xFFFFFFFF), ((ADC_CFGR = (ADC_CFGR & ~(0x3FDFFDFBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FDFFDFB) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR_DMAEN
// - SFDITEM_FIELD__ADC_CFGR_DMACFG
// - SFDITEM_FIELD__ADC_CFGR_RES
// - SFDITEM_FIELD__ADC_CFGR_EXTSEL
// - SFDITEM_FIELD__ADC_CFGR_EXTEN
// - SFDITEM_FIELD__ADC_CFGR_OVRMOD
// - SFDITEM_FIELD__ADC_CFGR_CONT
// - SFDITEM_FIELD__ADC_CFGR_AUTDLY
// - SFDITEM_FIELD__ADC_CFGR_ALIGN
// - SFDITEM_FIELD__ADC_CFGR_DISCEN
// - SFDITEM_FIELD__ADC_CFGR_DISCNUM
// - SFDITEM_FIELD__ADC_CFGR_JDISCEN
// - SFDITEM_FIELD__ADC_CFGR_AWDSGL
// - SFDITEM_FIELD__ADC_CFGR_AWDEN
// - SFDITEM_FIELD__ADC_CFGR_JAWDEN
// - SFDITEM_FIELD__ADC_CFGR_JAUTO
// - SFDITEM_FIELD__ADC_CFGR_AWDCH
//
//
// ---------------------------- Register Item Address: ADC_CFGR2 --------------------------------
// SVD Line: 239
unsigned int ADC_CFGR2 __AT (0x40012410);
// ------------------------------ Field Item: ADC_CFGR2_CALNUM ----------------------------------
// SVD Line: 244
// - SFDITEM_FIELD__ADC_CFGR2_CALNUM
// CALNUM
//
// [Bits 30..28] RW (@ 0x40012410) CALNUM
//
// ( (unsigned char)((ADC_CFGR2 >> 28) & 0x7), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_CFGR2 -----------------------------------
// SVD Line: 239
// SFDITEM_REG__ADC_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40012410) ADC configuration register 2
// ( (unsigned int)((ADC_CFGR2 >> 0) & 0xFFFFFFFF), ((ADC_CFGR2 = (ADC_CFGR2 & ~(0x70000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70000000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CFGR2_CALNUM
//
//
// ---------------------------- Register Item Address: ADC_SMPR1 --------------------------------
// SVD Line: 250
unsigned int ADC_SMPR1 __AT (0x40012414);
// ------------------------------- Field Item: ADC_SMPR1_SMP0 -----------------------------------
// SVD Line: 255
// - SFDITEM_FIELD__ADC_SMPR1_SMP0
// SMP0
//
// [Bits 2..0] RW (@ 0x40012414) SMP0
//
// ( (unsigned char)((ADC_SMPR1 >> 0) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP1 -----------------------------------
// SVD Line: 259
// - SFDITEM_FIELD__ADC_SMPR1_SMP1
// SMP1
//
// [Bits 5..3] RW (@ 0x40012414) SMP1
//
// ( (unsigned char)((ADC_SMPR1 >> 3) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP2 -----------------------------------
// SVD Line: 263
// - SFDITEM_FIELD__ADC_SMPR1_SMP2
// SMP2
//
// [Bits 8..6] RW (@ 0x40012414) SMP2
//
// ( (unsigned char)((ADC_SMPR1 >> 6) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP3 -----------------------------------
// SVD Line: 267
// - SFDITEM_FIELD__ADC_SMPR1_SMP3
// SMP3
//
// [Bits 11..9] RW (@ 0x40012414) SMP3
//
// ( (unsigned char)((ADC_SMPR1 >> 9) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP4 -----------------------------------
// SVD Line: 271
// - SFDITEM_FIELD__ADC_SMPR1_SMP4
// SMP4
//
// [Bits 14..12] RW (@ 0x40012414) SMP4
//
// ( (unsigned char)((ADC_SMPR1 >> 12) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP5 -----------------------------------
// SVD Line: 275
// - SFDITEM_FIELD__ADC_SMPR1_SMP5
// SMP5
//
// [Bits 17..15] RW (@ 0x40012414) SMP5
//
// ( (unsigned char)((ADC_SMPR1 >> 15) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 15 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 15 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP6 -----------------------------------
// SVD Line: 279
// - SFDITEM_FIELD__ADC_SMPR1_SMP6
// SMP6
//
// [Bits 20..18] RW (@ 0x40012414) SMP6
//
// ( (unsigned char)((ADC_SMPR1 >> 18) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 18 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP7 -----------------------------------
// SVD Line: 283
// - SFDITEM_FIELD__ADC_SMPR1_SMP7
// SMP7
//
// [Bits 23..21] RW (@ 0x40012414) SMP7
//
// ( (unsigned char)((ADC_SMPR1 >> 21) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 21 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 21 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP8 -----------------------------------
// SVD Line: 287
// - SFDITEM_FIELD__ADC_SMPR1_SMP8
// SMP8
//
// [Bits 26..24] RW (@ 0x40012414) SMP8
//
// ( (unsigned char)((ADC_SMPR1 >> 24) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR1_SMP9 -----------------------------------
// SVD Line: 291
// - SFDITEM_FIELD__ADC_SMPR1_SMP9
// SMP9
//
// [Bits 29..27] RW (@ 0x40012414) SMP9
//
// ( (unsigned char)((ADC_SMPR1 >> 27) & 0x7), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x7UL << 27 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 27 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR1 -----------------------------------
// SVD Line: 250
// SFDITEM_REG__ADC_SMPR1
// SMPR1
//
// [Bits 31..0] RW (@ 0x40012414) ADC sampling time register 1
// ( (unsigned int)((ADC_SMPR1 >> 0) & 0xFFFFFFFF), ((ADC_SMPR1 = (ADC_SMPR1 & ~(0x3FFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR1_SMP0
// - SFDITEM_FIELD__ADC_SMPR1_SMP1
// - SFDITEM_FIELD__ADC_SMPR1_SMP2
// - SFDITEM_FIELD__ADC_SMPR1_SMP3
// - SFDITEM_FIELD__ADC_SMPR1_SMP4
// - SFDITEM_FIELD__ADC_SMPR1_SMP5
// - SFDITEM_FIELD__ADC_SMPR1_SMP6
// - SFDITEM_FIELD__ADC_SMPR1_SMP7
// - SFDITEM_FIELD__ADC_SMPR1_SMP8
// - SFDITEM_FIELD__ADC_SMPR1_SMP9
//
//
// ---------------------------- Register Item Address: ADC_SMPR2 --------------------------------
// SVD Line: 297
unsigned int ADC_SMPR2 __AT (0x40012418);
// ------------------------------- Field Item: ADC_SMPR2_SMP10 ----------------------------------
// SVD Line: 301
// - SFDITEM_FIELD__ADC_SMPR2_SMP10
// SMP10
//
// [Bits 2..0] RW (@ 0x40012418) SMP10
//
// ( (unsigned char)((ADC_SMPR2 >> 0) & 0x7), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR2_SMP11 ----------------------------------
// SVD Line: 305
// - SFDITEM_FIELD__ADC_SMPR2_SMP11
// SMP11
//
// [Bits 5..3] RW (@ 0x40012418) SMP11
//
// ( (unsigned char)((ADC_SMPR2 >> 3) & 0x7), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR2_SMP12 ----------------------------------
// SVD Line: 309
// - SFDITEM_FIELD__ADC_SMPR2_SMP12
// SMP12
//
// [Bits 8..6] RW (@ 0x40012418) SMP12
//
// ( (unsigned char)((ADC_SMPR2 >> 6) & 0x7), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 6 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR2_SMP13 ----------------------------------
// SVD Line: 313
// - SFDITEM_FIELD__ADC_SMPR2_SMP13
// SMP13
//
// [Bits 11..9] RW (@ 0x40012418) SMP13
//
// ( (unsigned char)((ADC_SMPR2 >> 9) & 0x7), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_SMPR2_SMP14 ----------------------------------
// SVD Line: 317
// - SFDITEM_FIELD__ADC_SMPR2_SMP14
// SMP14
//
// [Bits 14..12] RW (@ 0x40012418) SMP14
//
// ( (unsigned char)((ADC_SMPR2 >> 12) & 0x7), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SMPR2 -----------------------------------
// SVD Line: 297
// SFDITEM_REG__ADC_SMPR2
// SMPR2
//
// [Bits 31..0] RW (@ 0x40012418) SMPR2
// ( (unsigned int)((ADC_SMPR2 >> 0) & 0xFFFFFFFF), ((ADC_SMPR2 = (ADC_SMPR2 & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SMPR2_SMP10
// - SFDITEM_FIELD__ADC_SMPR2_SMP11
// - SFDITEM_FIELD__ADC_SMPR2_SMP12
// - SFDITEM_FIELD__ADC_SMPR2_SMP13
// - SFDITEM_FIELD__ADC_SMPR2_SMP14
//
//
// ------------------------------ Register Item Address: ADC_TR ---------------------------------
// SVD Line: 323
unsigned int ADC_TR __AT (0x40012424);
// ---------------------------------- Field Item: ADC_TR_LT -------------------------------------
// SVD Line: 327
// - SFDITEM_FIELD__ADC_TR_LT
// LT
//
// [Bits 11..0] RW (@ 0x40012424) LT
//
// ( (unsigned short)((ADC_TR >> 0) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_TR_AWDFILT -----------------------------------
// SVD Line: 331
// - SFDITEM_FIELD__ADC_TR_AWDFILT
// AWDFILT
//
// [Bits 14..12] RW (@ 0x40012424) AWDFILT
//
// ( (unsigned char)((ADC_TR >> 12) & 0x7), ((ADC_TR = (ADC_TR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ---------------------------------- Field Item: ADC_TR_HT -------------------------------------
// SVD Line: 335
// - SFDITEM_FIELD__ADC_TR_HT
// HT
//
// [Bits 27..16] RW (@ 0x40012424) HT
//
// ( (unsigned short)((ADC_TR >> 16) & 0xFFF), ((ADC_TR = (ADC_TR & ~(0xFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 16 ) ) ))
//
//
//
// --------------------------------- Register RTree: ADC_TR -------------------------------------
// SVD Line: 323
// SFDITEM_REG__ADC_TR
// TR
//
// [Bits 31..0] RW (@ 0x40012424) TR
// ( (unsigned int)((ADC_TR >> 0) & 0xFFFFFFFF), ((ADC_TR = (ADC_TR & ~(0xFFF7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_TR_LT
// - SFDITEM_FIELD__ADC_TR_AWDFILT
// - SFDITEM_FIELD__ADC_TR_HT
//
//
// ----------------------------- Register Item Address: ADC_SQR1 --------------------------------
// SVD Line: 341
unsigned int ADC_SQR1 __AT (0x40012430);
// --------------------------------- Field Item: ADC_SQR1_L -------------------------------------
// SVD Line: 345
// - SFDITEM_FIELD__ADC_SQR1_L
// L
//
// [Bits 3..0] RW (@ 0x40012430) L
//
// ( (unsigned char)((ADC_SQR1 >> 0) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ1 ------------------------------------
// SVD Line: 349
// - SFDITEM_FIELD__ADC_SQR1_SQ1
// SQ1
//
// [Bits 9..6] RW (@ 0x40012430) SQ1
//
// ( (unsigned char)((ADC_SQR1 >> 6) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ2 ------------------------------------
// SVD Line: 353
// - SFDITEM_FIELD__ADC_SQR1_SQ2
// SQ2
//
// [Bits 15..12] RW (@ 0x40012430) SQ2
//
// ( (unsigned char)((ADC_SQR1 >> 12) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ3 ------------------------------------
// SVD Line: 357
// - SFDITEM_FIELD__ADC_SQR1_SQ3
// SQ3
//
// [Bits 21..18] RW (@ 0x40012430) SQ3
//
// ( (unsigned char)((ADC_SQR1 >> 18) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR1_SQ4 ------------------------------------
// SVD Line: 361
// - SFDITEM_FIELD__ADC_SQR1_SQ4
// SQ4
//
// [Bits 27..24] RW (@ 0x40012430) SQ4
//
// ( (unsigned char)((ADC_SQR1 >> 24) & 0xF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR1 ------------------------------------
// SVD Line: 341
// SFDITEM_REG__ADC_SQR1
// SQR1
//
// [Bits 31..0] RW (@ 0x40012430) SQR1
// ( (unsigned int)((ADC_SQR1 >> 0) & 0xFFFFFFFF), ((ADC_SQR1 = (ADC_SQR1 & ~(0xF3CF3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF3CF3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR1_L
// - SFDITEM_FIELD__ADC_SQR1_SQ1
// - SFDITEM_FIELD__ADC_SQR1_SQ2
// - SFDITEM_FIELD__ADC_SQR1_SQ3
// - SFDITEM_FIELD__ADC_SQR1_SQ4
//
//
// ----------------------------- Register Item Address: ADC_SQR2 --------------------------------
// SVD Line: 367
unsigned int ADC_SQR2 __AT (0x40012434);
// -------------------------------- Field Item: ADC_SQR2_SQ5 ------------------------------------
// SVD Line: 371
// - SFDITEM_FIELD__ADC_SQR2_SQ5
// SQ5
//
// [Bits 3..0] RW (@ 0x40012434) SQ5
//
// ( (unsigned char)((ADC_SQR2 >> 0) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ6 ------------------------------------
// SVD Line: 375
// - SFDITEM_FIELD__ADC_SQR2_SQ6
// SQ6
//
// [Bits 9..6] RW (@ 0x40012434) SQ6
//
// ( (unsigned char)((ADC_SQR2 >> 6) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ7 ------------------------------------
// SVD Line: 379
// - SFDITEM_FIELD__ADC_SQR2_SQ7
// SQ7
//
// [Bits 15..12] RW (@ 0x40012434) SQ7
//
// ( (unsigned char)((ADC_SQR2 >> 12) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ8 ------------------------------------
// SVD Line: 383
// - SFDITEM_FIELD__ADC_SQR2_SQ8
// SQ8
//
// [Bits 21..18] RW (@ 0x40012434) SQ8
//
// ( (unsigned char)((ADC_SQR2 >> 18) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR2_SQ9 ------------------------------------
// SVD Line: 387
// - SFDITEM_FIELD__ADC_SQR2_SQ9
// SQ9
//
// [Bits 27..24] RW (@ 0x40012434) SQ9
//
// ( (unsigned char)((ADC_SQR2 >> 24) & 0xF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR2 ------------------------------------
// SVD Line: 367
// SFDITEM_REG__ADC_SQR2
// SQR2
//
// [Bits 31..0] RW (@ 0x40012434) SQR2
// ( (unsigned int)((ADC_SQR2 >> 0) & 0xFFFFFFFF), ((ADC_SQR2 = (ADC_SQR2 & ~(0xF3CF3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF3CF3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR2_SQ5
// - SFDITEM_FIELD__ADC_SQR2_SQ6
// - SFDITEM_FIELD__ADC_SQR2_SQ7
// - SFDITEM_FIELD__ADC_SQR2_SQ8
// - SFDITEM_FIELD__ADC_SQR2_SQ9
//
//
// ----------------------------- Register Item Address: ADC_SQR3 --------------------------------
// SVD Line: 393
unsigned int ADC_SQR3 __AT (0x40012438);
// -------------------------------- Field Item: ADC_SQR3_SQ10 -----------------------------------
// SVD Line: 397
// - SFDITEM_FIELD__ADC_SQR3_SQ10
// SQ10
//
// [Bits 3..0] RW (@ 0x40012438) SQ10
//
// ( (unsigned char)((ADC_SQR3 >> 0) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR3_SQ11 -----------------------------------
// SVD Line: 401
// - SFDITEM_FIELD__ADC_SQR3_SQ11
// SQ11
//
// [Bits 9..6] RW (@ 0x40012438) SQ11
//
// ( (unsigned char)((ADC_SQR3 >> 6) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR3_SQ12 -----------------------------------
// SVD Line: 405
// - SFDITEM_FIELD__ADC_SQR3_SQ12
// SQ12
//
// [Bits 15..12] RW (@ 0x40012438) SQ12
//
// ( (unsigned char)((ADC_SQR3 >> 12) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR3_SQ13 -----------------------------------
// SVD Line: 409
// - SFDITEM_FIELD__ADC_SQR3_SQ13
// SQ13
//
// [Bits 21..18] RW (@ 0x40012438) SQ13
//
// ( (unsigned char)((ADC_SQR3 >> 18) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR3_SQ14 -----------------------------------
// SVD Line: 413
// - SFDITEM_FIELD__ADC_SQR3_SQ14
// SQ14
//
// [Bits 27..24] RW (@ 0x40012438) SQ14
//
// ( (unsigned char)((ADC_SQR3 >> 24) & 0xF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR3 ------------------------------------
// SVD Line: 393
// SFDITEM_REG__ADC_SQR3
// SQR3
//
// [Bits 31..0] RW (@ 0x40012438) SQR3
// ( (unsigned int)((ADC_SQR3 >> 0) & 0xFFFFFFFF), ((ADC_SQR3 = (ADC_SQR3 & ~(0xF3CF3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF3CF3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR3_SQ10
// - SFDITEM_FIELD__ADC_SQR3_SQ11
// - SFDITEM_FIELD__ADC_SQR3_SQ12
// - SFDITEM_FIELD__ADC_SQR3_SQ13
// - SFDITEM_FIELD__ADC_SQR3_SQ14
//
//
// ----------------------------- Register Item Address: ADC_SQR4 --------------------------------
// SVD Line: 419
unsigned int ADC_SQR4 __AT (0x4001243C);
// -------------------------------- Field Item: ADC_SQR4_SQ15 -----------------------------------
// SVD Line: 423
// - SFDITEM_FIELD__ADC_SQR4_SQ15
// SQ15
//
// [Bits 3..0] RW (@ 0x4001243C) SQ15
//
// ( (unsigned char)((ADC_SQR4 >> 0) & 0xF), ((ADC_SQR4 = (ADC_SQR4 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_SQR4_SQ16 -----------------------------------
// SVD Line: 427
// - SFDITEM_FIELD__ADC_SQR4_SQ16
// SQ16
//
// [Bits 9..6] RW (@ 0x4001243C) SQ16
//
// ( (unsigned char)((ADC_SQR4 >> 6) & 0xF), ((ADC_SQR4 = (ADC_SQR4 & ~(0xFUL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 6 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_SQR4 ------------------------------------
// SVD Line: 419
// SFDITEM_REG__ADC_SQR4
// SQR4
//
// [Bits 31..0] RW (@ 0x4001243C) SQR4
// ( (unsigned int)((ADC_SQR4 >> 0) & 0xFFFFFFFF), ((ADC_SQR4 = (ADC_SQR4 & ~(0x3CFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_SQR4_SQ15
// - SFDITEM_FIELD__ADC_SQR4_SQ16
//
//
// ------------------------------ Register Item Address: ADC_DR ---------------------------------
// SVD Line: 433
unsigned int ADC_DR __AT (0x40012440);
// -------------------------------- Field Item: ADC_DR_RDATA ------------------------------------
// SVD Line: 438
// - SFDITEM_FIELD__ADC_DR_RDATA
// RDATA
//
// [Bits 15..0] RO (@ 0x40012440) RDATA
//
// ( (unsigned short)((ADC_DR >> 0) & 0xFFFF) )
//
//
//
// --------------------------------- Register RTree: ADC_DR -------------------------------------
// SVD Line: 433
// SFDITEM_REG__ADC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40012440) ADC group regular data register
// ( (unsigned int)((ADC_DR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_DR_RDATA
//
//
// ----------------------------- Register Item Address: ADC_JSQR --------------------------------
// SVD Line: 445
unsigned int ADC_JSQR __AT (0x4001244C);
// --------------------------------- Field Item: ADC_JSQR_JL ------------------------------------
// SVD Line: 449
// - SFDITEM_FIELD__ADC_JSQR_JL
// JL
//
// [Bits 1..0] RW (@ 0x4001244C) JL
//
// ( (unsigned char)((ADC_JSQR >> 0) & 0x3), ((ADC_JSQR = (ADC_JSQR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_JSQR_JEXTSEL ----------------------------------
// SVD Line: 453
// - SFDITEM_FIELD__ADC_JSQR_JEXTSEL
// JEXTSEL
//
// [Bits 5..2] RW (@ 0x4001244C) JEXTSEL
//
// ( (unsigned char)((ADC_JSQR >> 2) & 0xF), ((ADC_JSQR = (ADC_JSQR & ~(0xFUL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 2 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_JSQR_JEXTEN ----------------------------------
// SVD Line: 457
// - SFDITEM_FIELD__ADC_JSQR_JEXTEN
// JEXTEN
//
// [Bits 7..6] RW (@ 0x4001244C) JEXTEN
//
// ( (unsigned char)((ADC_JSQR >> 6) & 0x3), ((ADC_JSQR = (ADC_JSQR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_JSQR_JSQ1 -----------------------------------
// SVD Line: 461
// - SFDITEM_FIELD__ADC_JSQR_JSQ1
// JSQ1
//
// [Bits 11..8] RW (@ 0x4001244C) JSQ1
//
// ( (unsigned char)((ADC_JSQR >> 8) & 0xF), ((ADC_JSQR = (ADC_JSQR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_JSQR_JSQ2 -----------------------------------
// SVD Line: 465
// - SFDITEM_FIELD__ADC_JSQR_JSQ2
// JSQ2
//
// [Bits 17..14] RW (@ 0x4001244C) JSQ2
//
// ( (unsigned char)((ADC_JSQR >> 14) & 0xF), ((ADC_JSQR = (ADC_JSQR & ~(0xFUL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 14 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_JSQR_JSQ3 -----------------------------------
// SVD Line: 469
// - SFDITEM_FIELD__ADC_JSQR_JSQ3
// JSQ3
//
// [Bits 23..20] RW (@ 0x4001244C) JSQ3
//
// ( (unsigned char)((ADC_JSQR >> 20) & 0xF), ((ADC_JSQR = (ADC_JSQR & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_JSQR_JSQ4 -----------------------------------
// SVD Line: 473
// - SFDITEM_FIELD__ADC_JSQR_JSQ4
// JSQ4
//
// [Bits 29..26] RW (@ 0x4001244C) JSQ4
//
// ( (unsigned char)((ADC_JSQR >> 26) & 0xF), ((ADC_JSQR = (ADC_JSQR & ~(0xFUL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: ADC_JSQR ------------------------------------
// SVD Line: 445
// SFDITEM_REG__ADC_JSQR
// JSQR
//
// [Bits 31..0] RW (@ 0x4001244C) JSQR
// ( (unsigned int)((ADC_JSQR >> 0) & 0xFFFFFFFF), ((ADC_JSQR = (ADC_JSQR & ~(0x3CF3CFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3CF3CFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_JSQR_JL
// - SFDITEM_FIELD__ADC_JSQR_JEXTSEL
// - SFDITEM_FIELD__ADC_JSQR_JEXTEN
// - SFDITEM_FIELD__ADC_JSQR_JSQ1
// - SFDITEM_FIELD__ADC_JSQR_JSQ2
// - SFDITEM_FIELD__ADC_JSQR_JSQ3
// - SFDITEM_FIELD__ADC_JSQR_JSQ4
//
//
// ----------------------------- Register Item Address: ADC_JDR1 --------------------------------
// SVD Line: 479
unsigned int ADC_JDR1 __AT (0x40012480);
// ------------------------------- Field Item: ADC_JDR1_JDATA -----------------------------------
// SVD Line: 483
// - SFDITEM_FIELD__ADC_JDR1_JDATA
// JDATA
//
// [Bits 15..0] RO (@ 0x40012480) JDATA
//
// ( (unsigned short)((ADC_JDR1 >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: ADC_JDR1 ------------------------------------
// SVD Line: 479
// SFDITEM_REG__ADC_JDR1
// JDR1
//
// [Bits 31..0] RW (@ 0x40012480) JDR1
// ( (unsigned int)((ADC_JDR1 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_JDR1_JDATA
//
//
// ----------------------------- Register Item Address: ADC_JDR2 --------------------------------
// SVD Line: 490
unsigned int ADC_JDR2 __AT (0x40012484);
// ------------------------------- Field Item: ADC_JDR2_JDATA -----------------------------------
// SVD Line: 494
// - SFDITEM_FIELD__ADC_JDR2_JDATA
// JDATA
//
// [Bits 15..0] RO (@ 0x40012484) JDATA
//
// ( (unsigned short)((ADC_JDR2 >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: ADC_JDR2 ------------------------------------
// SVD Line: 490
// SFDITEM_REG__ADC_JDR2
// JDR2
//
// [Bits 31..0] RW (@ 0x40012484) JDR2
// ( (unsigned int)((ADC_JDR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_JDR2_JDATA
//
//
// ----------------------------- Register Item Address: ADC_JDR3 --------------------------------
// SVD Line: 501
unsigned int ADC_JDR3 __AT (0x40012488);
// ------------------------------- Field Item: ADC_JDR3_JDATA -----------------------------------
// SVD Line: 505
// - SFDITEM_FIELD__ADC_JDR3_JDATA
// JDATA
//
// [Bits 15..0] RO (@ 0x40012488) JDATA
//
// ( (unsigned short)((ADC_JDR3 >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: ADC_JDR3 ------------------------------------
// SVD Line: 501
// SFDITEM_REG__ADC_JDR3
// JDR3
//
// [Bits 31..0] RW (@ 0x40012488) JDR3
// ( (unsigned int)((ADC_JDR3 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_JDR3_JDATA
//
//
// ----------------------------- Register Item Address: ADC_JDR4 --------------------------------
// SVD Line: 512
unsigned int ADC_JDR4 __AT (0x4001248C);
// ------------------------------- Field Item: ADC_JDR4_JDATA -----------------------------------
// SVD Line: 516
// - SFDITEM_FIELD__ADC_JDR4_JDATA
// JDATA
//
// [Bits 15..0] RO (@ 0x4001248C) JDATA
//
// ( (unsigned short)((ADC_JDR4 >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: ADC_JDR4 ------------------------------------
// SVD Line: 512
// SFDITEM_REG__ADC_JDR4
// JDR4
//
// [Bits 31..0] RW (@ 0x4001248C) JDR4
// ( (unsigned int)((ADC_JDR4 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__ADC_JDR4_JDATA
//
//
// --------------------------- Register Item Address: ADC_CALFACT -------------------------------
// SVD Line: 523
unsigned int ADC_CALFACT __AT (0x400124B4);
// ---------------------------- Field Item: ADC_CALFACT_WCALFACT --------------------------------
// SVD Line: 527
// - SFDITEM_FIELD__ADC_CALFACT_WCALFACT
// WCALFACT
//
// [Bits 8..0] RW (@ 0x400124B4) WCALFACT
//
// ( (unsigned short)((ADC_CALFACT >> 0) & 0x1FF), ((ADC_CALFACT = (ADC_CALFACT & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: ADC_CALFACT_FACTSEL --------------------------------
// SVD Line: 531
// - SFDITEM_FIELD__ADC_CALFACT_FACTSEL
// FACTSEL
//
// [Bits 13..9] RW (@ 0x400124B4) FACTSEL
//
// ( (unsigned char)((ADC_CALFACT >> 9) & 0x1F), ((ADC_CALFACT = (ADC_CALFACT & ~(0x1FUL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 9 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CALFACT_WRVLD ---------------------------------
// SVD Line: 535
// - SFDITEM_FIELD__ADC_CALFACT_WRVLD
// WRVLD
//
// [Bit 14] RW (@ 0x400124B4) WRVLD
//
// ( (unsigned int) ADC_CALFACT )
// WRVLD
//
//
//
// ------------------------------ Field Item: ADC_CALFACT_RDVLD ---------------------------------
// SVD Line: 539
// - SFDITEM_FIELD__ADC_CALFACT_RDVLD
// RDVLD
//
// [Bit 15] RW (@ 0x400124B4) RDVLD
//
// ( (unsigned int) ADC_CALFACT )
// RDVLD
//
//
//
// ----------------------------- Field Item: ADC_CALFACT_OFFSUC ---------------------------------
// SVD Line: 543
// - SFDITEM_FIELD__ADC_CALFACT_OFFSUC
// OFFSUC
//
// [Bit 20] RW (@ 0x400124B4) OFFSUC
//
// ( (unsigned int) ADC_CALFACT )
// OFFSUC
//
//
//
// ----------------------------- Field Item: ADC_CALFACT_CAPSUC ---------------------------------
// SVD Line: 547
// - SFDITEM_FIELD__ADC_CALFACT_CAPSUC
// CAPSUC
//
// [Bit 21] RW (@ 0x400124B4) CAPSUC
//
// ( (unsigned int) ADC_CALFACT )
// CAPSUC
//
//
//
// ---------------------------- Field Item: ADC_CALFACT_RCALFACT --------------------------------
// SVD Line: 551
// - SFDITEM_FIELD__ADC_CALFACT_RCALFACT
// RCALFACT
//
// [Bits 31..23] RO (@ 0x400124B4) RCALFACT
//
// ( (unsigned short)((ADC_CALFACT >> 23) & 0x1FF) )
//
//
//
// ------------------------------- Register RTree: ADC_CALFACT ----------------------------------
// SVD Line: 523
// SFDITEM_REG__ADC_CALFACT
// CALFACT
//
// [Bits 31..0] RW (@ 0x400124B4) CALFACT
// ( (unsigned int)((ADC_CALFACT >> 0) & 0xFFFFFFFF), ((ADC_CALFACT = (ADC_CALFACT & ~(0x30FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CALFACT_WCALFACT
// - SFDITEM_FIELD__ADC_CALFACT_FACTSEL
// - SFDITEM_FIELD__ADC_CALFACT_WRVLD
// - SFDITEM_FIELD__ADC_CALFACT_RDVLD
// - SFDITEM_FIELD__ADC_CALFACT_OFFSUC
// - SFDITEM_FIELD__ADC_CALFACT_CAPSUC
// - SFDITEM_FIELD__ADC_CALFACT_RCALFACT
//
//
// ----------------------------- Register Item Address: ADC_CCR ---------------------------------
// SVD Line: 558
unsigned int ADC_CCR __AT (0x40012708);
// ------------------------------- Field Item: ADC_CCR_CKMODE -----------------------------------
// SVD Line: 563
// - SFDITEM_FIELD__ADC_CCR_CKMODE
// CKMODE
//
// [Bits 17..16] RW (@ 0x40012708) CKMODE
//
// ( (unsigned char)((ADC_CCR >> 16) & 0x3), ((ADC_CCR = (ADC_CCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// -------------------------------- Field Item: ADC_CCR_PRESC -----------------------------------
// SVD Line: 567
// - SFDITEM_FIELD__ADC_CCR_PRESC
// PRESC
//
// [Bits 21..18] RW (@ 0x40012708) PRESC
//
// ( (unsigned char)((ADC_CCR >> 18) & 0xF), ((ADC_CCR = (ADC_CCR & ~(0xFUL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 18 ) ) ))
//
//
//
// ------------------------------- Field Item: ADC_CCR_VREFEN -----------------------------------
// SVD Line: 571
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// VREFEN
//
// [Bit 22] RW (@ 0x40012708) VREFEN
//
// ( (unsigned int) ADC_CCR )
// VREFEN
//
//
//
// -------------------------------- Field Item: ADC_CCR_TSEN ------------------------------------
// SVD Line: 575
// - SFDITEM_FIELD__ADC_CCR_TSEN
// TSEN
//
// [Bit 23] RW (@ 0x40012708) TSEN
//
// ( (unsigned int) ADC_CCR )
// TSEN
//
//
//
// ------------------------------ Field Item: ADC_CCR_PWR_MODE ----------------------------------
// SVD Line: 579
// - SFDITEM_FIELD__ADC_CCR_PWR_MODE
// PWR_MODE
//
// [Bits 27..25] RW (@ 0x40012708) PWR_MODE
//
// ( (unsigned char)((ADC_CCR >> 25) & 0x7), ((ADC_CCR = (ADC_CCR & ~(0x7UL << 25 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 25 ) ) ))
//
//
//
// ------------------------------ Field Item: ADC_CCR_VSENSESEL ---------------------------------
// SVD Line: 583
// - SFDITEM_FIELD__ADC_CCR_VSENSESEL
// VSENSESEL
//
// [Bit 28] RW (@ 0x40012708) VSENSESEL
//
// ( (unsigned int) ADC_CCR )
// VSENSESEL
//
//
//
// --------------------------------- Register RTree: ADC_CCR ------------------------------------
// SVD Line: 558
// SFDITEM_REG__ADC_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x40012708) ADC common configuration register
// ( (unsigned int)((ADC_CCR >> 0) & 0xFFFFFFFF), ((ADC_CCR = (ADC_CCR & ~(0x1EFF0000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1EFF0000) << 0 ) ) ))
// - SFDITEM_FIELD__ADC_CCR_CKMODE
// - SFDITEM_FIELD__ADC_CCR_PRESC
// - SFDITEM_FIELD__ADC_CCR_VREFEN
// - SFDITEM_FIELD__ADC_CCR_TSEN
// - SFDITEM_FIELD__ADC_CCR_PWR_MODE
// - SFDITEM_FIELD__ADC_CCR_VSENSESEL
//
//
// ---------------------------------- Peripheral View: ADC --------------------------------------
// SVD Line: 25
// ADC
// ADC
// - SFDITEM_REG__ADC_ISR
// - SFDITEM_REG__ADC_IER
// - SFDITEM_REG__ADC_CR
// - SFDITEM_REG__ADC_CFGR
// - SFDITEM_REG__ADC_CFGR2
// - SFDITEM_REG__ADC_SMPR1
// - SFDITEM_REG__ADC_SMPR2
// - SFDITEM_REG__ADC_TR
// - SFDITEM_REG__ADC_SQR1
// - SFDITEM_REG__ADC_SQR2
// - SFDITEM_REG__ADC_SQR3
// - SFDITEM_REG__ADC_SQR4
// - SFDITEM_REG__ADC_DR
// - SFDITEM_REG__ADC_JSQR
// - SFDITEM_REG__ADC_JDR1
// - SFDITEM_REG__ADC_JDR2
// - SFDITEM_REG__ADC_JDR3
// - SFDITEM_REG__ADC_JDR4
// - SFDITEM_REG__ADC_CALFACT
// - SFDITEM_REG__ADC_CCR
//
//
// ---------------------------- Register Item Address: COMP_CSR1 --------------------------------
// SVD Line: 605
unsigned int COMP_CSR1 __AT (0x40010200);
// ----------------------------- Field Item: COMP_CSR1_COMP1_EN ---------------------------------
// SVD Line: 609
// - SFDITEM_FIELD__COMP_CSR1_COMP1_EN
// COMP1_EN
//
// [Bit 0] RW (@ 0x40010200) COMP1 enable bit
//
// ( (unsigned int) COMP_CSR1 )
// COMP1_EN
//
//
//
// ------------------------------ Field Item: COMP_CSR1_INMSEL ----------------------------------
// SVD Line: 614
// - SFDITEM_FIELD__COMP_CSR1_INMSEL
// INMSEL
//
// [Bits 4..2] RW (@ 0x40010200) COMP1 negative input select
//
// ( (unsigned char)((COMP_CSR1 >> 2) & 0x7), ((COMP_CSR1 = (COMP_CSR1 & ~(0x7UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP_CSR1_INPSEL ----------------------------------
// SVD Line: 619
// - SFDITEM_FIELD__COMP_CSR1_INPSEL
// INPSEL
//
// [Bits 7..5] RW (@ 0x40010200) COMP1 positive input select
//
// ( (unsigned char)((COMP_CSR1 >> 5) & 0x7), ((COMP_CSR1 = (COMP_CSR1 & ~(0x7UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 5 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP_CSR1_WINMODE ---------------------------------
// SVD Line: 624
// - SFDITEM_FIELD__COMP_CSR1_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010200) COMP1 window mode enable
//
// ( (unsigned int) COMP_CSR1 )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP_CSR1_BLANKSEL ---------------------------------
// SVD Line: 629
// - SFDITEM_FIELD__COMP_CSR1_BLANKSEL
// BLANKSEL
//
// [Bits 14..12] RW (@ 0x40010200) Comparator 1 blanking signal selection
//
// ( (unsigned char)((COMP_CSR1 >> 12) & 0x7), ((COMP_CSR1 = (COMP_CSR1 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: COMP_CSR1_POLARITY ---------------------------------
// SVD Line: 634
// - SFDITEM_FIELD__COMP_CSR1_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010200) COMP1 output polarity selection
//
// ( (unsigned int) COMP_CSR1 )
// POLARITY
//
//
//
// ------------------------------- Field Item: COMP_CSR1_HYST -----------------------------------
// SVD Line: 639
// - SFDITEM_FIELD__COMP_CSR1_HYST
// HYST
//
// [Bit 16] RW (@ 0x40010200) COMP1 hysteresis function enable control
//
// ( (unsigned int) COMP_CSR1 )
// HYST
//
//
//
// ------------------------------ Field Item: COMP_CSR1_PWRMODE ---------------------------------
// SVD Line: 644
// - SFDITEM_FIELD__COMP_CSR1_PWRMODE
// PWRMODE
//
// [Bit 18] RW (@ 0x40010200) COMP1 power mode selection
//
// ( (unsigned int) COMP_CSR1 )
// PWRMODE
//
//
//
// ---------------------------- Field Item: COMP_CSR1_INT_OUT_SEL -------------------------------
// SVD Line: 649
// - SFDITEM_FIELD__COMP_CSR1_INT_OUT_SEL
// INT_OUT_SEL
//
// [Bit 29] RW (@ 0x40010200) COMP1 output to TIM/EXTI selection
//
// ( (unsigned int) COMP_CSR1 )
// INT_OUT_SEL
//
//
//
// ----------------------------- Field Item: COMP_CSR1_COMP1_OUT --------------------------------
// SVD Line: 654
// - SFDITEM_FIELD__COMP_CSR1_COMP1_OUT
// COMP1_OUT
//
// [Bit 30] RO (@ 0x40010200) COMP1 output status
//
// ( (unsigned int) COMP_CSR1 )
// COMP1_OUT
//
//
//
// ------------------------------- Field Item: COMP_CSR1_LOCK -----------------------------------
// SVD Line: 660
// - SFDITEM_FIELD__COMP_CSR1_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40010200) COMP1_CSR registerlock
//
// ( (unsigned int) COMP_CSR1 )
// LOCK
//
//
//
// -------------------------------- Register RTree: COMP_CSR1 -----------------------------------
// SVD Line: 605
// SFDITEM_REG__COMP_CSR1
// CSR1
//
// [Bits 31..0] RW (@ 0x40010200) CSR1
// ( (unsigned int)((COMP_CSR1 >> 0) & 0xFFFFFFFF), ((COMP_CSR1 = (COMP_CSR1 & ~(0xA005F8FDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA005F8FD) << 0 ) ) ))
// - SFDITEM_FIELD__COMP_CSR1_COMP1_EN
// - SFDITEM_FIELD__COMP_CSR1_INMSEL
// - SFDITEM_FIELD__COMP_CSR1_INPSEL
// - SFDITEM_FIELD__COMP_CSR1_WINMODE
// - SFDITEM_FIELD__COMP_CSR1_BLANKSEL
// - SFDITEM_FIELD__COMP_CSR1_POLARITY
// - SFDITEM_FIELD__COMP_CSR1_HYST
// - SFDITEM_FIELD__COMP_CSR1_PWRMODE
// - SFDITEM_FIELD__COMP_CSR1_INT_OUT_SEL
// - SFDITEM_FIELD__COMP_CSR1_COMP1_OUT
// - SFDITEM_FIELD__COMP_CSR1_LOCK
//
//
// ----------------------------- Register Item Address: COMP_FR1 --------------------------------
// SVD Line: 667
unsigned int COMP_FR1 __AT (0x40010204);
// ------------------------------- Field Item: COMP_FR1_FLTEN1 ----------------------------------
// SVD Line: 671
// - SFDITEM_FIELD__COMP_FR1_FLTEN1
// FLTEN1
//
// [Bit 0] RW (@ 0x40010204) Comparator 1 digital filter configuration
//
// ( (unsigned int) COMP_FR1 )
// FLTEN1
//
//
//
// ------------------------------ Field Item: COMP_FR1_FLTCNT1 ----------------------------------
// SVD Line: 676
// - SFDITEM_FIELD__COMP_FR1_FLTCNT1
// FLTCNT1
//
// [Bits 31..16] RW (@ 0x40010204) Comparator 1 sampling filter counter
//
// ( (unsigned short)((COMP_FR1 >> 16) & 0xFFFF), ((COMP_FR1 = (COMP_FR1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP_FR1 ------------------------------------
// SVD Line: 667
// SFDITEM_REG__COMP_FR1
// FR1
//
// [Bits 31..0] RW (@ 0x40010204) FR1
// ( (unsigned int)((COMP_FR1 >> 0) & 0xFFFFFFFF), ((COMP_FR1 = (COMP_FR1 & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP_FR1_FLTEN1
// - SFDITEM_FIELD__COMP_FR1_FLTCNT1
//
//
// ---------------------------- Register Item Address: COMP_CCSR --------------------------------
// SVD Line: 683
unsigned int COMP_CCSR __AT (0x40010208);
// ---------------------------- Field Item: COMP_CCSR_VREFCMP_EN --------------------------------
// SVD Line: 687
// - SFDITEM_FIELD__COMP_CCSR_VREFCMP_EN
// VREFCMP_EN
//
// [Bit 0] RW (@ 0x40010208) VREFCMP voltage divider enable signal
//
// ( (unsigned int) COMP_CCSR )
// VREFCMP_EN
//
//
//
// ------------------------------- Field Item: COMP_CCSR_VCDIV ----------------------------------
// SVD Line: 692
// - SFDITEM_FIELD__COMP_CCSR_VCDIV
// VCDIV
//
// [Bits 6..1] RW (@ 0x40010208) VCDIV
//
// ( (unsigned char)((COMP_CCSR >> 1) & 0x3F), ((COMP_CCSR = (COMP_CCSR & ~(0x3FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 1 ) ) ))
//
//
//
// ------------------------------- Field Item: COMP_CCSR_SSEL -----------------------------------
// SVD Line: 696
// - SFDITEM_FIELD__COMP_CCSR_SSEL
// SSEL
//
// [Bit 7] RW (@ 0x40010208) SSEL
//
// ( (unsigned int) COMP_CCSR )
// SSEL
//
//
//
// -------------------------------- Register RTree: COMP_CCSR -----------------------------------
// SVD Line: 683
// SFDITEM_REG__COMP_CCSR
// CCSR
//
// [Bits 31..0] RW (@ 0x40010208) CCSR
// ( (unsigned int)((COMP_CCSR >> 0) & 0xFFFFFFFF), ((COMP_CCSR = (COMP_CCSR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__COMP_CCSR_VREFCMP_EN
// - SFDITEM_FIELD__COMP_CCSR_VCDIV
// - SFDITEM_FIELD__COMP_CCSR_SSEL
//
//
// ---------------------------- Register Item Address: COMP_CSR2 --------------------------------
// SVD Line: 702
unsigned int COMP_CSR2 __AT (0x40010210);
// ----------------------------- Field Item: COMP_CSR2_COMP2_EN ---------------------------------
// SVD Line: 706
// - SFDITEM_FIELD__COMP_CSR2_COMP2_EN
// COMP2_EN
//
// [Bit 0] RW (@ 0x40010210) COMP2 enable bit
//
// ( (unsigned int) COMP_CSR2 )
// COMP2_EN
//
//
//
// ------------------------------ Field Item: COMP_CSR2_INMSEL ----------------------------------
// SVD Line: 711
// - SFDITEM_FIELD__COMP_CSR2_INMSEL
// INMSEL
//
// [Bits 4..1] RW (@ 0x40010210) COMP2 negative input select
//
// ( (unsigned char)((COMP_CSR2 >> 1) & 0xF), ((COMP_CSR2 = (COMP_CSR2 & ~(0xFUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 1 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP_CSR2_INPSEL ----------------------------------
// SVD Line: 716
// - SFDITEM_FIELD__COMP_CSR2_INPSEL
// INPSEL
//
// [Bits 7..5] RW (@ 0x40010210) COMP2 positive input select
//
// ( (unsigned char)((COMP_CSR2 >> 5) & 0x7), ((COMP_CSR2 = (COMP_CSR2 & ~(0x7UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 5 ) ) ))
//
//
//
// ------------------------------ Field Item: COMP_CSR2_WINMODE ---------------------------------
// SVD Line: 721
// - SFDITEM_FIELD__COMP_CSR2_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010210) WINMODE
//
// ( (unsigned int) COMP_CSR2 )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP_CSR2_BLANKSEL ---------------------------------
// SVD Line: 725
// - SFDITEM_FIELD__COMP_CSR2_BLANKSEL
// BLANKSEL
//
// [Bits 14..12] RW (@ 0x40010210) Comparator 2 blanking signal selection
//
// ( (unsigned char)((COMP_CSR2 >> 12) & 0x7), ((COMP_CSR2 = (COMP_CSR2 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: COMP_CSR2_POLARITY ---------------------------------
// SVD Line: 730
// - SFDITEM_FIELD__COMP_CSR2_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010210) COMP2 output polarity selection
//
// ( (unsigned int) COMP_CSR2 )
// POLARITY
//
//
//
// ------------------------------- Field Item: COMP_CSR2_HYST -----------------------------------
// SVD Line: 735
// - SFDITEM_FIELD__COMP_CSR2_HYST
// HYST
//
// [Bit 16] RW (@ 0x40010210) COMP1 hysteresis function enable control
//
// ( (unsigned int) COMP_CSR2 )
// HYST
//
//
//
// ------------------------------ Field Item: COMP_CSR2_PWRMODE ---------------------------------
// SVD Line: 740
// - SFDITEM_FIELD__COMP_CSR2_PWRMODE
// PWRMODE
//
// [Bit 18] RW (@ 0x40010210) COMP2 power mode selection
//
// ( (unsigned int) COMP_CSR2 )
// PWRMODE
//
//
//
// ---------------------------- Field Item: COMP_CSR2_INT_OUT_SEL -------------------------------
// SVD Line: 745
// - SFDITEM_FIELD__COMP_CSR2_INT_OUT_SEL
// INT_OUT_SEL
//
// [Bit 29] RW (@ 0x40010210) COMP2 output to TIM/EXTI selection
//
// ( (unsigned int) COMP_CSR2 )
// INT_OUT_SEL
//
//
//
// ----------------------------- Field Item: COMP_CSR2_COMP_OUT ---------------------------------
// SVD Line: 750
// - SFDITEM_FIELD__COMP_CSR2_COMP_OUT
// COMP_OUT
//
// [Bit 30] RO (@ 0x40010210) COMP2 output status
//
// ( (unsigned int) COMP_CSR2 )
// COMP_OUT
//
//
//
// ------------------------------- Field Item: COMP_CSR2_LOCK -----------------------------------
// SVD Line: 756
// - SFDITEM_FIELD__COMP_CSR2_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40010210) COMP2_CSR register lock
//
// ( (unsigned int) COMP_CSR2 )
// LOCK
//
//
//
// -------------------------------- Register RTree: COMP_CSR2 -----------------------------------
// SVD Line: 702
// SFDITEM_REG__COMP_CSR2
// CSR2
//
// [Bits 31..0] RW (@ 0x40010210) CSR2
// ( (unsigned int)((COMP_CSR2 >> 0) & 0xFFFFFFFF), ((COMP_CSR2 = (COMP_CSR2 & ~(0xA005F8FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA005F8FF) << 0 ) ) ))
// - SFDITEM_FIELD__COMP_CSR2_COMP2_EN
// - SFDITEM_FIELD__COMP_CSR2_INMSEL
// - SFDITEM_FIELD__COMP_CSR2_INPSEL
// - SFDITEM_FIELD__COMP_CSR2_WINMODE
// - SFDITEM_FIELD__COMP_CSR2_BLANKSEL
// - SFDITEM_FIELD__COMP_CSR2_POLARITY
// - SFDITEM_FIELD__COMP_CSR2_HYST
// - SFDITEM_FIELD__COMP_CSR2_PWRMODE
// - SFDITEM_FIELD__COMP_CSR2_INT_OUT_SEL
// - SFDITEM_FIELD__COMP_CSR2_COMP_OUT
// - SFDITEM_FIELD__COMP_CSR2_LOCK
//
//
// ----------------------------- Register Item Address: COMP_FR2 --------------------------------
// SVD Line: 763
unsigned int COMP_FR2 __AT (0x40010214);
// ------------------------------- Field Item: COMP_FR2_FLTEN2 ----------------------------------
// SVD Line: 767
// - SFDITEM_FIELD__COMP_FR2_FLTEN2
// FLTEN2
//
// [Bit 0] RW (@ 0x40010214) Comparator 2 digital filtering configuration
//
// ( (unsigned int) COMP_FR2 )
// FLTEN2
//
//
//
// ------------------------------ Field Item: COMP_FR2_FLTCNT2 ----------------------------------
// SVD Line: 772
// - SFDITEM_FIELD__COMP_FR2_FLTCNT2
// FLTCNT2
//
// [Bits 31..16] RW (@ 0x40010214) Comparator 2 sampling filter counter
//
// ( (unsigned short)((COMP_FR2 >> 16) & 0xFFFF), ((COMP_FR2 = (COMP_FR2 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP_FR2 ------------------------------------
// SVD Line: 763
// SFDITEM_REG__COMP_FR2
// FR2
//
// [Bits 31..0] RW (@ 0x40010214) FR2
// ( (unsigned int)((COMP_FR2 >> 0) & 0xFFFFFFFF), ((COMP_FR2 = (COMP_FR2 & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP_FR2_FLTEN2
// - SFDITEM_FIELD__COMP_FR2_FLTCNT2
//
//
// ---------------------------------- Peripheral View: COMP -------------------------------------
// SVD Line: 591
// COMP
// COMP
// - SFDITEM_REG__COMP_CSR1
// - SFDITEM_REG__COMP_FR1
// - SFDITEM_REG__COMP_CCSR
// - SFDITEM_REG__COMP_CSR2
// - SFDITEM_REG__COMP_FR2
//
//
// ------------------------------ Register Item Address: CRC_DR ---------------------------------
// SVD Line: 791
unsigned int CRC_DR __AT (0x40023000);
// ---------------------------------- Field Item: CRC_DR_DR -------------------------------------
// SVD Line: 796
// - SFDITEM_FIELD__CRC_DR_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) DR
//
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_DR -------------------------------------
// SVD Line: 791
// SFDITEM_REG__CRC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_DR_DR
//
//
// ----------------------------- Register Item Address: CRC_IDR ---------------------------------
// SVD Line: 802
unsigned int CRC_IDR __AT (0x40023004);
// --------------------------------- Field Item: CRC_IDR_IDR ------------------------------------
// SVD Line: 807
// - SFDITEM_FIELD__CRC_IDR_IDR
// IDR
//
// [Bits 7..0] RW (@ 0x40023004) IDR
//
// ( (unsigned char)((CRC_IDR >> 0) & 0xFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_IDR ------------------------------------
// SVD Line: 802
// SFDITEM_REG__CRC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x40023004) Independent Data register
// ( (unsigned int)((CRC_IDR >> 0) & 0xFFFFFFFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_IDR_IDR
//
//
// ------------------------------ Register Item Address: CRC_CR ---------------------------------
// SVD Line: 813
unsigned int CRC_CR __AT (0x40023008);
// -------------------------------- Field Item: CRC_CR_RESET ------------------------------------
// SVD Line: 819
// - SFDITEM_FIELD__CRC_CR_RESET
// RESET
//
// [Bit 0] WO (@ 0x40023008) RESET
//
// ( (unsigned int) CRC_CR )
// RESET
//
//
//
// --------------------------------- Register RTree: CRC_CR -------------------------------------
// SVD Line: 813
// SFDITEM_REG__CRC_CR
// CR
//
// [Bits 31..0] WO (@ 0x40023008) Control register
// ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_CR_RESET
//
//
// ---------------------------------- Peripheral View: CRC --------------------------------------
// SVD Line: 781
// CRC
// CRC
// - SFDITEM_REG__CRC_DR
// - SFDITEM_REG__CRC_IDR
// - SFDITEM_REG__CRC_CR
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_IDCODE ----------------------------
// SVD Line: 837
unsigned int DBGMCU_DBG_IDCODE __AT (0x40015800);
// -------------------------- Field Item: DBGMCU_DBG_IDCODE_DBG_ID ------------------------------
// SVD Line: 841
// - SFDITEM_FIELD__DBGMCU_DBG_IDCODE_DBG_ID
// DBG_ID
//
// [Bits 31..0] RO (@ 0x40015800) DBG_ID
//
// ( (unsigned int)((DBGMCU_DBG_IDCODE >> 0) & 0xFFFFFFFF) )
//
//
//
// ---------------------------- Register RTree: DBGMCU_DBG_IDCODE -------------------------------
// SVD Line: 837
// SFDITEM_REG__DBGMCU_DBG_IDCODE
// DBG_IDCODE
//
// [Bits 31..0] RW (@ 0x40015800) DBG_IDCODE
// ( (unsigned int)((DBGMCU_DBG_IDCODE >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DBGMCU_DBG_IDCODE_DBG_ID
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 848
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_SLEEP --------------------------------
// SVD Line: 853
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// DBG_SLEEP
//
// [Bit 0] RW (@ 0x40015804) DBG_SLEEP
//
// ( (unsigned int) DBGMCU_CR )
// DBG_SLEEP
//
//
//
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 857
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) DBG_STOP
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 848
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_APB_FZ1 ---------------------------
// SVD Line: 863
unsigned int DBGMCU_DBG_APB_FZ1 __AT (0x40015808);
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_TIM1_STOP --------------------------
// SVD Line: 867
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_TIM1_STOP
// DBG_TIM1_STOP
//
// [Bit 0] RW (@ 0x40015808) DBG_TIM1_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_TIM1_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_TIM3_STOP --------------------------
// SVD Line: 871
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_TIM3_STOP
// DBG_TIM3_STOP
//
// [Bit 1] RW (@ 0x40015808) DBG_TIM3_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_TIM3_STOP
//
//
//
// ----------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_RTC_STOP --------------------------
// SVD Line: 875
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_RTC_STOP
// DBG_RTC_STOP
//
// [Bit 10] RW (@ 0x40015808) DBG_RTC_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_RTC_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_WWDG_STOP --------------------------
// SVD Line: 879
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_WWDG_STOP
// DBG_WWDG_STOP
//
// [Bit 11] RW (@ 0x40015808) DBG_WWDG_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_WWDG_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP --------------------------
// SVD Line: 883
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP
// DBG_IWDG_STOP
//
// [Bit 12] RW (@ 0x40015808) DBG_IWDG_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_IWDG_STOP
//
//
//
// --------------------- Field Item: DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP -------------------------
// SVD Line: 887
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP
// DBG_LPTIM1_STOP
//
// [Bit 31] RW (@ 0x40015808) DBG_LPTIM1_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ1 )
// DBG_LPTIM1_STOP
//
//
//
// --------------------------- Register RTree: DBGMCU_DBG_APB_FZ1 -------------------------------
// SVD Line: 863
// SFDITEM_REG__DBGMCU_DBG_APB_FZ1
// DBG_APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) DBG_APB_FZ1
// ( (unsigned int)((DBGMCU_DBG_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_DBG_APB_FZ1 = (DBGMCU_DBG_APB_FZ1 & ~(0x80001C03UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80001C03) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_TIM1_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_TIM3_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_RTC_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_WWDG_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_IWDG_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ1_DBG_LPTIM1_STOP
//
//
// ------------------------ Register Item Address: DBGMCU_DBG_APB_FZ2 ---------------------------
// SVD Line: 893
unsigned int DBGMCU_DBG_APB_FZ2 __AT (0x4001580C);
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP -------------------------
// SVD Line: 897
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP
// DBG_TIM14_STOP
//
// [Bit 15] RW (@ 0x4001580C) DBG_TIM14_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_TIM14_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_TIM16_STOP -------------------------
// SVD Line: 901
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM16_STOP
// DBG_TIM16_STOP
//
// [Bit 17] RW (@ 0x4001580C) DBG_TIM16_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_TIM16_STOP
//
//
//
// ---------------------- Field Item: DBGMCU_DBG_APB_FZ2_DBG_TIM17_STOP -------------------------
// SVD Line: 905
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM17_STOP
// DBG_TIM17_STOP
//
// [Bit 18] RW (@ 0x4001580C) DBG_TIM17_STOP
//
// ( (unsigned int) DBGMCU_DBG_APB_FZ2 )
// DBG_TIM17_STOP
//
//
//
// --------------------------- Register RTree: DBGMCU_DBG_APB_FZ2 -------------------------------
// SVD Line: 893
// SFDITEM_REG__DBGMCU_DBG_APB_FZ2
// DBG_APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) DBG_APB_FZ2
// ( (unsigned int)((DBGMCU_DBG_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_DBG_APB_FZ2 = (DBGMCU_DBG_APB_FZ2 & ~(0x68000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x68000) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM14_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM16_STOP
// - SFDITEM_FIELD__DBGMCU_DBG_APB_FZ2_DBG_TIM17_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 827
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_DBG_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_DBG_APB_FZ1
// - SFDITEM_REG__DBGMCU_DBG_APB_FZ2
//
//
// ----------------------------- Register Item Address: DMA_ISR ---------------------------------
// SVD Line: 938
unsigned int DMA_ISR __AT (0x40020000);
// -------------------------------- Field Item: DMA_ISR_TCIF1 -----------------------------------
// SVD Line: 943
// - SFDITEM_FIELD__DMA_ISR_TCIF1
// TCIF1
//
// [Bit 0] RO (@ 0x40020000) Transfer Complete Flag for Channel 1
//
// ( (unsigned int) DMA_ISR )
// TCIF1
//
//
//
// ------------------------------- Field Item: DMA_ISR_BTCIF1 -----------------------------------
// SVD Line: 949
// - SFDITEM_FIELD__DMA_ISR_BTCIF1
// BTCIF1
//
// [Bit 1] RO (@ 0x40020000) Block Transfer Complete Flag for Channel 1
//
// ( (unsigned int) DMA_ISR )
// BTCIF1
//
//
//
// ------------------------------- Field Item: DMA_ISR_HBTIF1 -----------------------------------
// SVD Line: 955
// - SFDITEM_FIELD__DMA_ISR_HBTIF1
// HBTIF1
//
// [Bit 2] RO (@ 0x40020000) Half Block Transfer Complete Flag for Channel 1
//
// ( (unsigned int) DMA_ISR )
// HBTIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF1 -----------------------------------
// SVD Line: 961
// - SFDITEM_FIELD__DMA_ISR_TEIF1
// TEIF1
//
// [Bit 3] RO (@ 0x40020000) Transfer Error Flag for Channel 1
//
// ( (unsigned int) DMA_ISR )
// TEIF1
//
//
//
// -------------------------------- Field Item: DMA_ISR_TCIF2 -----------------------------------
// SVD Line: 967
// - SFDITEM_FIELD__DMA_ISR_TCIF2
// TCIF2
//
// [Bit 4] RO (@ 0x40020000) Transfer Complete Flag for Channel 2
//
// ( (unsigned int) DMA_ISR )
// TCIF2
//
//
//
// ------------------------------- Field Item: DMA_ISR_BTCIF2 -----------------------------------
// SVD Line: 973
// - SFDITEM_FIELD__DMA_ISR_BTCIF2
// BTCIF2
//
// [Bit 5] RO (@ 0x40020000) Block Transfer Complete Flag for Channel 2
//
// ( (unsigned int) DMA_ISR )
// BTCIF2
//
//
//
// ------------------------------- Field Item: DMA_ISR_HBTIF2 -----------------------------------
// SVD Line: 979
// - SFDITEM_FIELD__DMA_ISR_HBTIF2
// HBTIF2
//
// [Bit 6] RO (@ 0x40020000) Half Block Transfer Complete Flag for Channel 2
//
// ( (unsigned int) DMA_ISR )
// HBTIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF2 -----------------------------------
// SVD Line: 985
// - SFDITEM_FIELD__DMA_ISR_TEIF2
// TEIF2
//
// [Bit 7] RO (@ 0x40020000) Transfer Error Flag for Channel 2
//
// ( (unsigned int) DMA_ISR )
// TEIF2
//
//
//
// -------------------------------- Field Item: DMA_ISR_TCIF3 -----------------------------------
// SVD Line: 991
// - SFDITEM_FIELD__DMA_ISR_TCIF3
// TCIF3
//
// [Bit 8] RO (@ 0x40020000) Transfer Complete Flag for Channel 3
//
// ( (unsigned int) DMA_ISR )
// TCIF3
//
//
//
// ------------------------------- Field Item: DMA_ISR_BTCIF3 -----------------------------------
// SVD Line: 997
// - SFDITEM_FIELD__DMA_ISR_BTCIF3
// BTCIF3
//
// [Bit 9] RO (@ 0x40020000) Block Transfer Complete Flag for Channel 3
//
// ( (unsigned int) DMA_ISR )
// BTCIF3
//
//
//
// ------------------------------- Field Item: DMA_ISR_HBTIF3 -----------------------------------
// SVD Line: 1003
// - SFDITEM_FIELD__DMA_ISR_HBTIF3
// HBTIF3
//
// [Bit 10] RO (@ 0x40020000) Half Block Transfer Complete Flag for Channel 3
//
// ( (unsigned int) DMA_ISR )
// HBTIF3
//
//
//
// -------------------------------- Field Item: DMA_ISR_TEIF3 -----------------------------------
// SVD Line: 1009
// - SFDITEM_FIELD__DMA_ISR_TEIF3
// TEIF3
//
// [Bit 11] RO (@ 0x40020000) Transfer Error Flag for Channel 3
//
// ( (unsigned int) DMA_ISR )
// TEIF3
//
//
//
// --------------------------------- Register RTree: DMA_ISR ------------------------------------
// SVD Line: 938
// SFDITEM_REG__DMA_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40020000) DMA interrupt status register(DMA_ISR)
// ( (unsigned int)((DMA_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DMA_ISR_TCIF1
// - SFDITEM_FIELD__DMA_ISR_BTCIF1
// - SFDITEM_FIELD__DMA_ISR_HBTIF1
// - SFDITEM_FIELD__DMA_ISR_TEIF1
// - SFDITEM_FIELD__DMA_ISR_TCIF2
// - SFDITEM_FIELD__DMA_ISR_BTCIF2
// - SFDITEM_FIELD__DMA_ISR_HBTIF2
// - SFDITEM_FIELD__DMA_ISR_TEIF2
// - SFDITEM_FIELD__DMA_ISR_TCIF3
// - SFDITEM_FIELD__DMA_ISR_BTCIF3
// - SFDITEM_FIELD__DMA_ISR_HBTIF3
// - SFDITEM_FIELD__DMA_ISR_TEIF3
//
//
// ----------------------------- Register Item Address: DMA_IFCR --------------------------------
// SVD Line: 1017
unsigned int DMA_IFCR __AT (0x40020004);
// ------------------------------- Field Item: DMA_IFCR_CTCIF1 ----------------------------------
// SVD Line: 1022
// - SFDITEM_FIELD__DMA_IFCR_CTCIF1
// CTCIF1
//
// [Bit 0] RW (@ 0x40020004) Transfer Complete Flag Clear for Channel 1
//
// ( (unsigned int) DMA_IFCR )
// CTCIF1
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CBTCIF1 ----------------------------------
// SVD Line: 1027
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF1
// CBTCIF1
//
// [Bit 1] RW (@ 0x40020004) Block Transfer Complete Flag Clear for Channel 1
//
// ( (unsigned int) DMA_IFCR )
// CBTCIF1
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CHBTIF1 ----------------------------------
// SVD Line: 1032
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF1
// CHBTIF1
//
// [Bit 2] RW (@ 0x40020004) Half Block Transfer Complete Flag Clear for Channel 1
//
// ( (unsigned int) DMA_IFCR )
// CHBTIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF1 ----------------------------------
// SVD Line: 1037
// - SFDITEM_FIELD__DMA_IFCR_CTEIF1
// CTEIF1
//
// [Bit 3] RW (@ 0x40020004) Transfer Error Flag Clear for Channel 1
//
// ( (unsigned int) DMA_IFCR )
// CTEIF1
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTCIF2 ----------------------------------
// SVD Line: 1042
// - SFDITEM_FIELD__DMA_IFCR_CTCIF2
// CTCIF2
//
// [Bit 4] RW (@ 0x40020004) Transfer Complete Flag Clear for Channel 2
//
// ( (unsigned int) DMA_IFCR )
// CTCIF2
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CBTCIF2 ----------------------------------
// SVD Line: 1047
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF2
// CBTCIF2
//
// [Bit 5] RW (@ 0x40020004) Block Transfer Complete Flag Clear for Channel 2
//
// ( (unsigned int) DMA_IFCR )
// CBTCIF2
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CHBTIF2 ----------------------------------
// SVD Line: 1052
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF2
// CHBTIF2
//
// [Bit 6] RW (@ 0x40020004) Half Block Transfer Complete Flag Clear for Channel 2
//
// ( (unsigned int) DMA_IFCR )
// CHBTIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF2 ----------------------------------
// SVD Line: 1057
// - SFDITEM_FIELD__DMA_IFCR_CTEIF2
// CTEIF2
//
// [Bit 7] RW (@ 0x40020004) Transfer Error Flag Clear for Channel 2
//
// ( (unsigned int) DMA_IFCR )
// CTEIF2
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTCIF3 ----------------------------------
// SVD Line: 1062
// - SFDITEM_FIELD__DMA_IFCR_CTCIF3
// CTCIF3
//
// [Bit 8] RW (@ 0x40020004) Transfer Complete Flag Clear for Channel 3
//
// ( (unsigned int) DMA_IFCR )
// CTCIF3
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CBTCIF3 ----------------------------------
// SVD Line: 1067
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF3
// CBTCIF3
//
// [Bit 9] RW (@ 0x40020004) Block Transfer Complete Flag Clear for Channel 3
//
// ( (unsigned int) DMA_IFCR )
// CBTCIF3
//
//
//
// ------------------------------ Field Item: DMA_IFCR_CHBTIF3 ----------------------------------
// SVD Line: 1072
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF3
// CHBTIF3
//
// [Bit 10] RW (@ 0x40020004) Half Block Transfer Complete Flag Clear for Channel 3
//
// ( (unsigned int) DMA_IFCR )
// CHBTIF3
//
//
//
// ------------------------------- Field Item: DMA_IFCR_CTEIF3 ----------------------------------
// SVD Line: 1077
// - SFDITEM_FIELD__DMA_IFCR_CTEIF3
// CTEIF3
//
// [Bit 11] RW (@ 0x40020004) Transfer Error Flag Clear for Channel 3
//
// ( (unsigned int) DMA_IFCR )
// CTEIF3
//
//
//
// -------------------------------- Register RTree: DMA_IFCR ------------------------------------
// SVD Line: 1017
// SFDITEM_REG__DMA_IFCR
// IFCR
//
// [Bits 31..0] RW (@ 0x40020004) DMA interrupt flag clear register(DMA_IFCR)
// ( (unsigned int)((DMA_IFCR >> 0) & 0xFFFFFFFF), ((DMA_IFCR = (DMA_IFCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_IFCR_CTCIF1
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF1
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF1
// - SFDITEM_FIELD__DMA_IFCR_CTEIF1
// - SFDITEM_FIELD__DMA_IFCR_CTCIF2
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF2
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF2
// - SFDITEM_FIELD__DMA_IFCR_CTEIF2
// - SFDITEM_FIELD__DMA_IFCR_CTCIF3
// - SFDITEM_FIELD__DMA_IFCR_CBTCIF3
// - SFDITEM_FIELD__DMA_IFCR_CHBTIF3
// - SFDITEM_FIELD__DMA_IFCR_CTEIF3
//
//
// ----------------------------- Register Item Address: DMA_CCR1 --------------------------------
// SVD Line: 1084
unsigned int DMA_CCR1 __AT (0x40020008);
// --------------------------------- Field Item: DMA_CCR1_EN ------------------------------------
// SVD Line: 1089
// - SFDITEM_FIELD__DMA_CCR1_EN
// EN
//
// [Bit 0] RW (@ 0x40020008) Channel Enable
//
// ( (unsigned int) DMA_CCR1 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR1_TCIE -----------------------------------
// SVD Line: 1094
// - SFDITEM_FIELD__DMA_CCR1_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x40020008) Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR1 )
// TCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR1_BTCIE -----------------------------------
// SVD Line: 1099
// - SFDITEM_FIELD__DMA_CCR1_BTCIE
// BTCIE
//
// [Bit 2] RW (@ 0x40020008) Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR1 )
// BTCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR1_HBTIE -----------------------------------
// SVD Line: 1104
// - SFDITEM_FIELD__DMA_CCR1_HBTIE
// HBTIE
//
// [Bit 3] RW (@ 0x40020008) Half Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR1 )
// HBTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR1_TEIE -----------------------------------
// SVD Line: 1109
// - SFDITEM_FIELD__DMA_CCR1_TEIE
// TEIE
//
// [Bit 4] RW (@ 0x40020008) Transfer Error Interrupt Enable
//
// ( (unsigned int) DMA_CCR1 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR1_DIR ------------------------------------
// SVD Line: 1114
// - SFDITEM_FIELD__DMA_CCR1_DIR
// DIR
//
// [Bit 5] RW (@ 0x40020008) Data Transfer Direction
//
// ( (unsigned int) DMA_CCR1 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR1_CIRC -----------------------------------
// SVD Line: 1119
// - SFDITEM_FIELD__DMA_CCR1_CIRC
// CIRC
//
// [Bit 6] RW (@ 0x40020008) Circular Mode
//
// ( (unsigned int) DMA_CCR1 )
// CIRC
//
//
//
// ------------------------------- Field Item: DMA_CCR1_TRANST ----------------------------------
// SVD Line: 1124
// - SFDITEM_FIELD__DMA_CCR1_TRANST
// TRANST
//
// [Bit 7] RW (@ 0x40020008) Transfer Type
//
// ( (unsigned int) DMA_CCR1 )
// TRANST
//
//
//
// -------------------------------- Field Item: DMA_CCR1_PINC -----------------------------------
// SVD Line: 1129
// - SFDITEM_FIELD__DMA_CCR1_PINC
// PINC
//
// [Bits 9..8] RW (@ 0x40020008) Peripheral Increment Mode
//
// ( (unsigned char)((DMA_CCR1 >> 8) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: DMA_CCR1_MINC -----------------------------------
// SVD Line: 1134
// - SFDITEM_FIELD__DMA_CCR1_MINC
// MINC
//
// [Bits 11..10] RW (@ 0x40020008) Memory Increment Mode
//
// ( (unsigned char)((DMA_CCR1 >> 10) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR1_PSIZE -----------------------------------
// SVD Line: 1139
// - SFDITEM_FIELD__DMA_CCR1_PSIZE
// PSIZE
//
// [Bits 13..12] RW (@ 0x40020008) Peripheral Size
//
// ( (unsigned char)((DMA_CCR1 >> 12) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR1_MSIZE -----------------------------------
// SVD Line: 1144
// - SFDITEM_FIELD__DMA_CCR1_MSIZE
// MSIZE
//
// [Bits 15..14] RW (@ 0x40020008) Memory Size
//
// ( (unsigned char)((DMA_CCR1 >> 14) & 0x3), ((DMA_CCR1 = (DMA_CCR1 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR1_PL ------------------------------------
// SVD Line: 1149
// - SFDITEM_FIELD__DMA_CCR1_PL
// PL
//
// [Bits 18..16] RW (@ 0x40020008) Priority Level
//
// ( (unsigned char)((DMA_CCR1 >> 16) & 0x7), ((DMA_CCR1 = (DMA_CCR1 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR1_MEM2MEM ----------------------------------
// SVD Line: 1154
// - SFDITEM_FIELD__DMA_CCR1_MEM2MEM
// MEM2MEM
//
// [Bit 19] RW (@ 0x40020008) Memory-to-memory Mode
//
// ( (unsigned int) DMA_CCR1 )
// MEM2MEM
//
//
//
// ------------------------------- Field Item: DMA_CCR1_PNORLD ----------------------------------
// SVD Line: 1159
// - SFDITEM_FIELD__DMA_CCR1_PNORLD
// PNORLD
//
// [Bit 20] RW (@ 0x40020008) Peripheral No Reload
//
// ( (unsigned int) DMA_CCR1 )
// PNORLD
//
//
//
// ------------------------------- Field Item: DMA_CCR1_MNORLD ----------------------------------
// SVD Line: 1164
// - SFDITEM_FIELD__DMA_CCR1_MNORLD
// MNORLD
//
// [Bit 21] RW (@ 0x40020008) Memory No Reload
//
// ( (unsigned int) DMA_CCR1 )
// MNORLD
//
//
//
// ------------------------------ Field Item: DMA_CCR1_BTCSUSP ----------------------------------
// SVD Line: 1169
// - SFDITEM_FIELD__DMA_CCR1_BTCSUSP
// BTCSUSP
//
// [Bit 22] RW (@ 0x40020008) Suspend in Block Transfer Complete Interrupt
//
// ( (unsigned int) DMA_CCR1 )
// BTCSUSP
//
//
//
// ------------------------------- Field Item: DMA_CCR1_M2MARB ----------------------------------
// SVD Line: 1174
// - SFDITEM_FIELD__DMA_CCR1_M2MARB
// M2MARB
//
// [Bit 23] RW (@ 0x40020008) Memory-to-memory Mode Arbitration
//
// ( (unsigned int) DMA_CCR1 )
// M2MARB
//
//
//
// -------------------------------- Register RTree: DMA_CCR1 ------------------------------------
// SVD Line: 1084
// SFDITEM_REG__DMA_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40020008) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR1 >> 0) & 0xFFFFFFFF), ((DMA_CCR1 = (DMA_CCR1 & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR1_EN
// - SFDITEM_FIELD__DMA_CCR1_TCIE
// - SFDITEM_FIELD__DMA_CCR1_BTCIE
// - SFDITEM_FIELD__DMA_CCR1_HBTIE
// - SFDITEM_FIELD__DMA_CCR1_TEIE
// - SFDITEM_FIELD__DMA_CCR1_DIR
// - SFDITEM_FIELD__DMA_CCR1_CIRC
// - SFDITEM_FIELD__DMA_CCR1_TRANST
// - SFDITEM_FIELD__DMA_CCR1_PINC
// - SFDITEM_FIELD__DMA_CCR1_MINC
// - SFDITEM_FIELD__DMA_CCR1_PSIZE
// - SFDITEM_FIELD__DMA_CCR1_MSIZE
// - SFDITEM_FIELD__DMA_CCR1_PL
// - SFDITEM_FIELD__DMA_CCR1_MEM2MEM
// - SFDITEM_FIELD__DMA_CCR1_PNORLD
// - SFDITEM_FIELD__DMA_CCR1_MNORLD
// - SFDITEM_FIELD__DMA_CCR1_BTCSUSP
// - SFDITEM_FIELD__DMA_CCR1_M2MARB
//
//
// ---------------------------- Register Item Address: DMA_CNDTR1 -------------------------------
// SVD Line: 1181
unsigned int DMA_CNDTR1 __AT (0x4002000C);
// ------------------------------- Field Item: DMA_CNDTR1_NDT -----------------------------------
// SVD Line: 1186
// - SFDITEM_FIELD__DMA_CNDTR1_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x4002000C) Number of Data to Transfer
//
// ( (unsigned short)((DMA_CNDTR1 >> 0) & 0xFFFF), ((DMA_CNDTR1 = (DMA_CNDTR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR1 -----------------------------------
// SVD Line: 1181
// SFDITEM_REG__DMA_CNDTR1
// CNDTR1
//
// [Bits 31..0] RW (@ 0x4002000C) DMA channel 1 number of dataregister
// ( (unsigned int)((DMA_CNDTR1 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR1 = (DMA_CNDTR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR1_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR1 --------------------------------
// SVD Line: 1193
unsigned int DMA_CPAR1 __AT (0x40020010);
// -------------------------------- Field Item: DMA_CPAR1_PA ------------------------------------
// SVD Line: 1198
// - SFDITEM_FIELD__DMA_CPAR1_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020010) Peripheral Address
//
// ( (unsigned int)((DMA_CPAR1 >> 0) & 0xFFFFFFFF), ((DMA_CPAR1 = (DMA_CPAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR1 -----------------------------------
// SVD Line: 1193
// SFDITEM_REG__DMA_CPAR1
// CPAR1
//
// [Bits 31..0] RW (@ 0x40020010) DMA channel 1 peripheral addressregister
// ( (unsigned int)((DMA_CPAR1 >> 0) & 0xFFFFFFFF), ((DMA_CPAR1 = (DMA_CPAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR1_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR1 --------------------------------
// SVD Line: 1205
unsigned int DMA_CMAR1 __AT (0x40020014);
// -------------------------------- Field Item: DMA_CMAR1_MA ------------------------------------
// SVD Line: 1210
// - SFDITEM_FIELD__DMA_CMAR1_MA
// MA
//
// [Bits 31..0] RW (@ 0x40020014) Memory Address
//
// ( (unsigned int)((DMA_CMAR1 >> 0) & 0xFFFFFFFF), ((DMA_CMAR1 = (DMA_CMAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR1 -----------------------------------
// SVD Line: 1205
// SFDITEM_REG__DMA_CMAR1
// CMAR1
//
// [Bits 31..0] RW (@ 0x40020014) DMA channel 1 memory addressregister
// ( (unsigned int)((DMA_CMAR1 >> 0) & 0xFFFFFFFF), ((DMA_CMAR1 = (DMA_CMAR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR1_MA
//
//
// --------------------------- Register Item Address: DMA_CCCFGR1 -------------------------------
// SVD Line: 1217
unsigned int DMA_CCCFGR1 __AT (0x40020018);
// ------------------------------- Field Item: DMA_CCCFGR1_NBT ----------------------------------
// SVD Line: 1221
// - SFDITEM_FIELD__DMA_CCCFGR1_NBT
// NBT
//
// [Bits 7..0] RW (@ 0x40020018) Number of Block to Loop Transfer
//
// ( (unsigned char)((DMA_CCCFGR1 >> 0) & 0xFF), ((DMA_CCCFGR1 = (DMA_CCCFGR1 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCCFGR1_NDTL ----------------------------------
// SVD Line: 1226
// - SFDITEM_FIELD__DMA_CCCFGR1_NDTL
// NDTL
//
// [Bits 31..16] RW (@ 0x40020018) Number of Data to Transfer Last Loop
//
// ( (unsigned short)((DMA_CCCFGR1 >> 16) & 0xFFFF), ((DMA_CCCFGR1 = (DMA_CCCFGR1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CCCFGR1 ----------------------------------
// SVD Line: 1217
// SFDITEM_REG__DMA_CCCFGR1
// CCCFGR1
//
// [Bits 31..0] RW (@ 0x40020018) CCCFGR1
// ( (unsigned int)((DMA_CCCFGR1 >> 0) & 0xFFFFFFFF), ((DMA_CCCFGR1 = (DMA_CCCFGR1 & ~(0xFFFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCCFGR1_NBT
// - SFDITEM_FIELD__DMA_CCCFGR1_NDTL
//
//
// ----------------------------- Register Item Address: DMA_CCR2 --------------------------------
// SVD Line: 1233
unsigned int DMA_CCR2 __AT (0x4002001C);
// --------------------------------- Field Item: DMA_CCR2_EN ------------------------------------
// SVD Line: 1238
// - SFDITEM_FIELD__DMA_CCR2_EN
// EN
//
// [Bit 0] RW (@ 0x4002001C) Channel Enable
//
// ( (unsigned int) DMA_CCR2 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR2_TCIE -----------------------------------
// SVD Line: 1243
// - SFDITEM_FIELD__DMA_CCR2_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x4002001C) Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR2 )
// TCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR2_BTCIE -----------------------------------
// SVD Line: 1248
// - SFDITEM_FIELD__DMA_CCR2_BTCIE
// BTCIE
//
// [Bit 2] RW (@ 0x4002001C) Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR2 )
// BTCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR2_HBTIE -----------------------------------
// SVD Line: 1253
// - SFDITEM_FIELD__DMA_CCR2_HBTIE
// HBTIE
//
// [Bit 3] RW (@ 0x4002001C) Half Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR2 )
// HBTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR2_TEIE -----------------------------------
// SVD Line: 1258
// - SFDITEM_FIELD__DMA_CCR2_TEIE
// TEIE
//
// [Bit 4] RW (@ 0x4002001C) Transfer Error Interrupt Enable
//
// ( (unsigned int) DMA_CCR2 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR2_DIR ------------------------------------
// SVD Line: 1263
// - SFDITEM_FIELD__DMA_CCR2_DIR
// DIR
//
// [Bit 5] RW (@ 0x4002001C) Data Transfer Direction
//
// ( (unsigned int) DMA_CCR2 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR2_CIRC -----------------------------------
// SVD Line: 1268
// - SFDITEM_FIELD__DMA_CCR2_CIRC
// CIRC
//
// [Bit 6] RW (@ 0x4002001C) Circular Mode
//
// ( (unsigned int) DMA_CCR2 )
// CIRC
//
//
//
// ------------------------------- Field Item: DMA_CCR2_TRANST ----------------------------------
// SVD Line: 1273
// - SFDITEM_FIELD__DMA_CCR2_TRANST
// TRANST
//
// [Bit 7] RW (@ 0x4002001C) Transfer Type
//
// ( (unsigned int) DMA_CCR2 )
// TRANST
//
//
//
// -------------------------------- Field Item: DMA_CCR2_PINC -----------------------------------
// SVD Line: 1278
// - SFDITEM_FIELD__DMA_CCR2_PINC
// PINC
//
// [Bits 9..8] RW (@ 0x4002001C) Peripheral Increment Mode
//
// ( (unsigned char)((DMA_CCR2 >> 8) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: DMA_CCR2_MINC -----------------------------------
// SVD Line: 1283
// - SFDITEM_FIELD__DMA_CCR2_MINC
// MINC
//
// [Bits 11..10] RW (@ 0x4002001C) Memory Increment Mode
//
// ( (unsigned char)((DMA_CCR2 >> 10) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR2_PSIZE -----------------------------------
// SVD Line: 1288
// - SFDITEM_FIELD__DMA_CCR2_PSIZE
// PSIZE
//
// [Bits 13..12] RW (@ 0x4002001C) Peripheral Size
//
// ( (unsigned char)((DMA_CCR2 >> 12) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR2_MSIZE -----------------------------------
// SVD Line: 1293
// - SFDITEM_FIELD__DMA_CCR2_MSIZE
// MSIZE
//
// [Bits 15..14] RW (@ 0x4002001C) Memory Size
//
// ( (unsigned char)((DMA_CCR2 >> 14) & 0x3), ((DMA_CCR2 = (DMA_CCR2 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR2_PL ------------------------------------
// SVD Line: 1298
// - SFDITEM_FIELD__DMA_CCR2_PL
// PL
//
// [Bits 18..16] RW (@ 0x4002001C) Priority Level
//
// ( (unsigned char)((DMA_CCR2 >> 16) & 0x7), ((DMA_CCR2 = (DMA_CCR2 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR2_MEM2MEM ----------------------------------
// SVD Line: 1303
// - SFDITEM_FIELD__DMA_CCR2_MEM2MEM
// MEM2MEM
//
// [Bit 19] RW (@ 0x4002001C) Memory-to-memory Mode
//
// ( (unsigned int) DMA_CCR2 )
// MEM2MEM
//
//
//
// ------------------------------- Field Item: DMA_CCR2_PNORLD ----------------------------------
// SVD Line: 1308
// - SFDITEM_FIELD__DMA_CCR2_PNORLD
// PNORLD
//
// [Bit 20] RW (@ 0x4002001C) Peripheral No Reload
//
// ( (unsigned int) DMA_CCR2 )
// PNORLD
//
//
//
// ------------------------------- Field Item: DMA_CCR2_MNORLD ----------------------------------
// SVD Line: 1313
// - SFDITEM_FIELD__DMA_CCR2_MNORLD
// MNORLD
//
// [Bit 21] RW (@ 0x4002001C) Memory No Reload
//
// ( (unsigned int) DMA_CCR2 )
// MNORLD
//
//
//
// ------------------------------ Field Item: DMA_CCR2_BTCSUSP ----------------------------------
// SVD Line: 1318
// - SFDITEM_FIELD__DMA_CCR2_BTCSUSP
// BTCSUSP
//
// [Bit 22] RW (@ 0x4002001C) Suspend in Block Transfer Complete Interrupt
//
// ( (unsigned int) DMA_CCR2 )
// BTCSUSP
//
//
//
// ------------------------------- Field Item: DMA_CCR2_M2MARB ----------------------------------
// SVD Line: 1323
// - SFDITEM_FIELD__DMA_CCR2_M2MARB
// M2MARB
//
// [Bit 23] RW (@ 0x4002001C) Memory-to-memory Mode Arbitration
//
// ( (unsigned int) DMA_CCR2 )
// M2MARB
//
//
//
// -------------------------------- Register RTree: DMA_CCR2 ------------------------------------
// SVD Line: 1233
// SFDITEM_REG__DMA_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x4002001C) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR2 >> 0) & 0xFFFFFFFF), ((DMA_CCR2 = (DMA_CCR2 & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR2_EN
// - SFDITEM_FIELD__DMA_CCR2_TCIE
// - SFDITEM_FIELD__DMA_CCR2_BTCIE
// - SFDITEM_FIELD__DMA_CCR2_HBTIE
// - SFDITEM_FIELD__DMA_CCR2_TEIE
// - SFDITEM_FIELD__DMA_CCR2_DIR
// - SFDITEM_FIELD__DMA_CCR2_CIRC
// - SFDITEM_FIELD__DMA_CCR2_TRANST
// - SFDITEM_FIELD__DMA_CCR2_PINC
// - SFDITEM_FIELD__DMA_CCR2_MINC
// - SFDITEM_FIELD__DMA_CCR2_PSIZE
// - SFDITEM_FIELD__DMA_CCR2_MSIZE
// - SFDITEM_FIELD__DMA_CCR2_PL
// - SFDITEM_FIELD__DMA_CCR2_MEM2MEM
// - SFDITEM_FIELD__DMA_CCR2_PNORLD
// - SFDITEM_FIELD__DMA_CCR2_MNORLD
// - SFDITEM_FIELD__DMA_CCR2_BTCSUSP
// - SFDITEM_FIELD__DMA_CCR2_M2MARB
//
//
// ---------------------------- Register Item Address: DMA_CNDTR2 -------------------------------
// SVD Line: 1330
unsigned int DMA_CNDTR2 __AT (0x40020020);
// ------------------------------- Field Item: DMA_CNDTR2_NDT -----------------------------------
// SVD Line: 1335
// - SFDITEM_FIELD__DMA_CNDTR2_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x40020020) Number of Data to Transfer
//
// ( (unsigned short)((DMA_CNDTR2 >> 0) & 0xFFFF), ((DMA_CNDTR2 = (DMA_CNDTR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR2 -----------------------------------
// SVD Line: 1330
// SFDITEM_REG__DMA_CNDTR2
// CNDTR2
//
// [Bits 31..0] RW (@ 0x40020020) DMA channel 2 number of dataregister
// ( (unsigned int)((DMA_CNDTR2 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR2 = (DMA_CNDTR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR2_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR2 --------------------------------
// SVD Line: 1342
unsigned int DMA_CPAR2 __AT (0x40020024);
// -------------------------------- Field Item: DMA_CPAR2_PA ------------------------------------
// SVD Line: 1347
// - SFDITEM_FIELD__DMA_CPAR2_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020024) Peripheral Address
//
// ( (unsigned int)((DMA_CPAR2 >> 0) & 0xFFFFFFFF), ((DMA_CPAR2 = (DMA_CPAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR2 -----------------------------------
// SVD Line: 1342
// SFDITEM_REG__DMA_CPAR2
// CPAR2
//
// [Bits 31..0] RW (@ 0x40020024) DMA channel 2 peripheral addressregister
// ( (unsigned int)((DMA_CPAR2 >> 0) & 0xFFFFFFFF), ((DMA_CPAR2 = (DMA_CPAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR2_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR2 --------------------------------
// SVD Line: 1354
unsigned int DMA_CMAR2 __AT (0x40020028);
// -------------------------------- Field Item: DMA_CMAR2_MA ------------------------------------
// SVD Line: 1359
// - SFDITEM_FIELD__DMA_CMAR2_MA
// MA
//
// [Bits 31..0] RW (@ 0x40020028) Memory Address
//
// ( (unsigned int)((DMA_CMAR2 >> 0) & 0xFFFFFFFF), ((DMA_CMAR2 = (DMA_CMAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR2 -----------------------------------
// SVD Line: 1354
// SFDITEM_REG__DMA_CMAR2
// CMAR2
//
// [Bits 31..0] RW (@ 0x40020028) DMA channel 2 memory addressregister
// ( (unsigned int)((DMA_CMAR2 >> 0) & 0xFFFFFFFF), ((DMA_CMAR2 = (DMA_CMAR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR2_MA
//
//
// --------------------------- Register Item Address: DMA_CCCFGR2 -------------------------------
// SVD Line: 1366
unsigned int DMA_CCCFGR2 __AT (0x4002002C);
// ------------------------------- Field Item: DMA_CCCFGR2_NBT ----------------------------------
// SVD Line: 1370
// - SFDITEM_FIELD__DMA_CCCFGR2_NBT
// NBT
//
// [Bits 7..0] RW (@ 0x4002002C) Number of Block to Loop Transfer
//
// ( (unsigned char)((DMA_CCCFGR2 >> 0) & 0xFF), ((DMA_CCCFGR2 = (DMA_CCCFGR2 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCCFGR2_NDTL ----------------------------------
// SVD Line: 1375
// - SFDITEM_FIELD__DMA_CCCFGR2_NDTL
// NDTL
//
// [Bits 31..16] RW (@ 0x4002002C) Number of Data to Transfer Last Loop
//
// ( (unsigned short)((DMA_CCCFGR2 >> 16) & 0xFFFF), ((DMA_CCCFGR2 = (DMA_CCCFGR2 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CCCFGR2 ----------------------------------
// SVD Line: 1366
// SFDITEM_REG__DMA_CCCFGR2
// CCCFGR2
//
// [Bits 31..0] RW (@ 0x4002002C) CCCFGR2
// ( (unsigned int)((DMA_CCCFGR2 >> 0) & 0xFFFFFFFF), ((DMA_CCCFGR2 = (DMA_CCCFGR2 & ~(0xFFFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCCFGR2_NBT
// - SFDITEM_FIELD__DMA_CCCFGR2_NDTL
//
//
// ----------------------------- Register Item Address: DMA_CCR3 --------------------------------
// SVD Line: 1382
unsigned int DMA_CCR3 __AT (0x40020030);
// --------------------------------- Field Item: DMA_CCR3_EN ------------------------------------
// SVD Line: 1387
// - SFDITEM_FIELD__DMA_CCR3_EN
// EN
//
// [Bit 0] RW (@ 0x40020030) Channel Enable
//
// ( (unsigned int) DMA_CCR3 )
// EN
//
//
//
// -------------------------------- Field Item: DMA_CCR3_TCIE -----------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__DMA_CCR3_TCIE
// TCIE
//
// [Bit 1] RW (@ 0x40020030) Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR3 )
// TCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR3_BTCIE -----------------------------------
// SVD Line: 1397
// - SFDITEM_FIELD__DMA_CCR3_BTCIE
// BTCIE
//
// [Bit 2] RW (@ 0x40020030) Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR3 )
// BTCIE
//
//
//
// ------------------------------- Field Item: DMA_CCR3_HBTIE -----------------------------------
// SVD Line: 1402
// - SFDITEM_FIELD__DMA_CCR3_HBTIE
// HBTIE
//
// [Bit 3] RW (@ 0x40020030) Half Block Transfer Complete Interrupt Enable
//
// ( (unsigned int) DMA_CCR3 )
// HBTIE
//
//
//
// -------------------------------- Field Item: DMA_CCR3_TEIE -----------------------------------
// SVD Line: 1407
// - SFDITEM_FIELD__DMA_CCR3_TEIE
// TEIE
//
// [Bit 4] RW (@ 0x40020030) Transfer Error Interrupt Enable
//
// ( (unsigned int) DMA_CCR3 )
// TEIE
//
//
//
// -------------------------------- Field Item: DMA_CCR3_DIR ------------------------------------
// SVD Line: 1412
// - SFDITEM_FIELD__DMA_CCR3_DIR
// DIR
//
// [Bit 5] RW (@ 0x40020030) Data Transfer Direction
//
// ( (unsigned int) DMA_CCR3 )
// DIR
//
//
//
// -------------------------------- Field Item: DMA_CCR3_CIRC -----------------------------------
// SVD Line: 1417
// - SFDITEM_FIELD__DMA_CCR3_CIRC
// CIRC
//
// [Bit 6] RW (@ 0x40020030) Circular Mode
//
// ( (unsigned int) DMA_CCR3 )
// CIRC
//
//
//
// ------------------------------- Field Item: DMA_CCR3_TRANST ----------------------------------
// SVD Line: 1422
// - SFDITEM_FIELD__DMA_CCR3_TRANST
// TRANST
//
// [Bit 7] RW (@ 0x40020030) Transfer Type
//
// ( (unsigned int) DMA_CCR3 )
// TRANST
//
//
//
// -------------------------------- Field Item: DMA_CCR3_PINC -----------------------------------
// SVD Line: 1427
// - SFDITEM_FIELD__DMA_CCR3_PINC
// PINC
//
// [Bits 9..8] RW (@ 0x40020030) Peripheral Increment Mode
//
// ( (unsigned char)((DMA_CCR3 >> 8) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: DMA_CCR3_MINC -----------------------------------
// SVD Line: 1432
// - SFDITEM_FIELD__DMA_CCR3_MINC
// MINC
//
// [Bits 11..10] RW (@ 0x40020030) Memory Increment Mode
//
// ( (unsigned char)((DMA_CCR3 >> 10) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR3_PSIZE -----------------------------------
// SVD Line: 1437
// - SFDITEM_FIELD__DMA_CCR3_PSIZE
// PSIZE
//
// [Bits 13..12] RW (@ 0x40020030) Peripheral Size
//
// ( (unsigned char)((DMA_CCR3 >> 12) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: DMA_CCR3_MSIZE -----------------------------------
// SVD Line: 1442
// - SFDITEM_FIELD__DMA_CCR3_MSIZE
// MSIZE
//
// [Bits 15..14] RW (@ 0x40020030) Memory Size
//
// ( (unsigned char)((DMA_CCR3 >> 14) & 0x3), ((DMA_CCR3 = (DMA_CCR3 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// --------------------------------- Field Item: DMA_CCR3_PL ------------------------------------
// SVD Line: 1447
// - SFDITEM_FIELD__DMA_CCR3_PL
// PL
//
// [Bits 18..16] RW (@ 0x40020030) Priority Level
//
// ( (unsigned char)((DMA_CCR3 >> 16) & 0x7), ((DMA_CCR3 = (DMA_CCR3 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCR3_MEM2MEM ----------------------------------
// SVD Line: 1452
// - SFDITEM_FIELD__DMA_CCR3_MEM2MEM
// MEM2MEM
//
// [Bit 19] RW (@ 0x40020030) Memory-to-memory Mode
//
// ( (unsigned int) DMA_CCR3 )
// MEM2MEM
//
//
//
// ------------------------------- Field Item: DMA_CCR3_PNORLD ----------------------------------
// SVD Line: 1457
// - SFDITEM_FIELD__DMA_CCR3_PNORLD
// PNORLD
//
// [Bit 20] RW (@ 0x40020030) Peripheral No Reload
//
// ( (unsigned int) DMA_CCR3 )
// PNORLD
//
//
//
// ------------------------------- Field Item: DMA_CCR3_MNORLD ----------------------------------
// SVD Line: 1462
// - SFDITEM_FIELD__DMA_CCR3_MNORLD
// MNORLD
//
// [Bit 21] RW (@ 0x40020030) Memory No Reload
//
// ( (unsigned int) DMA_CCR3 )
// MNORLD
//
//
//
// ------------------------------ Field Item: DMA_CCR3_BTCSUSP ----------------------------------
// SVD Line: 1467
// - SFDITEM_FIELD__DMA_CCR3_BTCSUSP
// BTCSUSP
//
// [Bit 22] RW (@ 0x40020030) Suspend in Block Transfer Complete Interrupt
//
// ( (unsigned int) DMA_CCR3 )
// BTCSUSP
//
//
//
// ------------------------------- Field Item: DMA_CCR3_M2MARB ----------------------------------
// SVD Line: 1472
// - SFDITEM_FIELD__DMA_CCR3_M2MARB
// M2MARB
//
// [Bit 23] RW (@ 0x40020030) Memory-to-memory Mode Arbitration
//
// ( (unsigned int) DMA_CCR3 )
// M2MARB
//
//
//
// -------------------------------- Register RTree: DMA_CCR3 ------------------------------------
// SVD Line: 1382
// SFDITEM_REG__DMA_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40020030) DMA channel configuration register(DMA_CCR)
// ( (unsigned int)((DMA_CCR3 >> 0) & 0xFFFFFFFF), ((DMA_CCR3 = (DMA_CCR3 & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCR3_EN
// - SFDITEM_FIELD__DMA_CCR3_TCIE
// - SFDITEM_FIELD__DMA_CCR3_BTCIE
// - SFDITEM_FIELD__DMA_CCR3_HBTIE
// - SFDITEM_FIELD__DMA_CCR3_TEIE
// - SFDITEM_FIELD__DMA_CCR3_DIR
// - SFDITEM_FIELD__DMA_CCR3_CIRC
// - SFDITEM_FIELD__DMA_CCR3_TRANST
// - SFDITEM_FIELD__DMA_CCR3_PINC
// - SFDITEM_FIELD__DMA_CCR3_MINC
// - SFDITEM_FIELD__DMA_CCR3_PSIZE
// - SFDITEM_FIELD__DMA_CCR3_MSIZE
// - SFDITEM_FIELD__DMA_CCR3_PL
// - SFDITEM_FIELD__DMA_CCR3_MEM2MEM
// - SFDITEM_FIELD__DMA_CCR3_PNORLD
// - SFDITEM_FIELD__DMA_CCR3_MNORLD
// - SFDITEM_FIELD__DMA_CCR3_BTCSUSP
// - SFDITEM_FIELD__DMA_CCR3_M2MARB
//
//
// ---------------------------- Register Item Address: DMA_CNDTR3 -------------------------------
// SVD Line: 1479
unsigned int DMA_CNDTR3 __AT (0x40020034);
// ------------------------------- Field Item: DMA_CNDTR3_NDT -----------------------------------
// SVD Line: 1484
// - SFDITEM_FIELD__DMA_CNDTR3_NDT
// NDT
//
// [Bits 15..0] RW (@ 0x40020034) Number of Data to Transfer
//
// ( (unsigned short)((DMA_CNDTR3 >> 0) & 0xFFFF), ((DMA_CNDTR3 = (DMA_CNDTR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CNDTR3 -----------------------------------
// SVD Line: 1479
// SFDITEM_REG__DMA_CNDTR3
// CNDTR3
//
// [Bits 31..0] RW (@ 0x40020034) DMA channel 3 number of dataregister
// ( (unsigned int)((DMA_CNDTR3 >> 0) & 0xFFFFFFFF), ((DMA_CNDTR3 = (DMA_CNDTR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CNDTR3_NDT
//
//
// ---------------------------- Register Item Address: DMA_CPAR3 --------------------------------
// SVD Line: 1491
unsigned int DMA_CPAR3 __AT (0x40020038);
// -------------------------------- Field Item: DMA_CPAR3_PA ------------------------------------
// SVD Line: 1496
// - SFDITEM_FIELD__DMA_CPAR3_PA
// PA
//
// [Bits 31..0] RW (@ 0x40020038) Peripheral Address
//
// ( (unsigned int)((DMA_CPAR3 >> 0) & 0xFFFFFFFF), ((DMA_CPAR3 = (DMA_CPAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CPAR3 -----------------------------------
// SVD Line: 1491
// SFDITEM_REG__DMA_CPAR3
// CPAR3
//
// [Bits 31..0] RW (@ 0x40020038) DMA channel 3 peripheral addressregister
// ( (unsigned int)((DMA_CPAR3 >> 0) & 0xFFFFFFFF), ((DMA_CPAR3 = (DMA_CPAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CPAR3_PA
//
//
// ---------------------------- Register Item Address: DMA_CMAR3 --------------------------------
// SVD Line: 1503
unsigned int DMA_CMAR3 __AT (0x4002003C);
// -------------------------------- Field Item: DMA_CMAR3_MA ------------------------------------
// SVD Line: 1508
// - SFDITEM_FIELD__DMA_CMAR3_MA
// MA
//
// [Bits 31..0] RW (@ 0x4002003C) Memory Address
//
// ( (unsigned int)((DMA_CMAR3 >> 0) & 0xFFFFFFFF), ((DMA_CMAR3 = (DMA_CMAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: DMA_CMAR3 -----------------------------------
// SVD Line: 1503
// SFDITEM_REG__DMA_CMAR3
// CMAR3
//
// [Bits 31..0] RW (@ 0x4002003C) DMA channel 3 memory addressregister
// ( (unsigned int)((DMA_CMAR3 >> 0) & 0xFFFFFFFF), ((DMA_CMAR3 = (DMA_CMAR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CMAR3_MA
//
//
// --------------------------- Register Item Address: DMA_CCCFGR3 -------------------------------
// SVD Line: 1515
unsigned int DMA_CCCFGR3 __AT (0x40020040);
// ------------------------------- Field Item: DMA_CCCFGR3_NBT ----------------------------------
// SVD Line: 1519
// - SFDITEM_FIELD__DMA_CCCFGR3_NBT
// NBT
//
// [Bits 7..0] RW (@ 0x40020040) Number of Block to Loop Transfer
//
// ( (unsigned char)((DMA_CCCFGR3 >> 0) & 0xFF), ((DMA_CCCFGR3 = (DMA_CCCFGR3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: DMA_CCCFGR3_NDTL ----------------------------------
// SVD Line: 1524
// - SFDITEM_FIELD__DMA_CCCFGR3_NDTL
// NDTL
//
// [Bits 31..16] RW (@ 0x40020040) Number of Data to Transfer Last Loop
//
// ( (unsigned short)((DMA_CCCFGR3 >> 16) & 0xFFFF), ((DMA_CCCFGR3 = (DMA_CCCFGR3 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: DMA_CCCFGR3 ----------------------------------
// SVD Line: 1515
// SFDITEM_REG__DMA_CCCFGR3
// CCCFGR3
//
// [Bits 31..0] RW (@ 0x40020040) CCCFGR3
// ( (unsigned int)((DMA_CCCFGR3 >> 0) & 0xFFFFFFFF), ((DMA_CCCFGR3 = (DMA_CCCFGR3 & ~(0xFFFF00FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF00FF) << 0 ) ) ))
// - SFDITEM_FIELD__DMA_CCCFGR3_NBT
// - SFDITEM_FIELD__DMA_CCCFGR3_NDTL
//
//
// ---------------------------------- Peripheral View: DMA --------------------------------------
// SVD Line: 913
// DMA
// DMA
// - SFDITEM_REG__DMA_ISR
// - SFDITEM_REG__DMA_IFCR
// - SFDITEM_REG__DMA_CCR1
// - SFDITEM_REG__DMA_CNDTR1
// - SFDITEM_REG__DMA_CPAR1
// - SFDITEM_REG__DMA_CMAR1
// - SFDITEM_REG__DMA_CCCFGR1
// - SFDITEM_REG__DMA_CCR2
// - SFDITEM_REG__DMA_CNDTR2
// - SFDITEM_REG__DMA_CPAR2
// - SFDITEM_REG__DMA_CMAR2
// - SFDITEM_REG__DMA_CCCFGR2
// - SFDITEM_REG__DMA_CCR3
// - SFDITEM_REG__DMA_CNDTR3
// - SFDITEM_REG__DMA_CPAR3
// - SFDITEM_REG__DMA_CMAR3
// - SFDITEM_REG__DMA_CCCFGR3
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 1563
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 1568
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) RT0
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 1572
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) RT1
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 1576
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) RT2
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 1580
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) RT3
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 1584
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) RT4
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 1588
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) RT5
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 1592
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) RT6
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 1596
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) RT7
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT8 -----------------------------------
// SVD Line: 1600
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// RT8
//
// [Bit 8] RW (@ 0x40021800) RT8
//
// ( (unsigned int) EXTI_RTSR )
// RT8
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT9 -----------------------------------
// SVD Line: 1604
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// RT9
//
// [Bit 9] RW (@ 0x40021800) RT9
//
// ( (unsigned int) EXTI_RTSR )
// RT9
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT10 -----------------------------------
// SVD Line: 1608
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// RT10
//
// [Bit 10] RW (@ 0x40021800) RT10
//
// ( (unsigned int) EXTI_RTSR )
// RT10
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT11 -----------------------------------
// SVD Line: 1612
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// RT11
//
// [Bit 11] RW (@ 0x40021800) RT11
//
// ( (unsigned int) EXTI_RTSR )
// RT11
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT12 -----------------------------------
// SVD Line: 1616
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// RT12
//
// [Bit 12] RW (@ 0x40021800) RT12
//
// ( (unsigned int) EXTI_RTSR )
// RT12
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT13 -----------------------------------
// SVD Line: 1620
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// RT13
//
// [Bit 13] RW (@ 0x40021800) RT13
//
// ( (unsigned int) EXTI_RTSR )
// RT13
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT14 -----------------------------------
// SVD Line: 1624
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// RT14
//
// [Bit 14] RW (@ 0x40021800) RT14
//
// ( (unsigned int) EXTI_RTSR )
// RT14
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT15 -----------------------------------
// SVD Line: 1628
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// RT15
//
// [Bit 15] RW (@ 0x40021800) RT15
//
// ( (unsigned int) EXTI_RTSR )
// RT15
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT16 -----------------------------------
// SVD Line: 1632
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// RT16
//
// [Bit 16] RW (@ 0x40021800) RT16
//
// ( (unsigned int) EXTI_RTSR )
// RT16
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT17 -----------------------------------
// SVD Line: 1636
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// RT17
//
// [Bit 17] RW (@ 0x40021800) RT17
//
// ( (unsigned int) EXTI_RTSR )
// RT17
//
//
//
// ------------------------------- Field Item: EXTI_RTSR_RT18 -----------------------------------
// SVD Line: 1640
// - SFDITEM_FIELD__EXTI_RTSR_RT18
// RT18
//
// [Bit 18] RW (@ 0x40021800) RT18
//
// ( (unsigned int) EXTI_RTSR )
// RT18
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 1563
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selectionregister
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// - SFDITEM_FIELD__EXTI_RTSR_RT8
// - SFDITEM_FIELD__EXTI_RTSR_RT9
// - SFDITEM_FIELD__EXTI_RTSR_RT10
// - SFDITEM_FIELD__EXTI_RTSR_RT11
// - SFDITEM_FIELD__EXTI_RTSR_RT12
// - SFDITEM_FIELD__EXTI_RTSR_RT13
// - SFDITEM_FIELD__EXTI_RTSR_RT14
// - SFDITEM_FIELD__EXTI_RTSR_RT15
// - SFDITEM_FIELD__EXTI_RTSR_RT16
// - SFDITEM_FIELD__EXTI_RTSR_RT17
// - SFDITEM_FIELD__EXTI_RTSR_RT18
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 1646
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 1651
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) FT0
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 1655
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) FT1
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 1659
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) FT2
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 1663
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) FT3
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 1667
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) FT4
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 1671
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) FT5
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 1675
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) FT6
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 1679
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) FT7
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT8 -----------------------------------
// SVD Line: 1683
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// FT8
//
// [Bit 8] RW (@ 0x40021804) FT8
//
// ( (unsigned int) EXTI_FTSR )
// FT8
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT9 -----------------------------------
// SVD Line: 1687
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// FT9
//
// [Bit 9] RW (@ 0x40021804) FT9
//
// ( (unsigned int) EXTI_FTSR )
// FT9
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT10 -----------------------------------
// SVD Line: 1691
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// FT10
//
// [Bit 10] RW (@ 0x40021804) FT10
//
// ( (unsigned int) EXTI_FTSR )
// FT10
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT11 -----------------------------------
// SVD Line: 1695
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// FT11
//
// [Bit 11] RW (@ 0x40021804) FT11
//
// ( (unsigned int) EXTI_FTSR )
// FT11
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT12 -----------------------------------
// SVD Line: 1699
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// FT12
//
// [Bit 12] RW (@ 0x40021804) FT12
//
// ( (unsigned int) EXTI_FTSR )
// FT12
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT13 -----------------------------------
// SVD Line: 1703
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// FT13
//
// [Bit 13] RW (@ 0x40021804) FT13
//
// ( (unsigned int) EXTI_FTSR )
// FT13
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT14 -----------------------------------
// SVD Line: 1707
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// FT14
//
// [Bit 14] RW (@ 0x40021804) FT14
//
// ( (unsigned int) EXTI_FTSR )
// FT14
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT15 -----------------------------------
// SVD Line: 1711
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// FT15
//
// [Bit 15] RW (@ 0x40021804) FT15
//
// ( (unsigned int) EXTI_FTSR )
// FT15
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT16 -----------------------------------
// SVD Line: 1715
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// FT16
//
// [Bit 16] RW (@ 0x40021804) FT16
//
// ( (unsigned int) EXTI_FTSR )
// FT16
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT17 -----------------------------------
// SVD Line: 1719
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// FT17
//
// [Bit 17] RW (@ 0x40021804) FT17
//
// ( (unsigned int) EXTI_FTSR )
// FT17
//
//
//
// ------------------------------- Field Item: EXTI_FTSR_FT18 -----------------------------------
// SVD Line: 1723
// - SFDITEM_FIELD__EXTI_FTSR_FT18
// FT18
//
// [Bit 18] RW (@ 0x40021804) FT18
//
// ( (unsigned int) EXTI_FTSR )
// FT18
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 1646
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selectionregister
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// - SFDITEM_FIELD__EXTI_FTSR_FT8
// - SFDITEM_FIELD__EXTI_FTSR_FT9
// - SFDITEM_FIELD__EXTI_FTSR_FT10
// - SFDITEM_FIELD__EXTI_FTSR_FT11
// - SFDITEM_FIELD__EXTI_FTSR_FT12
// - SFDITEM_FIELD__EXTI_FTSR_FT13
// - SFDITEM_FIELD__EXTI_FTSR_FT14
// - SFDITEM_FIELD__EXTI_FTSR_FT15
// - SFDITEM_FIELD__EXTI_FTSR_FT16
// - SFDITEM_FIELD__EXTI_FTSR_FT17
// - SFDITEM_FIELD__EXTI_FTSR_FT18
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 1729
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------ Field Item: EXTI_SWIER_SWIE0 ----------------------------------
// SVD Line: 1734
// - SFDITEM_FIELD__EXTI_SWIER_SWIE0
// SWIE0
//
// [Bit 0] RW (@ 0x40021808) SWIE0
//
// ( (unsigned int) EXTI_SWIER )
// SWIE0
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE1 ----------------------------------
// SVD Line: 1738
// - SFDITEM_FIELD__EXTI_SWIER_SWIE1
// SWIE1
//
// [Bit 1] RW (@ 0x40021808) SWIE1
//
// ( (unsigned int) EXTI_SWIER )
// SWIE1
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE2 ----------------------------------
// SVD Line: 1742
// - SFDITEM_FIELD__EXTI_SWIER_SWIE2
// SWIE2
//
// [Bit 2] RW (@ 0x40021808) SWIE2
//
// ( (unsigned int) EXTI_SWIER )
// SWIE2
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE3 ----------------------------------
// SVD Line: 1746
// - SFDITEM_FIELD__EXTI_SWIER_SWIE3
// SWIE3
//
// [Bit 3] RW (@ 0x40021808) SWIE3
//
// ( (unsigned int) EXTI_SWIER )
// SWIE3
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE4 ----------------------------------
// SVD Line: 1750
// - SFDITEM_FIELD__EXTI_SWIER_SWIE4
// SWIE4
//
// [Bit 4] RW (@ 0x40021808) SWIE4
//
// ( (unsigned int) EXTI_SWIER )
// SWIE4
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE5 ----------------------------------
// SVD Line: 1754
// - SFDITEM_FIELD__EXTI_SWIER_SWIE5
// SWIE5
//
// [Bit 5] RW (@ 0x40021808) SWIE5
//
// ( (unsigned int) EXTI_SWIER )
// SWIE5
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE6 ----------------------------------
// SVD Line: 1758
// - SFDITEM_FIELD__EXTI_SWIER_SWIE6
// SWIE6
//
// [Bit 6] RW (@ 0x40021808) SWIE6
//
// ( (unsigned int) EXTI_SWIER )
// SWIE6
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE7 ----------------------------------
// SVD Line: 1762
// - SFDITEM_FIELD__EXTI_SWIER_SWIE7
// SWIE7
//
// [Bit 7] RW (@ 0x40021808) SWIE7
//
// ( (unsigned int) EXTI_SWIER )
// SWIE7
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE8 ----------------------------------
// SVD Line: 1766
// - SFDITEM_FIELD__EXTI_SWIER_SWIE8
// SWIE8
//
// [Bit 8] RW (@ 0x40021808) SWIE8
//
// ( (unsigned int) EXTI_SWIER )
// SWIE8
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE9 ----------------------------------
// SVD Line: 1770
// - SFDITEM_FIELD__EXTI_SWIER_SWIE9
// SWIE9
//
// [Bit 9] RW (@ 0x40021808) SWIE9
//
// ( (unsigned int) EXTI_SWIER )
// SWIE9
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE10 ---------------------------------
// SVD Line: 1774
// - SFDITEM_FIELD__EXTI_SWIER_SWIE10
// SWIE10
//
// [Bit 10] RW (@ 0x40021808) SWIE10
//
// ( (unsigned int) EXTI_SWIER )
// SWIE10
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE11 ---------------------------------
// SVD Line: 1778
// - SFDITEM_FIELD__EXTI_SWIER_SWIE11
// SWIE11
//
// [Bit 11] RW (@ 0x40021808) SWIE11
//
// ( (unsigned int) EXTI_SWIER )
// SWIE11
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE12 ---------------------------------
// SVD Line: 1782
// - SFDITEM_FIELD__EXTI_SWIER_SWIE12
// SWIE12
//
// [Bit 12] RW (@ 0x40021808) SWIE12
//
// ( (unsigned int) EXTI_SWIER )
// SWIE12
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE13 ---------------------------------
// SVD Line: 1786
// - SFDITEM_FIELD__EXTI_SWIER_SWIE13
// SWIE13
//
// [Bit 13] RW (@ 0x40021808) SWIE13
//
// ( (unsigned int) EXTI_SWIER )
// SWIE13
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE14 ---------------------------------
// SVD Line: 1790
// - SFDITEM_FIELD__EXTI_SWIER_SWIE14
// SWIE14
//
// [Bit 14] RW (@ 0x40021808) SWIE14
//
// ( (unsigned int) EXTI_SWIER )
// SWIE14
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE15 ---------------------------------
// SVD Line: 1794
// - SFDITEM_FIELD__EXTI_SWIER_SWIE15
// SWIE15
//
// [Bit 15] RW (@ 0x40021808) SWIE15
//
// ( (unsigned int) EXTI_SWIER )
// SWIE15
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE16 ---------------------------------
// SVD Line: 1798
// - SFDITEM_FIELD__EXTI_SWIER_SWIE16
// SWIE16
//
// [Bit 16] RW (@ 0x40021808) SWIE16
//
// ( (unsigned int) EXTI_SWIER )
// SWIE16
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE17 ---------------------------------
// SVD Line: 1802
// - SFDITEM_FIELD__EXTI_SWIER_SWIE17
// SWIE17
//
// [Bit 17] RW (@ 0x40021808) SWIE17
//
// ( (unsigned int) EXTI_SWIER )
// SWIE17
//
//
//
// ------------------------------ Field Item: EXTI_SWIER_SWIE18 ---------------------------------
// SVD Line: 1806
// - SFDITEM_FIELD__EXTI_SWIER_SWIE18
// SWIE18
//
// [Bit 18] RW (@ 0x40021808) SWIE18
//
// ( (unsigned int) EXTI_SWIER )
// SWIE18
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 1729
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt eventregister
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWIE0
// - SFDITEM_FIELD__EXTI_SWIER_SWIE1
// - SFDITEM_FIELD__EXTI_SWIER_SWIE2
// - SFDITEM_FIELD__EXTI_SWIER_SWIE3
// - SFDITEM_FIELD__EXTI_SWIER_SWIE4
// - SFDITEM_FIELD__EXTI_SWIER_SWIE5
// - SFDITEM_FIELD__EXTI_SWIER_SWIE6
// - SFDITEM_FIELD__EXTI_SWIER_SWIE7
// - SFDITEM_FIELD__EXTI_SWIER_SWIE8
// - SFDITEM_FIELD__EXTI_SWIER_SWIE9
// - SFDITEM_FIELD__EXTI_SWIER_SWIE10
// - SFDITEM_FIELD__EXTI_SWIER_SWIE11
// - SFDITEM_FIELD__EXTI_SWIER_SWIE12
// - SFDITEM_FIELD__EXTI_SWIER_SWIE13
// - SFDITEM_FIELD__EXTI_SWIER_SWIE14
// - SFDITEM_FIELD__EXTI_SWIER_SWIE15
// - SFDITEM_FIELD__EXTI_SWIER_SWIE16
// - SFDITEM_FIELD__EXTI_SWIER_SWIE17
// - SFDITEM_FIELD__EXTI_SWIER_SWIE18
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 1812
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 1817
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) PR0
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 1821
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) PR1
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 1825
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) PR2
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 1829
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) PR3
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 1833
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) PR4
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 1837
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) PR5
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 1841
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) PR6
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 1845
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) PR7
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR8 ------------------------------------
// SVD Line: 1849
// - SFDITEM_FIELD__EXTI_PR_PR8
// PR8
//
// [Bit 8] RW (@ 0x4002180C) PR8
//
// ( (unsigned int) EXTI_PR )
// PR8
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR9 ------------------------------------
// SVD Line: 1853
// - SFDITEM_FIELD__EXTI_PR_PR9
// PR9
//
// [Bit 9] RW (@ 0x4002180C) PR9
//
// ( (unsigned int) EXTI_PR )
// PR9
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR10 ------------------------------------
// SVD Line: 1857
// - SFDITEM_FIELD__EXTI_PR_PR10
// PR10
//
// [Bit 10] RW (@ 0x4002180C) PR10
//
// ( (unsigned int) EXTI_PR )
// PR10
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR11 ------------------------------------
// SVD Line: 1861
// - SFDITEM_FIELD__EXTI_PR_PR11
// PR11
//
// [Bit 11] RW (@ 0x4002180C) PR11
//
// ( (unsigned int) EXTI_PR )
// PR11
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR12 ------------------------------------
// SVD Line: 1865
// - SFDITEM_FIELD__EXTI_PR_PR12
// PR12
//
// [Bit 12] RW (@ 0x4002180C) PR12
//
// ( (unsigned int) EXTI_PR )
// PR12
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR13 ------------------------------------
// SVD Line: 1869
// - SFDITEM_FIELD__EXTI_PR_PR13
// PR13
//
// [Bit 13] RW (@ 0x4002180C) PR13
//
// ( (unsigned int) EXTI_PR )
// PR13
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR14 ------------------------------------
// SVD Line: 1873
// - SFDITEM_FIELD__EXTI_PR_PR14
// PR14
//
// [Bit 14] RW (@ 0x4002180C) PR14
//
// ( (unsigned int) EXTI_PR )
// PR14
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR15 ------------------------------------
// SVD Line: 1877
// - SFDITEM_FIELD__EXTI_PR_PR15
// PR15
//
// [Bit 15] RW (@ 0x4002180C) PR15
//
// ( (unsigned int) EXTI_PR )
// PR15
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR16 ------------------------------------
// SVD Line: 1881
// - SFDITEM_FIELD__EXTI_PR_PR16
// PR16
//
// [Bit 16] RW (@ 0x4002180C) PR16
//
// ( (unsigned int) EXTI_PR )
// PR16
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR17 ------------------------------------
// SVD Line: 1885
// - SFDITEM_FIELD__EXTI_PR_PR17
// PR17
//
// [Bit 17] RW (@ 0x4002180C) PR17
//
// ( (unsigned int) EXTI_PR )
// PR17
//
//
//
// -------------------------------- Field Item: EXTI_PR_PR18 ------------------------------------
// SVD Line: 1889
// - SFDITEM_FIELD__EXTI_PR_PR18
// PR18
//
// [Bit 18] RW (@ 0x4002180C) PR18
//
// ( (unsigned int) EXTI_PR )
// PR18
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 1812
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pendingregister
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0x7FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
// - SFDITEM_FIELD__EXTI_PR_PR8
// - SFDITEM_FIELD__EXTI_PR_PR9
// - SFDITEM_FIELD__EXTI_PR_PR10
// - SFDITEM_FIELD__EXTI_PR_PR11
// - SFDITEM_FIELD__EXTI_PR_PR12
// - SFDITEM_FIELD__EXTI_PR_PR13
// - SFDITEM_FIELD__EXTI_PR_PR14
// - SFDITEM_FIELD__EXTI_PR_PR15
// - SFDITEM_FIELD__EXTI_PR_PR16
// - SFDITEM_FIELD__EXTI_PR_PR17
// - SFDITEM_FIELD__EXTI_PR_PR18
//
//
// --------------------------- Register Item Address: EXTI_IOSEL1 -------------------------------
// SVD Line: 1895
unsigned int EXTI_IOSEL1 __AT (0x40021810);
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI0SEL --------------------------------
// SVD Line: 1899
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI0SEL
// EXTI0SEL
//
// [Bits 1..0] RW (@ 0x40021810) EXTI0SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 0) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI1SEL --------------------------------
// SVD Line: 1903
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI1SEL
// EXTI1SEL
//
// [Bits 5..4] RW (@ 0x40021810) EXTI1SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 4) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI2SEL --------------------------------
// SVD Line: 1907
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI2SEL
// EXTI2SEL
//
// [Bits 9..8] RW (@ 0x40021810) EXTI2SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 8) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI3SEL --------------------------------
// SVD Line: 1911
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI3SEL
// EXTI3SEL
//
// [Bits 13..12] RW (@ 0x40021810) EXTI3SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 12) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI4SEL --------------------------------
// SVD Line: 1915
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI4SEL
// EXTI4SEL
//
// [Bits 17..16] RW (@ 0x40021810) EXTI4SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 16) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI5SEL --------------------------------
// SVD Line: 1919
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI5SEL
// EXTI5SEL
//
// [Bits 21..20] RW (@ 0x40021810) EXTI5SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 20) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI6SEL --------------------------------
// SVD Line: 1923
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI6SEL
// EXTI6SEL
//
// [Bits 25..24] RW (@ 0x40021810) EXTI6SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 24) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL1_EXTI7SEL --------------------------------
// SVD Line: 1927
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI7SEL
// EXTI7SEL
//
// [Bits 29..28] RW (@ 0x40021810) EXTI7SEL
//
// ( (unsigned char)((EXTI_IOSEL1 >> 28) & 0x3), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: EXTI_IOSEL1 ----------------------------------
// SVD Line: 1895
// SFDITEM_REG__EXTI_IOSEL1
// IOSEL1
//
// [Bits 31..0] RW (@ 0x40021810) IOSEL1
// ( (unsigned int)((EXTI_IOSEL1 >> 0) & 0xFFFFFFFF), ((EXTI_IOSEL1 = (EXTI_IOSEL1 & ~(0x33333333UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33333333) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI0SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI1SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI2SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI3SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI4SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI5SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI6SEL
// - SFDITEM_FIELD__EXTI_IOSEL1_EXTI7SEL
//
//
// --------------------------- Register Item Address: EXTI_IOSEL2 -------------------------------
// SVD Line: 1933
unsigned int EXTI_IOSEL2 __AT (0x40021814);
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI8SEL --------------------------------
// SVD Line: 1937
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI8SEL
// EXTI8SEL
//
// [Bits 1..0] RW (@ 0x40021814) EXTI8SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 0) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI9SEL --------------------------------
// SVD Line: 1941
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI9SEL
// EXTI9SEL
//
// [Bits 5..4] RW (@ 0x40021814) EXTI9SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 4) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI10SEL -------------------------------
// SVD Line: 1945
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI10SEL
// EXTI10SEL
//
// [Bits 9..8] RW (@ 0x40021814) EXTI10SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 8) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI11SEL -------------------------------
// SVD Line: 1949
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI11SEL
// EXTI11SEL
//
// [Bits 13..12] RW (@ 0x40021814) EXTI11SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 12) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI12SEL -------------------------------
// SVD Line: 1953
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI12SEL
// EXTI12SEL
//
// [Bits 17..16] RW (@ 0x40021814) EXTI12SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 16) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI13SEL -------------------------------
// SVD Line: 1957
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI13SEL
// EXTI13SEL
//
// [Bits 21..20] RW (@ 0x40021814) EXTI13SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 20) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI14SEL -------------------------------
// SVD Line: 1961
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI14SEL
// EXTI14SEL
//
// [Bits 25..24] RW (@ 0x40021814) EXTI14SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 24) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ---------------------------- Field Item: EXTI_IOSEL2_EXTI15SEL -------------------------------
// SVD Line: 1965
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI15SEL
// EXTI15SEL
//
// [Bits 29..28] RW (@ 0x40021814) EXTI15SEL
//
// ( (unsigned char)((EXTI_IOSEL2 >> 28) & 0x3), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: EXTI_IOSEL2 ----------------------------------
// SVD Line: 1933
// SFDITEM_REG__EXTI_IOSEL2
// IOSEL2
//
// [Bits 31..0] RW (@ 0x40021814) IOSEL2
// ( (unsigned int)((EXTI_IOSEL2 >> 0) & 0xFFFFFFFF), ((EXTI_IOSEL2 = (EXTI_IOSEL2 & ~(0x33333333UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33333333) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI8SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI9SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI10SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI11SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI12SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI13SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI14SEL
// - SFDITEM_FIELD__EXTI_IOSEL2_EXTI15SEL
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 1971
unsigned int EXTI_IMR __AT (0x40021818);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 1976
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021818) IM0
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 1980
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021818) IM1
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 1984
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021818) IM2
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 1988
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021818) IM3
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 1992
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021818) IM4
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 1996
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021818) IM5
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 2000
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021818) IM6
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 2004
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021818) IM7
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM8 ------------------------------------
// SVD Line: 2008
// - SFDITEM_FIELD__EXTI_IMR_IM8
// IM8
//
// [Bit 8] RW (@ 0x40021818) IM8
//
// ( (unsigned int) EXTI_IMR )
// IM8
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM9 ------------------------------------
// SVD Line: 2012
// - SFDITEM_FIELD__EXTI_IMR_IM9
// IM9
//
// [Bit 9] RW (@ 0x40021818) IM9
//
// ( (unsigned int) EXTI_IMR )
// IM9
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM10 -----------------------------------
// SVD Line: 2016
// - SFDITEM_FIELD__EXTI_IMR_IM10
// IM10
//
// [Bit 10] RW (@ 0x40021818) IM10
//
// ( (unsigned int) EXTI_IMR )
// IM10
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM11 -----------------------------------
// SVD Line: 2020
// - SFDITEM_FIELD__EXTI_IMR_IM11
// IM11
//
// [Bit 11] RW (@ 0x40021818) IM11
//
// ( (unsigned int) EXTI_IMR )
// IM11
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM12 -----------------------------------
// SVD Line: 2024
// - SFDITEM_FIELD__EXTI_IMR_IM12
// IM12
//
// [Bit 12] RW (@ 0x40021818) IM12
//
// ( (unsigned int) EXTI_IMR )
// IM12
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM13 -----------------------------------
// SVD Line: 2028
// - SFDITEM_FIELD__EXTI_IMR_IM13
// IM13
//
// [Bit 13] RW (@ 0x40021818) IM13
//
// ( (unsigned int) EXTI_IMR )
// IM13
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM14 -----------------------------------
// SVD Line: 2032
// - SFDITEM_FIELD__EXTI_IMR_IM14
// IM14
//
// [Bit 14] RW (@ 0x40021818) IM14
//
// ( (unsigned int) EXTI_IMR )
// IM14
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM15 -----------------------------------
// SVD Line: 2036
// - SFDITEM_FIELD__EXTI_IMR_IM15
// IM15
//
// [Bit 15] RW (@ 0x40021818) IM15
//
// ( (unsigned int) EXTI_IMR )
// IM15
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM16 -----------------------------------
// SVD Line: 2040
// - SFDITEM_FIELD__EXTI_IMR_IM16
// IM16
//
// [Bit 16] RW (@ 0x40021818) IM16
//
// ( (unsigned int) EXTI_IMR )
// IM16
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM17 -----------------------------------
// SVD Line: 2044
// - SFDITEM_FIELD__EXTI_IMR_IM17
// IM17
//
// [Bit 17] RW (@ 0x40021818) IM17
//
// ( (unsigned int) EXTI_IMR )
// IM17
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM18 -----------------------------------
// SVD Line: 2048
// - SFDITEM_FIELD__EXTI_IMR_IM18
// IM18
//
// [Bit 18] RW (@ 0x40021818) IM18
//
// ( (unsigned int) EXTI_IMR )
// IM18
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM20 -----------------------------------
// SVD Line: 2052
// - SFDITEM_FIELD__EXTI_IMR_IM20
// IM20
//
// [Bit 20] RW (@ 0x40021818) IM20
//
// ( (unsigned int) EXTI_IMR )
// IM20
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM22 -----------------------------------
// SVD Line: 2056
// - SFDITEM_FIELD__EXTI_IMR_IM22
// IM22
//
// [Bit 22] RW (@ 0x40021818) IM22
//
// ( (unsigned int) EXTI_IMR )
// IM22
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM24 -----------------------------------
// SVD Line: 2060
// - SFDITEM_FIELD__EXTI_IMR_IM24
// IM24
//
// [Bit 24] RW (@ 0x40021818) IM24
//
// ( (unsigned int) EXTI_IMR )
// IM24
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM25 -----------------------------------
// SVD Line: 2064
// - SFDITEM_FIELD__EXTI_IMR_IM25
// IM25
//
// [Bit 25] RW (@ 0x40021818) IM25
//
// ( (unsigned int) EXTI_IMR )
// IM25
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM27 -----------------------------------
// SVD Line: 2068
// - SFDITEM_FIELD__EXTI_IMR_IM27
// IM27
//
// [Bit 27] RW (@ 0x40021818) IM27
//
// ( (unsigned int) EXTI_IMR )
// IM27
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 1971
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021818) EXTI CPU wakeup with interrupt maskregister
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0xB57FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB57FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM8
// - SFDITEM_FIELD__EXTI_IMR_IM9
// - SFDITEM_FIELD__EXTI_IMR_IM10
// - SFDITEM_FIELD__EXTI_IMR_IM11
// - SFDITEM_FIELD__EXTI_IMR_IM12
// - SFDITEM_FIELD__EXTI_IMR_IM13
// - SFDITEM_FIELD__EXTI_IMR_IM14
// - SFDITEM_FIELD__EXTI_IMR_IM15
// - SFDITEM_FIELD__EXTI_IMR_IM16
// - SFDITEM_FIELD__EXTI_IMR_IM17
// - SFDITEM_FIELD__EXTI_IMR_IM18
// - SFDITEM_FIELD__EXTI_IMR_IM20
// - SFDITEM_FIELD__EXTI_IMR_IM22
// - SFDITEM_FIELD__EXTI_IMR_IM24
// - SFDITEM_FIELD__EXTI_IMR_IM25
// - SFDITEM_FIELD__EXTI_IMR_IM27
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 2074
unsigned int EXTI_EMR __AT (0x4002181C);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 2079
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x4002181C) EM0
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 2083
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x4002181C) EM1
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 2087
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x4002181C) EM2
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 2091
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x4002181C) EM3
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 2095
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x4002181C) EM4
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 2099
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x4002181C) EM5
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x4002181C) EM6
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 2107
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x4002181C) EM7
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM8 ------------------------------------
// SVD Line: 2111
// - SFDITEM_FIELD__EXTI_EMR_EM8
// EM8
//
// [Bit 8] RW (@ 0x4002181C) EM8
//
// ( (unsigned int) EXTI_EMR )
// EM8
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM9 ------------------------------------
// SVD Line: 2115
// - SFDITEM_FIELD__EXTI_EMR_EM9
// EM9
//
// [Bit 9] RW (@ 0x4002181C) EM9
//
// ( (unsigned int) EXTI_EMR )
// EM9
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM10 -----------------------------------
// SVD Line: 2119
// - SFDITEM_FIELD__EXTI_EMR_EM10
// EM10
//
// [Bit 10] RW (@ 0x4002181C) EM10
//
// ( (unsigned int) EXTI_EMR )
// EM10
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM11 -----------------------------------
// SVD Line: 2123
// - SFDITEM_FIELD__EXTI_EMR_EM11
// EM11
//
// [Bit 11] RW (@ 0x4002181C) EM11
//
// ( (unsigned int) EXTI_EMR )
// EM11
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM12 -----------------------------------
// SVD Line: 2127
// - SFDITEM_FIELD__EXTI_EMR_EM12
// EM12
//
// [Bit 12] RW (@ 0x4002181C) EM12
//
// ( (unsigned int) EXTI_EMR )
// EM12
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM13 -----------------------------------
// SVD Line: 2131
// - SFDITEM_FIELD__EXTI_EMR_EM13
// EM13
//
// [Bit 13] RW (@ 0x4002181C) EM13
//
// ( (unsigned int) EXTI_EMR )
// EM13
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM14 -----------------------------------
// SVD Line: 2135
// - SFDITEM_FIELD__EXTI_EMR_EM14
// EM14
//
// [Bit 14] RW (@ 0x4002181C) EM14
//
// ( (unsigned int) EXTI_EMR )
// EM14
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM15 -----------------------------------
// SVD Line: 2139
// - SFDITEM_FIELD__EXTI_EMR_EM15
// EM15
//
// [Bit 15] RW (@ 0x4002181C) EM15
//
// ( (unsigned int) EXTI_EMR )
// EM15
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM16 -----------------------------------
// SVD Line: 2143
// - SFDITEM_FIELD__EXTI_EMR_EM16
// EM16
//
// [Bit 16] RW (@ 0x4002181C) EM16
//
// ( (unsigned int) EXTI_EMR )
// EM16
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM17 -----------------------------------
// SVD Line: 2147
// - SFDITEM_FIELD__EXTI_EMR_EM17
// EM17
//
// [Bit 17] RW (@ 0x4002181C) EM17
//
// ( (unsigned int) EXTI_EMR )
// EM17
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM18 -----------------------------------
// SVD Line: 2151
// - SFDITEM_FIELD__EXTI_EMR_EM18
// EM18
//
// [Bit 18] RW (@ 0x4002181C) EM18
//
// ( (unsigned int) EXTI_EMR )
// EM18
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM20 -----------------------------------
// SVD Line: 2155
// - SFDITEM_FIELD__EXTI_EMR_EM20
// EM20
//
// [Bit 20] RW (@ 0x4002181C) EM20
//
// ( (unsigned int) EXTI_EMR )
// EM20
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM22 -----------------------------------
// SVD Line: 2159
// - SFDITEM_FIELD__EXTI_EMR_EM22
// EM22
//
// [Bit 22] RW (@ 0x4002181C) EM22
//
// ( (unsigned int) EXTI_EMR )
// EM22
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM24 -----------------------------------
// SVD Line: 2163
// - SFDITEM_FIELD__EXTI_EMR_EM24
// EM24
//
// [Bit 24] RW (@ 0x4002181C) EM24
//
// ( (unsigned int) EXTI_EMR )
// EM24
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM25 -----------------------------------
// SVD Line: 2167
// - SFDITEM_FIELD__EXTI_EMR_EM25
// EM25
//
// [Bit 25] RW (@ 0x4002181C) EM25
//
// ( (unsigned int) EXTI_EMR )
// EM25
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM27 -----------------------------------
// SVD Line: 2171
// - SFDITEM_FIELD__EXTI_EMR_EM27
// EM27
//
// [Bit 27] RW (@ 0x4002181C) EM27
//
// ( (unsigned int) EXTI_EMR )
// EM27
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 2074
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x4002181C) EXTI CPU wakeup with event maskregister
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0xB57FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB57FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM8
// - SFDITEM_FIELD__EXTI_EMR_EM9
// - SFDITEM_FIELD__EXTI_EMR_EM10
// - SFDITEM_FIELD__EXTI_EMR_EM11
// - SFDITEM_FIELD__EXTI_EMR_EM12
// - SFDITEM_FIELD__EXTI_EMR_EM13
// - SFDITEM_FIELD__EXTI_EMR_EM14
// - SFDITEM_FIELD__EXTI_EMR_EM15
// - SFDITEM_FIELD__EXTI_EMR_EM16
// - SFDITEM_FIELD__EXTI_EMR_EM17
// - SFDITEM_FIELD__EXTI_EMR_EM18
// - SFDITEM_FIELD__EXTI_EMR_EM20
// - SFDITEM_FIELD__EXTI_EMR_EM22
// - SFDITEM_FIELD__EXTI_EMR_EM24
// - SFDITEM_FIELD__EXTI_EMR_EM25
// - SFDITEM_FIELD__EXTI_EMR_EM27
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 1533
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_IOSEL1
// - SFDITEM_REG__EXTI_IOSEL2
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_ACR --------------------------------
// SVD Line: 2194
unsigned int FLASH_ACR __AT (0x40022000);
// ------------------------------ Field Item: FLASH_ACR_LATENCY ---------------------------------
// SVD Line: 2199
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
// LATENCY
//
// [Bits 1..0] RW (@ 0x40022000) Latency
//
// ( (unsigned char)((FLASH_ACR >> 0) & 0x3), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_ACR -----------------------------------
// SVD Line: 2194
// SFDITEM_REG__FLASH_ACR
// ACR
//
// [Bits 31..0] RW (@ 0x40022000) Access control register
// ( (unsigned int)((FLASH_ACR >> 0) & 0xFFFFFFFF), ((FLASH_ACR = (FLASH_ACR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
//
//
// ---------------------------- Register Item Address: FLASH_KEYR -------------------------------
// SVD Line: 2206
unsigned int FLASH_KEYR __AT (0x40022008);
// ------------------------------- Field Item: FLASH_KEYR_KEY -----------------------------------
// SVD Line: 2211
// - SFDITEM_FIELD__FLASH_KEYR_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash CR key
//
// ( (unsigned int)((FLASH_KEYR >> 0) & 0x0), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_KEYR -----------------------------------
// SVD Line: 2206
// SFDITEM_REG__FLASH_KEYR
// KEYR
//
// [Bits 31..0] RW (@ 0x40022008) Flash key register
// ( (unsigned int)((FLASH_KEYR >> 0) & 0xFFFFFFFF), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEYR_KEY
//
//
// -------------------------- Register Item Address: FLASH_OPTKEYR ------------------------------
// SVD Line: 2219
unsigned int FLASH_OPTKEYR __AT (0x4002200C);
// ---------------------------- Field Item: FLASH_OPTKEYR_OPTKEY --------------------------------
// SVD Line: 2224
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Flash Option key
//
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0x0), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEYR ---------------------------------
// SVD Line: 2219
// SFDITEM_REG__FLASH_OPTKEYR
// OPTKEYR
//
// [Bits 31..0] RW (@ 0x4002200C) Option byte key register
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 2232
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 2237
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 2242
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protection error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------- Field Item: FLASH_SR_RDERR -----------------------------------
// SVD Line: 2247
// - SFDITEM_FIELD__FLASH_SR_RDERR
// RDERR
//
// [Bit 11] RW (@ 0x40022010) Bank pcrop read error
//
// ( (unsigned int) FLASH_SR )
// RDERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 2252
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and trimming bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 2257
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RO (@ 0x40022010) Bank Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// ------------------------------ Field Item: FLASH_SR_USERLOCK ---------------------------------
// SVD Line: 2263
// - SFDITEM_FIELD__FLASH_SR_USERLOCK
// USERLOCK
//
// [Bit 28] RO (@ 0x40022010) User data lock
//
// ( (unsigned int) FLASH_SR )
// USERLOCK
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 2232
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) Status register
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x8811UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8811) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_RDERR
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
// - SFDITEM_FIELD__FLASH_SR_USERLOCK
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 2271
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 2276
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Page Program
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 2281
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page Erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 2286
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Bank Mass Erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_UPG ------------------------------------
// SVD Line: 2291
// - SFDITEM_FIELD__FLASH_CR_UPG
// UPG
//
// [Bit 4] RW (@ 0x40022014) Userdata Program
//
// ( (unsigned int) FLASH_CR )
// UPG
//
//
//
// -------------------------------- Field Item: FLASH_CR_UPER -----------------------------------
// SVD Line: 2296
// - SFDITEM_FIELD__FLASH_CR_UPER
// UPER
//
// [Bit 5] RW (@ 0x40022014) Userdata Page Erase
//
// ( (unsigned int) FLASH_CR )
// UPER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 2301
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector Erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 2306
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option bytes Programming Start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------ Field Item: FLASH_CR_UPGSTRT ----------------------------------
// SVD Line: 2311
// - SFDITEM_FIELD__FLASH_CR_UPGSTRT
// UPGSTRT
//
// [Bit 18] RW (@ 0x40022014) Userdata Programming Start
//
// ( (unsigned int) FLASH_CR )
// UPGSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_PGSTRT ----------------------------------
// SVD Line: 2316
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// PGSTRT
//
// [Bit 19] RW (@ 0x40022014) Programming Start
//
// ( (unsigned int) FLASH_CR )
// PGSTRT
//
//
//
// ------------------------------ Field Item: FLASH_CR_RDERRIE ----------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__FLASH_CR_RDERRIE
// RDERRIE
//
// [Bit 22] RW (@ 0x40022014) Bank pcrop read error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// RDERRIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 2326
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 2331
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 2336
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option bytes loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_SECPROT ----------------------------------
// SVD Line: 2341
// - SFDITEM_FIELD__FLASH_CR_SECPROT
// SECPROT
//
// [Bit 28] RW (@ 0x40022014) Secure protect
//
// ( (unsigned int) FLASH_CR )
// SECPROT
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 2346
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Option Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 2351
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 2271
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) Flash control register
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xDB4E0837UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDB4E0837) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_UPG
// - SFDITEM_FIELD__FLASH_CR_UPER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_UPGSTRT
// - SFDITEM_FIELD__FLASH_CR_PGSTRT
// - SFDITEM_FIELD__FLASH_CR_RDERRIE
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_SECPROT
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 2358
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------- Field Item: FLASH_OPTR_RDP -----------------------------------
// SVD Line: 2363
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// RDP
//
// [Bits 7..0] RW (@ 0x40022020) Read Protection
//
// ( (unsigned char)((FLASH_OPTR >> 0) & 0xFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 2368
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 10] RW (@ 0x40022020) nrst mode
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_IWDG_STOP --------------------------------
// SVD Line: 2373
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
// IWDG_STOP
//
// [Bit 13] RW (@ 0x40022020) IWDG Stop Count Control
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_STOP
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IWDG_SW ---------------------------------
// SVD Line: 2378
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// IWDG_SW
//
// [Bit 14] RW (@ 0x40022020) IWDG Software Enable
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_SW
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_WWDG_SW ---------------------------------
// SVD Line: 2383
// - SFDITEM_FIELD__FLASH_OPTR_WWDG_SW
// WWDG_SW
//
// [Bit 15] RW (@ 0x40022020) WWDG Software Enable
//
// ( (unsigned int) FLASH_OPTR )
// WWDG_SW
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_NBOOT1 ---------------------------------
// SVD Line: 2388
// - SFDITEM_FIELD__FLASH_OPTR_NBOOT1
// NBOOT1
//
// [Bit 17] RW (@ 0x40022020) nboot1
//
// ( (unsigned int) FLASH_OPTR )
// NBOOT1
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_BOOT_LOCK --------------------------------
// SVD Line: 2393
// - SFDITEM_FIELD__FLASH_OPTR_BOOT_LOCK
// BOOT_LOCK
//
// [Bit 20] RW (@ 0x40022020) Boot Lock
//
// ( (unsigned int) FLASH_OPTR )
// BOOT_LOCK
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_BOR_EN ---------------------------------
// SVD Line: 2398
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// BOR_EN
//
// [Bit 21] RW (@ 0x40022020) BOR enable
//
// ( (unsigned int) FLASH_OPTR )
// BOR_EN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BOR_OPCR --------------------------------
// SVD Line: 2403
// - SFDITEM_FIELD__FLASH_OPTR_BOR_OPCR
// BOR_OPCR
//
// [Bits 24..22] RW (@ 0x40022020) BOR Level
//
// ( (unsigned char)((FLASH_OPTR >> 22) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_SWD_MODE --------------------------------
// SVD Line: 2408
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
// SWD_MODE
//
// [Bits 26..25] RW (@ 0x40022020) SWD mode
//
// ( (unsigned char)((FLASH_OPTR >> 25) & 0x3), ((FLASH_OPTR = (FLASH_OPTR & ~(0x3UL << 25 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 25 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 2358
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) Flash option register
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7F2E4FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F2E4FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_WWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_NBOOT1
// - SFDITEM_FIELD__FLASH_OPTR_BOOT_LOCK
// - SFDITEM_FIELD__FLASH_OPTR_BOR_EN
// - SFDITEM_FIELD__FLASH_OPTR_BOR_OPCR
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 2415
unsigned int FLASH_WRPR __AT (0x40022028);
// ----------------------------- Field Item: FLASH_WRPR_BK_WRPX ---------------------------------
// SVD Line: 2419
// - SFDITEM_FIELD__FLASH_WRPR_BK_WRPX
// BK_WRPX
//
// [Bits 15..0] RW (@ 0x40022028) Bank Sector Write Protection
//
// ( (unsigned short)((FLASH_WRPR >> 0) & 0xFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 2415
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x40022028) WRPR
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_BK_WRPX
//
//
// --------------------------- Register Item Address: FLASH_PCROPR ------------------------------
// SVD Line: 2426
unsigned int FLASH_PCROPR __AT (0x4002202C);
// ---------------------------- Field Item: FLASH_PCROPR_PCROPSR --------------------------------
// SVD Line: 2430
// - SFDITEM_FIELD__FLASH_PCROPR_PCROPSR
// PCROPSR
//
// [Bits 8..0] RW (@ 0x4002202C) Bank pcrop start address
//
// ( (unsigned short)((FLASH_PCROPR >> 0) & 0x1FF), ((FLASH_PCROPR = (FLASH_PCROPR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: FLASH_PCROPR_PCROPER --------------------------------
// SVD Line: 2435
// - SFDITEM_FIELD__FLASH_PCROPR_PCROPER
// PCROPER
//
// [Bits 24..16] RW (@ 0x4002202C) Bank pcrop end address
//
// ( (unsigned short)((FLASH_PCROPR >> 16) & 0x1FF), ((FLASH_PCROPR = (FLASH_PCROPR & ~(0x1FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 16 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PCROPR ----------------------------------
// SVD Line: 2426
// SFDITEM_REG__FLASH_PCROPR
// PCROPR
//
// [Bits 31..0] RW (@ 0x4002202C) PCROPR
// ( (unsigned int)((FLASH_PCROPR >> 0) & 0xFFFFFFFF), ((FLASH_PCROPR = (FLASH_PCROPR & ~(0x1FF01FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF01FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PCROPR_PCROPSR
// - SFDITEM_FIELD__FLASH_PCROPR_PCROPER
//
//
// ---------------------------- Register Item Address: FLASH_SECR -------------------------------
// SVD Line: 2442
unsigned int FLASH_SECR __AT (0x40022030);
// ----------------------------- Field Item: FLASH_SECR_SEC_SIZE --------------------------------
// SVD Line: 2446
// - SFDITEM_FIELD__FLASH_SECR_SEC_SIZE
// SEC_SIZE
//
// [Bits 8..0] RW (@ 0x40022030) Bank securable seize
//
// ( (unsigned short)((FLASH_SECR >> 0) & 0x1FF), ((FLASH_SECR = (FLASH_SECR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SECR -----------------------------------
// SVD Line: 2442
// SFDITEM_REG__FLASH_SECR
// SECR
//
// [Bits 31..0] RW (@ 0x40022030) SECR
// ( (unsigned int)((FLASH_SECR >> 0) & 0xFFFFFFFF), ((FLASH_SECR = (FLASH_SECR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SECR_SEC_SIZE
//
//
// ---------------------------- Register Item Address: FLASH_LPCR -------------------------------
// SVD Line: 2453
unsigned int FLASH_LPCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_LPCR_SLEEP_EN --------------------------------
// SVD Line: 2457
// - SFDITEM_FIELD__FLASH_LPCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) Sleep enable
//
// ( (unsigned int) FLASH_LPCR )
// SLEEP_EN
//
//
//
// ---------------------------- Field Item: FLASH_LPCR_SLEEP_TIME -------------------------------
// SVD Line: 2462
// - SFDITEM_FIELD__FLASH_LPCR_SLEEP_TIME
// SLEEP_TIME
//
// [Bits 15..8] RW (@ 0x40022090) Sleep time
//
// ( (unsigned char)((FLASH_LPCR >> 8) & 0xFF), ((FLASH_LPCR = (FLASH_LPCR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: FLASH_LPCR_LPRUN_ENTERT ------------------------------
// SVD Line: 2467
// - SFDITEM_FIELD__FLASH_LPCR_LPRUN_ENTERT
// LPRUN_ENTERT
//
// [Bits 18..16] RW (@ 0x40022090) Low power run mode enter time
//
// ( (unsigned char)((FLASH_LPCR >> 16) & 0x7), ((FLASH_LPCR = (FLASH_LPCR & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// --------------------------- Field Item: FLASH_LPCR_LPRUN_EXITT -------------------------------
// SVD Line: 2472
// - SFDITEM_FIELD__FLASH_LPCR_LPRUN_EXITT
// LPRUN_EXITT
//
// [Bits 22..20] RW (@ 0x40022090) Low power run mode exit time
//
// ( (unsigned char)((FLASH_LPCR >> 20) & 0x7), ((FLASH_LPCR = (FLASH_LPCR & ~(0x7UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 20 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_LPCR -----------------------------------
// SVD Line: 2453
// SFDITEM_REG__FLASH_LPCR
// LPCR
//
// [Bits 31..0] RW (@ 0x40022090) LPCR
// ( (unsigned int)((FLASH_LPCR >> 0) & 0xFFFFFFFF), ((FLASH_LPCR = (FLASH_LPCR & ~(0x77FF01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77FF01) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_LPCR_SLEEP_EN
// - SFDITEM_FIELD__FLASH_LPCR_SLEEP_TIME
// - SFDITEM_FIELD__FLASH_LPCR_LPRUN_ENTERT
// - SFDITEM_FIELD__FLASH_LPCR_LPRUN_EXITT
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 2479
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 2484
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 6..0] RW (@ 0x40022100) TS0
//
// ( (unsigned char)((FLASH_TS0 >> 0) & 0x7F), ((FLASH_TS0 = (FLASH_TS0 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 2479
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) Flash TS0 register
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 2491
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 2496
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 6..0] RW (@ 0x40022104) TS1
//
// ( (unsigned char)((FLASH_TS1 >> 0) & 0x7F), ((FLASH_TS1 = (FLASH_TS1 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 2491
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) Flash TS1 register
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 2503
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 2508
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 6..0] RW (@ 0x40022108) TS2P
//
// ( (unsigned char)((FLASH_TS2P >> 0) & 0x7F), ((FLASH_TS2P = (FLASH_TS2P & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 2503
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) Flash TS2P register
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 2515
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 2520
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 8..0] RW (@ 0x4002210C) TPS3
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0x1FF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 2515
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) Flash TPS3 register
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 2527
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 2532
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 6..0] RW (@ 0x40022110) TS3
//
// ( (unsigned char)((FLASH_TS3 >> 0) & 0x7F), ((FLASH_TS3 = (FLASH_TS3 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 2527
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) Flash TS3 register
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_ERSTPE ------------------------------
// SVD Line: 2539
unsigned int FLASH_ERSTPE __AT (0x40022114);
// ----------------------------- Field Item: FLASH_ERSTPE_ERSTPE --------------------------------
// SVD Line: 2543
// - SFDITEM_FIELD__FLASH_ERSTPE_ERSTPE
// ERSTPE
//
// [Bits 14..0] RW (@ 0x40022114) ERSTPE
//
// ( (unsigned short)((FLASH_ERSTPE >> 0) & 0x7FFF), ((FLASH_ERSTPE = (FLASH_ERSTPE & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x7FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_ERSTPE ----------------------------------
// SVD Line: 2539
// SFDITEM_REG__FLASH_ERSTPE
// ERSTPE
//
// [Bits 31..0] RW (@ 0x40022114) ERSTPE
// ( (unsigned int)((FLASH_ERSTPE >> 0) & 0xFFFFFFFF), ((FLASH_ERSTPE = (FLASH_ERSTPE & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ERSTPE_ERSTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 2550
unsigned int FLASH_PRGTPE __AT (0x40022118);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 2555
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 14..0] RW (@ 0x40022118) PRGTPE
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0x7FFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x7FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 2550
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x40022118) Flash PRGTPE register
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 2562
unsigned int FLASH_PRETPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 2567
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 11..0] RW (@ 0x4002211C) PRETPE
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0xFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 2562
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x4002211C) Flash PRETPE register
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// -------------------------- Register Item Address: FLASH_TACLK2PW -----------------------------
// SVD Line: 2574
unsigned int FLASH_TACLK2PW __AT (0x40022120);
// --------------------------- Field Item: FLASH_TACLK2PW_TACLK2PW ------------------------------
// SVD Line: 2578
// - SFDITEM_FIELD__FLASH_TACLK2PW_TACLK2PW
// TACLK2PW
//
// [Bits 3..0] RW (@ 0x40022120) TACLK2PW
//
// ( (unsigned char)((FLASH_TACLK2PW >> 0) & 0xF), ((FLASH_TACLK2PW = (FLASH_TACLK2PW & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Register RTree: FLASH_TACLK2PW ---------------------------------
// SVD Line: 2574
// SFDITEM_REG__FLASH_TACLK2PW
// TACLK2PW
//
// [Bits 31..0] RW (@ 0x40022120) TACLK2PW
// ( (unsigned int)((FLASH_TACLK2PW >> 0) & 0xFFFFFFFF), ((FLASH_TACLK2PW = (FLASH_TACLK2PW & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TACLK2PW_TACLK2PW
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 2179
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_ACR
// - SFDITEM_REG__FLASH_KEYR
// - SFDITEM_REG__FLASH_OPTKEYR
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_PCROPR
// - SFDITEM_REG__FLASH_SECR
// - SFDITEM_REG__FLASH_LPCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_ERSTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
// - SFDITEM_REG__FLASH_TACLK2PW
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 2597
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 2602
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 2607
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 2612
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 2617
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 2622
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 2627
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 2632
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE8 ---------------------------------
// SVD Line: 2642
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 16) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE9 ---------------------------------
// SVD Line: 2647
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 18) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE10 ---------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 20) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE11 ---------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 22) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE12 ---------------------------------
// SVD Line: 2662
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 24) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE13 ---------------------------------
// SVD Line: 2667
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 26) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE14 ---------------------------------
// SVD Line: 2672
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 28) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE15 ---------------------------------
// SVD Line: 2677
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 30) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 2597
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 2684
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 2689
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 2694
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 2699
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 2704
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 2709
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 2714
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 2719
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 2724
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT8 ----------------------------------
// SVD Line: 2729
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT9 ----------------------------------
// SVD Line: 2734
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT10 ---------------------------------
// SVD Line: 2739
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT11 ---------------------------------
// SVD Line: 2744
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT12 ---------------------------------
// SVD Line: 2749
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT13 ---------------------------------
// SVD Line: 2754
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT14 ---------------------------------
// SVD Line: 2759
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT15 ---------------------------------
// SVD Line: 2764
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 2684
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 2771
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2776
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2781
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2786
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2791
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2796
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2801
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2806
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2811
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2816
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 16) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 2821
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 18) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 2826
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 20) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 2831
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 22) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 2836
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 24) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 2841
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 26) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 2846
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 28) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 2851
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 30) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 2771
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 2858
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2863
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2868
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2873
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2878
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2883
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2888
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2893
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2898
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2903
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 16) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD9 ---------------------------------
// SVD Line: 2908
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 18) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD10 ---------------------------------
// SVD Line: 2913
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 20) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD11 ---------------------------------
// SVD Line: 2918
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 22) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD12 ---------------------------------
// SVD Line: 2923
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 24) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD13 ---------------------------------
// SVD Line: 2928
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 26) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD14 ---------------------------------
// SVD Line: 2933
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 28) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD15 ---------------------------------
// SVD Line: 2938
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 30) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 2858
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 2945
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 2950
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 2956
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 2962
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 2968
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 2974
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 2980
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 2986
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 2992
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID8 -----------------------------------
// SVD Line: 2998
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID9 -----------------------------------
// SVD Line: 3004
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID10 -----------------------------------
// SVD Line: 3010
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID11 -----------------------------------
// SVD Line: 3016
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID12 -----------------------------------
// SVD Line: 3022
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID13 -----------------------------------
// SVD Line: 3028
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID14 -----------------------------------
// SVD Line: 3034
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID15 -----------------------------------
// SVD Line: 3040
// - SFDITEM_FIELD__GPIOA_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 2945
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// - SFDITEM_FIELD__GPIOA_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 3048
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 3053
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 3058
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 3063
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 3068
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 3073
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 3078
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 3083
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 3088
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD8 -----------------------------------
// SVD Line: 3093
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD9 -----------------------------------
// SVD Line: 3098
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD10 -----------------------------------
// SVD Line: 3103
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD11 -----------------------------------
// SVD Line: 3108
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD12 -----------------------------------
// SVD Line: 3113
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD13 -----------------------------------
// SVD Line: 3118
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD14 -----------------------------------
// SVD Line: 3123
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD15 -----------------------------------
// SVD Line: 3128
// - SFDITEM_FIELD__GPIOA_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 3048
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// - SFDITEM_FIELD__GPIOA_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 3135
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 3140
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 3145
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 3150
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 3155
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 3160
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 3165
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 3170
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 3175
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS8 -----------------------------------
// SVD Line: 3180
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// BS8
//
// [Bit 8] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS9 -----------------------------------
// SVD Line: 3185
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// BS9
//
// [Bit 9] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS10 ----------------------------------
// SVD Line: 3190
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// BS10
//
// [Bit 10] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS11 ----------------------------------
// SVD Line: 3195
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// BS11
//
// [Bit 11] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS12 ----------------------------------
// SVD Line: 3200
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// BS12
//
// [Bit 12] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS13 ----------------------------------
// SVD Line: 3205
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// BS13
//
// [Bit 13] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS14 ----------------------------------
// SVD Line: 3210
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// BS14
//
// [Bit 14] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS15 ----------------------------------
// SVD Line: 3215
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// BS15
//
// [Bit 15] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 3220
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 3225
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 3230
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 3235
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 3240
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 3245
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 3250
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 3255
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR8 -----------------------------------
// SVD Line: 3260
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// BR8
//
// [Bit 24] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR9 -----------------------------------
// SVD Line: 3265
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// BR9
//
// [Bit 25] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR10 ----------------------------------
// SVD Line: 3270
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// BR10
//
// [Bit 26] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR11 ----------------------------------
// SVD Line: 3275
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// BR11
//
// [Bit 27] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR12 ----------------------------------
// SVD Line: 3280
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// BR12
//
// [Bit 28] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR13 ----------------------------------
// SVD Line: 3285
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// BR13
//
// [Bit 29] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR14 ----------------------------------
// SVD Line: 3290
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// BR14
//
// [Bit 30] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR15 ----------------------------------
// SVD Line: 3295
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
// BR15
//
// [Bit 31] RW (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 3135
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 3302
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 3307
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 3312
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 3317
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 3322
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 3327
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 3332
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 3337
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 3342
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK8 ----------------------------------
// SVD Line: 3347
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK9 ----------------------------------
// SVD Line: 3352
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK10 ----------------------------------
// SVD Line: 3357
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK11 ----------------------------------
// SVD Line: 3362
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK12 ----------------------------------
// SVD Line: 3367
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK13 ----------------------------------
// SVD Line: 3372
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK14 ----------------------------------
// SVD Line: 3377
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK15 ----------------------------------
// SVD Line: 3382
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 3387
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 3302
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 3394
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3399
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3404
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3409
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3414
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3419
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3424
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 3394
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_AFRH -------------------------------
// SVD Line: 3441
unsigned int GPIOA_AFRH __AT (0x50000024);
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3446
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 0) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3451
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 4) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3456
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 8) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3461
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 12) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3466
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 16) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3471
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 20) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3476
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 24) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3481
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 28) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRH -----------------------------------
// SVD Line: 3441
// SFDITEM_REG__GPIOA_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000024) GPIO alternate function highregister
// ( (unsigned int)((GPIOA_AFRH >> 0) & 0xFFFFFFFF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 3488
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 3493
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 3498
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 3503
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 3508
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 3513
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 3518
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 3523
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 3528
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR8 -----------------------------------
// SVD Line: 3533
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// BR8
//
// [Bit 8] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR9 -----------------------------------
// SVD Line: 3538
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// BR9
//
// [Bit 9] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR10 -----------------------------------
// SVD Line: 3543
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// BR10
//
// [Bit 10] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR11 -----------------------------------
// SVD Line: 3548
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// BR11
//
// [Bit 11] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR12 -----------------------------------
// SVD Line: 3553
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// BR12
//
// [Bit 12] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR13 -----------------------------------
// SVD Line: 3558
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// BR13
//
// [Bit 13] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR14 -----------------------------------
// SVD Line: 3563
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// BR14
//
// [Bit 14] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR15 -----------------------------------
// SVD Line: 3568
// - SFDITEM_FIELD__GPIOA_BRR_BR15
// BR15
//
// [Bit 15] RW (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 3488
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// - SFDITEM_FIELD__GPIOA_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 2587
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_AFRH
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 2597
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 2602
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 2607
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 2612
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 2617
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE4 ---------------------------------
// SVD Line: 2622
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 8) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE5 ---------------------------------
// SVD Line: 2627
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 10) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE6 ---------------------------------
// SVD Line: 2632
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 12) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE7 ---------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 14) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE8 ---------------------------------
// SVD Line: 2642
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 16) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE9 ---------------------------------
// SVD Line: 2647
// - SFDITEM_FIELD__GPIOB_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 18) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE10 ---------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__GPIOB_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 20) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE11 ---------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__GPIOB_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 22) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE12 ---------------------------------
// SVD Line: 2662
// - SFDITEM_FIELD__GPIOB_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 24) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE13 ---------------------------------
// SVD Line: 2667
// - SFDITEM_FIELD__GPIOB_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 26) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE14 ---------------------------------
// SVD Line: 2672
// - SFDITEM_FIELD__GPIOB_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 28) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_MODER_MODE15 ---------------------------------
// SVD Line: 2677
// - SFDITEM_FIELD__GPIOB_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 30) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 2597
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
// - SFDITEM_FIELD__GPIOB_MODER_MODE9
// - SFDITEM_FIELD__GPIOB_MODER_MODE10
// - SFDITEM_FIELD__GPIOB_MODER_MODE11
// - SFDITEM_FIELD__GPIOB_MODER_MODE12
// - SFDITEM_FIELD__GPIOB_MODER_MODE13
// - SFDITEM_FIELD__GPIOB_MODER_MODE14
// - SFDITEM_FIELD__GPIOB_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 2684
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 2689
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 2694
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 2699
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 2704
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT4 ----------------------------------
// SVD Line: 2709
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT5 ----------------------------------
// SVD Line: 2714
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT6 ----------------------------------
// SVD Line: 2719
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT7 ----------------------------------
// SVD Line: 2724
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT8 ----------------------------------
// SVD Line: 2729
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT9 ----------------------------------
// SVD Line: 2734
// - SFDITEM_FIELD__GPIOB_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT10 ---------------------------------
// SVD Line: 2739
// - SFDITEM_FIELD__GPIOB_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT11 ---------------------------------
// SVD Line: 2744
// - SFDITEM_FIELD__GPIOB_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT12 ---------------------------------
// SVD Line: 2749
// - SFDITEM_FIELD__GPIOB_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT13 ---------------------------------
// SVD Line: 2754
// - SFDITEM_FIELD__GPIOB_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT14 ---------------------------------
// SVD Line: 2759
// - SFDITEM_FIELD__GPIOB_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT15 ---------------------------------
// SVD Line: 2764
// - SFDITEM_FIELD__GPIOB_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 2684
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
// - SFDITEM_FIELD__GPIOB_OTYPER_OT9
// - SFDITEM_FIELD__GPIOB_OTYPER_OT10
// - SFDITEM_FIELD__GPIOB_OTYPER_OT11
// - SFDITEM_FIELD__GPIOB_OTYPER_OT12
// - SFDITEM_FIELD__GPIOB_OTYPER_OT13
// - SFDITEM_FIELD__GPIOB_OTYPER_OT14
// - SFDITEM_FIELD__GPIOB_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 2771
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2776
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2781
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2786
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2791
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2796
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 8) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2801
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 10) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2806
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 12) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2811
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 14) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2816
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 16) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 2821
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 18) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 2826
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 20) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 2831
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 22) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 2836
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 24) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 2841
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 26) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 2846
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 28) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOB_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 2851
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 30) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 2771
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 2858
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2863
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2868
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2873
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2878
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2883
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 8) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2888
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 10) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2893
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 12) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2898
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 14) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2903
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 16) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD9 ---------------------------------
// SVD Line: 2908
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 18) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD10 ---------------------------------
// SVD Line: 2913
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 20) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD11 ---------------------------------
// SVD Line: 2918
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 22) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD12 ---------------------------------
// SVD Line: 2923
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 24) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD13 ---------------------------------
// SVD Line: 2928
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 26) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD14 ---------------------------------
// SVD Line: 2933
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 28) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_PUPDR_PUPD15 ---------------------------------
// SVD Line: 2938
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 30) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 2858
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 2945
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 2950
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 2956
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 2962
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 2968
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID4 -----------------------------------
// SVD Line: 2974
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID5 -----------------------------------
// SVD Line: 2980
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID6 -----------------------------------
// SVD Line: 2986
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID7 -----------------------------------
// SVD Line: 2992
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID8 -----------------------------------
// SVD Line: 2998
// - SFDITEM_FIELD__GPIOB_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID9 -----------------------------------
// SVD Line: 3004
// - SFDITEM_FIELD__GPIOB_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID10 -----------------------------------
// SVD Line: 3010
// - SFDITEM_FIELD__GPIOB_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID11 -----------------------------------
// SVD Line: 3016
// - SFDITEM_FIELD__GPIOB_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID12 -----------------------------------
// SVD Line: 3022
// - SFDITEM_FIELD__GPIOB_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID13 -----------------------------------
// SVD Line: 3028
// - SFDITEM_FIELD__GPIOB_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID14 -----------------------------------
// SVD Line: 3034
// - SFDITEM_FIELD__GPIOB_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOB_IDR_ID15 -----------------------------------
// SVD Line: 3040
// - SFDITEM_FIELD__GPIOB_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 2945
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// - SFDITEM_FIELD__GPIOB_IDR_ID8
// - SFDITEM_FIELD__GPIOB_IDR_ID9
// - SFDITEM_FIELD__GPIOB_IDR_ID10
// - SFDITEM_FIELD__GPIOB_IDR_ID11
// - SFDITEM_FIELD__GPIOB_IDR_ID12
// - SFDITEM_FIELD__GPIOB_IDR_ID13
// - SFDITEM_FIELD__GPIOB_IDR_ID14
// - SFDITEM_FIELD__GPIOB_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 3048
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 3053
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 3058
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 3063
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 3068
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD4 -----------------------------------
// SVD Line: 3073
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD5 -----------------------------------
// SVD Line: 3078
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD6 -----------------------------------
// SVD Line: 3083
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD7 -----------------------------------
// SVD Line: 3088
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD8 -----------------------------------
// SVD Line: 3093
// - SFDITEM_FIELD__GPIOB_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD9 -----------------------------------
// SVD Line: 3098
// - SFDITEM_FIELD__GPIOB_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD10 -----------------------------------
// SVD Line: 3103
// - SFDITEM_FIELD__GPIOB_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD11 -----------------------------------
// SVD Line: 3108
// - SFDITEM_FIELD__GPIOB_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD12 -----------------------------------
// SVD Line: 3113
// - SFDITEM_FIELD__GPIOB_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD13 -----------------------------------
// SVD Line: 3118
// - SFDITEM_FIELD__GPIOB_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD14 -----------------------------------
// SVD Line: 3123
// - SFDITEM_FIELD__GPIOB_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOB_ODR_OD15 -----------------------------------
// SVD Line: 3128
// - SFDITEM_FIELD__GPIOB_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 3048
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// - SFDITEM_FIELD__GPIOB_ODR_OD8
// - SFDITEM_FIELD__GPIOB_ODR_OD9
// - SFDITEM_FIELD__GPIOB_ODR_OD10
// - SFDITEM_FIELD__GPIOB_ODR_OD11
// - SFDITEM_FIELD__GPIOB_ODR_OD12
// - SFDITEM_FIELD__GPIOB_ODR_OD13
// - SFDITEM_FIELD__GPIOB_ODR_OD14
// - SFDITEM_FIELD__GPIOB_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 3135
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 3140
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 3145
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 3150
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 3155
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS4 -----------------------------------
// SVD Line: 3160
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS5 -----------------------------------
// SVD Line: 3165
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS6 -----------------------------------
// SVD Line: 3170
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS7 -----------------------------------
// SVD Line: 3175
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS8 -----------------------------------
// SVD Line: 3180
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// BS8
//
// [Bit 8] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS9 -----------------------------------
// SVD Line: 3185
// - SFDITEM_FIELD__GPIOB_BSRR_BS9
// BS9
//
// [Bit 9] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS10 ----------------------------------
// SVD Line: 3190
// - SFDITEM_FIELD__GPIOB_BSRR_BS10
// BS10
//
// [Bit 10] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS11 ----------------------------------
// SVD Line: 3195
// - SFDITEM_FIELD__GPIOB_BSRR_BS11
// BS11
//
// [Bit 11] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS12 ----------------------------------
// SVD Line: 3200
// - SFDITEM_FIELD__GPIOB_BSRR_BS12
// BS12
//
// [Bit 12] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS13 ----------------------------------
// SVD Line: 3205
// - SFDITEM_FIELD__GPIOB_BSRR_BS13
// BS13
//
// [Bit 13] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS14 ----------------------------------
// SVD Line: 3210
// - SFDITEM_FIELD__GPIOB_BSRR_BS14
// BS14
//
// [Bit 14] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS15 ----------------------------------
// SVD Line: 3215
// - SFDITEM_FIELD__GPIOB_BSRR_BS15
// BS15
//
// [Bit 15] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 3220
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 3225
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 3230
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 3235
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR4 -----------------------------------
// SVD Line: 3240
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR5 -----------------------------------
// SVD Line: 3245
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR6 -----------------------------------
// SVD Line: 3250
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR7 -----------------------------------
// SVD Line: 3255
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR8 -----------------------------------
// SVD Line: 3260
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
// BR8
//
// [Bit 24] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR9 -----------------------------------
// SVD Line: 3265
// - SFDITEM_FIELD__GPIOB_BSRR_BR9
// BR9
//
// [Bit 25] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR10 ----------------------------------
// SVD Line: 3270
// - SFDITEM_FIELD__GPIOB_BSRR_BR10
// BR10
//
// [Bit 26] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR11 ----------------------------------
// SVD Line: 3275
// - SFDITEM_FIELD__GPIOB_BSRR_BR11
// BR11
//
// [Bit 27] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR12 ----------------------------------
// SVD Line: 3280
// - SFDITEM_FIELD__GPIOB_BSRR_BR12
// BR12
//
// [Bit 28] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR13 ----------------------------------
// SVD Line: 3285
// - SFDITEM_FIELD__GPIOB_BSRR_BR13
// BR13
//
// [Bit 29] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR14 ----------------------------------
// SVD Line: 3290
// - SFDITEM_FIELD__GPIOB_BSRR_BR14
// BR14
//
// [Bit 30] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR15 ----------------------------------
// SVD Line: 3295
// - SFDITEM_FIELD__GPIOB_BSRR_BR15
// BR15
//
// [Bit 31] RW (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 3135
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// - SFDITEM_FIELD__GPIOB_BSRR_BS9
// - SFDITEM_FIELD__GPIOB_BSRR_BS10
// - SFDITEM_FIELD__GPIOB_BSRR_BS11
// - SFDITEM_FIELD__GPIOB_BSRR_BS12
// - SFDITEM_FIELD__GPIOB_BSRR_BS13
// - SFDITEM_FIELD__GPIOB_BSRR_BS14
// - SFDITEM_FIELD__GPIOB_BSRR_BS15
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
// - SFDITEM_FIELD__GPIOB_BSRR_BR9
// - SFDITEM_FIELD__GPIOB_BSRR_BR10
// - SFDITEM_FIELD__GPIOB_BSRR_BR11
// - SFDITEM_FIELD__GPIOB_BSRR_BR12
// - SFDITEM_FIELD__GPIOB_BSRR_BR13
// - SFDITEM_FIELD__GPIOB_BSRR_BR14
// - SFDITEM_FIELD__GPIOB_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 3302
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 3307
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 3312
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 3317
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 3322
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK4 ----------------------------------
// SVD Line: 3327
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK5 ----------------------------------
// SVD Line: 3332
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK6 ----------------------------------
// SVD Line: 3337
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK7 ----------------------------------
// SVD Line: 3342
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK8 ----------------------------------
// SVD Line: 3347
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK9 ----------------------------------
// SVD Line: 3352
// - SFDITEM_FIELD__GPIOB_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK10 ----------------------------------
// SVD Line: 3357
// - SFDITEM_FIELD__GPIOB_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK11 ----------------------------------
// SVD Line: 3362
// - SFDITEM_FIELD__GPIOB_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK12 ----------------------------------
// SVD Line: 3367
// - SFDITEM_FIELD__GPIOB_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK13 ----------------------------------
// SVD Line: 3372
// - SFDITEM_FIELD__GPIOB_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK14 ----------------------------------
// SVD Line: 3377
// - SFDITEM_FIELD__GPIOB_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOB_LCKR_LCK15 ----------------------------------
// SVD Line: 3382
// - SFDITEM_FIELD__GPIOB_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 3387
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 3302
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// - SFDITEM_FIELD__GPIOB_LCKR_LCK9
// - SFDITEM_FIELD__GPIOB_LCKR_LCK10
// - SFDITEM_FIELD__GPIOB_LCKR_LCK11
// - SFDITEM_FIELD__GPIOB_LCKR_LCK12
// - SFDITEM_FIELD__GPIOB_LCKR_LCK13
// - SFDITEM_FIELD__GPIOB_LCKR_LCK14
// - SFDITEM_FIELD__GPIOB_LCKR_LCK15
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 3394
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3399
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3404
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3409
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3414
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3419
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 16) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3424
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 20) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 24) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 28) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 3394
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOB_AFRH -------------------------------
// SVD Line: 3441
unsigned int GPIOB_AFRH __AT (0x50000424);
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3446
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 0) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3451
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 4) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3456
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 8) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3461
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 12) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3466
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 16) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3471
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 20) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3476
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 24) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3481
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 28) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRH -----------------------------------
// SVD Line: 3441
// SFDITEM_REG__GPIOB_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000424) GPIO alternate function highregister
// ( (unsigned int)((GPIOB_AFRH >> 0) & 0xFFFFFFFF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 3488
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 3493
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 3498
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 3503
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 3508
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR4 -----------------------------------
// SVD Line: 3513
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR5 -----------------------------------
// SVD Line: 3518
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR6 -----------------------------------
// SVD Line: 3523
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR7 -----------------------------------
// SVD Line: 3528
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR8 -----------------------------------
// SVD Line: 3533
// - SFDITEM_FIELD__GPIOB_BRR_BR8
// BR8
//
// [Bit 8] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR9 -----------------------------------
// SVD Line: 3538
// - SFDITEM_FIELD__GPIOB_BRR_BR9
// BR9
//
// [Bit 9] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR10 -----------------------------------
// SVD Line: 3543
// - SFDITEM_FIELD__GPIOB_BRR_BR10
// BR10
//
// [Bit 10] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR11 -----------------------------------
// SVD Line: 3548
// - SFDITEM_FIELD__GPIOB_BRR_BR11
// BR11
//
// [Bit 11] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR12 -----------------------------------
// SVD Line: 3553
// - SFDITEM_FIELD__GPIOB_BRR_BR12
// BR12
//
// [Bit 12] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR13 -----------------------------------
// SVD Line: 3558
// - SFDITEM_FIELD__GPIOB_BRR_BR13
// BR13
//
// [Bit 13] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR14 -----------------------------------
// SVD Line: 3563
// - SFDITEM_FIELD__GPIOB_BRR_BR14
// BR14
//
// [Bit 14] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOB_BRR_BR15 -----------------------------------
// SVD Line: 3568
// - SFDITEM_FIELD__GPIOB_BRR_BR15
// BR15
//
// [Bit 15] RW (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 3488
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// - SFDITEM_FIELD__GPIOB_BRR_BR8
// - SFDITEM_FIELD__GPIOB_BRR_BR9
// - SFDITEM_FIELD__GPIOB_BRR_BR10
// - SFDITEM_FIELD__GPIOB_BRR_BR11
// - SFDITEM_FIELD__GPIOB_BRR_BR12
// - SFDITEM_FIELD__GPIOB_BRR_BR13
// - SFDITEM_FIELD__GPIOB_BRR_BR14
// - SFDITEM_FIELD__GPIOB_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 3577
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_AFRH
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOF_MODER -------------------------------
// SVD Line: 2597
unsigned int GPIOF_MODER __AT (0x50001400);
// ------------------------------ Field Item: GPIOF_MODER_MODE0 ---------------------------------
// SVD Line: 2602
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 0) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE1 ---------------------------------
// SVD Line: 2607
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 2) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE2 ---------------------------------
// SVD Line: 2612
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 4) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE3 ---------------------------------
// SVD Line: 2617
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 6) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE4 ---------------------------------
// SVD Line: 2622
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 8) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE5 ---------------------------------
// SVD Line: 2627
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 10) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE6 ---------------------------------
// SVD Line: 2632
// - SFDITEM_FIELD__GPIOF_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 12) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE7 ---------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOF_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 14) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE8 ---------------------------------
// SVD Line: 2642
// - SFDITEM_FIELD__GPIOF_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 16) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_MODER_MODE9 ---------------------------------
// SVD Line: 2647
// - SFDITEM_FIELD__GPIOF_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 18) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE10 ---------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__GPIOF_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 20) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE11 ---------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__GPIOF_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 22) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE12 ---------------------------------
// SVD Line: 2662
// - SFDITEM_FIELD__GPIOF_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 24) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE13 ---------------------------------
// SVD Line: 2667
// - SFDITEM_FIELD__GPIOF_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 26) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE14 ---------------------------------
// SVD Line: 2672
// - SFDITEM_FIELD__GPIOF_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 28) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_MODER_MODE15 ---------------------------------
// SVD Line: 2677
// - SFDITEM_FIELD__GPIOF_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50001400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_MODER >> 30) & 0x3), ((GPIOF_MODER = (GPIOF_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_MODER ----------------------------------
// SVD Line: 2597
// SFDITEM_REG__GPIOF_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50001400) GPIO port mode register
// ( (unsigned int)((GPIOF_MODER >> 0) & 0xFFFFFFFF), ((GPIOF_MODER = (GPIOF_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_MODER_MODE0
// - SFDITEM_FIELD__GPIOF_MODER_MODE1
// - SFDITEM_FIELD__GPIOF_MODER_MODE2
// - SFDITEM_FIELD__GPIOF_MODER_MODE3
// - SFDITEM_FIELD__GPIOF_MODER_MODE4
// - SFDITEM_FIELD__GPIOF_MODER_MODE5
// - SFDITEM_FIELD__GPIOF_MODER_MODE6
// - SFDITEM_FIELD__GPIOF_MODER_MODE7
// - SFDITEM_FIELD__GPIOF_MODER_MODE8
// - SFDITEM_FIELD__GPIOF_MODER_MODE9
// - SFDITEM_FIELD__GPIOF_MODER_MODE10
// - SFDITEM_FIELD__GPIOF_MODER_MODE11
// - SFDITEM_FIELD__GPIOF_MODER_MODE12
// - SFDITEM_FIELD__GPIOF_MODER_MODE13
// - SFDITEM_FIELD__GPIOF_MODER_MODE14
// - SFDITEM_FIELD__GPIOF_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOF_OTYPER ------------------------------
// SVD Line: 2684
unsigned int GPIOF_OTYPER __AT (0x50001404);
// ------------------------------ Field Item: GPIOF_OTYPER_OT0 ----------------------------------
// SVD Line: 2689
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT1 ----------------------------------
// SVD Line: 2694
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT2 ----------------------------------
// SVD Line: 2699
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT3 ----------------------------------
// SVD Line: 2704
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT4 ----------------------------------
// SVD Line: 2709
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT5 ----------------------------------
// SVD Line: 2714
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT6 ----------------------------------
// SVD Line: 2719
// - SFDITEM_FIELD__GPIOF_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT7 ----------------------------------
// SVD Line: 2724
// - SFDITEM_FIELD__GPIOF_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT8 ----------------------------------
// SVD Line: 2729
// - SFDITEM_FIELD__GPIOF_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT9 ----------------------------------
// SVD Line: 2734
// - SFDITEM_FIELD__GPIOF_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT10 ---------------------------------
// SVD Line: 2739
// - SFDITEM_FIELD__GPIOF_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT11 ---------------------------------
// SVD Line: 2744
// - SFDITEM_FIELD__GPIOF_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT12 ---------------------------------
// SVD Line: 2749
// - SFDITEM_FIELD__GPIOF_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT13 ---------------------------------
// SVD Line: 2754
// - SFDITEM_FIELD__GPIOF_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT14 ---------------------------------
// SVD Line: 2759
// - SFDITEM_FIELD__GPIOF_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOF_OTYPER_OT15 ---------------------------------
// SVD Line: 2764
// - SFDITEM_FIELD__GPIOF_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50001404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOF_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOF_OTYPER ----------------------------------
// SVD Line: 2684
// SFDITEM_REG__GPIOF_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50001404) GPIO port output type register
// ( (unsigned int)((GPIOF_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOF_OTYPER = (GPIOF_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OTYPER_OT0
// - SFDITEM_FIELD__GPIOF_OTYPER_OT1
// - SFDITEM_FIELD__GPIOF_OTYPER_OT2
// - SFDITEM_FIELD__GPIOF_OTYPER_OT3
// - SFDITEM_FIELD__GPIOF_OTYPER_OT4
// - SFDITEM_FIELD__GPIOF_OTYPER_OT5
// - SFDITEM_FIELD__GPIOF_OTYPER_OT6
// - SFDITEM_FIELD__GPIOF_OTYPER_OT7
// - SFDITEM_FIELD__GPIOF_OTYPER_OT8
// - SFDITEM_FIELD__GPIOF_OTYPER_OT9
// - SFDITEM_FIELD__GPIOF_OTYPER_OT10
// - SFDITEM_FIELD__GPIOF_OTYPER_OT11
// - SFDITEM_FIELD__GPIOF_OTYPER_OT12
// - SFDITEM_FIELD__GPIOF_OTYPER_OT13
// - SFDITEM_FIELD__GPIOF_OTYPER_OT14
// - SFDITEM_FIELD__GPIOF_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOF_OSPEEDR ------------------------------
// SVD Line: 2771
unsigned int GPIOF_OSPEEDR __AT (0x50001408);
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2776
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 0) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2781
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 2) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2786
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 4) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2791
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 6) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2796
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 8) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2801
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 10) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2806
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 12) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2811
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 14) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2816
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 16) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOF_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 2821
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 18) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 2826
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 20) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 2831
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 22) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 2836
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 24) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 2841
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 26) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 2846
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 28) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOF_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 2851
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50001408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_OSPEEDR >> 30) & 0x3), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOF_OSPEEDR ---------------------------------
// SVD Line: 2771
// SFDITEM_REG__GPIOF_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50001408) GPIO port output speed register
// ( (unsigned int)((GPIOF_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOF_OSPEEDR = (GPIOF_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOF_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOF_PUPDR -------------------------------
// SVD Line: 2858
unsigned int GPIOF_PUPDR __AT (0x5000140C);
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2863
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 0) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2868
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 2) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2873
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 4) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2878
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 6) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2883
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 8) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2888
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 10) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2893
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 12) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2898
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 14) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2903
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 16) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_PUPDR_PUPD9 ---------------------------------
// SVD Line: 2908
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 18) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD10 ---------------------------------
// SVD Line: 2913
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 20) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD11 ---------------------------------
// SVD Line: 2918
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 22) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD12 ---------------------------------
// SVD Line: 2923
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 24) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD13 ---------------------------------
// SVD Line: 2928
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 26) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD14 ---------------------------------
// SVD Line: 2933
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 28) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_PUPDR_PUPD15 ---------------------------------
// SVD Line: 2938
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000140C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOF_PUPDR >> 30) & 0x3), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_PUPDR ----------------------------------
// SVD Line: 2858
// SFDITEM_REG__GPIOF_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000140C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOF_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOF_PUPDR = (GPIOF_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOF_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOF_IDR --------------------------------
// SVD Line: 2945
unsigned int GPIOF_IDR __AT (0x50001410);
// -------------------------------- Field Item: GPIOF_IDR_ID0 -----------------------------------
// SVD Line: 2950
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID1 -----------------------------------
// SVD Line: 2956
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID2 -----------------------------------
// SVD Line: 2962
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID3 -----------------------------------
// SVD Line: 2968
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID4 -----------------------------------
// SVD Line: 2974
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID5 -----------------------------------
// SVD Line: 2980
// - SFDITEM_FIELD__GPIOF_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID6 -----------------------------------
// SVD Line: 2986
// - SFDITEM_FIELD__GPIOF_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID7 -----------------------------------
// SVD Line: 2992
// - SFDITEM_FIELD__GPIOF_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID8 -----------------------------------
// SVD Line: 2998
// - SFDITEM_FIELD__GPIOF_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOF_IDR_ID9 -----------------------------------
// SVD Line: 3004
// - SFDITEM_FIELD__GPIOF_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID10 -----------------------------------
// SVD Line: 3010
// - SFDITEM_FIELD__GPIOF_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID11 -----------------------------------
// SVD Line: 3016
// - SFDITEM_FIELD__GPIOF_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID12 -----------------------------------
// SVD Line: 3022
// - SFDITEM_FIELD__GPIOF_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID13 -----------------------------------
// SVD Line: 3028
// - SFDITEM_FIELD__GPIOF_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID14 -----------------------------------
// SVD Line: 3034
// - SFDITEM_FIELD__GPIOF_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOF_IDR_ID15 -----------------------------------
// SVD Line: 3040
// - SFDITEM_FIELD__GPIOF_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50001410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOF_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOF_IDR -----------------------------------
// SVD Line: 2945
// SFDITEM_REG__GPIOF_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x50001410) GPIO port input data register
// ( (unsigned int)((GPIOF_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOF_IDR_ID0
// - SFDITEM_FIELD__GPIOF_IDR_ID1
// - SFDITEM_FIELD__GPIOF_IDR_ID2
// - SFDITEM_FIELD__GPIOF_IDR_ID3
// - SFDITEM_FIELD__GPIOF_IDR_ID4
// - SFDITEM_FIELD__GPIOF_IDR_ID5
// - SFDITEM_FIELD__GPIOF_IDR_ID6
// - SFDITEM_FIELD__GPIOF_IDR_ID7
// - SFDITEM_FIELD__GPIOF_IDR_ID8
// - SFDITEM_FIELD__GPIOF_IDR_ID9
// - SFDITEM_FIELD__GPIOF_IDR_ID10
// - SFDITEM_FIELD__GPIOF_IDR_ID11
// - SFDITEM_FIELD__GPIOF_IDR_ID12
// - SFDITEM_FIELD__GPIOF_IDR_ID13
// - SFDITEM_FIELD__GPIOF_IDR_ID14
// - SFDITEM_FIELD__GPIOF_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOF_ODR --------------------------------
// SVD Line: 3048
unsigned int GPIOF_ODR __AT (0x50001414);
// -------------------------------- Field Item: GPIOF_ODR_OD0 -----------------------------------
// SVD Line: 3053
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD1 -----------------------------------
// SVD Line: 3058
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD2 -----------------------------------
// SVD Line: 3063
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD3 -----------------------------------
// SVD Line: 3068
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD4 -----------------------------------
// SVD Line: 3073
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD5 -----------------------------------
// SVD Line: 3078
// - SFDITEM_FIELD__GPIOF_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD6 -----------------------------------
// SVD Line: 3083
// - SFDITEM_FIELD__GPIOF_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD7 -----------------------------------
// SVD Line: 3088
// - SFDITEM_FIELD__GPIOF_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD8 -----------------------------------
// SVD Line: 3093
// - SFDITEM_FIELD__GPIOF_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOF_ODR_OD9 -----------------------------------
// SVD Line: 3098
// - SFDITEM_FIELD__GPIOF_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD10 -----------------------------------
// SVD Line: 3103
// - SFDITEM_FIELD__GPIOF_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD11 -----------------------------------
// SVD Line: 3108
// - SFDITEM_FIELD__GPIOF_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD12 -----------------------------------
// SVD Line: 3113
// - SFDITEM_FIELD__GPIOF_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD13 -----------------------------------
// SVD Line: 3118
// - SFDITEM_FIELD__GPIOF_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD14 -----------------------------------
// SVD Line: 3123
// - SFDITEM_FIELD__GPIOF_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOF_ODR_OD15 -----------------------------------
// SVD Line: 3128
// - SFDITEM_FIELD__GPIOF_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50001414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOF_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOF_ODR -----------------------------------
// SVD Line: 3048
// SFDITEM_REG__GPIOF_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50001414) GPIO port output data register
// ( (unsigned int)((GPIOF_ODR >> 0) & 0xFFFFFFFF), ((GPIOF_ODR = (GPIOF_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_ODR_OD0
// - SFDITEM_FIELD__GPIOF_ODR_OD1
// - SFDITEM_FIELD__GPIOF_ODR_OD2
// - SFDITEM_FIELD__GPIOF_ODR_OD3
// - SFDITEM_FIELD__GPIOF_ODR_OD4
// - SFDITEM_FIELD__GPIOF_ODR_OD5
// - SFDITEM_FIELD__GPIOF_ODR_OD6
// - SFDITEM_FIELD__GPIOF_ODR_OD7
// - SFDITEM_FIELD__GPIOF_ODR_OD8
// - SFDITEM_FIELD__GPIOF_ODR_OD9
// - SFDITEM_FIELD__GPIOF_ODR_OD10
// - SFDITEM_FIELD__GPIOF_ODR_OD11
// - SFDITEM_FIELD__GPIOF_ODR_OD12
// - SFDITEM_FIELD__GPIOF_ODR_OD13
// - SFDITEM_FIELD__GPIOF_ODR_OD14
// - SFDITEM_FIELD__GPIOF_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOF_BSRR -------------------------------
// SVD Line: 3135
unsigned int GPIOF_BSRR __AT (0x50001418);
// ------------------------------- Field Item: GPIOF_BSRR_BS0 -----------------------------------
// SVD Line: 3140
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// BS0
//
// [Bit 0] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS1 -----------------------------------
// SVD Line: 3145
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// BS1
//
// [Bit 1] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS2 -----------------------------------
// SVD Line: 3150
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// BS2
//
// [Bit 2] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS3 -----------------------------------
// SVD Line: 3155
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// BS3
//
// [Bit 3] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS4 -----------------------------------
// SVD Line: 3160
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// BS4
//
// [Bit 4] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS5 -----------------------------------
// SVD Line: 3165
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// BS5
//
// [Bit 5] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS6 -----------------------------------
// SVD Line: 3170
// - SFDITEM_FIELD__GPIOF_BSRR_BS6
// BS6
//
// [Bit 6] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS7 -----------------------------------
// SVD Line: 3175
// - SFDITEM_FIELD__GPIOF_BSRR_BS7
// BS7
//
// [Bit 7] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS8 -----------------------------------
// SVD Line: 3180
// - SFDITEM_FIELD__GPIOF_BSRR_BS8
// BS8
//
// [Bit 8] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS9 -----------------------------------
// SVD Line: 3185
// - SFDITEM_FIELD__GPIOF_BSRR_BS9
// BS9
//
// [Bit 9] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS10 ----------------------------------
// SVD Line: 3190
// - SFDITEM_FIELD__GPIOF_BSRR_BS10
// BS10
//
// [Bit 10] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS11 ----------------------------------
// SVD Line: 3195
// - SFDITEM_FIELD__GPIOF_BSRR_BS11
// BS11
//
// [Bit 11] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS12 ----------------------------------
// SVD Line: 3200
// - SFDITEM_FIELD__GPIOF_BSRR_BS12
// BS12
//
// [Bit 12] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS13 ----------------------------------
// SVD Line: 3205
// - SFDITEM_FIELD__GPIOF_BSRR_BS13
// BS13
//
// [Bit 13] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS14 ----------------------------------
// SVD Line: 3210
// - SFDITEM_FIELD__GPIOF_BSRR_BS14
// BS14
//
// [Bit 14] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BS15 ----------------------------------
// SVD Line: 3215
// - SFDITEM_FIELD__GPIOF_BSRR_BS15
// BS15
//
// [Bit 15] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR0 -----------------------------------
// SVD Line: 3220
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// BR0
//
// [Bit 16] RW (@ 0x50001418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR1 -----------------------------------
// SVD Line: 3225
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// BR1
//
// [Bit 17] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR2 -----------------------------------
// SVD Line: 3230
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// BR2
//
// [Bit 18] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR3 -----------------------------------
// SVD Line: 3235
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// BR3
//
// [Bit 19] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR4 -----------------------------------
// SVD Line: 3240
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// BR4
//
// [Bit 20] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR5 -----------------------------------
// SVD Line: 3245
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
// BR5
//
// [Bit 21] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR6 -----------------------------------
// SVD Line: 3250
// - SFDITEM_FIELD__GPIOF_BSRR_BR6
// BR6
//
// [Bit 22] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR7 -----------------------------------
// SVD Line: 3255
// - SFDITEM_FIELD__GPIOF_BSRR_BR7
// BR7
//
// [Bit 23] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR8 -----------------------------------
// SVD Line: 3260
// - SFDITEM_FIELD__GPIOF_BSRR_BR8
// BR8
//
// [Bit 24] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR9 -----------------------------------
// SVD Line: 3265
// - SFDITEM_FIELD__GPIOF_BSRR_BR9
// BR9
//
// [Bit 25] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR10 ----------------------------------
// SVD Line: 3270
// - SFDITEM_FIELD__GPIOF_BSRR_BR10
// BR10
//
// [Bit 26] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR11 ----------------------------------
// SVD Line: 3275
// - SFDITEM_FIELD__GPIOF_BSRR_BR11
// BR11
//
// [Bit 27] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR12 ----------------------------------
// SVD Line: 3280
// - SFDITEM_FIELD__GPIOF_BSRR_BR12
// BR12
//
// [Bit 28] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR13 ----------------------------------
// SVD Line: 3285
// - SFDITEM_FIELD__GPIOF_BSRR_BR13
// BR13
//
// [Bit 29] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR14 ----------------------------------
// SVD Line: 3290
// - SFDITEM_FIELD__GPIOF_BSRR_BR14
// BR14
//
// [Bit 30] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOF_BSRR_BR15 ----------------------------------
// SVD Line: 3295
// - SFDITEM_FIELD__GPIOF_BSRR_BR15
// BR15
//
// [Bit 31] RW (@ 0x50001418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOF_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOF_BSRR -----------------------------------
// SVD Line: 3135
// SFDITEM_REG__GPIOF_BSRR
// BSRR
//
// [Bits 31..0] RW (@ 0x50001418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOF_BSRR >> 0) & 0xFFFFFFFF), ((GPIOF_BSRR = (GPIOF_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BSRR_BS0
// - SFDITEM_FIELD__GPIOF_BSRR_BS1
// - SFDITEM_FIELD__GPIOF_BSRR_BS2
// - SFDITEM_FIELD__GPIOF_BSRR_BS3
// - SFDITEM_FIELD__GPIOF_BSRR_BS4
// - SFDITEM_FIELD__GPIOF_BSRR_BS5
// - SFDITEM_FIELD__GPIOF_BSRR_BS6
// - SFDITEM_FIELD__GPIOF_BSRR_BS7
// - SFDITEM_FIELD__GPIOF_BSRR_BS8
// - SFDITEM_FIELD__GPIOF_BSRR_BS9
// - SFDITEM_FIELD__GPIOF_BSRR_BS10
// - SFDITEM_FIELD__GPIOF_BSRR_BS11
// - SFDITEM_FIELD__GPIOF_BSRR_BS12
// - SFDITEM_FIELD__GPIOF_BSRR_BS13
// - SFDITEM_FIELD__GPIOF_BSRR_BS14
// - SFDITEM_FIELD__GPIOF_BSRR_BS15
// - SFDITEM_FIELD__GPIOF_BSRR_BR0
// - SFDITEM_FIELD__GPIOF_BSRR_BR1
// - SFDITEM_FIELD__GPIOF_BSRR_BR2
// - SFDITEM_FIELD__GPIOF_BSRR_BR3
// - SFDITEM_FIELD__GPIOF_BSRR_BR4
// - SFDITEM_FIELD__GPIOF_BSRR_BR5
// - SFDITEM_FIELD__GPIOF_BSRR_BR6
// - SFDITEM_FIELD__GPIOF_BSRR_BR7
// - SFDITEM_FIELD__GPIOF_BSRR_BR8
// - SFDITEM_FIELD__GPIOF_BSRR_BR9
// - SFDITEM_FIELD__GPIOF_BSRR_BR10
// - SFDITEM_FIELD__GPIOF_BSRR_BR11
// - SFDITEM_FIELD__GPIOF_BSRR_BR12
// - SFDITEM_FIELD__GPIOF_BSRR_BR13
// - SFDITEM_FIELD__GPIOF_BSRR_BR14
// - SFDITEM_FIELD__GPIOF_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOF_LCKR -------------------------------
// SVD Line: 3302
unsigned int GPIOF_LCKR __AT (0x5000141C);
// ------------------------------- Field Item: GPIOF_LCKR_LCK0 ----------------------------------
// SVD Line: 3307
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK1 ----------------------------------
// SVD Line: 3312
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK2 ----------------------------------
// SVD Line: 3317
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK3 ----------------------------------
// SVD Line: 3322
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK4 ----------------------------------
// SVD Line: 3327
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK5 ----------------------------------
// SVD Line: 3332
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK6 ----------------------------------
// SVD Line: 3337
// - SFDITEM_FIELD__GPIOF_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK7 ----------------------------------
// SVD Line: 3342
// - SFDITEM_FIELD__GPIOF_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK8 ----------------------------------
// SVD Line: 3347
// - SFDITEM_FIELD__GPIOF_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCK9 ----------------------------------
// SVD Line: 3352
// - SFDITEM_FIELD__GPIOF_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK10 ----------------------------------
// SVD Line: 3357
// - SFDITEM_FIELD__GPIOF_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK11 ----------------------------------
// SVD Line: 3362
// - SFDITEM_FIELD__GPIOF_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK12 ----------------------------------
// SVD Line: 3367
// - SFDITEM_FIELD__GPIOF_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK13 ----------------------------------
// SVD Line: 3372
// - SFDITEM_FIELD__GPIOF_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK14 ----------------------------------
// SVD Line: 3377
// - SFDITEM_FIELD__GPIOF_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOF_LCKR_LCK15 ----------------------------------
// SVD Line: 3382
// - SFDITEM_FIELD__GPIOF_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOF_LCKR_LCKK ----------------------------------
// SVD Line: 3387
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000141C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOF_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOF_LCKR -----------------------------------
// SVD Line: 3302
// SFDITEM_REG__GPIOF_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000141C) GPIO port configuration lock register
// ( (unsigned int)((GPIOF_LCKR >> 0) & 0xFFFFFFFF), ((GPIOF_LCKR = (GPIOF_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_LCKR_LCK0
// - SFDITEM_FIELD__GPIOF_LCKR_LCK1
// - SFDITEM_FIELD__GPIOF_LCKR_LCK2
// - SFDITEM_FIELD__GPIOF_LCKR_LCK3
// - SFDITEM_FIELD__GPIOF_LCKR_LCK4
// - SFDITEM_FIELD__GPIOF_LCKR_LCK5
// - SFDITEM_FIELD__GPIOF_LCKR_LCK6
// - SFDITEM_FIELD__GPIOF_LCKR_LCK7
// - SFDITEM_FIELD__GPIOF_LCKR_LCK8
// - SFDITEM_FIELD__GPIOF_LCKR_LCK9
// - SFDITEM_FIELD__GPIOF_LCKR_LCK10
// - SFDITEM_FIELD__GPIOF_LCKR_LCK11
// - SFDITEM_FIELD__GPIOF_LCKR_LCK12
// - SFDITEM_FIELD__GPIOF_LCKR_LCK13
// - SFDITEM_FIELD__GPIOF_LCKR_LCK14
// - SFDITEM_FIELD__GPIOF_LCKR_LCK15
// - SFDITEM_FIELD__GPIOF_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOF_AFRL -------------------------------
// SVD Line: 3394
unsigned int GPIOF_AFRL __AT (0x50001420);
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL0 ---------------------------------
// SVD Line: 3399
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 0) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL1 ---------------------------------
// SVD Line: 3404
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 4) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL2 ---------------------------------
// SVD Line: 3409
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 8) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL3 ---------------------------------
// SVD Line: 3414
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 12) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL4 ---------------------------------
// SVD Line: 3419
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 16) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL5 ---------------------------------
// SVD Line: 3424
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 20) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL6 ---------------------------------
// SVD Line: 3429
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 24) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRL_AFSEL7 ---------------------------------
// SVD Line: 3434
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50001420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOF_AFRL >> 28) & 0xF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_AFRL -----------------------------------
// SVD Line: 3394
// SFDITEM_REG__GPIOF_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50001420) GPIO alternate function low register
// ( (unsigned int)((GPIOF_AFRL >> 0) & 0xFFFFFFFF), ((GPIOF_AFRL = (GPIOF_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOF_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOF_AFRH -------------------------------
// SVD Line: 3441
unsigned int GPIOF_AFRH __AT (0x50001424);
// ------------------------------ Field Item: GPIOF_AFRH_AFSEL8 ---------------------------------
// SVD Line: 3446
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 0) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOF_AFRH_AFSEL9 ---------------------------------
// SVD Line: 3451
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 4) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL10 ---------------------------------
// SVD Line: 3456
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 8) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL11 ---------------------------------
// SVD Line: 3461
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 12) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL12 ---------------------------------
// SVD Line: 3466
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 16) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL13 ---------------------------------
// SVD Line: 3471
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 20) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL14 ---------------------------------
// SVD Line: 3476
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 24) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOF_AFRH_AFSEL15 ---------------------------------
// SVD Line: 3481
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50001424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOF_AFRH >> 28) & 0xF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOF_AFRH -----------------------------------
// SVD Line: 3441
// SFDITEM_REG__GPIOF_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50001424) GPIO alternate function highregister
// ( (unsigned int)((GPIOF_AFRH >> 0) & 0xFFFFFFFF), ((GPIOF_AFRH = (GPIOF_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOF_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOF_BRR --------------------------------
// SVD Line: 3488
unsigned int GPIOF_BRR __AT (0x50001428);
// -------------------------------- Field Item: GPIOF_BRR_BR0 -----------------------------------
// SVD Line: 3493
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// BR0
//
// [Bit 0] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR1 -----------------------------------
// SVD Line: 3498
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// BR1
//
// [Bit 1] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR2 -----------------------------------
// SVD Line: 3503
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// BR2
//
// [Bit 2] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR3 -----------------------------------
// SVD Line: 3508
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// BR3
//
// [Bit 3] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR4 -----------------------------------
// SVD Line: 3513
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// BR4
//
// [Bit 4] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR5 -----------------------------------
// SVD Line: 3518
// - SFDITEM_FIELD__GPIOF_BRR_BR5
// BR5
//
// [Bit 5] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR6 -----------------------------------
// SVD Line: 3523
// - SFDITEM_FIELD__GPIOF_BRR_BR6
// BR6
//
// [Bit 6] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR7 -----------------------------------
// SVD Line: 3528
// - SFDITEM_FIELD__GPIOF_BRR_BR7
// BR7
//
// [Bit 7] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR8 -----------------------------------
// SVD Line: 3533
// - SFDITEM_FIELD__GPIOF_BRR_BR8
// BR8
//
// [Bit 8] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOF_BRR_BR9 -----------------------------------
// SVD Line: 3538
// - SFDITEM_FIELD__GPIOF_BRR_BR9
// BR9
//
// [Bit 9] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR10 -----------------------------------
// SVD Line: 3543
// - SFDITEM_FIELD__GPIOF_BRR_BR10
// BR10
//
// [Bit 10] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR11 -----------------------------------
// SVD Line: 3548
// - SFDITEM_FIELD__GPIOF_BRR_BR11
// BR11
//
// [Bit 11] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR12 -----------------------------------
// SVD Line: 3553
// - SFDITEM_FIELD__GPIOF_BRR_BR12
// BR12
//
// [Bit 12] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR13 -----------------------------------
// SVD Line: 3558
// - SFDITEM_FIELD__GPIOF_BRR_BR13
// BR13
//
// [Bit 13] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR14 -----------------------------------
// SVD Line: 3563
// - SFDITEM_FIELD__GPIOF_BRR_BR14
// BR14
//
// [Bit 14] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOF_BRR_BR15 -----------------------------------
// SVD Line: 3568
// - SFDITEM_FIELD__GPIOF_BRR_BR15
// BR15
//
// [Bit 15] RW (@ 0x50001428) Port Reset bit
//
// ( (unsigned int) GPIOF_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOF_BRR -----------------------------------
// SVD Line: 3488
// SFDITEM_REG__GPIOF_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x50001428) port bit reset register
// ( (unsigned int)((GPIOF_BRR >> 0) & 0xFFFFFFFF), ((GPIOF_BRR = (GPIOF_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOF_BRR_BR0
// - SFDITEM_FIELD__GPIOF_BRR_BR1
// - SFDITEM_FIELD__GPIOF_BRR_BR2
// - SFDITEM_FIELD__GPIOF_BRR_BR3
// - SFDITEM_FIELD__GPIOF_BRR_BR4
// - SFDITEM_FIELD__GPIOF_BRR_BR5
// - SFDITEM_FIELD__GPIOF_BRR_BR6
// - SFDITEM_FIELD__GPIOF_BRR_BR7
// - SFDITEM_FIELD__GPIOF_BRR_BR8
// - SFDITEM_FIELD__GPIOF_BRR_BR9
// - SFDITEM_FIELD__GPIOF_BRR_BR10
// - SFDITEM_FIELD__GPIOF_BRR_BR11
// - SFDITEM_FIELD__GPIOF_BRR_BR12
// - SFDITEM_FIELD__GPIOF_BRR_BR13
// - SFDITEM_FIELD__GPIOF_BRR_BR14
// - SFDITEM_FIELD__GPIOF_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOF -------------------------------------
// SVD Line: 3581
// GPIOF
// GPIOF
// - SFDITEM_REG__GPIOF_MODER
// - SFDITEM_REG__GPIOF_OTYPER
// - SFDITEM_REG__GPIOF_OSPEEDR
// - SFDITEM_REG__GPIOF_PUPDR
// - SFDITEM_REG__GPIOF_IDR
// - SFDITEM_REG__GPIOF_ODR
// - SFDITEM_REG__GPIOF_BSRR
// - SFDITEM_REG__GPIOF_LCKR
// - SFDITEM_REG__GPIOF_AFRL
// - SFDITEM_REG__GPIOF_AFRH
// - SFDITEM_REG__GPIOF_BRR
//
//
// ----------------------------- Register Item Address: I2C1_CR1 --------------------------------
// SVD Line: 3606
unsigned int I2C1_CR1 __AT (0x40005400);
// --------------------------------- Field Item: I2C1_CR1_PE ------------------------------------
// SVD Line: 3611
// - SFDITEM_FIELD__I2C1_CR1_PE
// PE
//
// [Bit 0] RW (@ 0x40005400) Peripheral enable
//
// ( (unsigned int) I2C1_CR1 )
// PE
//
//
//
// ------------------------------- Field Item: I2C1_CR1_WUPEN -----------------------------------
// SVD Line: 3616
// - SFDITEM_FIELD__I2C1_CR1_WUPEN
// WUPEN
//
// [Bit 2] RW (@ 0x40005400) Wakeup from Stop mode enable
//
// ( (unsigned int) I2C1_CR1 )
// WUPEN
//
//
//
// -------------------------------- Field Item: I2C1_CR1_ENGC -----------------------------------
// SVD Line: 3621
// - SFDITEM_FIELD__I2C1_CR1_ENGC
// ENGC
//
// [Bit 6] RW (@ 0x40005400) General call enable
//
// ( (unsigned int) I2C1_CR1 )
// ENGC
//
//
//
// ----------------------------- Field Item: I2C1_CR1_NOSTRETCH ---------------------------------
// SVD Line: 3626
// - SFDITEM_FIELD__I2C1_CR1_NOSTRETCH
// NOSTRETCH
//
// [Bit 7] RW (@ 0x40005400) Clock stretching disable (Slave mode)
//
// ( (unsigned int) I2C1_CR1 )
// NOSTRETCH
//
//
//
// ------------------------------- Field Item: I2C1_CR1_START -----------------------------------
// SVD Line: 3631
// - SFDITEM_FIELD__I2C1_CR1_START
// START
//
// [Bit 8] RW (@ 0x40005400) Start generation
//
// ( (unsigned int) I2C1_CR1 )
// START
//
//
//
// -------------------------------- Field Item: I2C1_CR1_STOP -----------------------------------
// SVD Line: 3636
// - SFDITEM_FIELD__I2C1_CR1_STOP
// STOP
//
// [Bit 9] RW (@ 0x40005400) Stop generation
//
// ( (unsigned int) I2C1_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: I2C1_CR1_ACK ------------------------------------
// SVD Line: 3641
// - SFDITEM_FIELD__I2C1_CR1_ACK
// ACK
//
// [Bit 10] RW (@ 0x40005400) Acknowledge enable
//
// ( (unsigned int) I2C1_CR1 )
// ACK
//
//
//
// -------------------------------- Field Item: I2C1_CR1_POS ------------------------------------
// SVD Line: 3646
// - SFDITEM_FIELD__I2C1_CR1_POS
// POS
//
// [Bit 11] RW (@ 0x40005400) Acknowledge(for data reception)
//
// ( (unsigned int) I2C1_CR1 )
// POS
//
//
//
// ------------------------------- Field Item: I2C1_CR1_SWRST -----------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__I2C1_CR1_SWRST
// SWRST
//
// [Bit 15] RW (@ 0x40005400) Software reset
//
// ( (unsigned int) I2C1_CR1 )
// SWRST
//
//
//
// ------------------------------ Field Item: I2C1_CR1_WKUP_DIV ---------------------------------
// SVD Line: 3656
// - SFDITEM_FIELD__I2C1_CR1_WKUP_DIV
// WKUP_DIV
//
// [Bits 17..16] RW (@ 0x40005400) PCLK division
//
// ( (unsigned char)((I2C1_CR1 >> 16) & 0x3), ((I2C1_CR1 = (I2C1_CR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: I2C1_CR1_WKUP_CNT ---------------------------------
// SVD Line: 3661
// - SFDITEM_FIELD__I2C1_CR1_WKUP_CNT
// WKUP_CNT
//
// [Bits 19..18] RW (@ 0x40005400) Timeout count number
//
// ( (unsigned char)((I2C1_CR1 >> 18) & 0x3), ((I2C1_CR1 = (I2C1_CR1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C1_CR1 ------------------------------------
// SVD Line: 3606
// SFDITEM_REG__I2C1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40005400) Control register 1
// ( (unsigned int)((I2C1_CR1 >> 0) & 0xFFFFFFFF), ((I2C1_CR1 = (I2C1_CR1 & ~(0xF8FC5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF8FC5) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CR1_PE
// - SFDITEM_FIELD__I2C1_CR1_WUPEN
// - SFDITEM_FIELD__I2C1_CR1_ENGC
// - SFDITEM_FIELD__I2C1_CR1_NOSTRETCH
// - SFDITEM_FIELD__I2C1_CR1_START
// - SFDITEM_FIELD__I2C1_CR1_STOP
// - SFDITEM_FIELD__I2C1_CR1_ACK
// - SFDITEM_FIELD__I2C1_CR1_POS
// - SFDITEM_FIELD__I2C1_CR1_SWRST
// - SFDITEM_FIELD__I2C1_CR1_WKUP_DIV
// - SFDITEM_FIELD__I2C1_CR1_WKUP_CNT
//
//
// ----------------------------- Register Item Address: I2C1_CR2 --------------------------------
// SVD Line: 3668
unsigned int I2C1_CR2 __AT (0x40005404);
// -------------------------------- Field Item: I2C1_CR2_FREQ -----------------------------------
// SVD Line: 3673
// - SFDITEM_FIELD__I2C1_CR2_FREQ
// FREQ
//
// [Bits 6..0] RW (@ 0x40005404) Peripheral clock frequency
//
// ( (unsigned char)((I2C1_CR2 >> 0) & 0x7F), ((I2C1_CR2 = (I2C1_CR2 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: I2C1_CR2_ITERREN ----------------------------------
// SVD Line: 3678
// - SFDITEM_FIELD__I2C1_CR2_ITERREN
// ITERREN
//
// [Bit 8] RW (@ 0x40005404) Error interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ITERREN
//
//
//
// ------------------------------- Field Item: I2C1_CR2_DMAEN -----------------------------------
// SVD Line: 3683
// - SFDITEM_FIELD__I2C1_CR2_DMAEN
// DMAEN
//
// [Bit 11] RW (@ 0x40005404) DMA requests enable
//
// ( (unsigned int) I2C1_CR2 )
// DMAEN
//
//
//
// -------------------------------- Field Item: I2C1_CR2_LAST -----------------------------------
// SVD Line: 3688
// - SFDITEM_FIELD__I2C1_CR2_LAST
// LAST
//
// [Bit 12] RW (@ 0x40005404) DMA last transfer
//
// ( (unsigned int) I2C1_CR2 )
// LAST
//
//
//
// -------------------------------- Field Item: I2C1_CR2_SBIE -----------------------------------
// SVD Line: 3693
// - SFDITEM_FIELD__I2C1_CR2_SBIE
// SBIE
//
// [Bit 16] RW (@ 0x40005404) Start bit (Master mode) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// SBIE
//
//
//
// ------------------------------- Field Item: I2C1_CR2_ADDRIE ----------------------------------
// SVD Line: 3698
// - SFDITEM_FIELD__I2C1_CR2_ADDRIE
// ADDRIE
//
// [Bit 17] RW (@ 0x40005404) Address sent (master mode)/matched (slave mode) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ADDRIE
//
//
//
// ------------------------------- Field Item: I2C1_CR2_BTFIE -----------------------------------
// SVD Line: 3703
// - SFDITEM_FIELD__I2C1_CR2_BTFIE
// BTFIE
//
// [Bit 18] RW (@ 0x40005404) Byte transfer finished interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// BTFIE
//
//
//
// ------------------------------ Field Item: I2C1_CR2_ADD10IE ----------------------------------
// SVD Line: 3708
// - SFDITEM_FIELD__I2C1_CR2_ADD10IE
// ADD10IE
//
// [Bit 19] RW (@ 0x40005404) 10-bit header sent (Master mode) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// ADD10IE
//
//
//
// ------------------------------- Field Item: I2C1_CR2_STOPIE ----------------------------------
// SVD Line: 3713
// - SFDITEM_FIELD__I2C1_CR2_STOPIE
// STOPIE
//
// [Bit 20] RW (@ 0x40005404) Stop detection (slave mode) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// STOPIE
//
//
//
// -------------------------------- Field Item: I2C1_CR2_RXIE -----------------------------------
// SVD Line: 3718
// - SFDITEM_FIELD__I2C1_CR2_RXIE
// RXIE
//
// [Bit 22] RW (@ 0x40005404) Data register not empty (receivers) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// RXIE
//
//
//
// -------------------------------- Field Item: I2C1_CR2_TXIE -----------------------------------
// SVD Line: 3723
// - SFDITEM_FIELD__I2C1_CR2_TXIE
// TXIE
//
// [Bit 23] RW (@ 0x40005404) Data register empty (transmitters) interrupt enable
//
// ( (unsigned int) I2C1_CR2 )
// TXIE
//
//
//
// -------------------------------- Register RTree: I2C1_CR2 ------------------------------------
// SVD Line: 3668
// SFDITEM_REG__I2C1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40005404) Control register 2
// ( (unsigned int)((I2C1_CR2 >> 0) & 0xFFFFFFFF), ((I2C1_CR2 = (I2C1_CR2 & ~(0xDF197FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDF197F) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CR2_FREQ
// - SFDITEM_FIELD__I2C1_CR2_ITERREN
// - SFDITEM_FIELD__I2C1_CR2_DMAEN
// - SFDITEM_FIELD__I2C1_CR2_LAST
// - SFDITEM_FIELD__I2C1_CR2_SBIE
// - SFDITEM_FIELD__I2C1_CR2_ADDRIE
// - SFDITEM_FIELD__I2C1_CR2_BTFIE
// - SFDITEM_FIELD__I2C1_CR2_ADD10IE
// - SFDITEM_FIELD__I2C1_CR2_STOPIE
// - SFDITEM_FIELD__I2C1_CR2_RXIE
// - SFDITEM_FIELD__I2C1_CR2_TXIE
//
//
// ---------------------------- Register Item Address: I2C1_OAR1 --------------------------------
// SVD Line: 3730
unsigned int I2C1_OAR1 __AT (0x40005408);
// -------------------------------- Field Item: I2C1_OAR1_ADD -----------------------------------
// SVD Line: 3735
// - SFDITEM_FIELD__I2C1_OAR1_ADD
// ADD
//
// [Bits 9..0] RW (@ 0x40005408) Interface address
//
// ( (unsigned short)((I2C1_OAR1 >> 0) & 0x3FF), ((I2C1_OAR1 = (I2C1_OAR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: I2C1_OAR1_ADDMODE ---------------------------------
// SVD Line: 3740
// - SFDITEM_FIELD__I2C1_OAR1_ADDMODE
// ADDMODE
//
// [Bit 15] RW (@ 0x40005408) Addressing mode (slave mode)
//
// ( (unsigned int) I2C1_OAR1 )
// ADDMODE
//
//
//
// -------------------------------- Register RTree: I2C1_OAR1 -----------------------------------
// SVD Line: 3730
// SFDITEM_REG__I2C1_OAR1
// OAR1
//
// [Bits 31..0] RW (@ 0x40005408) Own address register 1
// ( (unsigned int)((I2C1_OAR1 >> 0) & 0xFFFFFFFF), ((I2C1_OAR1 = (I2C1_OAR1 & ~(0x83FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x83FF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_OAR1_ADD
// - SFDITEM_FIELD__I2C1_OAR1_ADDMODE
//
//
// ---------------------------- Register Item Address: I2C1_OAR2 --------------------------------
// SVD Line: 3747
unsigned int I2C1_OAR2 __AT (0x4000540C);
// ------------------------------ Field Item: I2C1_OAR2_ENDUAL ----------------------------------
// SVD Line: 3751
// - SFDITEM_FIELD__I2C1_OAR2_ENDUAL
// ENDUAL
//
// [Bit 0] RW (@ 0x4000540C) Dual addressing mode enable
//
// ( (unsigned int) I2C1_OAR2 )
// ENDUAL
//
//
//
// ------------------------------- Field Item: I2C1_OAR2_ADD2 -----------------------------------
// SVD Line: 3756
// - SFDITEM_FIELD__I2C1_OAR2_ADD2
// ADD2
//
// [Bits 7..1] RW (@ 0x4000540C) Interface address
//
// ( (unsigned char)((I2C1_OAR2 >> 1) & 0x7F), ((I2C1_OAR2 = (I2C1_OAR2 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) ))
//
//
//
// ------------------------------ Field Item: I2C1_OAR2_OA2MSK ----------------------------------
// SVD Line: 3761
// - SFDITEM_FIELD__I2C1_OAR2_OA2MSK
// OA2MSK
//
// [Bits 10..8] RW (@ 0x4000540C) Own Address 2 masks
//
// ( (unsigned char)((I2C1_OAR2 >> 8) & 0x7), ((I2C1_OAR2 = (I2C1_OAR2 & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C1_OAR2 -----------------------------------
// SVD Line: 3747
// SFDITEM_REG__I2C1_OAR2
// OAR2
//
// [Bits 31..0] RW (@ 0x4000540C) OAR2
// ( (unsigned int)((I2C1_OAR2 >> 0) & 0xFFFFFFFF), ((I2C1_OAR2 = (I2C1_OAR2 & ~(0x7FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_OAR2_ENDUAL
// - SFDITEM_FIELD__I2C1_OAR2_ADD2
// - SFDITEM_FIELD__I2C1_OAR2_OA2MSK
//
//
// ----------------------------- Register Item Address: I2C1_DR ---------------------------------
// SVD Line: 3768
unsigned int I2C1_DR __AT (0x40005410);
// --------------------------------- Field Item: I2C1_DR_DR -------------------------------------
// SVD Line: 3773
// - SFDITEM_FIELD__I2C1_DR_DR
// DR
//
// [Bits 7..0] RW (@ 0x40005410) 8-bit data register
//
// ( (unsigned char)((I2C1_DR >> 0) & 0xFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: I2C1_DR ------------------------------------
// SVD Line: 3768
// SFDITEM_REG__I2C1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40005410) Data register
// ( (unsigned int)((I2C1_DR >> 0) & 0xFFFFFFFF), ((I2C1_DR = (I2C1_DR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_DR_DR
//
//
// ----------------------------- Register Item Address: I2C1_SR1 --------------------------------
// SVD Line: 3780
unsigned int I2C1_SR1 __AT (0x40005414);
// --------------------------------- Field Item: I2C1_SR1_SB ------------------------------------
// SVD Line: 3785
// - SFDITEM_FIELD__I2C1_SR1_SB
// SB
//
// [Bit 0] RO (@ 0x40005414) Start bit (Master mode)
//
// ( (unsigned int) I2C1_SR1 )
// SB
//
//
//
// -------------------------------- Field Item: I2C1_SR1_ADDR -----------------------------------
// SVD Line: 3791
// - SFDITEM_FIELD__I2C1_SR1_ADDR
// ADDR
//
// [Bit 1] RO (@ 0x40005414) Address sent (master mode)/matched (slave mode)
//
// ( (unsigned int) I2C1_SR1 )
// ADDR
//
//
//
// -------------------------------- Field Item: I2C1_SR1_BTF ------------------------------------
// SVD Line: 3797
// - SFDITEM_FIELD__I2C1_SR1_BTF
// BTF
//
// [Bit 2] RO (@ 0x40005414) Byte transfer finished
//
// ( (unsigned int) I2C1_SR1 )
// BTF
//
//
//
// ------------------------------- Field Item: I2C1_SR1_ADD10 -----------------------------------
// SVD Line: 3803
// - SFDITEM_FIELD__I2C1_SR1_ADD10
// ADD10
//
// [Bit 3] RO (@ 0x40005414) 10-bit header sent (Master mode)
//
// ( (unsigned int) I2C1_SR1 )
// ADD10
//
//
//
// ------------------------------- Field Item: I2C1_SR1_STOPF -----------------------------------
// SVD Line: 3809
// - SFDITEM_FIELD__I2C1_SR1_STOPF
// STOPF
//
// [Bit 4] RO (@ 0x40005414) Stop detection (slave mode)
//
// ( (unsigned int) I2C1_SR1 )
// STOPF
//
//
//
// -------------------------------- Field Item: I2C1_SR1_RXNE -----------------------------------
// SVD Line: 3815
// - SFDITEM_FIELD__I2C1_SR1_RXNE
// RXNE
//
// [Bit 6] RO (@ 0x40005414) Data register not empty (receivers)
//
// ( (unsigned int) I2C1_SR1 )
// RXNE
//
//
//
// -------------------------------- Field Item: I2C1_SR1_TXE ------------------------------------
// SVD Line: 3821
// - SFDITEM_FIELD__I2C1_SR1_TXE
// TXE
//
// [Bit 7] RO (@ 0x40005414) Data register empty (transmitters)
//
// ( (unsigned int) I2C1_SR1 )
// TXE
//
//
//
// -------------------------------- Field Item: I2C1_SR1_BERR -----------------------------------
// SVD Line: 3827
// - SFDITEM_FIELD__I2C1_SR1_BERR
// BERR
//
// [Bit 8] RW (@ 0x40005414) Bus error
//
// ( (unsigned int) I2C1_SR1 )
// BERR
//
//
//
// -------------------------------- Field Item: I2C1_SR1_ARLO -----------------------------------
// SVD Line: 3832
// - SFDITEM_FIELD__I2C1_SR1_ARLO
// ARLO
//
// [Bit 9] RW (@ 0x40005414) Arbitration lost (master mode)
//
// ( (unsigned int) I2C1_SR1 )
// ARLO
//
//
//
// --------------------------------- Field Item: I2C1_SR1_AF ------------------------------------
// SVD Line: 3837
// - SFDITEM_FIELD__I2C1_SR1_AF
// AF
//
// [Bit 10] RW (@ 0x40005414) Acknowledge failure
//
// ( (unsigned int) I2C1_SR1 )
// AF
//
//
//
// -------------------------------- Field Item: I2C1_SR1_OVR ------------------------------------
// SVD Line: 3842
// - SFDITEM_FIELD__I2C1_SR1_OVR
// OVR
//
// [Bit 11] RW (@ 0x40005414) Overrun/Underrun
//
// ( (unsigned int) I2C1_SR1 )
// OVR
//
//
//
// ------------------------------ Field Item: I2C1_SR1_TIMEOUT ----------------------------------
// SVD Line: 3847
// - SFDITEM_FIELD__I2C1_SR1_TIMEOUT
// TIMEOUT
//
// [Bit 14] RW (@ 0x40005414) Timeout or Tlow error
//
// ( (unsigned int) I2C1_SR1 )
// TIMEOUT
//
//
//
// -------------------------------- Register RTree: I2C1_SR1 ------------------------------------
// SVD Line: 3780
// SFDITEM_REG__I2C1_SR1
// SR1
//
// [Bits 31..0] RW (@ 0x40005414) Status register 1
// ( (unsigned int)((I2C1_SR1 >> 0) & 0xFFFFFFFF), ((I2C1_SR1 = (I2C1_SR1 & ~(0x4F00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4F00) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_SR1_SB
// - SFDITEM_FIELD__I2C1_SR1_ADDR
// - SFDITEM_FIELD__I2C1_SR1_BTF
// - SFDITEM_FIELD__I2C1_SR1_ADD10
// - SFDITEM_FIELD__I2C1_SR1_STOPF
// - SFDITEM_FIELD__I2C1_SR1_RXNE
// - SFDITEM_FIELD__I2C1_SR1_TXE
// - SFDITEM_FIELD__I2C1_SR1_BERR
// - SFDITEM_FIELD__I2C1_SR1_ARLO
// - SFDITEM_FIELD__I2C1_SR1_AF
// - SFDITEM_FIELD__I2C1_SR1_OVR
// - SFDITEM_FIELD__I2C1_SR1_TIMEOUT
//
//
// ----------------------------- Register Item Address: I2C1_SR2 --------------------------------
// SVD Line: 3854
unsigned int I2C1_SR2 __AT (0x40005418);
// -------------------------------- Field Item: I2C1_SR2_MSL ------------------------------------
// SVD Line: 3859
// - SFDITEM_FIELD__I2C1_SR2_MSL
// MSL
//
// [Bit 0] RO (@ 0x40005418) Master/slave
//
// ( (unsigned int) I2C1_SR2 )
// MSL
//
//
//
// -------------------------------- Field Item: I2C1_SR2_BUSY -----------------------------------
// SVD Line: 3865
// - SFDITEM_FIELD__I2C1_SR2_BUSY
// BUSY
//
// [Bit 1] RO (@ 0x40005418) Bus busy
//
// ( (unsigned int) I2C1_SR2 )
// BUSY
//
//
//
// -------------------------------- Field Item: I2C1_SR2_TRA ------------------------------------
// SVD Line: 3871
// - SFDITEM_FIELD__I2C1_SR2_TRA
// TRA
//
// [Bit 2] RO (@ 0x40005418) Transmitter/receiver
//
// ( (unsigned int) I2C1_SR2 )
// TRA
//
//
//
// ------------------------------ Field Item: I2C1_SR2_GENCALL ----------------------------------
// SVD Line: 3877
// - SFDITEM_FIELD__I2C1_SR2_GENCALL
// GENCALL
//
// [Bit 4] RO (@ 0x40005418) General call address (Slave mode)
//
// ( (unsigned int) I2C1_SR2 )
// GENCALL
//
//
//
// ------------------------------- Field Item: I2C1_SR2_DUALF -----------------------------------
// SVD Line: 3883
// - SFDITEM_FIELD__I2C1_SR2_DUALF
// DUALF
//
// [Bit 7] RO (@ 0x40005418) Dual flag (Slave mode)
//
// ( (unsigned int) I2C1_SR2 )
// DUALF
//
//
//
// ------------------------------- Field Item: I2C1_SR2_SBUSY -----------------------------------
// SVD Line: 3889
// - SFDITEM_FIELD__I2C1_SR2_SBUSY
// SBUSY
//
// [Bit 16] RO (@ 0x40005418) Slave busy
//
// ( (unsigned int) I2C1_SR2 )
// SBUSY
//
//
//
// -------------------------------- Register RTree: I2C1_SR2 ------------------------------------
// SVD Line: 3854
// SFDITEM_REG__I2C1_SR2
// SR2
//
// [Bits 31..0] RW (@ 0x40005418) Status register 2
// ( (unsigned int)((I2C1_SR2 >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__I2C1_SR2_MSL
// - SFDITEM_FIELD__I2C1_SR2_BUSY
// - SFDITEM_FIELD__I2C1_SR2_TRA
// - SFDITEM_FIELD__I2C1_SR2_GENCALL
// - SFDITEM_FIELD__I2C1_SR2_DUALF
// - SFDITEM_FIELD__I2C1_SR2_SBUSY
//
//
// ----------------------------- Register Item Address: I2C1_CCR --------------------------------
// SVD Line: 3897
unsigned int I2C1_CCR __AT (0x4000541C);
// -------------------------------- Field Item: I2C1_CCR_CCR ------------------------------------
// SVD Line: 3902
// - SFDITEM_FIELD__I2C1_CCR_CCR
// CCR
//
// [Bits 11..0] RW (@ 0x4000541C) Clock control register in Fm/Sm mode (Master mode)
//
// ( (unsigned short)((I2C1_CCR >> 0) & 0xFFF), ((I2C1_CCR = (I2C1_CCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: I2C1_CCR_FP ------------------------------------
// SVD Line: 3907
// - SFDITEM_FIELD__I2C1_CCR_FP
// FP
//
// [Bit 13] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C1_CCR )
// FP
//
//
//
// -------------------------------- Field Item: I2C1_CCR_DUTY -----------------------------------
// SVD Line: 3912
// - SFDITEM_FIELD__I2C1_CCR_DUTY
// DUTY
//
// [Bit 14] RW (@ 0x4000541C) Fm mode duty cycle
//
// ( (unsigned int) I2C1_CCR )
// DUTY
//
//
//
// --------------------------------- Field Item: I2C1_CCR_FS ------------------------------------
// SVD Line: 3917
// - SFDITEM_FIELD__I2C1_CCR_FS
// FS
//
// [Bit 15] RW (@ 0x4000541C) I2C master mode selection
//
// ( (unsigned int) I2C1_CCR )
// FS
//
//
//
// -------------------------------- Register RTree: I2C1_CCR ------------------------------------
// SVD Line: 3897
// SFDITEM_REG__I2C1_CCR
// CCR
//
// [Bits 31..0] RW (@ 0x4000541C) Clock control register
// ( (unsigned int)((I2C1_CCR >> 0) & 0xFFFFFFFF), ((I2C1_CCR = (I2C1_CCR & ~(0xEFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xEFFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_CCR_CCR
// - SFDITEM_FIELD__I2C1_CCR_FP
// - SFDITEM_FIELD__I2C1_CCR_DUTY
// - SFDITEM_FIELD__I2C1_CCR_FS
//
//
// ---------------------------- Register Item Address: I2C1_TRISE -------------------------------
// SVD Line: 3924
unsigned int I2C1_TRISE __AT (0x40005420);
// ------------------------------ Field Item: I2C1_TRISE_TRISE ----------------------------------
// SVD Line: 3929
// - SFDITEM_FIELD__I2C1_TRISE_TRISE
// TRISE
//
// [Bits 6..0] RW (@ 0x40005420) Maximum rise time in Fm+/Fm/Sm mode (Master mode)
//
// ( (unsigned char)((I2C1_TRISE >> 0) & 0x7F), ((I2C1_TRISE = (I2C1_TRISE & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: I2C1_TRISE_THOLDDATA --------------------------------
// SVD Line: 3934
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA
// THOLDDATA
//
// [Bits 11..7] RW (@ 0x40005420) Data hold time
//
// ( (unsigned char)((I2C1_TRISE >> 7) & 0x1F), ((I2C1_TRISE = (I2C1_TRISE & ~(0x1FUL << 7 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 7 ) ) ))
//
//
//
// -------------------------- Field Item: I2C1_TRISE_THOLDDATA_SEL ------------------------------
// SVD Line: 3939
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA_SEL
// THOLDDATA_SEL
//
// [Bit 12] RW (@ 0x40005420) Data hold time select
//
// ( (unsigned int) I2C1_TRISE )
// THOLDDATA_SEL
//
//
//
// ------------------------------- Register RTree: I2C1_TRISE -----------------------------------
// SVD Line: 3924
// SFDITEM_REG__I2C1_TRISE
// TRISE
//
// [Bits 31..0] RW (@ 0x40005420) TRISE register
// ( (unsigned int)((I2C1_TRISE >> 0) & 0xFFFFFFFF), ((I2C1_TRISE = (I2C1_TRISE & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_TRISE_TRISE
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA
// - SFDITEM_FIELD__I2C1_TRISE_THOLDDATA_SEL
//
//
// ---------------------------- Register Item Address: I2C1_OAR3 --------------------------------
// SVD Line: 3946
unsigned int I2C1_OAR3 __AT (0x40005428);
// ----------------------------- Field Item: I2C1_OAR3_ENTRIPLE ---------------------------------
// SVD Line: 3950
// - SFDITEM_FIELD__I2C1_OAR3_ENTRIPLE
// ENTRIPLE
//
// [Bit 0] RW (@ 0x40005428) Triple addressing mode enable
//
// ( (unsigned int) I2C1_OAR3 )
// ENTRIPLE
//
//
//
// ------------------------------- Field Item: I2C1_OAR3_ADD3 -----------------------------------
// SVD Line: 3955
// - SFDITEM_FIELD__I2C1_OAR3_ADD3
// ADD3
//
// [Bits 7..1] RW (@ 0x40005428) Interface address
//
// ( (unsigned char)((I2C1_OAR3 >> 1) & 0x7F), ((I2C1_OAR3 = (I2C1_OAR3 & ~(0x7FUL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 1 ) ) ))
//
//
//
// -------------------------------- Register RTree: I2C1_OAR3 -----------------------------------
// SVD Line: 3946
// SFDITEM_REG__I2C1_OAR3
// OAR3
//
// [Bits 31..0] RW (@ 0x40005428) OAR3
// ( (unsigned int)((I2C1_OAR3 >> 0) & 0xFFFFFFFF), ((I2C1_OAR3 = (I2C1_OAR3 & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__I2C1_OAR3_ENTRIPLE
// - SFDITEM_FIELD__I2C1_OAR3_ADD3
//
//
// ---------------------------------- Peripheral View: I2C1 -------------------------------------
// SVD Line: 3585
// I2C1
// I2C1
// - SFDITEM_REG__I2C1_CR1
// - SFDITEM_REG__I2C1_CR2
// - SFDITEM_REG__I2C1_OAR1
// - SFDITEM_REG__I2C1_OAR2
// - SFDITEM_REG__I2C1_DR
// - SFDITEM_REG__I2C1_SR1
// - SFDITEM_REG__I2C1_SR2
// - SFDITEM_REG__I2C1_CCR
// - SFDITEM_REG__I2C1_TRISE
// - SFDITEM_REG__I2C1_OAR3
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 3974
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 3979
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] RW (@ 0x40003000) IWDG KEY
//
// ( (unsigned short)((IWDG_KR >> 0) & 0xFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 3974
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] RW (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 3986
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 3991
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) IWDG preload
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 3986
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 3998
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 4003
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) IWDG reload
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 3998
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 4010
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 4015
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 4021
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 4010
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RW (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 3964
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM_ISR --------------------------------
// SVD Line: 4046
unsigned int LPTIM_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM_ISR_ARRM -----------------------------------
// SVD Line: 4051
// - SFDITEM_FIELD__LPTIM_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM_ISR )
// ARRM
//
//
//
// ------------------------------- Field Item: LPTIM_ISR_ARROK ----------------------------------
// SVD Line: 4057
// - SFDITEM_FIELD__LPTIM_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload register update OK
//
// ( (unsigned int) LPTIM_ISR )
// ARROK
//
//
//
// -------------------------------- Register RTree: LPTIM_ISR -----------------------------------
// SVD Line: 4046
// SFDITEM_REG__LPTIM_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM_ISR_ARRM
// - SFDITEM_FIELD__LPTIM_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM_ICR --------------------------------
// SVD Line: 4065
unsigned int LPTIM_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM_ICR_ARRMCF ----------------------------------
// SVD Line: 4070
// - SFDITEM_FIELD__LPTIM_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] RW (@ 0x40007C04) Autoreload match clear flag
//
// ( (unsigned int) LPTIM_ICR )
// ARRMCF
//
//
//
// ------------------------------ Field Item: LPTIM_ICR_ARROKCF ---------------------------------
// SVD Line: 4075
// - SFDITEM_FIELD__LPTIM_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] RW (@ 0x40007C04) Autoreload register update OK clear flag
//
// ( (unsigned int) LPTIM_ICR )
// ARROKCF
//
//
//
// -------------------------------- Register RTree: LPTIM_ICR -----------------------------------
// SVD Line: 4065
// SFDITEM_REG__LPTIM_ICR
// ICR
//
// [Bits 31..0] RW (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM_ICR >> 0) & 0xFFFFFFFF), ((LPTIM_ICR = (LPTIM_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM_IER --------------------------------
// SVD Line: 4082
unsigned int LPTIM_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM_IER_ARRMIE ----------------------------------
// SVD Line: 4087
// - SFDITEM_FIELD__LPTIM_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload match Interrupt Enable
//
// ( (unsigned int) LPTIM_IER )
// ARRMIE
//
//
//
// ------------------------------ Field Item: LPTIM_IER_ARROKIE ---------------------------------
// SVD Line: 4092
// - SFDITEM_FIELD__LPTIM_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload register update OK Interrupt Enable
//
// ( (unsigned int) LPTIM_IER )
// ARROKIE
//
//
//
// -------------------------------- Register RTree: LPTIM_IER -----------------------------------
// SVD Line: 4082
// SFDITEM_REG__LPTIM_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM_IER >> 0) & 0xFFFFFFFF), ((LPTIM_IER = (LPTIM_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM_IER_ARROKIE
//
//
// ---------------------------- Register Item Address: LPTIM_CFGR -------------------------------
// SVD Line: 4099
unsigned int LPTIM_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM_CFGR_PRESC ----------------------------------
// SVD Line: 4104
// - SFDITEM_FIELD__LPTIM_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM_CFGR >> 9) & 0x7), ((LPTIM_CFGR = (LPTIM_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM_CFGR_PRELOAD ---------------------------------
// SVD Line: 4109
// - SFDITEM_FIELD__LPTIM_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM_CFGR -----------------------------------
// SVD Line: 4099
// SFDITEM_REG__LPTIM_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM_CFGR = (LPTIM_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM_CFGR_PRELOAD
//
//
// ----------------------------- Register Item Address: LPTIM_CR --------------------------------
// SVD Line: 4116
unsigned int LPTIM_CR __AT (0x40007C10);
// ------------------------------- Field Item: LPTIM_CR_ENABLE ----------------------------------
// SVD Line: 4121
// - SFDITEM_FIELD__LPTIM_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM enable
//
// ( (unsigned int) LPTIM_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM_CR_SNGSTRT ----------------------------------
// SVD Line: 4126
// - SFDITEM_FIELD__LPTIM_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in Single mode
//
// ( (unsigned int) LPTIM_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM_CR_CNTSTRT ----------------------------------
// SVD Line: 4131
// - SFDITEM_FIELD__LPTIM_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) Timer start in Continuous mode
//
// ( (unsigned int) LPTIM_CR )
// CNTSTRT
//
//
//
// ------------------------------ Field Item: LPTIM_CR_COUNTRST ---------------------------------
// SVD Line: 4136
// - SFDITEM_FIELD__LPTIM_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) Counter reset
//
// ( (unsigned int) LPTIM_CR )
// COUNTRST
//
//
//
// ------------------------------- Field Item: LPTIM_CR_RSTARE ----------------------------------
// SVD Line: 4141
// - SFDITEM_FIELD__LPTIM_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM_CR ------------------------------------
// SVD Line: 4116
// SFDITEM_REG__LPTIM_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM_CR >> 0) & 0xFFFFFFFF), ((LPTIM_CR = (LPTIM_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_CR_ENABLE
// - SFDITEM_FIELD__LPTIM_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM_ARR --------------------------------
// SVD Line: 4148
unsigned int LPTIM_ARR __AT (0x40007C18);
// -------------------------------- Field Item: LPTIM_ARR_ARR -----------------------------------
// SVD Line: 4153
// - SFDITEM_FIELD__LPTIM_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM_ARR >> 0) & 0xFFFF), ((LPTIM_ARR = (LPTIM_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: LPTIM_ARR -----------------------------------
// SVD Line: 4148
// SFDITEM_REG__LPTIM_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM_ARR >> 0) & 0xFFFFFFFF), ((LPTIM_ARR = (LPTIM_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM_CNT --------------------------------
// SVD Line: 4160
unsigned int LPTIM_CNT __AT (0x40007C1C);
// -------------------------------- Field Item: LPTIM_CNT_CNT -----------------------------------
// SVD Line: 4165
// - SFDITEM_FIELD__LPTIM_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM_CNT >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: LPTIM_CNT -----------------------------------
// SVD Line: 4160
// SFDITEM_REG__LPTIM_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM -------------------------------------
// SVD Line: 4031
// LPTIM
// LPTIM
// - SFDITEM_REG__LPTIM_ISR
// - SFDITEM_REG__LPTIM_ICR
// - SFDITEM_REG__LPTIM_IER
// - SFDITEM_REG__LPTIM_CFGR
// - SFDITEM_REG__LPTIM_CR
// - SFDITEM_REG__LPTIM_ARR
// - SFDITEM_REG__LPTIM_CNT
//
//
// ---------------------------- Register Item Address: LPUART_CR1 -------------------------------
// SVD Line: 4189
unsigned int LPUART_CR1 __AT (0x40008000);
// -------------------------------- Field Item: LPUART_CR1_UE -----------------------------------
// SVD Line: 4193
// - SFDITEM_FIELD__LPUART_CR1_UE
// UE
//
// [Bit 0] RW (@ 0x40008000) LPUART enabled
//
// ( (unsigned int) LPUART_CR1 )
// UE
//
//
//
// ------------------------------- Field Item: LPUART_CR1_UESM ----------------------------------
// SVD Line: 4198
// - SFDITEM_FIELD__LPUART_CR1_UESM
// UESM
//
// [Bit 1] RW (@ 0x40008000) LPUART enabled in Stop mode
//
// ( (unsigned int) LPUART_CR1 )
// UESM
//
//
//
// -------------------------------- Field Item: LPUART_CR1_RE -----------------------------------
// SVD Line: 4203
// - SFDITEM_FIELD__LPUART_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x40008000) Receive enable
//
// ( (unsigned int) LPUART_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: LPUART_CR1_TE -----------------------------------
// SVD Line: 4208
// - SFDITEM_FIELD__LPUART_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x40008000) Transfer enable
//
// ( (unsigned int) LPUART_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: LPUART_CR1_IDLEIE ---------------------------------
// SVD Line: 4213
// - SFDITEM_FIELD__LPUART_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x40008000) IDLE interrupt enable
//
// ( (unsigned int) LPUART_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: LPUART_CR1_RXNEIE ---------------------------------
// SVD Line: 4218
// - SFDITEM_FIELD__LPUART_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x40008000) RXNE interrupt enable
//
// ( (unsigned int) LPUART_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: LPUART_CR1_TCIE ----------------------------------
// SVD Line: 4223
// - SFDITEM_FIELD__LPUART_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x40008000) End of Transfer interrupt enabled
//
// ( (unsigned int) LPUART_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: LPUART_CR1_TXEIE ----------------------------------
// SVD Line: 4228
// - SFDITEM_FIELD__LPUART_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40008000) TXE interrupt enable
//
// ( (unsigned int) LPUART_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: LPUART_CR1_PEIE ----------------------------------
// SVD Line: 4233
// - SFDITEM_FIELD__LPUART_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x40008000) PE interrupt enable
//
// ( (unsigned int) LPUART_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: LPUART_CR1_PS -----------------------------------
// SVD Line: 4238
// - SFDITEM_FIELD__LPUART_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x40008000) Parity selection
//
// ( (unsigned int) LPUART_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: LPUART_CR1_PCE -----------------------------------
// SVD Line: 4243
// - SFDITEM_FIELD__LPUART_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x40008000) Parity control
//
// ( (unsigned int) LPUART_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: LPUART_CR1_WAKE ----------------------------------
// SVD Line: 4248
// - SFDITEM_FIELD__LPUART_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x40008000) Receive wake-up mode
//
// ( (unsigned int) LPUART_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: LPUART_CR1_M0 -----------------------------------
// SVD Line: 4253
// - SFDITEM_FIELD__LPUART_CR1_M0
// M0
//
// [Bit 12] RW (@ 0x40008000) Configure the word length in combination with M1
//
// ( (unsigned int) LPUART_CR1 )
// M0
//
//
//
// ------------------------------- Field Item: LPUART_CR1_MME -----------------------------------
// SVD Line: 4258
// - SFDITEM_FIELD__LPUART_CR1_MME
// MME
//
// [Bit 13] RW (@ 0x40008000) Silent mode enabled
//
// ( (unsigned int) LPUART_CR1 )
// MME
//
//
//
// ------------------------------- Field Item: LPUART_CR1_CMIE ----------------------------------
// SVD Line: 4263
// - SFDITEM_FIELD__LPUART_CR1_CMIE
// CMIE
//
// [Bit 14] RW (@ 0x40008000) Character match interrupt enabled
//
// ( (unsigned int) LPUART_CR1 )
// CMIE
//
//
//
// ------------------------------- Field Item: LPUART_CR1_DEDT ----------------------------------
// SVD Line: 4268
// - SFDITEM_FIELD__LPUART_CR1_DEDT
// DEDT
//
// [Bits 20..16] RW (@ 0x40008000) The time between the transmit frame stop bit and the invalid DE (driver enable) signal
//
// ( (unsigned char)((LPUART_CR1 >> 16) & 0x1F), ((LPUART_CR1 = (LPUART_CR1 & ~(0x1FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 16 ) ) ))
//
//
//
// ------------------------------- Field Item: LPUART_CR1_DEAT ----------------------------------
// SVD Line: 4273
// - SFDITEM_FIELD__LPUART_CR1_DEAT
// DEAT
//
// [Bits 25..21] RW (@ 0x40008000) The time between the DE (driver enable) signal validity and the start bit
//
// ( (unsigned char)((LPUART_CR1 >> 21) & 0x1F), ((LPUART_CR1 = (LPUART_CR1 & ~(0x1FUL << 21 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 21 ) ) ))
//
//
//
// -------------------------------- Field Item: LPUART_CR1_M1 -----------------------------------
// SVD Line: 4278
// - SFDITEM_FIELD__LPUART_CR1_M1
// M1
//
// [Bit 28] RW (@ 0x40008000) The value of {M1,M0} the configurate length
//
// ( (unsigned int) LPUART_CR1 )
// M1
//
//
//
// ------------------------------- Register RTree: LPUART_CR1 -----------------------------------
// SVD Line: 4189
// SFDITEM_REG__LPUART_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40008000) CR1
// ( (unsigned int)((LPUART_CR1 >> 0) & 0xFFFFFFFF), ((LPUART_CR1 = (LPUART_CR1 & ~(0x13FF7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x13FF7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_CR1_UE
// - SFDITEM_FIELD__LPUART_CR1_UESM
// - SFDITEM_FIELD__LPUART_CR1_RE
// - SFDITEM_FIELD__LPUART_CR1_TE
// - SFDITEM_FIELD__LPUART_CR1_IDLEIE
// - SFDITEM_FIELD__LPUART_CR1_RXNEIE
// - SFDITEM_FIELD__LPUART_CR1_TCIE
// - SFDITEM_FIELD__LPUART_CR1_TXEIE
// - SFDITEM_FIELD__LPUART_CR1_PEIE
// - SFDITEM_FIELD__LPUART_CR1_PS
// - SFDITEM_FIELD__LPUART_CR1_PCE
// - SFDITEM_FIELD__LPUART_CR1_WAKE
// - SFDITEM_FIELD__LPUART_CR1_M0
// - SFDITEM_FIELD__LPUART_CR1_MME
// - SFDITEM_FIELD__LPUART_CR1_CMIE
// - SFDITEM_FIELD__LPUART_CR1_DEDT
// - SFDITEM_FIELD__LPUART_CR1_DEAT
// - SFDITEM_FIELD__LPUART_CR1_M1
//
//
// ---------------------------- Register Item Address: LPUART_CR2 -------------------------------
// SVD Line: 4285
unsigned int LPUART_CR2 __AT (0x40008004);
// ------------------------------ Field Item: LPUART_CR2_ADDM7 ----------------------------------
// SVD Line: 4289
// - SFDITEM_FIELD__LPUART_CR2_ADDM7
// ADDM7
//
// [Bit 4] RW (@ 0x40008004) 7bit/4bit address detection configuration
//
// ( (unsigned int) LPUART_CR2 )
// ADDM7
//
//
//
// ------------------------------- Field Item: LPUART_CR2_STOP ----------------------------------
// SVD Line: 4294
// - SFDITEM_FIELD__LPUART_CR2_STOP
// STOP
//
// [Bits 13..12] RW (@ 0x40008004) Stop bit configuration
//
// ( (unsigned char)((LPUART_CR2 >> 12) & 0x3), ((LPUART_CR2 = (LPUART_CR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: LPUART_CR2_SWAP ----------------------------------
// SVD Line: 4299
// - SFDITEM_FIELD__LPUART_CR2_SWAP
// SWAP
//
// [Bit 15] RW (@ 0x40008004) TX/RX pin interchangeable
//
// ( (unsigned int) LPUART_CR2 )
// SWAP
//
//
//
// ------------------------------ Field Item: LPUART_CR2_RXINV ----------------------------------
// SVD Line: 4304
// - SFDITEM_FIELD__LPUART_CR2_RXINV
// RXINV
//
// [Bit 16] RW (@ 0x40008004) The RX pin is active level inverting
//
// ( (unsigned int) LPUART_CR2 )
// RXINV
//
//
//
// ------------------------------ Field Item: LPUART_CR2_TXINV ----------------------------------
// SVD Line: 4309
// - SFDITEM_FIELD__LPUART_CR2_TXINV
// TXINV
//
// [Bit 17] RW (@ 0x40008004) TX pin active level inverted
//
// ( (unsigned int) LPUART_CR2 )
// TXINV
//
//
//
// ----------------------------- Field Item: LPUART_CR2_DATAINV ---------------------------------
// SVD Line: 4314
// - SFDITEM_FIELD__LPUART_CR2_DATAINV
// DATAINV
//
// [Bit 18] RW (@ 0x40008004) Inverse binary data processing
//
// ( (unsigned int) LPUART_CR2 )
// DATAINV
//
//
//
// ----------------------------- Field Item: LPUART_CR2_MSBFIRST --------------------------------
// SVD Line: 4319
// - SFDITEM_FIELD__LPUART_CR2_MSBFIRST
// MSBFIRST
//
// [Bit 19] RW (@ 0x40008004) MSB first
//
// ( (unsigned int) LPUART_CR2 )
// MSBFIRST
//
//
//
// -------------------------- Field Item: LPUART_CR2_TXOE_ALWAYS_ON -----------------------------
// SVD Line: 4324
// - SFDITEM_FIELD__LPUART_CR2_TXOE_ALWAYS_ON
// TXOE_ALWAYS_ON
//
// [Bit 20] RW (@ 0x40008004) TXOE_ALWAYS_ON
//
// ( (unsigned int) LPUART_CR2 )
// TXOE_ALWAYS_ON
//
//
//
// ------------------------------- Field Item: LPUART_CR2_ADD -----------------------------------
// SVD Line: 4328
// - SFDITEM_FIELD__LPUART_CR2_ADD
// ADD
//
// [Bits 31..24] RW (@ 0x40008004) LPUART address
//
// ( (unsigned char)((LPUART_CR2 >> 24) & 0xFF), ((LPUART_CR2 = (LPUART_CR2 & ~(0xFFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPUART_CR2 -----------------------------------
// SVD Line: 4285
// SFDITEM_REG__LPUART_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40008004) CR2
// ( (unsigned int)((LPUART_CR2 >> 0) & 0xFFFFFFFF), ((LPUART_CR2 = (LPUART_CR2 & ~(0xFF1FB010UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1FB010) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_CR2_ADDM7
// - SFDITEM_FIELD__LPUART_CR2_STOP
// - SFDITEM_FIELD__LPUART_CR2_SWAP
// - SFDITEM_FIELD__LPUART_CR2_RXINV
// - SFDITEM_FIELD__LPUART_CR2_TXINV
// - SFDITEM_FIELD__LPUART_CR2_DATAINV
// - SFDITEM_FIELD__LPUART_CR2_MSBFIRST
// - SFDITEM_FIELD__LPUART_CR2_TXOE_ALWAYS_ON
// - SFDITEM_FIELD__LPUART_CR2_ADD
//
//
// ---------------------------- Register Item Address: LPUART_CR3 -------------------------------
// SVD Line: 4335
unsigned int LPUART_CR3 __AT (0x40008008);
// ------------------------------- Field Item: LPUART_CR3_EIE -----------------------------------
// SVD Line: 4339
// - SFDITEM_FIELD__LPUART_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40008008) Error interrupts are enabled
//
// ( (unsigned int) LPUART_CR3 )
// EIE
//
//
//
// ------------------------------ Field Item: LPUART_CR3_HDSEL ----------------------------------
// SVD Line: 4344
// - SFDITEM_FIELD__LPUART_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40008008) Half-duplex selection
//
// ( (unsigned int) LPUART_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: LPUART_CR3_DMAR ----------------------------------
// SVD Line: 4349
// - SFDITEM_FIELD__LPUART_CR3_DMAR
// DMAR
//
// [Bit 6] RW (@ 0x40008008) Enable DMA on reception
//
// ( (unsigned int) LPUART_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: LPUART_CR3_DMAT ----------------------------------
// SVD Line: 4354
// - SFDITEM_FIELD__LPUART_CR3_DMAT
// DMAT
//
// [Bit 7] RW (@ 0x40008008) Enable DMA while transmitting
//
// ( (unsigned int) LPUART_CR3 )
// DMAT
//
//
//
// ------------------------------- Field Item: LPUART_CR3_RTSE ----------------------------------
// SVD Line: 4359
// - SFDITEM_FIELD__LPUART_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40008008) RTS enabled
//
// ( (unsigned int) LPUART_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: LPUART_CR3_CTSE ----------------------------------
// SVD Line: 4364
// - SFDITEM_FIELD__LPUART_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40008008) CTS enabled
//
// ( (unsigned int) LPUART_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: LPUART_CR3_CTSIE ----------------------------------
// SVD Line: 4369
// - SFDITEM_FIELD__LPUART_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40008008) CTS interrupt enable
//
// ( (unsigned int) LPUART_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: LPUART_CR3_OVRDIS ---------------------------------
// SVD Line: 4374
// - SFDITEM_FIELD__LPUART_CR3_OVRDIS
// OVRDIS
//
// [Bit 12] RW (@ 0x40008008) Overrun is prohibited
//
// ( (unsigned int) LPUART_CR3 )
// OVRDIS
//
//
//
// ------------------------------- Field Item: LPUART_CR3_DDRE ----------------------------------
// SVD Line: 4379
// - SFDITEM_FIELD__LPUART_CR3_DDRE
// DDRE
//
// [Bit 13] RW (@ 0x40008008) Whether DMA is disabled when receiving an error
//
// ( (unsigned int) LPUART_CR3 )
// DDRE
//
//
//
// ------------------------------- Field Item: LPUART_CR3_DEM -----------------------------------
// SVD Line: 4384
// - SFDITEM_FIELD__LPUART_CR3_DEM
// DEM
//
// [Bit 14] RW (@ 0x40008008) DE mode enabled
//
// ( (unsigned int) LPUART_CR3 )
// DEM
//
//
//
// ------------------------------- Field Item: LPUART_CR3_DEP -----------------------------------
// SVD Line: 4389
// - SFDITEM_FIELD__LPUART_CR3_DEP
// DEP
//
// [Bit 15] RW (@ 0x40008008) DE polarity selection
//
// ( (unsigned int) LPUART_CR3 )
// DEP
//
//
//
// ------------------------------- Field Item: LPUART_CR3_WUS -----------------------------------
// SVD Line: 4394
// - SFDITEM_FIELD__LPUART_CR3_WUS
// WUS
//
// [Bits 21..20] RW (@ 0x40008008) Low-power wake-up options
//
// ( (unsigned char)((LPUART_CR3 >> 20) & 0x3), ((LPUART_CR3 = (LPUART_CR3 & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: LPUART_CR3_WUFIE ----------------------------------
// SVD Line: 4399
// - SFDITEM_FIELD__LPUART_CR3_WUFIE
// WUFIE
//
// [Bit 22] RW (@ 0x40008008) Low-power wake-up interrupt enable
//
// ( (unsigned int) LPUART_CR3 )
// WUFIE
//
//
//
// ------------------------------- Register RTree: LPUART_CR3 -----------------------------------
// SVD Line: 4335
// SFDITEM_REG__LPUART_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40008008) CR3
// ( (unsigned int)((LPUART_CR3 >> 0) & 0xFFFFFFFF), ((LPUART_CR3 = (LPUART_CR3 & ~(0x70F7C9UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70F7C9) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_CR3_EIE
// - SFDITEM_FIELD__LPUART_CR3_HDSEL
// - SFDITEM_FIELD__LPUART_CR3_DMAR
// - SFDITEM_FIELD__LPUART_CR3_DMAT
// - SFDITEM_FIELD__LPUART_CR3_RTSE
// - SFDITEM_FIELD__LPUART_CR3_CTSE
// - SFDITEM_FIELD__LPUART_CR3_CTSIE
// - SFDITEM_FIELD__LPUART_CR3_OVRDIS
// - SFDITEM_FIELD__LPUART_CR3_DDRE
// - SFDITEM_FIELD__LPUART_CR3_DEM
// - SFDITEM_FIELD__LPUART_CR3_DEP
// - SFDITEM_FIELD__LPUART_CR3_WUS
// - SFDITEM_FIELD__LPUART_CR3_WUFIE
//
//
// ---------------------------- Register Item Address: LPUART_BRR -------------------------------
// SVD Line: 4406
unsigned int LPUART_BRR __AT (0x4000800C);
// ------------------------------- Field Item: LPUART_BRR_BBR -----------------------------------
// SVD Line: 4410
// - SFDITEM_FIELD__LPUART_BRR_BBR
// BBR
//
// [Bits 19..0] RW (@ 0x4000800C) LPUART baud rate
//
// ( (unsigned int)((LPUART_BRR >> 0) & 0xFFFFF), ((LPUART_BRR = (LPUART_BRR & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPUART_BRR -----------------------------------
// SVD Line: 4406
// SFDITEM_REG__LPUART_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x4000800C) BRR
// ( (unsigned int)((LPUART_BRR >> 0) & 0xFFFFFFFF), ((LPUART_BRR = (LPUART_BRR & ~(0xFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_BRR_BBR
//
//
// ---------------------------- Register Item Address: LPUART_RQR -------------------------------
// SVD Line: 4417
unsigned int LPUART_RQR __AT (0x40008018);
// ------------------------------ Field Item: LPUART_RQR_SBKRQ ----------------------------------
// SVD Line: 4421
// - SFDITEM_FIELD__LPUART_RQR_SBKRQ
// SBKRQ
//
// [Bit 1] RW (@ 0x40008018) Send an abort request
//
// ( (unsigned int) LPUART_RQR )
// SBKRQ
//
//
//
// ------------------------------- Field Item: LPUART_RQR_MMRQ ----------------------------------
// SVD Line: 4426
// - SFDITEM_FIELD__LPUART_RQR_MMRQ
// MMRQ
//
// [Bit 2] RW (@ 0x40008018) Silent mode request
//
// ( (unsigned int) LPUART_RQR )
// MMRQ
//
//
//
// ------------------------------- Register RTree: LPUART_RQR -----------------------------------
// SVD Line: 4417
// SFDITEM_REG__LPUART_RQR
// RQR
//
// [Bits 31..0] RW (@ 0x40008018) RQR
// ( (unsigned int)((LPUART_RQR >> 0) & 0xFFFFFFFF), ((LPUART_RQR = (LPUART_RQR & ~(0x6UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x6) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_RQR_SBKRQ
// - SFDITEM_FIELD__LPUART_RQR_MMRQ
//
//
// ---------------------------- Register Item Address: LPUART_ISR -------------------------------
// SVD Line: 4433
unsigned int LPUART_ISR __AT (0x4000801C);
// -------------------------------- Field Item: LPUART_ISR_PE -----------------------------------
// SVD Line: 4437
// - SFDITEM_FIELD__LPUART_ISR_PE
// PE
//
// [Bit 0] RO (@ 0x4000801C) Parity error
//
// ( (unsigned int) LPUART_ISR )
// PE
//
//
//
// -------------------------------- Field Item: LPUART_ISR_FE -----------------------------------
// SVD Line: 4443
// - SFDITEM_FIELD__LPUART_ISR_FE
// FE
//
// [Bit 1] RO (@ 0x4000801C) Frame error flag
//
// ( (unsigned int) LPUART_ISR )
// FE
//
//
//
// -------------------------------- Field Item: LPUART_ISR_NE -----------------------------------
// SVD Line: 4449
// - SFDITEM_FIELD__LPUART_ISR_NE
// NE
//
// [Bit 2] RO (@ 0x4000801C) START bit noise flag
//
// ( (unsigned int) LPUART_ISR )
// NE
//
//
//
// ------------------------------- Field Item: LPUART_ISR_ORE -----------------------------------
// SVD Line: 4455
// - SFDITEM_FIELD__LPUART_ISR_ORE
// ORE
//
// [Bit 3] RO (@ 0x4000801C) Overrun error flag
//
// ( (unsigned int) LPUART_ISR )
// ORE
//
//
//
// ------------------------------- Field Item: LPUART_ISR_IDLE ----------------------------------
// SVD Line: 4461
// - SFDITEM_FIELD__LPUART_ISR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x4000801C) idle flag
//
// ( (unsigned int) LPUART_ISR )
// IDLE
//
//
//
// ------------------------------- Field Item: LPUART_ISR_RXNE ----------------------------------
// SVD Line: 4467
// - SFDITEM_FIELD__LPUART_ISR_RXNE
// RXNE
//
// [Bit 5] RO (@ 0x4000801C) RX register not empty
//
// ( (unsigned int) LPUART_ISR )
// RXNE
//
//
//
// -------------------------------- Field Item: LPUART_ISR_TC -----------------------------------
// SVD Line: 4473
// - SFDITEM_FIELD__LPUART_ISR_TC
// TC
//
// [Bit 6] RO (@ 0x4000801C) Transmission completion flag
//
// ( (unsigned int) LPUART_ISR )
// TC
//
//
//
// ------------------------------- Field Item: LPUART_ISR_TXE -----------------------------------
// SVD Line: 4479
// - SFDITEM_FIELD__LPUART_ISR_TXE
// TXE
//
// [Bit 7] RO (@ 0x4000801C) TX register empty
//
// ( (unsigned int) LPUART_ISR )
// TXE
//
//
//
// ------------------------------ Field Item: LPUART_ISR_CTSIF ----------------------------------
// SVD Line: 4485
// - SFDITEM_FIELD__LPUART_ISR_CTSIF
// CTSIF
//
// [Bit 9] RO (@ 0x4000801C) CTS interrupt flag
//
// ( (unsigned int) LPUART_ISR )
// CTSIF
//
//
//
// ------------------------------- Field Item: LPUART_ISR_CTS -----------------------------------
// SVD Line: 4491
// - SFDITEM_FIELD__LPUART_ISR_CTS
// CTS
//
// [Bit 10] RO (@ 0x4000801C) CTS flag
//
// ( (unsigned int) LPUART_ISR )
// CTS
//
//
//
// ------------------------------- Field Item: LPUART_ISR_BUSY ----------------------------------
// SVD Line: 4497
// - SFDITEM_FIELD__LPUART_ISR_BUSY
// BUSY
//
// [Bit 16] RO (@ 0x4000801C) Busy flag
//
// ( (unsigned int) LPUART_ISR )
// BUSY
//
//
//
// ------------------------------- Field Item: LPUART_ISR_CMF -----------------------------------
// SVD Line: 4503
// - SFDITEM_FIELD__LPUART_ISR_CMF
// CMF
//
// [Bit 17] RO (@ 0x4000801C) Address match flag
//
// ( (unsigned int) LPUART_ISR )
// CMF
//
//
//
// ------------------------------- Field Item: LPUART_ISR_SBKF ----------------------------------
// SVD Line: 4509
// - SFDITEM_FIELD__LPUART_ISR_SBKF
// SBKF
//
// [Bit 18] RO (@ 0x4000801C) Send abort flag
//
// ( (unsigned int) LPUART_ISR )
// SBKF
//
//
//
// ------------------------------- Field Item: LPUART_ISR_RWU -----------------------------------
// SVD Line: 4515
// - SFDITEM_FIELD__LPUART_ISR_RWU
// RWU
//
// [Bit 19] RO (@ 0x4000801C) Receive Mute mode wake-up flag
//
// ( (unsigned int) LPUART_ISR )
// RWU
//
//
//
// ------------------------------- Field Item: LPUART_ISR_WUF -----------------------------------
// SVD Line: 4521
// - SFDITEM_FIELD__LPUART_ISR_WUF
// WUF
//
// [Bit 20] RO (@ 0x4000801C) Wake flag from low-power mode
//
// ( (unsigned int) LPUART_ISR )
// WUF
//
//
//
// ------------------------------ Field Item: LPUART_ISR_TEACK ----------------------------------
// SVD Line: 4527
// - SFDITEM_FIELD__LPUART_ISR_TEACK
// TEACK
//
// [Bit 21] RO (@ 0x4000801C) Transport enable acknowledgement flag
//
// ( (unsigned int) LPUART_ISR )
// TEACK
//
//
//
// ------------------------------ Field Item: LPUART_ISR_REACK ----------------------------------
// SVD Line: 4533
// - SFDITEM_FIELD__LPUART_ISR_REACK
// REACK
//
// [Bit 22] RO (@ 0x4000801C) Receive the enable acknowledgment flag
//
// ( (unsigned int) LPUART_ISR )
// REACK
//
//
//
// ------------------------------- Register RTree: LPUART_ISR -----------------------------------
// SVD Line: 4433
// SFDITEM_REG__LPUART_ISR
// ISR
//
// [Bits 31..0] RW (@ 0x4000801C) ISR
// ( (unsigned int)((LPUART_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPUART_ISR_PE
// - SFDITEM_FIELD__LPUART_ISR_FE
// - SFDITEM_FIELD__LPUART_ISR_NE
// - SFDITEM_FIELD__LPUART_ISR_ORE
// - SFDITEM_FIELD__LPUART_ISR_IDLE
// - SFDITEM_FIELD__LPUART_ISR_RXNE
// - SFDITEM_FIELD__LPUART_ISR_TC
// - SFDITEM_FIELD__LPUART_ISR_TXE
// - SFDITEM_FIELD__LPUART_ISR_CTSIF
// - SFDITEM_FIELD__LPUART_ISR_CTS
// - SFDITEM_FIELD__LPUART_ISR_BUSY
// - SFDITEM_FIELD__LPUART_ISR_CMF
// - SFDITEM_FIELD__LPUART_ISR_SBKF
// - SFDITEM_FIELD__LPUART_ISR_RWU
// - SFDITEM_FIELD__LPUART_ISR_WUF
// - SFDITEM_FIELD__LPUART_ISR_TEACK
// - SFDITEM_FIELD__LPUART_ISR_REACK
//
//
// ---------------------------- Register Item Address: LPUART_ICR -------------------------------
// SVD Line: 4541
unsigned int LPUART_ICR __AT (0x40008020);
// ------------------------------- Field Item: LPUART_ICR_PECF ----------------------------------
// SVD Line: 4545
// - SFDITEM_FIELD__LPUART_ICR_PECF
// PECF
//
// [Bit 0] RW (@ 0x40008020) Check value error flag reset
//
// ( (unsigned int) LPUART_ICR )
// PECF
//
//
//
// ------------------------------- Field Item: LPUART_ICR_FECF ----------------------------------
// SVD Line: 4550
// - SFDITEM_FIELD__LPUART_ICR_FECF
// FECF
//
// [Bit 1] RW (@ 0x40008020) Frame error flag reset
//
// ( (unsigned int) LPUART_ICR )
// FECF
//
//
//
// ------------------------------- Field Item: LPUART_ICR_NECF ----------------------------------
// SVD Line: 4555
// - SFDITEM_FIELD__LPUART_ICR_NECF
// NECF
//
// [Bit 2] RW (@ 0x40008020) Clear the START bit noise flag
//
// ( (unsigned int) LPUART_ICR )
// NECF
//
//
//
// ------------------------------ Field Item: LPUART_ICR_ORECF ----------------------------------
// SVD Line: 4560
// - SFDITEM_FIELD__LPUART_ICR_ORECF
// ORECF
//
// [Bit 3] RW (@ 0x40008020) Overrun error flag reset
//
// ( (unsigned int) LPUART_ICR )
// ORECF
//
//
//
// ------------------------------ Field Item: LPUART_ICR_IDLECF ---------------------------------
// SVD Line: 4565
// - SFDITEM_FIELD__LPUART_ICR_IDLECF
// IDLECF
//
// [Bit 4] RW (@ 0x40008020) Clear idle flag
//
// ( (unsigned int) LPUART_ICR )
// IDLECF
//
//
//
// ------------------------------- Field Item: LPUART_ICR_TCCF ----------------------------------
// SVD Line: 4570
// - SFDITEM_FIELD__LPUART_ICR_TCCF
// TCCF
//
// [Bit 6] RW (@ 0x40008020) Transfer completion flag reset
//
// ( (unsigned int) LPUART_ICR )
// TCCF
//
//
//
// ------------------------------ Field Item: LPUART_ICR_CTSCF ----------------------------------
// SVD Line: 4575
// - SFDITEM_FIELD__LPUART_ICR_CTSCF
// CTSCF
//
// [Bit 9] RW (@ 0x40008020) CTS flag reset
//
// ( (unsigned int) LPUART_ICR )
// CTSCF
//
//
//
// ------------------------------- Field Item: LPUART_ICR_CMCF ----------------------------------
// SVD Line: 4580
// - SFDITEM_FIELD__LPUART_ICR_CMCF
// CMCF
//
// [Bit 17] RW (@ 0x40008020) Address matching flag reset
//
// ( (unsigned int) LPUART_ICR )
// CMCF
//
//
//
// ------------------------------- Field Item: LPUART_ICR_WUCF ----------------------------------
// SVD Line: 4585
// - SFDITEM_FIELD__LPUART_ICR_WUCF
// WUCF
//
// [Bit 20] RW (@ 0x40008020) Low power wake-up flag reset
//
// ( (unsigned int) LPUART_ICR )
// WUCF
//
//
//
// ------------------------------- Register RTree: LPUART_ICR -----------------------------------
// SVD Line: 4541
// SFDITEM_REG__LPUART_ICR
// ICR
//
// [Bits 31..0] RW (@ 0x40008020) ICR
// ( (unsigned int)((LPUART_ICR >> 0) & 0xFFFFFFFF), ((LPUART_ICR = (LPUART_ICR & ~(0x12025FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12025F) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_ICR_PECF
// - SFDITEM_FIELD__LPUART_ICR_FECF
// - SFDITEM_FIELD__LPUART_ICR_NECF
// - SFDITEM_FIELD__LPUART_ICR_ORECF
// - SFDITEM_FIELD__LPUART_ICR_IDLECF
// - SFDITEM_FIELD__LPUART_ICR_TCCF
// - SFDITEM_FIELD__LPUART_ICR_CTSCF
// - SFDITEM_FIELD__LPUART_ICR_CMCF
// - SFDITEM_FIELD__LPUART_ICR_WUCF
//
//
// ---------------------------- Register Item Address: LPUART_RDR -------------------------------
// SVD Line: 4592
unsigned int LPUART_RDR __AT (0x40008024);
// ------------------------------- Field Item: LPUART_RDR_RDR -----------------------------------
// SVD Line: 4596
// - SFDITEM_FIELD__LPUART_RDR_RDR
// RDR
//
// [Bits 8..0] RO (@ 0x40008024) Receive Data Register
//
// ( (unsigned short)((LPUART_RDR >> 0) & 0x1FF) )
//
//
//
// ------------------------------- Register RTree: LPUART_RDR -----------------------------------
// SVD Line: 4592
// SFDITEM_REG__LPUART_RDR
// RDR
//
// [Bits 31..0] RW (@ 0x40008024) RDR
// ( (unsigned int)((LPUART_RDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPUART_RDR_RDR
//
//
// ---------------------------- Register Item Address: LPUART_TDR -------------------------------
// SVD Line: 4604
unsigned int LPUART_TDR __AT (0x40008028);
// ------------------------------- Field Item: LPUART_TDR_TDR -----------------------------------
// SVD Line: 4608
// - SFDITEM_FIELD__LPUART_TDR_TDR
// TDR
//
// [Bits 8..0] RW (@ 0x40008028) Transmit Data Register
//
// ( (unsigned short)((LPUART_TDR >> 0) & 0x1FF), ((LPUART_TDR = (LPUART_TDR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPUART_TDR -----------------------------------
// SVD Line: 4604
// SFDITEM_REG__LPUART_TDR
// TDR
//
// [Bits 31..0] RW (@ 0x40008028) TDR
// ( (unsigned int)((LPUART_TDR >> 0) & 0xFFFFFFFF), ((LPUART_TDR = (LPUART_TDR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_TDR_TDR
//
//
// --------------------------- Register Item Address: LPUART_PRESC ------------------------------
// SVD Line: 4615
unsigned int LPUART_PRESC __AT (0x4000802C);
// --------------------------- Field Item: LPUART_PRESC_PRESCALER -------------------------------
// SVD Line: 4619
// - SFDITEM_FIELD__LPUART_PRESC_PRESCALER
// PRESCALER
//
// [Bits 3..0] RW (@ 0x4000802C) Input clock prescaler register
//
// ( (unsigned char)((LPUART_PRESC >> 0) & 0xF), ((LPUART_PRESC = (LPUART_PRESC & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: LPUART_PRESC ----------------------------------
// SVD Line: 4615
// SFDITEM_REG__LPUART_PRESC
// PRESC
//
// [Bits 31..0] RW (@ 0x4000802C) PRESC
// ( (unsigned int)((LPUART_PRESC >> 0) & 0xFFFFFFFF), ((LPUART_PRESC = (LPUART_PRESC & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_PRESC_PRESCALER
//
//
// -------------------------- Register Item Address: LPUART_SAMPMOD -----------------------------
// SVD Line: 4626
unsigned int LPUART_SAMPMOD __AT (0x40008034);
// --------------------------- Field Item: LPUART_SAMPMOD_SAMPMOD -------------------------------
// SVD Line: 4630
// - SFDITEM_FIELD__LPUART_SAMPMOD_SAMPMOD
// SAMPMOD
//
// [Bit 0] RW (@ 0x40008034) Tolerance sampling mode register
//
// ( (unsigned int) LPUART_SAMPMOD )
// SAMPMOD
//
//
//
// ----------------------------- Register RTree: LPUART_SAMPMOD ---------------------------------
// SVD Line: 4626
// SFDITEM_REG__LPUART_SAMPMOD
// SAMPMOD
//
// [Bits 31..0] RW (@ 0x40008034) SAMPMOD
// ( (unsigned int)((LPUART_SAMPMOD >> 0) & 0xFFFFFFFF), ((LPUART_SAMPMOD = (LPUART_SAMPMOD & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__LPUART_SAMPMOD_SAMPMOD
//
//
// --------------------------------- Peripheral View: LPUART ------------------------------------
// SVD Line: 4175
// LPUART
// LPUART
// - SFDITEM_REG__LPUART_CR1
// - SFDITEM_REG__LPUART_CR2
// - SFDITEM_REG__LPUART_CR3
// - SFDITEM_REG__LPUART_BRR
// - SFDITEM_REG__LPUART_RQR
// - SFDITEM_REG__LPUART_ISR
// - SFDITEM_REG__LPUART_ICR
// - SFDITEM_REG__LPUART_RDR
// - SFDITEM_REG__LPUART_TDR
// - SFDITEM_REG__LPUART_PRESC
// - SFDITEM_REG__LPUART_SAMPMOD
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 4649
unsigned int PWR_CR1 __AT (0x40007000);
// -------------------------------- Field Item: PWR_CR1_LPMS ------------------------------------
// SVD Line: 4654
// - SFDITEM_FIELD__PWR_CR1_LPMS
// LPMS
//
// [Bits 2..0] RW (@ 0x40007000) LPMS
//
// ( (unsigned char)((PWR_CR1 >> 0) & 0x7), ((PWR_CR1 = (PWR_CR1 & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Field Item: PWR_CR1_DBP ------------------------------------
// SVD Line: 4658
// - SFDITEM_FIELD__PWR_CR1_DBP
// DBP
//
// [Bit 8] RW (@ 0x40007000) DBP
//
// ( (unsigned int) PWR_CR1 )
// DBP
//
//
//
// ------------------------------- Field Item: PWR_CR1_VR_MODE ----------------------------------
// SVD Line: 4662
// - SFDITEM_FIELD__PWR_CR1_VR_MODE
// VR_MODE
//
// [Bits 10..9] RW (@ 0x40007000) VR_MODE
//
// ( (unsigned char)((PWR_CR1 >> 9) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 4666
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) FLS_SLPTIME
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: PWR_CR1_MR_VSEL ----------------------------------
// SVD Line: 4670
// - SFDITEM_FIELD__PWR_CR1_MR_VSEL
// MR_VSEL
//
// [Bits 17..16] RW (@ 0x40007000) MR_VSEL
//
// ( (unsigned char)((PWR_CR1 >> 16) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: PWR_CR1_LPR_VSEL ----------------------------------
// SVD Line: 4674
// - SFDITEM_FIELD__PWR_CR1_LPR_VSEL
// LPR_VSEL
//
// [Bits 19..18] RW (@ 0x40007000) LPR_VSEL
//
// ( (unsigned char)((PWR_CR1 >> 18) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ------------------------------ Field Item: PWR_CR1_DLPR_VSEL ---------------------------------
// SVD Line: 4678
// - SFDITEM_FIELD__PWR_CR1_DLPR_VSEL
// DLPR_VSEL
//
// [Bits 21..20] RW (@ 0x40007000) DLPR_VSEL
//
// ( (unsigned char)((PWR_CR1 >> 20) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLSSLP_CTRL --------------------------------
// SVD Line: 4682
// - SFDITEM_FIELD__PWR_CR1_FLSSLP_CTRL
// FLSSLP_CTRL
//
// [Bit 24] RW (@ 0x40007000) FLSSLP_CTRL
//
// ( (unsigned int) PWR_CR1 )
// FLSSLP_CTRL
//
//
//
// ----------------------------- Field Item: PWR_CR1_HSION_CTRL ---------------------------------
// SVD Line: 4686
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
// HSION_CTRL
//
// [Bit 25] RW (@ 0x40007000) HSION_CTRL
//
// ( (unsigned int) PWR_CR1 )
// HSION_CTRL
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 4649
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0x33F3707UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33F3707) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_LPMS
// - SFDITEM_FIELD__PWR_CR1_DBP
// - SFDITEM_FIELD__PWR_CR1_VR_MODE
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_MR_VSEL
// - SFDITEM_FIELD__PWR_CR1_LPR_VSEL
// - SFDITEM_FIELD__PWR_CR1_DLPR_VSEL
// - SFDITEM_FIELD__PWR_CR1_FLSSLP_CTRL
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
//
//
// ----------------------------- Register Item Address: PWR_CR2 ---------------------------------
// SVD Line: 4692
unsigned int PWR_CR2 __AT (0x40007004);
// -------------------------------- Field Item: PWR_CR2_PVDE ------------------------------------
// SVD Line: 4697
// - SFDITEM_FIELD__PWR_CR2_PVDE
// PVDE
//
// [Bit 0] RW (@ 0x40007004) PVDE
//
// ( (unsigned int) PWR_CR2 )
// PVDE
//
//
//
// -------------------------------- Field Item: PWR_CR2_PVDT ------------------------------------
// SVD Line: 4701
// - SFDITEM_FIELD__PWR_CR2_PVDT
// PVDT
//
// [Bits 6..4] RW (@ 0x40007004) PVDT
//
// ( (unsigned char)((PWR_CR2 >> 4) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR2_PVD_OUT_SEL --------------------------------
// SVD Line: 4705
// - SFDITEM_FIELD__PWR_CR2_PVD_OUT_SEL
// PVD_OUT_SEL
//
// [Bit 7] RW (@ 0x40007004) PVD_OUT_SEL
//
// ( (unsigned int) PWR_CR2 )
// PVD_OUT_SEL
//
//
//
// -------------------------------- Field Item: PWR_CR2_FLTEN -----------------------------------
// SVD Line: 4709
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// FLTEN
//
// [Bit 8] RW (@ 0x40007004) FLTEN
//
// ( (unsigned int) PWR_CR2 )
// FLTEN
//
//
//
// ------------------------------ Field Item: PWR_CR2_FLT_TIME ----------------------------------
// SVD Line: 4713
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
// FLT_TIME
//
// [Bits 11..9] RW (@ 0x40007004) FLT_TIME
//
// ( (unsigned char)((PWR_CR2 >> 9) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWR_CR2 ------------------------------------
// SVD Line: 4692
// SFDITEM_REG__PWR_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40007004) Power control register 2
// ( (unsigned int)((PWR_CR2 >> 0) & 0xFFFFFFFF), ((PWR_CR2 = (PWR_CR2 & ~(0xFF1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR2_PVDE
// - SFDITEM_FIELD__PWR_CR2_PVDT
// - SFDITEM_FIELD__PWR_CR2_PVD_OUT_SEL
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
//
//
// ------------------------------ Register Item Address: PWR_SR ---------------------------------
// SVD Line: 4719
unsigned int PWR_SR __AT (0x40007010);
// -------------------------------- Field Item: PWR_SR_MR_RDY -----------------------------------
// SVD Line: 4724
// - SFDITEM_FIELD__PWR_SR_MR_RDY
// MR_RDY
//
// [Bit 9] RO (@ 0x40007010) MR_RDY
//
// ( (unsigned int) PWR_SR )
// MR_RDY
//
//
//
// ---------------------------- Field Item: PWR_SR_LPRUN_RUN_SWF --------------------------------
// SVD Line: 4729
// - SFDITEM_FIELD__PWR_SR_LPRUN_RUN_SWF
// LPRUN_RUN_SWF
//
// [Bit 11] RO (@ 0x40007010) LPRUN_RUN_SWF
//
// ( (unsigned int) PWR_SR )
// LPRUN_RUN_SWF
//
//
//
// --------------------------------- Field Item: PWR_SR_PVDO ------------------------------------
// SVD Line: 4734
// - SFDITEM_FIELD__PWR_SR_PVDO
// PVDO
//
// [Bit 16] RO (@ 0x40007010) PVDO
//
// ( (unsigned int) PWR_SR )
// PVDO
//
//
//
// --------------------------------- Register RTree: PWR_SR -------------------------------------
// SVD Line: 4719
// SFDITEM_REG__PWR_SR
// SR
//
// [Bits 31..0] RW (@ 0x40007010) Power status register
// ( (unsigned int)((PWR_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__PWR_SR_MR_RDY
// - SFDITEM_FIELD__PWR_SR_LPRUN_RUN_SWF
// - SFDITEM_FIELD__PWR_SR_PVDO
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 4639
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
// - SFDITEM_REG__PWR_CR2
// - SFDITEM_REG__PWR_SR
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 4758
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 4763
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI clock enable bit
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 4768
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RO (@ 0x40021000) HSI clock ready logo
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 4774
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI generates the crossover factor when HSISYS clocks
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEON ------------------------------------
// SVD Line: 4779
// - SFDITEM_FIELD__RCC_CR_HSEON
// HSEON
//
// [Bit 16] RW (@ 0x40021000) HSE crystal oscillator enabled
//
// ( (unsigned int) RCC_CR )
// HSEON
//
//
//
// -------------------------------- Field Item: RCC_CR_HSERDY -----------------------------------
// SVD Line: 4784
// - SFDITEM_FIELD__RCC_CR_HSERDY
// HSERDY
//
// [Bit 17] RO (@ 0x40021000) HSE crystal clock ready logo
//
// ( (unsigned int) RCC_CR )
// HSERDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSEBYP -----------------------------------
// SVD Line: 4790
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// HSEBYP
//
// [Bit 18] RW (@ 0x40021000) HSE shields the crystal oscillator and selects the pin input clock
//
// ( (unsigned int) RCC_CR )
// HSEBYP
//
//
//
// ------------------------------ Field Item: RCC_CR_HSE_CSSON ----------------------------------
// SVD Line: 4795
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
// HSE_CSSON
//
// [Bit 19] RW (@ 0x40021000) HSE clock security system enabled
//
// ( (unsigned int) RCC_CR )
// HSE_CSSON
//
//
//
// -------------------------------- Field Item: RCC_CR_PLLON ------------------------------------
// SVD Line: 4800
// - SFDITEM_FIELD__RCC_CR_PLLON
// PLLON
//
// [Bit 24] RW (@ 0x40021000) PLL clock enable
//
// ( (unsigned int) RCC_CR )
// PLLON
//
//
//
// -------------------------------- Field Item: RCC_CR_PLLRDY -----------------------------------
// SVD Line: 4805
// - SFDITEM_FIELD__RCC_CR_PLLRDY
// PLLRDY
//
// [Bit 25] RO (@ 0x40021000) PLL clock ready
//
// ( (unsigned int) RCC_CR )
// PLLRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_PLLDIV -----------------------------------
// SVD Line: 4811
// - SFDITEM_FIELD__RCC_CR_PLLDIV
// PLLDIV
//
// [Bit 26] RW (@ 0x40021000) PLL div
//
// ( (unsigned int) RCC_CR )
// PLLDIV
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 4758
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0x50D3900UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x50D3900) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// - SFDITEM_FIELD__RCC_CR_HSEON
// - SFDITEM_FIELD__RCC_CR_HSERDY
// - SFDITEM_FIELD__RCC_CR_HSEBYP
// - SFDITEM_FIELD__RCC_CR_HSE_CSSON
// - SFDITEM_FIELD__RCC_CR_PLLON
// - SFDITEM_FIELD__RCC_CR_PLLRDY
// - SFDITEM_FIELD__RCC_CR_PLLDIV
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 4818
unsigned int RCC_ICSCR __AT (0x40021004);
// --------------------------- Field Item: RCC_ICSCR_HSI_ABS_TRIM -------------------------------
// SVD Line: 4823
// - SFDITEM_FIELD__RCC_ICSCR_HSI_ABS_TRIM
// HSI_ABS_TRIM
//
// [Bits 11..0] RW (@ 0x40021004) Clock frequency abs calibration value
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0xFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ICSCR_HSI_TC_TRIM -------------------------------
// SVD Line: 4828
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TC_TRIM
// HSI_TC_TRIM
//
// [Bits 15..12] RW (@ 0x40021004) Clock frequency tc calibration value
//
// ( (unsigned char)((RCC_ICSCR >> 12) & 0xF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 4833
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bits 18..16] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 16) & 0x7), ((RCC_ICSCR = (RCC_ICSCR & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 4838
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 27..19] RW (@ 0x40021004) Internal low-speed clock frequency calibration
//
// ( (unsigned short)((RCC_ICSCR >> 19) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 19 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 19 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 4818
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibrationregister
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_ABS_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TC_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 4845
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 4850
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 4855
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RW (@ 0x40021008) System clock source selection
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 4860
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) The AHB clock HCLK is based on the crossover coefficient of SYSCLK
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 4865
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB clock division factor
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 4870
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 27..24] RW (@ 0x40021008) MCO output clock selection
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 4875
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 31..28] RW (@ 0x40021008) Microprocessor output clock (MCO) divider factor
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 4845
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0xFF007F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF007F3F) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// --------------------------- Register Item Address: RCC_PLLCFGR -------------------------------
// SVD Line: 4882
unsigned int RCC_PLLCFGR __AT (0x4002100C);
// ----------------------------- Field Item: RCC_PLLCFGR_PLLSRC ---------------------------------
// SVD Line: 4887
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLSRC
// PLLSRC
//
// [Bit 0] RW (@ 0x4002100C) PLLSRC
//
// ( (unsigned int) RCC_PLLCFGR )
// PLLSRC
//
//
//
// ----------------------------- Field Item: RCC_PLLCFGR_PLLMUL ---------------------------------
// SVD Line: 4891
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLMUL
// PLLMUL
//
// [Bits 6..2] RW (@ 0x4002100C) PLLMUL
//
// ( (unsigned char)((RCC_PLLCFGR >> 2) & 0x1F), ((RCC_PLLCFGR = (RCC_PLLCFGR & ~(0x1FUL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 2 ) ) ))
//
//
//
// ------------------------------- Register RTree: RCC_PLLCFGR ----------------------------------
// SVD Line: 4882
// SFDITEM_REG__RCC_PLLCFGR
// PLLCFGR
//
// [Bits 31..0] RW (@ 0x4002100C) PLL configuration register
// ( (unsigned int)((RCC_PLLCFGR >> 0) & 0xFFFFFFFF), ((RCC_PLLCFGR = (RCC_PLLCFGR & ~(0x7DUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7D) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLSRC
// - SFDITEM_FIELD__RCC_PLLCFGR_PLLMUL
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 4897
unsigned int RCC_ECSCR __AT (0x40021010);
// ------------------------------ Field Item: RCC_ECSCR_HSE_DRV ---------------------------------
// SVD Line: 4902
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRV
// HSE_DRV
//
// [Bits 1..0] RW (@ 0x40021010) HSE drive capability setting
//
// ( (unsigned char)((RCC_ECSCR >> 0) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_HSE_RDYSEL --------------------------------
// SVD Line: 4907
// - SFDITEM_FIELD__RCC_ECSCR_HSE_RDYSEL
// HSE_RDYSEL
//
// [Bits 3..2] RW (@ 0x40021010) HSE stabilization time selection
//
// ( (unsigned char)((RCC_ECSCR >> 2) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_HSE_FILT_EN -------------------------------
// SVD Line: 4912
// - SFDITEM_FIELD__RCC_ECSCR_HSE_FILT_EN
// HSE_FILT_EN
//
// [Bit 4] RW (@ 0x40021010) HSE_FILT_EN
//
// ( (unsigned int) RCC_ECSCR )
// HSE_FILT_EN
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_DRIVER --------------------------------
// SVD Line: 4916
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// LSE_DRIVER
//
// [Bits 17..16] RW (@ 0x40021010) LSE drive capability setting
//
// ( (unsigned char)((RCC_ECSCR >> 16) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ECSCR_LSE_STARTUP -------------------------------
// SVD Line: 4921
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
// LSE_STARTUP
//
// [Bits 21..20] RW (@ 0x40021010) LSE crystal oscillator stabilization time selection
//
// ( (unsigned char)((RCC_ECSCR >> 20) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 4897
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x33001FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33001F) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_HSE_DRV
// - SFDITEM_FIELD__RCC_ECSCR_HSE_RDYSEL
// - SFDITEM_FIELD__RCC_ECSCR_HSE_FILT_EN
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// - SFDITEM_FIELD__RCC_ECSCR_LSE_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 4928
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 4933
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_LSERDYIE ---------------------------------
// SVD Line: 4938
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// LSERDYIE
//
// [Bit 1] RW (@ 0x40021018) LSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// LSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 4943
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSERDYIE ---------------------------------
// SVD Line: 4948
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
// HSERDYIE
//
// [Bit 4] RW (@ 0x40021018) HSE clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// HSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_PLLRDYIE ---------------------------------
// SVD Line: 4953
// - SFDITEM_FIELD__RCC_CIER_PLLRDYIE
// PLLRDYIE
//
// [Bit 5] RW (@ 0x40021018) PLL clock ready interrupt enabled
//
// ( (unsigned int) RCC_CIER )
// PLLRDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 4928
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enableregister
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0x3BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_HSERDYIE
// - SFDITEM_FIELD__RCC_CIER_PLLRDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 4960
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 4965
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSERDYF ----------------------------------
// SVD Line: 4971
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// LSERDYF
//
// [Bit 1] RO (@ 0x4002101C) LSE clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 4977
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSERDYF ----------------------------------
// SVD Line: 4983
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// HSERDYF
//
// [Bit 4] RO (@ 0x4002101C) HSE clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_PLLRDYF ----------------------------------
// SVD Line: 4989
// - SFDITEM_FIELD__RCC_CIFR_PLLRDYF
// PLLRDYF
//
// [Bit 5] RO (@ 0x4002101C) PLL clock ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// PLLRDYF
//
//
//
// -------------------------------- Field Item: RCC_CIFR_CSSF -----------------------------------
// SVD Line: 4995
// - SFDITEM_FIELD__RCC_CIFR_CSSF
// CSSF
//
// [Bit 8] RO (@ 0x4002101C) HSE Clock Security System (CSS) interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// CSSF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSECSSF ----------------------------------
// SVD Line: 5001
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
// LSECSSF
//
// [Bit 9] RO (@ 0x4002101C) LSE Clock Security System (CSS) interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSECSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 4960
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RW (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_HSERDYF
// - SFDITEM_FIELD__RCC_CIFR_PLLRDYF
// - SFDITEM_FIELD__RCC_CIFR_CSSF
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 5009
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 5014
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] RW (@ 0x40021020) The LSI ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSERDYC ----------------------------------
// SVD Line: 5019
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// LSERDYC
//
// [Bit 1] RW (@ 0x40021020) The LSE ready interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 5024
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] RW (@ 0x40021020) The HSI ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSERDYC ----------------------------------
// SVD Line: 5029
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// HSERDYC
//
// [Bit 4] RW (@ 0x40021020) The HSE ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// HSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_PLLRDYC ----------------------------------
// SVD Line: 5034
// - SFDITEM_FIELD__RCC_CICR_PLLRDYC
// PLLRDYC
//
// [Bit 5] RW (@ 0x40021020) The PLL ready interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// PLLRDYC
//
//
//
// -------------------------------- Field Item: RCC_CICR_CSSC -----------------------------------
// SVD Line: 5039
// - SFDITEM_FIELD__RCC_CICR_CSSC
// CSSC
//
// [Bit 8] RW (@ 0x40021020) The HSE Clock Security System (CSS) interrupt flag is cleared to zero
//
// ( (unsigned int) RCC_CICR )
// CSSC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSECSSC ----------------------------------
// SVD Line: 5044
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
// LSECSSC
//
// [Bit 9] RW (@ 0x40021020) The LSE Clock Security System (CSS) interrupt flag is cleared
//
// ( (unsigned int) RCC_CICR )
// LSECSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 5009
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] RW (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x33BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_HSERDYC
// - SFDITEM_FIELD__RCC_CICR_PLLRDYC
// - SFDITEM_FIELD__RCC_CICR_CSSC
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 5051
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 5056
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O PortA reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 5061
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O PortB reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOFRST --------------------------------
// SVD Line: 5066
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
// GPIOFRST
//
// [Bit 5] RW (@ 0x40021024) I/O PortF reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOFRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 5051
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOFRST
//
//
// --------------------------- Register Item Address: RCC_AHBRSTR -------------------------------
// SVD Line: 5073
unsigned int RCC_AHBRSTR __AT (0x40021028);
// ----------------------------- Field Item: RCC_AHBRSTR_DMARST ---------------------------------
// SVD Line: 5078
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// DMARST
//
// [Bit 0] RW (@ 0x40021028) DMARST
//
// ( (unsigned int) RCC_AHBRSTR )
// DMARST
//
//
//
// ----------------------------- Field Item: RCC_AHBRSTR_CRCRST ---------------------------------
// SVD Line: 5082
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// CRCRST
//
// [Bit 12] RW (@ 0x40021028) The CRC module is reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CRCRST
//
//
//
// ------------------------------- Register RTree: RCC_AHBRSTR ----------------------------------
// SVD Line: 5073
// SFDITEM_REG__RCC_AHBRSTR
// AHBRSTR
//
// [Bits 31..0] RW (@ 0x40021028) AHB peripheral reset register
// ( (unsigned int)((RCC_AHBRSTR >> 0) & 0xFFFFFFFF), ((RCC_AHBRSTR = (RCC_AHBRSTR & ~(0x1001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1001) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 5089
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// ---------------------------- Field Item: RCC_APBRSTR1_TIM3RST --------------------------------
// SVD Line: 5093
// - SFDITEM_FIELD__RCC_APBRSTR1_TIM3RST
// TIM3RST
//
// [Bit 1] RW (@ 0x4002102C) The Timer3 module APB is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// TIM3RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR1_RTCAPBRST -------------------------------
// SVD Line: 5098
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// RTCAPBRST
//
// [Bit 10] RW (@ 0x4002102C) The RTC module APB is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// RTCAPBRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_WWDGRST --------------------------------
// SVD Line: 5103
// - SFDITEM_FIELD__RCC_APBRSTR1_WWDGRST
// WWDGRST
//
// [Bit 11] RW (@ 0x4002102C) The WWDG module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// WWDGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_SPI2RST --------------------------------
// SVD Line: 5108
// - SFDITEM_FIELD__RCC_APBRSTR1_SPI2RST
// SPI2RST
//
// [Bit 14] RW (@ 0x4002102C) SPI2RST
//
// ( (unsigned int) RCC_APBRSTR1 )
// SPI2RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_UART1RST -------------------------------
// SVD Line: 5112
// - SFDITEM_FIELD__RCC_APBRSTR1_UART1RST
// UART1RST
//
// [Bit 18] RW (@ 0x4002102C) The UART2 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// UART1RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR1_LPUART1RST ------------------------------
// SVD Line: 5117
// - SFDITEM_FIELD__RCC_APBRSTR1_LPUART1RST
// LPUART1RST
//
// [Bit 20] RW (@ 0x4002102C) The LPUART1 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPUART1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_I2C1RST --------------------------------
// SVD Line: 5122
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// I2C1RST
//
// [Bit 21] RW (@ 0x4002102C) The I2C1 module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// I2C1RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 5127
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) The MCU Debug module is reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 5132
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) The Power interface module is reset.
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR1_LPTIM1RST -------------------------------
// SVD Line: 5137
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIM1RST
// LPTIM1RST
//
// [Bit 31] RW (@ 0x4002102C) LPTIM1RST
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPTIM1RST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 5089
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APBRSTR1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0x98344C02UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98344C02) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_TIM3RST
// - SFDITEM_FIELD__RCC_APBRSTR1_RTCAPBRST
// - SFDITEM_FIELD__RCC_APBRSTR1_WWDGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_SPI2RST
// - SFDITEM_FIELD__RCC_APBRSTR1_UART1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPUART1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_I2C1RST
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIM1RST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 5143
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 5148
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) The SYSCFG module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 5153
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) The TIM1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_SPI1RST --------------------------------
// SVD Line: 5158
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// SPI1RST
//
// [Bit 12] RW (@ 0x40021030) The SPI1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SPI1RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR2_USART1RST -------------------------------
// SVD Line: 5163
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// USART1RST
//
// [Bit 14] RW (@ 0x40021030) USART1RST
//
// ( (unsigned int) RCC_APBRSTR2 )
// USART1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 5167
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) The TIM14 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM16RST -------------------------------
// SVD Line: 5172
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM16RST
// TIM16RST
//
// [Bit 17] RW (@ 0x40021030) The TIM16 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM16RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM17RST -------------------------------
// SVD Line: 5177
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM17RST
// TIM17RST
//
// [Bit 18] RW (@ 0x40021030) The TIM17 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM17RST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR2_ADCRST --------------------------------
// SVD Line: 5182
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// ADCRST
//
// [Bit 20] RW (@ 0x40021030) The ADC block is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// ADCRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP1RST -------------------------------
// SVD Line: 5187
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// COMP1RST
//
// [Bit 21] RW (@ 0x40021030) The COMP1 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_COMP2RST -------------------------------
// SVD Line: 5192
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// COMP2RST
//
// [Bit 22] RW (@ 0x40021030) The COMP2 module is reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// COMP2RST
//
//
//
// --------------------------- Field Item: RCC_APBRSTR2_VREFBUFRST ------------------------------
// SVD Line: 5197
// - SFDITEM_FIELD__RCC_APBRSTR2_VREFBUFRST
// VREFBUFRST
//
// [Bit 26] RW (@ 0x40021030) VREFBUFRST
//
// ( (unsigned int) RCC_APBRSTR2 )
// VREFBUFRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 5143
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x476D801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x476D801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_SPI1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_USART1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM16RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM17RST
// - SFDITEM_FIELD__RCC_APBRSTR2_ADCRST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_COMP2RST
// - SFDITEM_FIELD__RCC_APBRSTR2_VREFBUFRST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 5203
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 5208
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O PortA clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 5213
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O PortB clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOFEN ---------------------------------
// SVD Line: 5218
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
// GPIOFEN
//
// [Bit 5] RW (@ 0x40021034) I/O PortF clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOFEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 5203
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x23UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x23) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOFEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 5225
unsigned int RCC_AHBENR __AT (0x40021038);
// ------------------------------ Field Item: RCC_AHBENR_DMAEN ----------------------------------
// SVD Line: 5230
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// DMAEN
//
// [Bit 0] RW (@ 0x40021038) DMA module clock enabled
//
// ( (unsigned int) RCC_AHBENR )
// DMAEN
//
//
//
// ----------------------------- Field Item: RCC_AHBENR_FLASHEN ---------------------------------
// SVD Line: 5235
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// FLASHEN
//
// [Bit 8] RW (@ 0x40021038) FLASHEN
//
// ( (unsigned int) RCC_AHBENR )
// FLASHEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_SRAMEN ---------------------------------
// SVD Line: 5239
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// SRAMEN
//
// [Bit 9] RW (@ 0x40021038) SRAMEN
//
// ( (unsigned int) RCC_AHBENR )
// SRAMEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_CRCEN ----------------------------------
// SVD Line: 5243
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// CRCEN
//
// [Bit 12] RW (@ 0x40021038) CRC module clock enabled
//
// ( (unsigned int) RCC_AHBENR )
// CRCEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 5225
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enableregister
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x1301UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1301) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 5250
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ----------------------------- Field Item: RCC_APBENR1_TIM3EN ---------------------------------
// SVD Line: 5255
// - SFDITEM_FIELD__RCC_APBENR1_TIM3EN
// TIM3EN
//
// [Bit 1] RW (@ 0x4002103C) TIM3EN
//
// ( (unsigned int) RCC_APBENR1 )
// TIM3EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR1_RTCAPBEN --------------------------------
// SVD Line: 5259
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// RTCAPBEN
//
// [Bit 10] RW (@ 0x4002103C) The RTC module APB clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// RTCAPBEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_WWDGEN ---------------------------------
// SVD Line: 5264
// - SFDITEM_FIELD__RCC_APBENR1_WWDGEN
// WWDGEN
//
// [Bit 11] RW (@ 0x4002103C) WWDGEN
//
// ( (unsigned int) RCC_APBENR1 )
// WWDGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_SPI2EN ---------------------------------
// SVD Line: 5268
// - SFDITEM_FIELD__RCC_APBENR1_SPI2EN
// SPI2EN
//
// [Bit 14] RW (@ 0x4002103C) SPI2EN
//
// ( (unsigned int) RCC_APBENR1 )
// SPI2EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_UART1EN --------------------------------
// SVD Line: 5272
// - SFDITEM_FIELD__RCC_APBENR1_UART1EN
// UART1EN
//
// [Bit 18] RW (@ 0x4002103C) The UART1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR1 )
// UART1EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR1_LPUART1EN -------------------------------
// SVD Line: 5277
// - SFDITEM_FIELD__RCC_APBENR1_LPUART1EN
// LPUART1EN
//
// [Bit 20] RW (@ 0x4002103C) LPUART1EN
//
// ( (unsigned int) RCC_APBENR1 )
// LPUART1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_I2C1EN ---------------------------------
// SVD Line: 5281
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// I2C1EN
//
// [Bit 21] RW (@ 0x4002103C) I2C1 module clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// I2C1EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 5286
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) MCU Debug module clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 5291
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) The Power interface module clock enables
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ---------------------------- Field Item: RCC_APBENR1_LPTIM1EN --------------------------------
// SVD Line: 5296
// - SFDITEM_FIELD__RCC_APBENR1_LPTIM1EN
// LPTIM1EN
//
// [Bit 31] RW (@ 0x4002103C) LPTIM1EN
//
// ( (unsigned int) RCC_APBENR1 )
// LPTIM1EN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 5250
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0x98344C02UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98344C02) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_TIM3EN
// - SFDITEM_FIELD__RCC_APBENR1_RTCAPBEN
// - SFDITEM_FIELD__RCC_APBENR1_WWDGEN
// - SFDITEM_FIELD__RCC_APBENR1_SPI2EN
// - SFDITEM_FIELD__RCC_APBENR1_UART1EN
// - SFDITEM_FIELD__RCC_APBENR1_LPUART1EN
// - SFDITEM_FIELD__RCC_APBENR1_I2C1EN
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// - SFDITEM_FIELD__RCC_APBENR1_LPTIM1EN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 5302
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 5307
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) The SYSCFG module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 5312
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) The TIM1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_SPI1EN ---------------------------------
// SVD Line: 5317
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// SPI1EN
//
// [Bit 12] RW (@ 0x40021040) The SPI1 module clock is enabled
//
// ( (unsigned int) RCC_APBENR2 )
// SPI1EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR2_USART1EN --------------------------------
// SVD Line: 5322
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// USART1EN
//
// [Bit 14] RW (@ 0x40021040) USART1EN
//
// ( (unsigned int) RCC_APBENR2 )
// USART1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 5326
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 module clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM16EN --------------------------------
// SVD Line: 5331
// - SFDITEM_FIELD__RCC_APBENR2_TIM16EN
// TIM16EN
//
// [Bit 17] RW (@ 0x40021040) TIM16EN
//
// ( (unsigned int) RCC_APBENR2 )
// TIM16EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM17EN --------------------------------
// SVD Line: 5335
// - SFDITEM_FIELD__RCC_APBENR2_TIM17EN
// TIM17EN
//
// [Bit 18] RW (@ 0x40021040) TIM17EN
//
// ( (unsigned int) RCC_APBENR2 )
// TIM17EN
//
//
//
// ------------------------------ Field Item: RCC_APBENR2_ADCEN ---------------------------------
// SVD Line: 5339
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// ADCEN
//
// [Bit 20] RW (@ 0x40021040) ADC block clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// ADCEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP1EN --------------------------------
// SVD Line: 5344
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// COMP1EN
//
// [Bit 21] RW (@ 0x40021040) COMP1 module clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP2EN --------------------------------
// SVD Line: 5349
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// COMP2EN
//
// [Bit 22] RW (@ 0x40021040) COMP2 module clock enabled
//
// ( (unsigned int) RCC_APBENR2 )
// COMP2EN
//
//
//
// ---------------------------- Field Item: RCC_APBENR2_VREFBUFEN -------------------------------
// SVD Line: 5354
// - SFDITEM_FIELD__RCC_APBENR2_VREFBUFEN
// VREFBUFEN
//
// [Bit 26] RW (@ 0x40021040) VREFBUFEN
//
// ( (unsigned int) RCC_APBENR2 )
// VREFBUFEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 5302
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x476D801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x476D801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_SPI1EN
// - SFDITEM_FIELD__RCC_APBENR2_USART1EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM16EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM17EN
// - SFDITEM_FIELD__RCC_APBENR2_ADCEN
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// - SFDITEM_FIELD__RCC_APBENR2_VREFBUFEN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 5360
unsigned int RCC_CCIPR __AT (0x40021054);
// ---------------------------- Field Item: RCC_CCIPR_TIMCLK_CTRL -------------------------------
// SVD Line: 5365
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLK_CTRL
// TIMCLK_CTRL
//
// [Bit 0] RW (@ 0x40021054) TIMER PCLK FREQUENCY CONTROL
//
// ( (unsigned int) RCC_CCIPR )
// TIMCLK_CTRL
//
//
//
// ------------------------------ Field Item: RCC_CCIPR_PVDSEL ----------------------------------
// SVD Line: 5370
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// PVDSEL
//
// [Bit 7] RW (@ 0x40021054) PVDSEL
//
// ( (unsigned int) RCC_CCIPR )
// PVDSEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP1SEL ---------------------------------
// SVD Line: 5374
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// COMP1SEL
//
// [Bit 8] RW (@ 0x40021054) COMP1 module clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP1SEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_COMP2SEL ---------------------------------
// SVD Line: 5379
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// COMP2SEL
//
// [Bit 9] RW (@ 0x40021054) COMP2 module clock source selection
//
// ( (unsigned int) RCC_CCIPR )
// COMP2SEL
//
//
//
// ---------------------------- Field Item: RCC_CCIPR_LPUART1SEL --------------------------------
// SVD Line: 5384
// - SFDITEM_FIELD__RCC_CCIPR_LPUART1SEL
// LPUART1SEL
//
// [Bits 12..11] RW (@ 0x40021054) LPUART1SEL
//
// ( (unsigned char)((RCC_CCIPR >> 11) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 11 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_LPTIM1SEL --------------------------------
// SVD Line: 5388
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// LPTIM1SEL
//
// [Bits 17..16] RW (@ 0x40021054) LPTIM1SEL
//
// ( (unsigned char)((RCC_CCIPR >> 16) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_CCIPR_TIM1SEL ---------------------------------
// SVD Line: 5392
// - SFDITEM_FIELD__RCC_CCIPR_TIM1SEL
// TIM1SEL
//
// [Bit 22] RW (@ 0x40021054) TIM1SEL
//
// ( (unsigned int) RCC_CCIPR )
// TIM1SEL
//
//
//
// ----------------------------- Field Item: RCC_CCIPR_TIM17SEL ---------------------------------
// SVD Line: 5396
// - SFDITEM_FIELD__RCC_CCIPR_TIM17SEL
// TIM17SEL
//
// [Bit 23] RW (@ 0x40021054) TIM17SEL
//
// ( (unsigned int) RCC_CCIPR )
// TIM17SEL
//
//
//
// ------------------------------ Field Item: RCC_CCIPR_ADCSEL ----------------------------------
// SVD Line: 5400
// - SFDITEM_FIELD__RCC_CCIPR_ADCSEL
// ADCSEL
//
// [Bits 31..30] RW (@ 0x40021054) ADCSEL
//
// ( (unsigned char)((RCC_CCIPR >> 30) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 5360
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configurationregister
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xC0C31B81UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC0C31B81) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_TIMCLK_CTRL
// - SFDITEM_FIELD__RCC_CCIPR_PVDSEL
// - SFDITEM_FIELD__RCC_CCIPR_COMP1SEL
// - SFDITEM_FIELD__RCC_CCIPR_COMP2SEL
// - SFDITEM_FIELD__RCC_CCIPR_LPUART1SEL
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// - SFDITEM_FIELD__RCC_CCIPR_TIM1SEL
// - SFDITEM_FIELD__RCC_CCIPR_TIM17SEL
// - SFDITEM_FIELD__RCC_CCIPR_ADCSEL
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 5406
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_LSEON -----------------------------------
// SVD Line: 5411
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// LSEON
//
// [Bit 0] RW (@ 0x4002105C) LSE OSC enabled
//
// ( (unsigned int) RCC_BDCR )
// LSEON
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSERDY ----------------------------------
// SVD Line: 5416
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// LSERDY
//
// [Bit 1] RW (@ 0x4002105C) LSE OSC ready
//
// ( (unsigned int) RCC_BDCR )
// LSERDY
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSEBYP ----------------------------------
// SVD Line: 5421
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// LSEBYP
//
// [Bit 2] RW (@ 0x4002105C) LSE OSC bypass
//
// ( (unsigned int) RCC_BDCR )
// LSEBYP
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSON ---------------------------------
// SVD Line: 5426
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// LSECSSON
//
// [Bit 5] RW (@ 0x4002105C) LSE CSS enables
//
// ( (unsigned int) RCC_BDCR )
// LSECSSON
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSD ----------------------------------
// SVD Line: 5431
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// LSECSSD
//
// [Bit 6] RW (@ 0x4002105C) LSE CSS (clock security system) detection failed
//
// ( (unsigned int) RCC_BDCR )
// LSECSSD
//
//
//
// ------------------------------- Field Item: RCC_BDCR_RTCSEL ----------------------------------
// SVD Line: 5436
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// RTCSEL
//
// [Bits 9..8] RW (@ 0x4002105C) RTC clock source selection
//
// ( (unsigned char)((RCC_BDCR >> 8) & 0x3), ((RCC_BDCR = (RCC_BDCR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: RCC_BDCR_RTC_HSEDIV_SEL ------------------------------
// SVD Line: 5441
// - SFDITEM_FIELD__RCC_BDCR_RTC_HSEDIV_SEL
// RTC_HSEDIV_SEL
//
// [Bits 11..10] RW (@ 0x4002105C) The RTC clock source is selected as the division of the HSE clock
//
// ( (unsigned char)((RCC_BDCR >> 10) & 0x3), ((RCC_BDCR = (RCC_BDCR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_BDCR_RTCEN -----------------------------------
// SVD Line: 5446
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// RTCEN
//
// [Bit 15] RW (@ 0x4002105C) RTC clock enabled
//
// ( (unsigned int) RCC_BDCR )
// RTCEN
//
//
//
// ------------------------------- Field Item: RCC_BDCR_BDRST -----------------------------------
// SVD Line: 5451
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// BDRST
//
// [Bit 16] RW (@ 0x4002105C) RTC soft reset
//
// ( (unsigned int) RCC_BDCR )
// BDRST
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCSEL ----------------------------------
// SVD Line: 5456
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
// LSCSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock selection
//
// ( (unsigned int) RCC_BDCR )
// LSCSEL
//
//
//
// ------------------------------ Field Item: RCC_BDCR_IWDGSEL ----------------------------------
// SVD Line: 5461
// - SFDITEM_FIELD__RCC_BDCR_IWDGSEL
// IWDGSEL
//
// [Bit 30] RW (@ 0x4002105C) IWDGSEL
//
// ( (unsigned int) RCC_BDCR )
// IWDGSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 5406
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x42018F67UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x42018F67) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// - SFDITEM_FIELD__RCC_BDCR_RTCSEL
// - SFDITEM_FIELD__RCC_BDCR_RTC_HSEDIV_SEL
// - SFDITEM_FIELD__RCC_BDCR_RTCEN
// - SFDITEM_FIELD__RCC_BDCR_BDRST
// - SFDITEM_FIELD__RCC_BDCR_LSCSEL
// - SFDITEM_FIELD__RCC_BDCR_IWDGSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 5467
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 5472
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI OSC enabled
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 5477
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RO (@ 0x40021060) LSI OSC stability flag
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// ---------------------------- Field Item: RCC_CSR_PINRST_FLTDIS -------------------------------
// SVD Line: 5483
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// PINRST_FLTDIS
//
// [Bit 8] RW (@ 0x40021060) NRST filtering is prohibited
//
// ( (unsigned int) RCC_CSR )
// PINRST_FLTDIS
//
//
//
// ------------------------------- Field Item: RCC_CSR_BORRSTF ----------------------------------
// SVD Line: 5488
// - SFDITEM_FIELD__RCC_CSR_BORRSTF
// BORRSTF
//
// [Bit 9] RO (@ 0x40021060) BOR reset flag
//
// ( (unsigned int) RCC_CSR )
// BORRSTF
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 5494
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Clear the reset flag
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 5499
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RO (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 5505
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RO (@ 0x40021060) External NRST pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PWRRSTF ----------------------------------
// SVD Line: 5511
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// PWRRSTF
//
// [Bit 27] RO (@ 0x40021060) BOR/POR/PDR reset flag
//
// ( (unsigned int) RCC_CSR )
// PWRRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 5517
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RO (@ 0x40021060) Soft reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 5523
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RO (@ 0x40021060) IWDG reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_WWDGRSTF ----------------------------------
// SVD Line: 5529
// - SFDITEM_FIELD__RCC_CSR_WWDGRSTF
// WWDGRSTF
//
// [Bit 30] RO (@ 0x40021060) WWDGRSTF
//
// ( (unsigned int) RCC_CSR )
// WWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 5467
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x800101UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x800101) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// - SFDITEM_FIELD__RCC_CSR_BORRSTF
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// - SFDITEM_FIELD__RCC_CSR_WWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 4743
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_PLLCFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_AHBRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// ----------------------------- Register Item Address: RTC_CRH ---------------------------------
// SVD Line: 5553
unsigned int RTC_CRH __AT (0x40002800);
// -------------------------------- Field Item: RTC_CRH_SECIE -----------------------------------
// SVD Line: 5558
// - SFDITEM_FIELD__RTC_CRH_SECIE
// SECIE
//
// [Bit 0] RW (@ 0x40002800) Seconds interrupt allowed bits
//
// ( (unsigned int) RTC_CRH )
// SECIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_ALRIE -----------------------------------
// SVD Line: 5563
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// ALRIE
//
// [Bit 1] RW (@ 0x40002800) Alarm interrupt allowed bits
//
// ( (unsigned int) RTC_CRH )
// ALRIE
//
//
//
// -------------------------------- Field Item: RTC_CRH_OWIE ------------------------------------
// SVD Line: 5568
// - SFDITEM_FIELD__RTC_CRH_OWIE
// OWIE
//
// [Bit 2] RW (@ 0x40002800) Overflow interrupt allow bits
//
// ( (unsigned int) RTC_CRH )
// OWIE
//
//
//
// --------------------------------- Register RTree: RTC_CRH ------------------------------------
// SVD Line: 5553
// SFDITEM_REG__RTC_CRH
// CRH
//
// [Bits 31..0] RW (@ 0x40002800) RTC Control Register High
// ( (unsigned int)((RTC_CRH >> 0) & 0xFFFFFFFF), ((RTC_CRH = (RTC_CRH & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRH_SECIE
// - SFDITEM_FIELD__RTC_CRH_ALRIE
// - SFDITEM_FIELD__RTC_CRH_OWIE
//
//
// ----------------------------- Register Item Address: RTC_CRL ---------------------------------
// SVD Line: 5575
unsigned int RTC_CRL __AT (0x40002804);
// -------------------------------- Field Item: RTC_CRL_SECF ------------------------------------
// SVD Line: 5580
// - SFDITEM_FIELD__RTC_CRL_SECF
// SECF
//
// [Bit 0] RW (@ 0x40002804) Second flag
//
// ( (unsigned int) RTC_CRL )
// SECF
//
//
//
// -------------------------------- Field Item: RTC_CRL_ALRF ------------------------------------
// SVD Line: 5585
// - SFDITEM_FIELD__RTC_CRL_ALRF
// ALRF
//
// [Bit 1] RW (@ 0x40002804) Alarm flag
//
// ( (unsigned int) RTC_CRL )
// ALRF
//
//
//
// --------------------------------- Field Item: RTC_CRL_OWF ------------------------------------
// SVD Line: 5590
// - SFDITEM_FIELD__RTC_CRL_OWF
// OWF
//
// [Bit 2] RW (@ 0x40002804) Overflow flag
//
// ( (unsigned int) RTC_CRL )
// OWF
//
//
//
// --------------------------------- Field Item: RTC_CRL_RSF ------------------------------------
// SVD Line: 5595
// - SFDITEM_FIELD__RTC_CRL_RSF
// RSF
//
// [Bit 3] RW (@ 0x40002804) Registers synchronized flag
//
// ( (unsigned int) RTC_CRL )
// RSF
//
//
//
// --------------------------------- Field Item: RTC_CRL_CNF ------------------------------------
// SVD Line: 5600
// - SFDITEM_FIELD__RTC_CRL_CNF
// CNF
//
// [Bit 4] RW (@ 0x40002804) Configuration flag
//
// ( (unsigned int) RTC_CRL )
// CNF
//
//
//
// -------------------------------- Field Item: RTC_CRL_RTOFF -----------------------------------
// SVD Line: 5605
// - SFDITEM_FIELD__RTC_CRL_RTOFF
// RTOFF
//
// [Bit 5] RO (@ 0x40002804) RTC operation OFF
//
// ( (unsigned int) RTC_CRL )
// RTOFF
//
//
//
// --------------------------------- Register RTree: RTC_CRL ------------------------------------
// SVD Line: 5575
// SFDITEM_REG__RTC_CRL
// CRL
//
// [Bits 31..0] RW (@ 0x40002804) RTC Control Register Low
// ( (unsigned int)((RTC_CRL >> 0) & 0xFFFFFFFF), ((RTC_CRL = (RTC_CRL & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CRL_SECF
// - SFDITEM_FIELD__RTC_CRL_ALRF
// - SFDITEM_FIELD__RTC_CRL_OWF
// - SFDITEM_FIELD__RTC_CRL_RSF
// - SFDITEM_FIELD__RTC_CRL_CNF
// - SFDITEM_FIELD__RTC_CRL_RTOFF
//
//
// ----------------------------- Register Item Address: RTC_PRLH --------------------------------
// SVD Line: 5613
unsigned int RTC_PRLH __AT (0x40002808);
// -------------------------------- Field Item: RTC_PRLH_PRL ------------------------------------
// SVD Line: 5618
// - SFDITEM_FIELD__RTC_PRLH_PRL
// PRL
//
// [Bits 5..0] RW (@ 0x40002808) RTC prescaler reload value high
//
// ( (unsigned char)((RTC_PRLH >> 0) & 0x3F), ((RTC_PRLH = (RTC_PRLH & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLH ------------------------------------
// SVD Line: 5613
// SFDITEM_REG__RTC_PRLH
// PRLH
//
// [Bits 31..0] RW (@ 0x40002808) RTC Prescaler Load Register High
// ( (unsigned int)((RTC_PRLH >> 0) & 0xFFFFFFFF), ((RTC_PRLH = (RTC_PRLH & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLH_PRL
//
//
// ----------------------------- Register Item Address: RTC_PRLL --------------------------------
// SVD Line: 5625
unsigned int RTC_PRLL __AT (0x4000280C);
// -------------------------------- Field Item: RTC_PRLL_PRL ------------------------------------
// SVD Line: 5630
// - SFDITEM_FIELD__RTC_PRLL_PRL
// PRL
//
// [Bits 15..0] RW (@ 0x4000280C) RTC prescaler reload value high
//
// ( (unsigned short)((RTC_PRLL >> 0) & 0xFFFF), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_PRLL ------------------------------------
// SVD Line: 5625
// SFDITEM_REG__RTC_PRLL
// PRLL
//
// [Bits 31..0] RW (@ 0x4000280C) RTC Prescaler Load Register Low
// ( (unsigned int)((RTC_PRLL >> 0) & 0xFFFFFFFF), ((RTC_PRLL = (RTC_PRLL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_PRLL_PRL
//
//
// ----------------------------- Register Item Address: RTC_DIVH --------------------------------
// SVD Line: 5637
unsigned int RTC_DIVH __AT (0x40002810);
// ------------------------------ Field Item: RTC_DIVH_RTC_DIV ----------------------------------
// SVD Line: 5642
// - SFDITEM_FIELD__RTC_DIVH_RTC_DIV
// RTC_DIV
//
// [Bits 3..0] RO (@ 0x40002810) RTC clock divider
//
// ( (unsigned char)((RTC_DIVH >> 0) & 0xF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVH ------------------------------------
// SVD Line: 5637
// SFDITEM_REG__RTC_DIVH
// DIVH
//
// [Bits 31..0] RW (@ 0x40002810) RTC Prescaler Divider Register High
// ( (unsigned int)((RTC_DIVH >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVH_RTC_DIV
//
//
// ----------------------------- Register Item Address: RTC_DIVL --------------------------------
// SVD Line: 5650
unsigned int RTC_DIVL __AT (0x40002814);
// ------------------------------ Field Item: RTC_DIVL_RTC_DIV ----------------------------------
// SVD Line: 5655
// - SFDITEM_FIELD__RTC_DIVL_RTC_DIV
// RTC_DIV
//
// [Bits 15..0] RO (@ 0x40002814) RTC clock divider
//
// ( (unsigned short)((RTC_DIVL >> 0) & 0xFFFF) )
//
//
//
// -------------------------------- Register RTree: RTC_DIVL ------------------------------------
// SVD Line: 5650
// SFDITEM_REG__RTC_DIVL
// DIVL
//
// [Bits 31..0] RW (@ 0x40002814) RTC Prescaler Divider Register Low
// ( (unsigned int)((RTC_DIVL >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RTC_DIVL_RTC_DIV
//
//
// ----------------------------- Register Item Address: RTC_CNTH --------------------------------
// SVD Line: 5663
unsigned int RTC_CNTH __AT (0x40002818);
// ------------------------------ Field Item: RTC_CNTH_RTC_CNT ----------------------------------
// SVD Line: 5668
// - SFDITEM_FIELD__RTC_CNTH_RTC_CNT
// RTC_CNT
//
// [Bits 15..0] RW (@ 0x40002818) RTC core counter
//
// ( (unsigned short)((RTC_CNTH >> 0) & 0xFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTH ------------------------------------
// SVD Line: 5663
// SFDITEM_REG__RTC_CNTH
// CNTH
//
// [Bits 31..0] RW (@ 0x40002818) RTC Counter Register High
// ( (unsigned int)((RTC_CNTH >> 0) & 0xFFFFFFFF), ((RTC_CNTH = (RTC_CNTH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTH_RTC_CNT
//
//
// ----------------------------- Register Item Address: RTC_CNTL --------------------------------
// SVD Line: 5675
unsigned int RTC_CNTL __AT (0x4000281C);
// ------------------------------ Field Item: RTC_CNTL_RTC_CNT ----------------------------------
// SVD Line: 5680
// - SFDITEM_FIELD__RTC_CNTL_RTC_CNT
// RTC_CNT
//
// [Bits 15..0] RW (@ 0x4000281C) RTC core counter
//
// ( (unsigned short)((RTC_CNTL >> 0) & 0xFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_CNTL ------------------------------------
// SVD Line: 5675
// SFDITEM_REG__RTC_CNTL
// CNTL
//
// [Bits 31..0] RW (@ 0x4000281C) RTC Counter Register Low
// ( (unsigned int)((RTC_CNTL >> 0) & 0xFFFFFFFF), ((RTC_CNTL = (RTC_CNTL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_CNTL_RTC_CNT
//
//
// ----------------------------- Register Item Address: RTC_ALRH --------------------------------
// SVD Line: 5687
unsigned int RTC_ALRH __AT (0x40002820);
// -------------------------------- Field Item: RTC_ALRH_ALR ------------------------------------
// SVD Line: 5692
// - SFDITEM_FIELD__RTC_ALRH_ALR
// ALR
//
// [Bits 15..0] RW (@ 0x40002820) RTC alarm value
//
// ( (unsigned short)((RTC_ALRH >> 0) & 0xFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRH ------------------------------------
// SVD Line: 5687
// SFDITEM_REG__RTC_ALRH
// ALRH
//
// [Bits 31..0] RW (@ 0x40002820) RTC Alarm Register High
// ( (unsigned int)((RTC_ALRH >> 0) & 0xFFFFFFFF), ((RTC_ALRH = (RTC_ALRH & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRH_ALR
//
//
// ----------------------------- Register Item Address: RTC_ALRL --------------------------------
// SVD Line: 5699
unsigned int RTC_ALRL __AT (0x40002824);
// -------------------------------- Field Item: RTC_ALRL_ALR ------------------------------------
// SVD Line: 5704
// - SFDITEM_FIELD__RTC_ALRL_ALR
// ALR
//
// [Bits 15..0] RW (@ 0x40002824) RTC alarm value
//
// ( (unsigned short)((RTC_ALRL >> 0) & 0xFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: RTC_ALRL ------------------------------------
// SVD Line: 5699
// SFDITEM_REG__RTC_ALRL
// ALRL
//
// [Bits 31..0] RW (@ 0x40002824) RTC Alarm Register Low
// ( (unsigned int)((RTC_ALRL >> 0) & 0xFFFFFFFF), ((RTC_ALRL = (RTC_ALRL & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_ALRL_ALR
//
//
// -------------------------- Register Item Address: RTC_BKP_RTCCR ------------------------------
// SVD Line: 5711
unsigned int RTC_BKP_RTCCR __AT (0x4000282C);
// ------------------------------ Field Item: RTC_BKP_RTCCR_CAL ---------------------------------
// SVD Line: 5715
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CAL
// CAL
//
// [Bits 6..0] RW (@ 0x4000282C) Calibration value
//
// ( (unsigned char)((RTC_BKP_RTCCR >> 0) & 0x7F), ((RTC_BKP_RTCCR = (RTC_BKP_RTCCR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RTC_BKP_RTCCR_CCO ---------------------------------
// SVD Line: 5720
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CCO
// CCO
//
// [Bit 7] RW (@ 0x4000282C) Calibrate the clock output bits
//
// ( (unsigned int) RTC_BKP_RTCCR )
// CCO
//
//
//
// ----------------------------- Field Item: RTC_BKP_RTCCR_ASOE ---------------------------------
// SVD Line: 5725
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOE
// ASOE
//
// [Bit 8] RW (@ 0x4000282C) Seconds/alarm pulse output enable bit
//
// ( (unsigned int) RTC_BKP_RTCCR )
// ASOE
//
//
//
// ----------------------------- Field Item: RTC_BKP_RTCCR_ASOS ---------------------------------
// SVD Line: 5730
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOS
// ASOS
//
// [Bit 9] RW (@ 0x4000282C) Seconds/alarm pulse output select bits
//
// ( (unsigned int) RTC_BKP_RTCCR )
// ASOS
//
//
//
// ------------------------------ Register RTree: RTC_BKP_RTCCR ---------------------------------
// SVD Line: 5711
// SFDITEM_REG__RTC_BKP_RTCCR
// BKP_RTCCR
//
// [Bits 31..0] RW (@ 0x4000282C) BKP_RTCCR
// ( (unsigned int)((RTC_BKP_RTCCR >> 0) & 0xFFFFFFFF), ((RTC_BKP_RTCCR = (RTC_BKP_RTCCR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CAL
// - SFDITEM_FIELD__RTC_BKP_RTCCR_CCO
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOE
// - SFDITEM_FIELD__RTC_BKP_RTCCR_ASOS
//
//
// ---------------------------------- Peripheral View: RTC --------------------------------------
// SVD Line: 5538
// RTC
// RTC
// - SFDITEM_REG__RTC_CRH
// - SFDITEM_REG__RTC_CRL
// - SFDITEM_REG__RTC_PRLH
// - SFDITEM_REG__RTC_PRLL
// - SFDITEM_REG__RTC_DIVH
// - SFDITEM_REG__RTC_DIVL
// - SFDITEM_REG__RTC_CNTH
// - SFDITEM_REG__RTC_CNTL
// - SFDITEM_REG__RTC_ALRH
// - SFDITEM_REG__RTC_ALRL
// - SFDITEM_REG__RTC_BKP_RTCCR
//
//
// ----------------------------- Register Item Address: SPI1_CR1 --------------------------------
// SVD Line: 5755
unsigned int SPI1_CR1 __AT (0x40013000);
// -------------------------------- Field Item: SPI1_CR1_CPHA -----------------------------------
// SVD Line: 5760
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// CPHA
//
// [Bit 0] RW (@ 0x40013000) Clock Phase
//
// ( (unsigned int) SPI1_CR1 )
// CPHA
//
//
//
// -------------------------------- Field Item: SPI1_CR1_CPOL -----------------------------------
// SVD Line: 5765
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// CPOL
//
// [Bit 1] RW (@ 0x40013000) Clock Polarity
//
// ( (unsigned int) SPI1_CR1 )
// CPOL
//
//
//
// -------------------------------- Field Item: SPI1_CR1_MSTR -----------------------------------
// SVD Line: 5770
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// MSTR
//
// [Bit 2] RW (@ 0x40013000) Master Selection
//
// ( (unsigned int) SPI1_CR1 )
// MSTR
//
//
//
// --------------------------------- Field Item: SPI1_CR1_BR ------------------------------------
// SVD Line: 5775
// - SFDITEM_FIELD__SPI1_CR1_BR
// BR
//
// [Bits 5..3] RW (@ 0x40013000) Baud Rate Control
//
// ( (unsigned char)((SPI1_CR1 >> 3) & 0x7), ((SPI1_CR1 = (SPI1_CR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SPE ------------------------------------
// SVD Line: 5780
// - SFDITEM_FIELD__SPI1_CR1_SPE
// SPE
//
// [Bit 6] RW (@ 0x40013000) SPI Enable
//
// ( (unsigned int) SPI1_CR1 )
// SPE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_LSBFIRST ---------------------------------
// SVD Line: 5785
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// LSBFIRST
//
// [Bit 7] RW (@ 0x40013000) Frame Format
//
// ( (unsigned int) SPI1_CR1 )
// LSBFIRST
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSI ------------------------------------
// SVD Line: 5790
// - SFDITEM_FIELD__SPI1_CR1_SSI
// SSI
//
// [Bit 8] RW (@ 0x40013000) Internal slave select
//
// ( (unsigned int) SPI1_CR1 )
// SSI
//
//
//
// -------------------------------- Field Item: SPI1_CR1_SSM ------------------------------------
// SVD Line: 5795
// - SFDITEM_FIELD__SPI1_CR1_SSM
// SSM
//
// [Bit 9] RW (@ 0x40013000) Software slave management
//
// ( (unsigned int) SPI1_CR1 )
// SSM
//
//
//
// ------------------------------- Field Item: SPI1_CR1_RXONLY ----------------------------------
// SVD Line: 5800
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// RXONLY
//
// [Bit 10] RW (@ 0x40013000) Receive only
//
// ( (unsigned int) SPI1_CR1 )
// RXONLY
//
//
//
// -------------------------------- Field Item: SPI1_CR1_DFF ------------------------------------
// SVD Line: 5805
// - SFDITEM_FIELD__SPI1_CR1_DFF
// DFF
//
// [Bit 11] RW (@ 0x40013000) Data frame format
//
// ( (unsigned int) SPI1_CR1 )
// DFF
//
//
//
// ------------------------------ Field Item: SPI1_CR1_CRCNEXT ----------------------------------
// SVD Line: 5810
// - SFDITEM_FIELD__SPI1_CR1_CRCNEXT
// CRCNEXT
//
// [Bit 12] RW (@ 0x40013000) Transmit CRC next
//
// ( (unsigned int) SPI1_CR1 )
// CRCNEXT
//
//
//
// ------------------------------- Field Item: SPI1_CR1_CRCEN -----------------------------------
// SVD Line: 5815
// - SFDITEM_FIELD__SPI1_CR1_CRCEN
// CRCEN
//
// [Bit 13] RW (@ 0x40013000) Hardware CRC calculation enable
//
// ( (unsigned int) SPI1_CR1 )
// CRCEN
//
//
//
// ------------------------------- Field Item: SPI1_CR1_BIDIOE ----------------------------------
// SVD Line: 5820
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// BIDIOE
//
// [Bit 14] RW (@ 0x40013000) Output enable in bidirectional mode
//
// ( (unsigned int) SPI1_CR1 )
// BIDIOE
//
//
//
// ------------------------------ Field Item: SPI1_CR1_BIDIMODE ---------------------------------
// SVD Line: 5825
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
// BIDIMODE
//
// [Bit 15] RW (@ 0x40013000) Bidirectional data mode enable
//
// ( (unsigned int) SPI1_CR1 )
// BIDIMODE
//
//
//
// -------------------------------- Register RTree: SPI1_CR1 ------------------------------------
// SVD Line: 5755
// SFDITEM_REG__SPI1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40013000) control register 1
// ( (unsigned int)((SPI1_CR1 >> 0) & 0xFFFFFFFF), ((SPI1_CR1 = (SPI1_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR1_CPHA
// - SFDITEM_FIELD__SPI1_CR1_CPOL
// - SFDITEM_FIELD__SPI1_CR1_MSTR
// - SFDITEM_FIELD__SPI1_CR1_BR
// - SFDITEM_FIELD__SPI1_CR1_SPE
// - SFDITEM_FIELD__SPI1_CR1_LSBFIRST
// - SFDITEM_FIELD__SPI1_CR1_SSI
// - SFDITEM_FIELD__SPI1_CR1_SSM
// - SFDITEM_FIELD__SPI1_CR1_RXONLY
// - SFDITEM_FIELD__SPI1_CR1_DFF
// - SFDITEM_FIELD__SPI1_CR1_CRCNEXT
// - SFDITEM_FIELD__SPI1_CR1_CRCEN
// - SFDITEM_FIELD__SPI1_CR1_BIDIOE
// - SFDITEM_FIELD__SPI1_CR1_BIDIMODE
//
//
// ----------------------------- Register Item Address: SPI1_CR2 --------------------------------
// SVD Line: 5832
unsigned int SPI1_CR2 __AT (0x40013004);
// ------------------------------ Field Item: SPI1_CR2_RXDMAEN ----------------------------------
// SVD Line: 5837
// - SFDITEM_FIELD__SPI1_CR2_RXDMAEN
// RXDMAEN
//
// [Bit 0] RW (@ 0x40013004) Rx buffer DMA enable
//
// ( (unsigned int) SPI1_CR2 )
// RXDMAEN
//
//
//
// ------------------------------ Field Item: SPI1_CR2_TXDMAEN ----------------------------------
// SVD Line: 5842
// - SFDITEM_FIELD__SPI1_CR2_TXDMAEN
// TXDMAEN
//
// [Bit 1] RW (@ 0x40013004) Tx buffer DMA enable
//
// ( (unsigned int) SPI1_CR2 )
// TXDMAEN
//
//
//
// -------------------------------- Field Item: SPI1_CR2_SSOE -----------------------------------
// SVD Line: 5847
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// SSOE
//
// [Bit 2] RW (@ 0x40013004) SS Output Enable
//
// ( (unsigned int) SPI1_CR2 )
// SSOE
//
//
//
// ----------------------------- Field Item: SPI1_CR2_CLRTXFIFO ---------------------------------
// SVD Line: 5852
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// CLRTXFIFO
//
// [Bit 4] RW (@ 0x40013004) Clear FIFO
//
// ( (unsigned int) SPI1_CR2 )
// CLRTXFIFO
//
//
//
// ------------------------------- Field Item: SPI1_CR2_ERRIE -----------------------------------
// SVD Line: 5857
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// ERRIE
//
// [Bit 5] RW (@ 0x40013004) Error Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// ERRIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_RXNEIE ----------------------------------
// SVD Line: 5862
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// RXNEIE
//
// [Bit 6] RW (@ 0x40013004) RX buffer Not Empty Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: SPI1_CR2_TXEIE -----------------------------------
// SVD Line: 5867
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40013004) Tx buffer Empty Interrupt Enable
//
// ( (unsigned int) SPI1_CR2 )
// TXEIE
//
//
//
// -------------------------------- Field Item: SPI1_CR2_FRF ------------------------------------
// SVD Line: 5872
// - SFDITEM_FIELD__SPI1_CR2_FRF
// FRF
//
// [Bit 15] RW (@ 0x40013004) FRF
//
// ( (unsigned int) SPI1_CR2 )
// FRF
//
//
//
// -------------------------------- Register RTree: SPI1_CR2 ------------------------------------
// SVD Line: 5832
// SFDITEM_REG__SPI1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013004) control register 2
// ( (unsigned int)((SPI1_CR2 >> 0) & 0xFFFFFFFF), ((SPI1_CR2 = (SPI1_CR2 & ~(0x80F7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80F7) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CR2_RXDMAEN
// - SFDITEM_FIELD__SPI1_CR2_TXDMAEN
// - SFDITEM_FIELD__SPI1_CR2_SSOE
// - SFDITEM_FIELD__SPI1_CR2_CLRTXFIFO
// - SFDITEM_FIELD__SPI1_CR2_ERRIE
// - SFDITEM_FIELD__SPI1_CR2_RXNEIE
// - SFDITEM_FIELD__SPI1_CR2_TXEIE
// - SFDITEM_FIELD__SPI1_CR2_FRF
//
//
// ----------------------------- Register Item Address: SPI1_SR ---------------------------------
// SVD Line: 5878
unsigned int SPI1_SR __AT (0x40013008);
// -------------------------------- Field Item: SPI1_SR_RXNE ------------------------------------
// SVD Line: 5883
// - SFDITEM_FIELD__SPI1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40013008) Receive buffer Not Empty
//
// ( (unsigned int) SPI1_SR )
// RXNE
//
//
//
// --------------------------------- Field Item: SPI1_SR_TXE ------------------------------------
// SVD Line: 5889
// - SFDITEM_FIELD__SPI1_SR_TXE
// TXE
//
// [Bit 1] RO (@ 0x40013008) Transmit buffer Empty
//
// ( (unsigned int) SPI1_SR )
// TXE
//
//
//
// ------------------------------- Field Item: SPI1_SR_CHSIDE -----------------------------------
// SVD Line: 5895
// - SFDITEM_FIELD__SPI1_SR_CHSIDE
// CHSIDE
//
// [Bit 2] RO (@ 0x40013008) Channel side
//
// ( (unsigned int) SPI1_SR )
// CHSIDE
//
//
//
// --------------------------------- Field Item: SPI1_SR_UDR ------------------------------------
// SVD Line: 5901
// - SFDITEM_FIELD__SPI1_SR_UDR
// UDR
//
// [Bit 3] RO (@ 0x40013008) Underrun flag
//
// ( (unsigned int) SPI1_SR )
// UDR
//
//
//
// ------------------------------- Field Item: SPI1_SR_CRCERR -----------------------------------
// SVD Line: 5907
// - SFDITEM_FIELD__SPI1_SR_CRCERR
// CRCERR
//
// [Bit 4] RW (@ 0x40013008) CRC error flag
//
// ( (unsigned int) SPI1_SR )
// CRCERR
//
//
//
// -------------------------------- Field Item: SPI1_SR_MODF ------------------------------------
// SVD Line: 5912
// - SFDITEM_FIELD__SPI1_SR_MODF
// MODF
//
// [Bit 5] RW (@ 0x40013008) Mode fault
//
// ( (unsigned int) SPI1_SR )
// MODF
//
//
//
// --------------------------------- Field Item: SPI1_SR_OVR ------------------------------------
// SVD Line: 5917
// - SFDITEM_FIELD__SPI1_SR_OVR
// OVR
//
// [Bit 6] RO (@ 0x40013008) Overrun flag
//
// ( (unsigned int) SPI1_SR )
// OVR
//
//
//
// --------------------------------- Field Item: SPI1_SR_BSY ------------------------------------
// SVD Line: 5923
// - SFDITEM_FIELD__SPI1_SR_BSY
// BSY
//
// [Bit 7] RO (@ 0x40013008) Busy flag
//
// ( (unsigned int) SPI1_SR )
// BSY
//
//
//
// --------------------------------- Field Item: SPI1_SR_FRE ------------------------------------
// SVD Line: 5929
// - SFDITEM_FIELD__SPI1_SR_FRE
// FRE
//
// [Bit 8] RO (@ 0x40013008) FRE
//
// ( (unsigned int) SPI1_SR )
// FRE
//
//
//
// -------------------------------- Field Item: SPI1_SR_FRLVL -----------------------------------
// SVD Line: 5934
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// FRLVL
//
// [Bits 10..9] RO (@ 0x40013008) FIFO Reception Level
//
// ( (unsigned char)((SPI1_SR >> 9) & 0x3) )
//
//
//
// -------------------------------- Field Item: SPI1_SR_FTLVL -----------------------------------
// SVD Line: 5940
// - SFDITEM_FIELD__SPI1_SR_FTLVL
// FTLVL
//
// [Bits 12..11] RO (@ 0x40013008) FIFO Transmission Level
//
// ( (unsigned char)((SPI1_SR >> 11) & 0x3) )
//
//
//
// --------------------------------- Register RTree: SPI1_SR ------------------------------------
// SVD Line: 5878
// SFDITEM_REG__SPI1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013008) status register
// ( (unsigned int)((SPI1_SR >> 0) & 0xFFFFFFFF), ((SPI1_SR = (SPI1_SR & ~(0x30UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_SR_RXNE
// - SFDITEM_FIELD__SPI1_SR_TXE
// - SFDITEM_FIELD__SPI1_SR_CHSIDE
// - SFDITEM_FIELD__SPI1_SR_UDR
// - SFDITEM_FIELD__SPI1_SR_CRCERR
// - SFDITEM_FIELD__SPI1_SR_MODF
// - SFDITEM_FIELD__SPI1_SR_OVR
// - SFDITEM_FIELD__SPI1_SR_BSY
// - SFDITEM_FIELD__SPI1_SR_FRE
// - SFDITEM_FIELD__SPI1_SR_FRLVL
// - SFDITEM_FIELD__SPI1_SR_FTLVL
//
//
// ----------------------------- Register Item Address: SPI1_DR ---------------------------------
// SVD Line: 5948
unsigned int SPI1_DR __AT (0x4001300C);
// --------------------------------- Field Item: SPI1_DR_DR -------------------------------------
// SVD Line: 5953
// - SFDITEM_FIELD__SPI1_DR_DR
// DR
//
// [Bits 15..0] RW (@ 0x4001300C) Data Register
//
// ( (unsigned short)((SPI1_DR >> 0) & 0xFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: SPI1_DR ------------------------------------
// SVD Line: 5948
// SFDITEM_REG__SPI1_DR
// DR
//
// [Bits 31..0] RW (@ 0x4001300C) data register
// ( (unsigned int)((SPI1_DR >> 0) & 0xFFFFFFFF), ((SPI1_DR = (SPI1_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_DR_DR
//
//
// ---------------------------- Register Item Address: SPI1_CRCPR -------------------------------
// SVD Line: 5960
unsigned int SPI1_CRCPR __AT (0x40013010);
// ----------------------------- Field Item: SPI1_CRCPR_CRCPOLY ---------------------------------
// SVD Line: 5965
// - SFDITEM_FIELD__SPI1_CRCPR_CRCPOLY
// CRCPOLY
//
// [Bits 15..0] RW (@ 0x40013010) CRC polynomial register
//
// ( (unsigned short)((SPI1_CRCPR >> 0) & 0xFFFF), ((SPI1_CRCPR = (SPI1_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI1_CRCPR -----------------------------------
// SVD Line: 5960
// SFDITEM_REG__SPI1_CRCPR
// CRCPR
//
// [Bits 31..0] RW (@ 0x40013010) CRC polynomial register
// ( (unsigned int)((SPI1_CRCPR >> 0) & 0xFFFFFFFF), ((SPI1_CRCPR = (SPI1_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_CRCPR_CRCPOLY
//
//
// --------------------------- Register Item Address: SPI1_RXCRCR -------------------------------
// SVD Line: 5972
unsigned int SPI1_RXCRCR __AT (0x40013014);
// ------------------------------ Field Item: SPI1_RXCRCR_RXCRC ---------------------------------
// SVD Line: 5976
// - SFDITEM_FIELD__SPI1_RXCRCR_RXCRC
// RXCRC
//
// [Bits 15..0] RW (@ 0x40013014) rcv crc reg
//
// ( (unsigned short)((SPI1_RXCRCR >> 0) & 0xFFFF), ((SPI1_RXCRCR = (SPI1_RXCRCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI1_RXCRCR ----------------------------------
// SVD Line: 5972
// SFDITEM_REG__SPI1_RXCRCR
// RXCRCR
//
// [Bits 31..0] RW (@ 0x40013014) RXCRCR
// ( (unsigned int)((SPI1_RXCRCR >> 0) & 0xFFFFFFFF), ((SPI1_RXCRCR = (SPI1_RXCRCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_RXCRCR_RXCRC
//
//
// --------------------------- Register Item Address: SPI1_TXCRCR -------------------------------
// SVD Line: 5983
unsigned int SPI1_TXCRCR __AT (0x40013018);
// ------------------------------ Field Item: SPI1_TXCRCR_TXCRC ---------------------------------
// SVD Line: 5987
// - SFDITEM_FIELD__SPI1_TXCRCR_TXCRC
// TXCRC
//
// [Bits 15..0] RO (@ 0x40013018) tx crc reg
//
// ( (unsigned short)((SPI1_TXCRCR >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: SPI1_TXCRCR ----------------------------------
// SVD Line: 5983
// SFDITEM_REG__SPI1_TXCRCR
// TXCRCR
//
// [Bits 31..0] RW (@ 0x40013018) TXCRCR
// ( (unsigned int)((SPI1_TXCRCR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__SPI1_TXCRCR_TXCRC
//
//
// -------------------------- Register Item Address: SPI1_I2S_CFGR ------------------------------
// SVD Line: 5995
unsigned int SPI1_I2S_CFGR __AT (0x4001301C);
// ----------------------------- Field Item: SPI1_I2S_CFGR_CHLEN --------------------------------
// SVD Line: 5999
// - SFDITEM_FIELD__SPI1_I2S_CFGR_CHLEN
// CHLEN
//
// [Bit 0] RW (@ 0x4001301C) Channel length (number of bits per audio channel)
//
// ( (unsigned int) SPI1_I2S_CFGR )
// CHLEN
//
//
//
// ---------------------------- Field Item: SPI1_I2S_CFGR_DATLEN --------------------------------
// SVD Line: 6004
// - SFDITEM_FIELD__SPI1_I2S_CFGR_DATLEN
// DATLEN
//
// [Bits 2..1] RW (@ 0x4001301C) Data length to be transferred
//
// ( (unsigned char)((SPI1_I2S_CFGR >> 1) & 0x3), ((SPI1_I2S_CFGR = (SPI1_I2S_CFGR & ~(0x3UL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 1 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI1_I2S_CFGR_CKPOL --------------------------------
// SVD Line: 6009
// - SFDITEM_FIELD__SPI1_I2S_CFGR_CKPOL
// CKPOL
//
// [Bit 3] RW (@ 0x4001301C) Steady state clock polarity
//
// ( (unsigned int) SPI1_I2S_CFGR )
// CKPOL
//
//
//
// ---------------------------- Field Item: SPI1_I2S_CFGR_I2SSTD --------------------------------
// SVD Line: 6014
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SSTD
// I2SSTD
//
// [Bits 5..4] RW (@ 0x4001301C) I2S standard selection
//
// ( (unsigned char)((SPI1_I2S_CFGR >> 4) & 0x3), ((SPI1_I2S_CFGR = (SPI1_I2S_CFGR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: SPI1_I2S_CFGR_PCMSYNC -------------------------------
// SVD Line: 6019
// - SFDITEM_FIELD__SPI1_I2S_CFGR_PCMSYNC
// PCMSYNC
//
// [Bit 7] RW (@ 0x4001301C) PCM frame synchronization
//
// ( (unsigned int) SPI1_I2S_CFGR )
// PCMSYNC
//
//
//
// ---------------------------- Field Item: SPI1_I2S_CFGR_I2SCFG --------------------------------
// SVD Line: 6024
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SCFG
// I2SCFG
//
// [Bits 9..8] RW (@ 0x4001301C) I2S configuration mode
//
// ( (unsigned char)((SPI1_I2S_CFGR >> 8) & 0x3), ((SPI1_I2S_CFGR = (SPI1_I2S_CFGR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI1_I2S_CFGR_I2SE ---------------------------------
// SVD Line: 6029
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SE
// I2SE
//
// [Bit 10] RW (@ 0x4001301C) I2S enable
//
// ( (unsigned int) SPI1_I2S_CFGR )
// I2SE
//
//
//
// ---------------------------- Field Item: SPI1_I2S_CFGR_I2SMOD --------------------------------
// SVD Line: 6034
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SMOD
// I2SMOD
//
// [Bit 11] RW (@ 0x4001301C) I2S mode selection
//
// ( (unsigned int) SPI1_I2S_CFGR )
// I2SMOD
//
//
//
// ------------------------------ Register RTree: SPI1_I2S_CFGR ---------------------------------
// SVD Line: 5995
// SFDITEM_REG__SPI1_I2S_CFGR
// I2S_CFGR
//
// [Bits 31..0] RW (@ 0x4001301C) I2S_CFGR
// ( (unsigned int)((SPI1_I2S_CFGR >> 0) & 0xFFFFFFFF), ((SPI1_I2S_CFGR = (SPI1_I2S_CFGR & ~(0xFBFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFBF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_I2S_CFGR_CHLEN
// - SFDITEM_FIELD__SPI1_I2S_CFGR_DATLEN
// - SFDITEM_FIELD__SPI1_I2S_CFGR_CKPOL
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SSTD
// - SFDITEM_FIELD__SPI1_I2S_CFGR_PCMSYNC
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SCFG
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SE
// - SFDITEM_FIELD__SPI1_I2S_CFGR_I2SMOD
//
//
// ---------------------------- Register Item Address: SPI1_I2SPR -------------------------------
// SVD Line: 6041
unsigned int SPI1_I2SPR __AT (0x40013020);
// ------------------------------ Field Item: SPI1_I2SPR_I2SDIV ---------------------------------
// SVD Line: 6046
// - SFDITEM_FIELD__SPI1_I2SPR_I2SDIV
// I2SDIV
//
// [Bits 7..0] RW (@ 0x40013020) I2S linear prescaler
//
// ( (unsigned char)((SPI1_I2SPR >> 0) & 0xFF), ((SPI1_I2SPR = (SPI1_I2SPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: SPI1_I2SPR_ODD -----------------------------------
// SVD Line: 6051
// - SFDITEM_FIELD__SPI1_I2SPR_ODD
// ODD
//
// [Bit 8] RW (@ 0x40013020) Odd factor for the prescaler
//
// ( (unsigned int) SPI1_I2SPR )
// ODD
//
//
//
// ------------------------------ Field Item: SPI1_I2SPR_MCKOE ----------------------------------
// SVD Line: 6056
// - SFDITEM_FIELD__SPI1_I2SPR_MCKOE
// MCKOE
//
// [Bit 9] RW (@ 0x40013020) Master clock output enable
//
// ( (unsigned int) SPI1_I2SPR )
// MCKOE
//
//
//
// ------------------------------- Register RTree: SPI1_I2SPR -----------------------------------
// SVD Line: 6041
// SFDITEM_REG__SPI1_I2SPR
// I2SPR
//
// [Bits 31..0] RW (@ 0x40013020) I2S prescaler register
// ( (unsigned int)((SPI1_I2SPR >> 0) & 0xFFFFFFFF), ((SPI1_I2SPR = (SPI1_I2SPR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI1_I2SPR_I2SDIV
// - SFDITEM_FIELD__SPI1_I2SPR_ODD
// - SFDITEM_FIELD__SPI1_I2SPR_MCKOE
//
//
// ---------------------------------- Peripheral View: SPI1 -------------------------------------
// SVD Line: 5739
// SPI1
// SPI1
// - SFDITEM_REG__SPI1_CR1
// - SFDITEM_REG__SPI1_CR2
// - SFDITEM_REG__SPI1_SR
// - SFDITEM_REG__SPI1_DR
// - SFDITEM_REG__SPI1_CRCPR
// - SFDITEM_REG__SPI1_RXCRCR
// - SFDITEM_REG__SPI1_TXCRCR
// - SFDITEM_REG__SPI1_I2S_CFGR
// - SFDITEM_REG__SPI1_I2SPR
//
//
// ----------------------------- Register Item Address: SPI2_CR1 --------------------------------
// SVD Line: 5755
unsigned int SPI2_CR1 __AT (0x40003800);
// -------------------------------- Field Item: SPI2_CR1_CPHA -----------------------------------
// SVD Line: 5760
// - SFDITEM_FIELD__SPI2_CR1_CPHA
// CPHA
//
// [Bit 0] RW (@ 0x40003800) Clock Phase
//
// ( (unsigned int) SPI2_CR1 )
// CPHA
//
//
//
// -------------------------------- Field Item: SPI2_CR1_CPOL -----------------------------------
// SVD Line: 5765
// - SFDITEM_FIELD__SPI2_CR1_CPOL
// CPOL
//
// [Bit 1] RW (@ 0x40003800) Clock Polarity
//
// ( (unsigned int) SPI2_CR1 )
// CPOL
//
//
//
// -------------------------------- Field Item: SPI2_CR1_MSTR -----------------------------------
// SVD Line: 5770
// - SFDITEM_FIELD__SPI2_CR1_MSTR
// MSTR
//
// [Bit 2] RW (@ 0x40003800) Master Selection
//
// ( (unsigned int) SPI2_CR1 )
// MSTR
//
//
//
// --------------------------------- Field Item: SPI2_CR1_BR ------------------------------------
// SVD Line: 5775
// - SFDITEM_FIELD__SPI2_CR1_BR
// BR
//
// [Bits 5..3] RW (@ 0x40003800) Baud Rate Control
//
// ( (unsigned char)((SPI2_CR1 >> 3) & 0x7), ((SPI2_CR1 = (SPI2_CR1 & ~(0x7UL << 3 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 3 ) ) ))
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SPE ------------------------------------
// SVD Line: 5780
// - SFDITEM_FIELD__SPI2_CR1_SPE
// SPE
//
// [Bit 6] RW (@ 0x40003800) SPI Enable
//
// ( (unsigned int) SPI2_CR1 )
// SPE
//
//
//
// ------------------------------ Field Item: SPI2_CR1_LSBFIRST ---------------------------------
// SVD Line: 5785
// - SFDITEM_FIELD__SPI2_CR1_LSBFIRST
// LSBFIRST
//
// [Bit 7] RW (@ 0x40003800) Frame Format
//
// ( (unsigned int) SPI2_CR1 )
// LSBFIRST
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SSI ------------------------------------
// SVD Line: 5790
// - SFDITEM_FIELD__SPI2_CR1_SSI
// SSI
//
// [Bit 8] RW (@ 0x40003800) Internal slave select
//
// ( (unsigned int) SPI2_CR1 )
// SSI
//
//
//
// -------------------------------- Field Item: SPI2_CR1_SSM ------------------------------------
// SVD Line: 5795
// - SFDITEM_FIELD__SPI2_CR1_SSM
// SSM
//
// [Bit 9] RW (@ 0x40003800) Software slave management
//
// ( (unsigned int) SPI2_CR1 )
// SSM
//
//
//
// ------------------------------- Field Item: SPI2_CR1_RXONLY ----------------------------------
// SVD Line: 5800
// - SFDITEM_FIELD__SPI2_CR1_RXONLY
// RXONLY
//
// [Bit 10] RW (@ 0x40003800) Receive only
//
// ( (unsigned int) SPI2_CR1 )
// RXONLY
//
//
//
// -------------------------------- Field Item: SPI2_CR1_DFF ------------------------------------
// SVD Line: 5805
// - SFDITEM_FIELD__SPI2_CR1_DFF
// DFF
//
// [Bit 11] RW (@ 0x40003800) Data frame format
//
// ( (unsigned int) SPI2_CR1 )
// DFF
//
//
//
// ------------------------------ Field Item: SPI2_CR1_CRCNEXT ----------------------------------
// SVD Line: 5810
// - SFDITEM_FIELD__SPI2_CR1_CRCNEXT
// CRCNEXT
//
// [Bit 12] RW (@ 0x40003800) Transmit CRC next
//
// ( (unsigned int) SPI2_CR1 )
// CRCNEXT
//
//
//
// ------------------------------- Field Item: SPI2_CR1_CRCEN -----------------------------------
// SVD Line: 5815
// - SFDITEM_FIELD__SPI2_CR1_CRCEN
// CRCEN
//
// [Bit 13] RW (@ 0x40003800) Hardware CRC calculation enable
//
// ( (unsigned int) SPI2_CR1 )
// CRCEN
//
//
//
// ------------------------------- Field Item: SPI2_CR1_BIDIOE ----------------------------------
// SVD Line: 5820
// - SFDITEM_FIELD__SPI2_CR1_BIDIOE
// BIDIOE
//
// [Bit 14] RW (@ 0x40003800) Output enable in bidirectional mode
//
// ( (unsigned int) SPI2_CR1 )
// BIDIOE
//
//
//
// ------------------------------ Field Item: SPI2_CR1_BIDIMODE ---------------------------------
// SVD Line: 5825
// - SFDITEM_FIELD__SPI2_CR1_BIDIMODE
// BIDIMODE
//
// [Bit 15] RW (@ 0x40003800) Bidirectional data mode enable
//
// ( (unsigned int) SPI2_CR1 )
// BIDIMODE
//
//
//
// -------------------------------- Register RTree: SPI2_CR1 ------------------------------------
// SVD Line: 5755
// SFDITEM_REG__SPI2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40003800) control register 1
// ( (unsigned int)((SPI2_CR1 >> 0) & 0xFFFFFFFF), ((SPI2_CR1 = (SPI2_CR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CR1_CPHA
// - SFDITEM_FIELD__SPI2_CR1_CPOL
// - SFDITEM_FIELD__SPI2_CR1_MSTR
// - SFDITEM_FIELD__SPI2_CR1_BR
// - SFDITEM_FIELD__SPI2_CR1_SPE
// - SFDITEM_FIELD__SPI2_CR1_LSBFIRST
// - SFDITEM_FIELD__SPI2_CR1_SSI
// - SFDITEM_FIELD__SPI2_CR1_SSM
// - SFDITEM_FIELD__SPI2_CR1_RXONLY
// - SFDITEM_FIELD__SPI2_CR1_DFF
// - SFDITEM_FIELD__SPI2_CR1_CRCNEXT
// - SFDITEM_FIELD__SPI2_CR1_CRCEN
// - SFDITEM_FIELD__SPI2_CR1_BIDIOE
// - SFDITEM_FIELD__SPI2_CR1_BIDIMODE
//
//
// ----------------------------- Register Item Address: SPI2_CR2 --------------------------------
// SVD Line: 5832
unsigned int SPI2_CR2 __AT (0x40003804);
// ------------------------------ Field Item: SPI2_CR2_RXDMAEN ----------------------------------
// SVD Line: 5837
// - SFDITEM_FIELD__SPI2_CR2_RXDMAEN
// RXDMAEN
//
// [Bit 0] RW (@ 0x40003804) Rx buffer DMA enable
//
// ( (unsigned int) SPI2_CR2 )
// RXDMAEN
//
//
//
// ------------------------------ Field Item: SPI2_CR2_TXDMAEN ----------------------------------
// SVD Line: 5842
// - SFDITEM_FIELD__SPI2_CR2_TXDMAEN
// TXDMAEN
//
// [Bit 1] RW (@ 0x40003804) Tx buffer DMA enable
//
// ( (unsigned int) SPI2_CR2 )
// TXDMAEN
//
//
//
// -------------------------------- Field Item: SPI2_CR2_SSOE -----------------------------------
// SVD Line: 5847
// - SFDITEM_FIELD__SPI2_CR2_SSOE
// SSOE
//
// [Bit 2] RW (@ 0x40003804) SS Output Enable
//
// ( (unsigned int) SPI2_CR2 )
// SSOE
//
//
//
// ----------------------------- Field Item: SPI2_CR2_CLRTXFIFO ---------------------------------
// SVD Line: 5852
// - SFDITEM_FIELD__SPI2_CR2_CLRTXFIFO
// CLRTXFIFO
//
// [Bit 4] RW (@ 0x40003804) Clear FIFO
//
// ( (unsigned int) SPI2_CR2 )
// CLRTXFIFO
//
//
//
// ------------------------------- Field Item: SPI2_CR2_ERRIE -----------------------------------
// SVD Line: 5857
// - SFDITEM_FIELD__SPI2_CR2_ERRIE
// ERRIE
//
// [Bit 5] RW (@ 0x40003804) Error Interrupt Enable
//
// ( (unsigned int) SPI2_CR2 )
// ERRIE
//
//
//
// ------------------------------- Field Item: SPI2_CR2_RXNEIE ----------------------------------
// SVD Line: 5862
// - SFDITEM_FIELD__SPI2_CR2_RXNEIE
// RXNEIE
//
// [Bit 6] RW (@ 0x40003804) RX buffer Not Empty Interrupt Enable
//
// ( (unsigned int) SPI2_CR2 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: SPI2_CR2_TXEIE -----------------------------------
// SVD Line: 5867
// - SFDITEM_FIELD__SPI2_CR2_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x40003804) Tx buffer Empty Interrupt Enable
//
// ( (unsigned int) SPI2_CR2 )
// TXEIE
//
//
//
// -------------------------------- Field Item: SPI2_CR2_FRF ------------------------------------
// SVD Line: 5872
// - SFDITEM_FIELD__SPI2_CR2_FRF
// FRF
//
// [Bit 15] RW (@ 0x40003804) FRF
//
// ( (unsigned int) SPI2_CR2 )
// FRF
//
//
//
// -------------------------------- Register RTree: SPI2_CR2 ------------------------------------
// SVD Line: 5832
// SFDITEM_REG__SPI2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40003804) control register 2
// ( (unsigned int)((SPI2_CR2 >> 0) & 0xFFFFFFFF), ((SPI2_CR2 = (SPI2_CR2 & ~(0x80F7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80F7) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CR2_RXDMAEN
// - SFDITEM_FIELD__SPI2_CR2_TXDMAEN
// - SFDITEM_FIELD__SPI2_CR2_SSOE
// - SFDITEM_FIELD__SPI2_CR2_CLRTXFIFO
// - SFDITEM_FIELD__SPI2_CR2_ERRIE
// - SFDITEM_FIELD__SPI2_CR2_RXNEIE
// - SFDITEM_FIELD__SPI2_CR2_TXEIE
// - SFDITEM_FIELD__SPI2_CR2_FRF
//
//
// ----------------------------- Register Item Address: SPI2_SR ---------------------------------
// SVD Line: 5878
unsigned int SPI2_SR __AT (0x40003808);
// -------------------------------- Field Item: SPI2_SR_RXNE ------------------------------------
// SVD Line: 5883
// - SFDITEM_FIELD__SPI2_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40003808) Receive buffer Not Empty
//
// ( (unsigned int) SPI2_SR )
// RXNE
//
//
//
// --------------------------------- Field Item: SPI2_SR_TXE ------------------------------------
// SVD Line: 5889
// - SFDITEM_FIELD__SPI2_SR_TXE
// TXE
//
// [Bit 1] RO (@ 0x40003808) Transmit buffer Empty
//
// ( (unsigned int) SPI2_SR )
// TXE
//
//
//
// ------------------------------- Field Item: SPI2_SR_CHSIDE -----------------------------------
// SVD Line: 5895
// - SFDITEM_FIELD__SPI2_SR_CHSIDE
// CHSIDE
//
// [Bit 2] RO (@ 0x40003808) Channel side
//
// ( (unsigned int) SPI2_SR )
// CHSIDE
//
//
//
// --------------------------------- Field Item: SPI2_SR_UDR ------------------------------------
// SVD Line: 5901
// - SFDITEM_FIELD__SPI2_SR_UDR
// UDR
//
// [Bit 3] RO (@ 0x40003808) Underrun flag
//
// ( (unsigned int) SPI2_SR )
// UDR
//
//
//
// ------------------------------- Field Item: SPI2_SR_CRCERR -----------------------------------
// SVD Line: 5907
// - SFDITEM_FIELD__SPI2_SR_CRCERR
// CRCERR
//
// [Bit 4] RW (@ 0x40003808) CRC error flag
//
// ( (unsigned int) SPI2_SR )
// CRCERR
//
//
//
// -------------------------------- Field Item: SPI2_SR_MODF ------------------------------------
// SVD Line: 5912
// - SFDITEM_FIELD__SPI2_SR_MODF
// MODF
//
// [Bit 5] RW (@ 0x40003808) Mode fault
//
// ( (unsigned int) SPI2_SR )
// MODF
//
//
//
// --------------------------------- Field Item: SPI2_SR_OVR ------------------------------------
// SVD Line: 5917
// - SFDITEM_FIELD__SPI2_SR_OVR
// OVR
//
// [Bit 6] RO (@ 0x40003808) Overrun flag
//
// ( (unsigned int) SPI2_SR )
// OVR
//
//
//
// --------------------------------- Field Item: SPI2_SR_BSY ------------------------------------
// SVD Line: 5923
// - SFDITEM_FIELD__SPI2_SR_BSY
// BSY
//
// [Bit 7] RO (@ 0x40003808) Busy flag
//
// ( (unsigned int) SPI2_SR )
// BSY
//
//
//
// --------------------------------- Field Item: SPI2_SR_FRE ------------------------------------
// SVD Line: 5929
// - SFDITEM_FIELD__SPI2_SR_FRE
// FRE
//
// [Bit 8] RO (@ 0x40003808) FRE
//
// ( (unsigned int) SPI2_SR )
// FRE
//
//
//
// -------------------------------- Field Item: SPI2_SR_FRLVL -----------------------------------
// SVD Line: 5934
// - SFDITEM_FIELD__SPI2_SR_FRLVL
// FRLVL
//
// [Bits 10..9] RO (@ 0x40003808) FIFO Reception Level
//
// ( (unsigned char)((SPI2_SR >> 9) & 0x3) )
//
//
//
// -------------------------------- Field Item: SPI2_SR_FTLVL -----------------------------------
// SVD Line: 5940
// - SFDITEM_FIELD__SPI2_SR_FTLVL
// FTLVL
//
// [Bits 12..11] RO (@ 0x40003808) FIFO Transmission Level
//
// ( (unsigned char)((SPI2_SR >> 11) & 0x3) )
//
//
//
// --------------------------------- Register RTree: SPI2_SR ------------------------------------
// SVD Line: 5878
// SFDITEM_REG__SPI2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40003808) status register
// ( (unsigned int)((SPI2_SR >> 0) & 0xFFFFFFFF), ((SPI2_SR = (SPI2_SR & ~(0x30UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_SR_RXNE
// - SFDITEM_FIELD__SPI2_SR_TXE
// - SFDITEM_FIELD__SPI2_SR_CHSIDE
// - SFDITEM_FIELD__SPI2_SR_UDR
// - SFDITEM_FIELD__SPI2_SR_CRCERR
// - SFDITEM_FIELD__SPI2_SR_MODF
// - SFDITEM_FIELD__SPI2_SR_OVR
// - SFDITEM_FIELD__SPI2_SR_BSY
// - SFDITEM_FIELD__SPI2_SR_FRE
// - SFDITEM_FIELD__SPI2_SR_FRLVL
// - SFDITEM_FIELD__SPI2_SR_FTLVL
//
//
// ----------------------------- Register Item Address: SPI2_DR ---------------------------------
// SVD Line: 5948
unsigned int SPI2_DR __AT (0x4000380C);
// --------------------------------- Field Item: SPI2_DR_DR -------------------------------------
// SVD Line: 5953
// - SFDITEM_FIELD__SPI2_DR_DR
// DR
//
// [Bits 15..0] RW (@ 0x4000380C) Data Register
//
// ( (unsigned short)((SPI2_DR >> 0) & 0xFFFF), ((SPI2_DR = (SPI2_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: SPI2_DR ------------------------------------
// SVD Line: 5948
// SFDITEM_REG__SPI2_DR
// DR
//
// [Bits 31..0] RW (@ 0x4000380C) data register
// ( (unsigned int)((SPI2_DR >> 0) & 0xFFFFFFFF), ((SPI2_DR = (SPI2_DR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_DR_DR
//
//
// ---------------------------- Register Item Address: SPI2_CRCPR -------------------------------
// SVD Line: 5960
unsigned int SPI2_CRCPR __AT (0x40003810);
// ----------------------------- Field Item: SPI2_CRCPR_CRCPOLY ---------------------------------
// SVD Line: 5965
// - SFDITEM_FIELD__SPI2_CRCPR_CRCPOLY
// CRCPOLY
//
// [Bits 15..0] RW (@ 0x40003810) CRC polynomial register
//
// ( (unsigned short)((SPI2_CRCPR >> 0) & 0xFFFF), ((SPI2_CRCPR = (SPI2_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI2_CRCPR -----------------------------------
// SVD Line: 5960
// SFDITEM_REG__SPI2_CRCPR
// CRCPR
//
// [Bits 31..0] RW (@ 0x40003810) CRC polynomial register
// ( (unsigned int)((SPI2_CRCPR >> 0) & 0xFFFFFFFF), ((SPI2_CRCPR = (SPI2_CRCPR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_CRCPR_CRCPOLY
//
//
// --------------------------- Register Item Address: SPI2_RXCRCR -------------------------------
// SVD Line: 5972
unsigned int SPI2_RXCRCR __AT (0x40003814);
// ------------------------------ Field Item: SPI2_RXCRCR_RXCRC ---------------------------------
// SVD Line: 5976
// - SFDITEM_FIELD__SPI2_RXCRCR_RXCRC
// RXCRC
//
// [Bits 15..0] RW (@ 0x40003814) rcv crc reg
//
// ( (unsigned short)((SPI2_RXCRCR >> 0) & 0xFFFF), ((SPI2_RXCRCR = (SPI2_RXCRCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: SPI2_RXCRCR ----------------------------------
// SVD Line: 5972
// SFDITEM_REG__SPI2_RXCRCR
// RXCRCR
//
// [Bits 31..0] RW (@ 0x40003814) RXCRCR
// ( (unsigned int)((SPI2_RXCRCR >> 0) & 0xFFFFFFFF), ((SPI2_RXCRCR = (SPI2_RXCRCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_RXCRCR_RXCRC
//
//
// --------------------------- Register Item Address: SPI2_TXCRCR -------------------------------
// SVD Line: 5983
unsigned int SPI2_TXCRCR __AT (0x40003818);
// ------------------------------ Field Item: SPI2_TXCRCR_TXCRC ---------------------------------
// SVD Line: 5987
// - SFDITEM_FIELD__SPI2_TXCRCR_TXCRC
// TXCRC
//
// [Bits 15..0] RO (@ 0x40003818) tx crc reg
//
// ( (unsigned short)((SPI2_TXCRCR >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: SPI2_TXCRCR ----------------------------------
// SVD Line: 5983
// SFDITEM_REG__SPI2_TXCRCR
// TXCRCR
//
// [Bits 31..0] RW (@ 0x40003818) TXCRCR
// ( (unsigned int)((SPI2_TXCRCR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__SPI2_TXCRCR_TXCRC
//
//
// -------------------------- Register Item Address: SPI2_I2S_CFGR ------------------------------
// SVD Line: 5995
unsigned int SPI2_I2S_CFGR __AT (0x4000381C);
// ----------------------------- Field Item: SPI2_I2S_CFGR_CHLEN --------------------------------
// SVD Line: 5999
// - SFDITEM_FIELD__SPI2_I2S_CFGR_CHLEN
// CHLEN
//
// [Bit 0] RW (@ 0x4000381C) Channel length (number of bits per audio channel)
//
// ( (unsigned int) SPI2_I2S_CFGR )
// CHLEN
//
//
//
// ---------------------------- Field Item: SPI2_I2S_CFGR_DATLEN --------------------------------
// SVD Line: 6004
// - SFDITEM_FIELD__SPI2_I2S_CFGR_DATLEN
// DATLEN
//
// [Bits 2..1] RW (@ 0x4000381C) Data length to be transferred
//
// ( (unsigned char)((SPI2_I2S_CFGR >> 1) & 0x3), ((SPI2_I2S_CFGR = (SPI2_I2S_CFGR & ~(0x3UL << 1 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 1 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI2_I2S_CFGR_CKPOL --------------------------------
// SVD Line: 6009
// - SFDITEM_FIELD__SPI2_I2S_CFGR_CKPOL
// CKPOL
//
// [Bit 3] RW (@ 0x4000381C) Steady state clock polarity
//
// ( (unsigned int) SPI2_I2S_CFGR )
// CKPOL
//
//
//
// ---------------------------- Field Item: SPI2_I2S_CFGR_I2SSTD --------------------------------
// SVD Line: 6014
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SSTD
// I2SSTD
//
// [Bits 5..4] RW (@ 0x4000381C) I2S standard selection
//
// ( (unsigned char)((SPI2_I2S_CFGR >> 4) & 0x3), ((SPI2_I2S_CFGR = (SPI2_I2S_CFGR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: SPI2_I2S_CFGR_PCMSYNC -------------------------------
// SVD Line: 6019
// - SFDITEM_FIELD__SPI2_I2S_CFGR_PCMSYNC
// PCMSYNC
//
// [Bit 7] RW (@ 0x4000381C) PCM frame synchronization
//
// ( (unsigned int) SPI2_I2S_CFGR )
// PCMSYNC
//
//
//
// ---------------------------- Field Item: SPI2_I2S_CFGR_I2SCFG --------------------------------
// SVD Line: 6024
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SCFG
// I2SCFG
//
// [Bits 9..8] RW (@ 0x4000381C) I2S configuration mode
//
// ( (unsigned char)((SPI2_I2S_CFGR >> 8) & 0x3), ((SPI2_I2S_CFGR = (SPI2_I2S_CFGR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: SPI2_I2S_CFGR_I2SE ---------------------------------
// SVD Line: 6029
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SE
// I2SE
//
// [Bit 10] RW (@ 0x4000381C) I2S enable
//
// ( (unsigned int) SPI2_I2S_CFGR )
// I2SE
//
//
//
// ---------------------------- Field Item: SPI2_I2S_CFGR_I2SMOD --------------------------------
// SVD Line: 6034
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SMOD
// I2SMOD
//
// [Bit 11] RW (@ 0x4000381C) I2S mode selection
//
// ( (unsigned int) SPI2_I2S_CFGR )
// I2SMOD
//
//
//
// ------------------------------ Register RTree: SPI2_I2S_CFGR ---------------------------------
// SVD Line: 5995
// SFDITEM_REG__SPI2_I2S_CFGR
// I2S_CFGR
//
// [Bits 31..0] RW (@ 0x4000381C) I2S_CFGR
// ( (unsigned int)((SPI2_I2S_CFGR >> 0) & 0xFFFFFFFF), ((SPI2_I2S_CFGR = (SPI2_I2S_CFGR & ~(0xFBFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFBF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_I2S_CFGR_CHLEN
// - SFDITEM_FIELD__SPI2_I2S_CFGR_DATLEN
// - SFDITEM_FIELD__SPI2_I2S_CFGR_CKPOL
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SSTD
// - SFDITEM_FIELD__SPI2_I2S_CFGR_PCMSYNC
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SCFG
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SE
// - SFDITEM_FIELD__SPI2_I2S_CFGR_I2SMOD
//
//
// ---------------------------- Register Item Address: SPI2_I2SPR -------------------------------
// SVD Line: 6041
unsigned int SPI2_I2SPR __AT (0x40003820);
// ------------------------------ Field Item: SPI2_I2SPR_I2SDIV ---------------------------------
// SVD Line: 6046
// - SFDITEM_FIELD__SPI2_I2SPR_I2SDIV
// I2SDIV
//
// [Bits 7..0] RW (@ 0x40003820) I2S linear prescaler
//
// ( (unsigned char)((SPI2_I2SPR >> 0) & 0xFF), ((SPI2_I2SPR = (SPI2_I2SPR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: SPI2_I2SPR_ODD -----------------------------------
// SVD Line: 6051
// - SFDITEM_FIELD__SPI2_I2SPR_ODD
// ODD
//
// [Bit 8] RW (@ 0x40003820) Odd factor for the prescaler
//
// ( (unsigned int) SPI2_I2SPR )
// ODD
//
//
//
// ------------------------------ Field Item: SPI2_I2SPR_MCKOE ----------------------------------
// SVD Line: 6056
// - SFDITEM_FIELD__SPI2_I2SPR_MCKOE
// MCKOE
//
// [Bit 9] RW (@ 0x40003820) Master clock output enable
//
// ( (unsigned int) SPI2_I2SPR )
// MCKOE
//
//
//
// ------------------------------- Register RTree: SPI2_I2SPR -----------------------------------
// SVD Line: 6041
// SFDITEM_REG__SPI2_I2SPR
// I2SPR
//
// [Bits 31..0] RW (@ 0x40003820) I2S prescaler register
// ( (unsigned int)((SPI2_I2SPR >> 0) & 0xFFFFFFFF), ((SPI2_I2SPR = (SPI2_I2SPR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__SPI2_I2SPR_I2SDIV
// - SFDITEM_FIELD__SPI2_I2SPR_ODD
// - SFDITEM_FIELD__SPI2_I2SPR_MCKOE
//
//
// ---------------------------------- Peripheral View: SPI2 -------------------------------------
// SVD Line: 6065
// SPI2
// SPI2
// - SFDITEM_REG__SPI2_CR1
// - SFDITEM_REG__SPI2_CR2
// - SFDITEM_REG__SPI2_SR
// - SFDITEM_REG__SPI2_DR
// - SFDITEM_REG__SPI2_CRCPR
// - SFDITEM_REG__SPI2_RXCRCR
// - SFDITEM_REG__SPI2_TXCRCR
// - SFDITEM_REG__SPI2_I2S_CFGR
// - SFDITEM_REG__SPI2_I2SPR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR1 ------------------------------
// SVD Line: 6084
unsigned int SYSCFG_CFGR1 __AT (0x40010000);
// ---------------------------- Field Item: SYSCFG_CFGR1_MEM_MODE -------------------------------
// SVD Line: 6089
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// MEM_MODE
//
// [Bits 1..0] RW (@ 0x40010000) MEM_MODE
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 0) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR1_GPIO_AHB_SEL -----------------------------
// SVD Line: 6093
// - SFDITEM_FIELD__SYSCFG_CFGR1_GPIO_AHB_SEL
// GPIO_AHB_SEL
//
// [Bit 24] RW (@ 0x40010000) GPIO_AHB_SEL
//
// ( (unsigned int) SYSCFG_CFGR1 )
// GPIO_AHB_SEL
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR1 ----------------------------------
// SVD Line: 6084
// SFDITEM_REG__SYSCFG_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x40010000) SYSCFG configuration register1
// ( (unsigned int)((SYSCFG_CFGR1 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x1000003UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1000003) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// - SFDITEM_FIELD__SYSCFG_CFGR1_GPIO_AHB_SEL
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 6099
unsigned int SYSCFG_CFGR2 __AT (0x40010004);
// ------------------------------ Field Item: SYSCFG_CFGR2_CLL ----------------------------------
// SVD Line: 6104
// - SFDITEM_FIELD__SYSCFG_CFGR2_CLL
// CLL
//
// [Bit 0] RW (@ 0x40010004) CLL
//
// ( (unsigned int) SYSCFG_CFGR2 )
// CLL
//
//
//
// ------------------------------ Field Item: SYSCFG_CFGR2_PVDL ---------------------------------
// SVD Line: 6108
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVDL
// PVDL
//
// [Bit 2] RW (@ 0x40010004) PVDL
//
// ( (unsigned int) SYSCFG_CFGR2 )
// PVDL
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 6099
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010004) SYSCFG configuration register2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x5) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_CLL
// - SFDITEM_FIELD__SYSCFG_CFGR2_PVDL
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR3 ------------------------------
// SVD Line: 6114
unsigned int SYSCFG_CFGR3 __AT (0x40010008);
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA1_MAP -------------------------------
// SVD Line: 6119
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA1_MAP
// DMA1_MAP
//
// [Bits 5..0] RW (@ 0x40010008) DMA1_MAP
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 0) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA2_MAP -------------------------------
// SVD Line: 6123
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA2_MAP
// DMA2_MAP
//
// [Bits 13..8] RW (@ 0x40010008) DMA2_MAP
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 8) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_CFGR3_DMA3_MAP -------------------------------
// SVD Line: 6127
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA3_MAP
// DMA3_MAP
//
// [Bits 21..16] RW (@ 0x40010008) DMA3_MAP
//
// ( (unsigned char)((SYSCFG_CFGR3 >> 16) & 0x3F), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3FUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 16 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR3 ----------------------------------
// SVD Line: 6114
// SFDITEM_REG__SYSCFG_CFGR3
// CFGR3
//
// [Bits 31..0] RW (@ 0x40010008) SYSCFG configuration register3
// ( (unsigned int)((SYSCFG_CFGR3 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR3 = (SYSCFG_CFGR3 & ~(0x3F3F3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F3F3F) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA1_MAP
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA2_MAP
// - SFDITEM_FIELD__SYSCFG_CFGR3_DMA3_MAP
//
//
// ------------------------ Register Item Address: SYSCFG_PA_ENS_REG ----------------------------
// SVD Line: 6133
unsigned int SYSCFG_PA_ENS_REG __AT (0x40010010);
// -------------------------- Field Item: SYSCFG_PA_ENS_REG_PA_ENS ------------------------------
// SVD Line: 6137
// - SFDITEM_FIELD__SYSCFG_PA_ENS_REG_PA_ENS
// PA_ENS
//
// [Bits 15..0] RW (@ 0x40010010) PA_ENS
//
// ( (unsigned short)((SYSCFG_PA_ENS_REG >> 0) & 0xFFFF), ((SYSCFG_PA_ENS_REG = (SYSCFG_PA_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PA_ENS_REG -------------------------------
// SVD Line: 6133
// SFDITEM_REG__SYSCFG_PA_ENS_REG
// PA_ENS_REG
//
// [Bits 31..0] RW (@ 0x40010010) PA_ENS_REG
// ( (unsigned int)((SYSCFG_PA_ENS_REG >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ENS_REG = (SYSCFG_PA_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ENS_REG_PA_ENS
//
//
// ------------------------ Register Item Address: SYSCFG_PB_ENS_REG ----------------------------
// SVD Line: 6143
unsigned int SYSCFG_PB_ENS_REG __AT (0x40010014);
// -------------------------- Field Item: SYSCFG_PB_ENS_REG_PB_ENS ------------------------------
// SVD Line: 6147
// - SFDITEM_FIELD__SYSCFG_PB_ENS_REG_PB_ENS
// PB_ENS
//
// [Bits 15..0] RW (@ 0x40010014) PB_ENS
//
// ( (unsigned short)((SYSCFG_PB_ENS_REG >> 0) & 0xFFFF), ((SYSCFG_PB_ENS_REG = (SYSCFG_PB_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PB_ENS_REG -------------------------------
// SVD Line: 6143
// SFDITEM_REG__SYSCFG_PB_ENS_REG
// PB_ENS_REG
//
// [Bits 31..0] RW (@ 0x40010014) PB_ENS_REG
// ( (unsigned int)((SYSCFG_PB_ENS_REG >> 0) & 0xFFFFFFFF), ((SYSCFG_PB_ENS_REG = (SYSCFG_PB_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PB_ENS_REG_PB_ENS
//
//
// ------------------------ Register Item Address: SYSCFG_PF_ENS_REG ----------------------------
// SVD Line: 6153
unsigned int SYSCFG_PF_ENS_REG __AT (0x40010018);
// -------------------------- Field Item: SYSCFG_PF_ENS_REG_PF_ENS ------------------------------
// SVD Line: 6157
// - SFDITEM_FIELD__SYSCFG_PF_ENS_REG_PF_ENS
// PF_ENS
//
// [Bits 15..0] RW (@ 0x40010018) PF_ENS
//
// ( (unsigned short)((SYSCFG_PF_ENS_REG >> 0) & 0xFFFF), ((SYSCFG_PF_ENS_REG = (SYSCFG_PF_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ---------------------------- Register RTree: SYSCFG_PF_ENS_REG -------------------------------
// SVD Line: 6153
// SFDITEM_REG__SYSCFG_PF_ENS_REG
// PF_ENS_REG
//
// [Bits 31..0] RW (@ 0x40010018) PF_ENS_REG
// ( (unsigned int)((SYSCFG_PF_ENS_REG >> 0) & 0xFFFFFFFF), ((SYSCFG_PF_ENS_REG = (SYSCFG_PF_ENS_REG & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PF_ENS_REG_PF_ENS
//
//
// --------------------------- Register Item Address: SYSCFG_IOCFG ------------------------------
// SVD Line: 6163
unsigned int SYSCFG_IOCFG __AT (0x4001001C);
// ---------------------------- Field Item: SYSCFG_IOCFG_PA_EIIC --------------------------------
// SVD Line: 6167
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EIIC
// PA_EIIC
//
// [Bits 7..0] RW (@ 0x4001001C) PA_EIIC
//
// ( (unsigned char)((SYSCFG_IOCFG >> 0) & 0xFF), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IOCFG_PB_EIIC --------------------------------
// SVD Line: 6171
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_EIIC
// PB_EIIC
//
// [Bits 10..8] RW (@ 0x4001001C) PB_EIIC
//
// ( (unsigned char)((SYSCFG_IOCFG >> 8) & 0x7), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x7UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: SYSCFG_IOCFG_PF_EIIC --------------------------------
// SVD Line: 6175
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_EIIC
// PF_EIIC
//
// [Bits 12..11] RW (@ 0x4001001C) PF_EIIC
//
// ( (unsigned char)((SYSCFG_IOCFG >> 11) & 0x3), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x3UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 11 ) ) ))
//
//
//
// ----------------------------- Field Item: SYSCFG_IOCFG_PB_EHS --------------------------------
// SVD Line: 6179
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_EHS
// PB_EHS
//
// [Bits 15..13] RW (@ 0x4001001C) PB_EHS
//
// ( (unsigned char)((SYSCFG_IOCFG >> 13) & 0x7), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x7UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 13 ) ) ))
//
//
//
// ----------------------------- Field Item: SYSCFG_IOCFG_PA_EHS --------------------------------
// SVD Line: 6183
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EHS
// PA_EHS
//
// [Bit 24] RW (@ 0x4001001C) PA_EHS
//
// ( (unsigned int) SYSCFG_IOCFG )
// PA_EHS
//
//
//
// --------------------------- Field Item: SYSCFG_IOCFG_PB_PU_EIIC ------------------------------
// SVD Line: 6187
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_PU_EIIC
// PB_PU_EIIC
//
// [Bits 27..25] RW (@ 0x4001001C) PB_PU_EIIC
//
// ( (unsigned char)((SYSCFG_IOCFG >> 25) & 0x7), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x7UL << 25 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 25 ) ) ))
//
//
//
// -------------------------- Field Item: SYSCFG_IOCFG_IIC1_FILT_EN -----------------------------
// SVD Line: 6191
// - SFDITEM_FIELD__SYSCFG_IOCFG_IIC1_FILT_EN
// IIC1_FILT_EN
//
// [Bit 30] RW (@ 0x4001001C) IIC1_FILT_EN
//
// ( (unsigned int) SYSCFG_IOCFG )
// IIC1_FILT_EN
//
//
//
// ------------------------------ Register RTree: SYSCFG_IOCFG ----------------------------------
// SVD Line: 6163
// SFDITEM_REG__SYSCFG_IOCFG
// IOCFG
//
// [Bits 31..0] RW (@ 0x4001001C) IOCFG
// ( (unsigned int)((SYSCFG_IOCFG >> 0) & 0xFFFFFFFF), ((SYSCFG_IOCFG = (SYSCFG_IOCFG & ~(0x4F00FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4F00FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PF_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_EHS
// - SFDITEM_FIELD__SYSCFG_IOCFG_PA_EHS
// - SFDITEM_FIELD__SYSCFG_IOCFG_PB_PU_EIIC
// - SFDITEM_FIELD__SYSCFG_IOCFG_IIC1_FILT_EN
//
//
// ------------------------- Register Item Address: SYSCFG_PA_ANA2EN ----------------------------
// SVD Line: 6197
unsigned int SYSCFG_PA_ANA2EN __AT (0x40010020);
// ------------------------- Field Item: SYSCFG_PA_ANA2EN_PA9_ANA2EN ----------------------------
// SVD Line: 6201
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA9_ANA2EN
// PA9_ANA2EN
//
// [Bit 9] RW (@ 0x40010020) PA9_ANA2EN
//
// ( (unsigned int) SYSCFG_PA_ANA2EN )
// PA9_ANA2EN
//
//
//
// ------------------------ Field Item: SYSCFG_PA_ANA2EN_PA10_ANA2EN ----------------------------
// SVD Line: 6205
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA10_ANA2EN
// PA10_ANA2EN
//
// [Bit 10] RW (@ 0x40010020) PA10_ANA2EN
//
// ( (unsigned int) SYSCFG_PA_ANA2EN )
// PA10_ANA2EN
//
//
//
// ---------------------------- Register RTree: SYSCFG_PA_ANA2EN --------------------------------
// SVD Line: 6197
// SFDITEM_REG__SYSCFG_PA_ANA2EN
// PA_ANA2EN
//
// [Bits 31..0] RW (@ 0x40010020) PA_ANA2EN
// ( (unsigned int)((SYSCFG_PA_ANA2EN >> 0) & 0xFFFFFFFF), ((SYSCFG_PA_ANA2EN = (SYSCFG_PA_ANA2EN & ~(0x600UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x600) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA9_ANA2EN
// - SFDITEM_FIELD__SYSCFG_PA_ANA2EN_PA10_ANA2EN
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 6074
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR1
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_CFGR3
// - SFDITEM_REG__SYSCFG_PA_ENS_REG
// - SFDITEM_REG__SYSCFG_PB_ENS_REG
// - SFDITEM_REG__SYSCFG_PF_ENS_REG
// - SFDITEM_REG__SYSCFG_IOCFG
// - SFDITEM_REG__SYSCFG_PA_ANA2EN
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 6234
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 6239
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) CEN
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 6243
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) UDIS
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 6247
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) URS
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 6251
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) OPM
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 6255
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) DIR
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 6259
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) CMS
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 6263
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) ARPE
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 6267
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) CKD
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 6234
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) control register 1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 6273
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 6278
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) CCPC
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 6282
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) CCUS
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCDS -----------------------------------
// SVD Line: 6286
// - SFDITEM_FIELD__TIM1_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40012C04) CCDS
//
// ( (unsigned int) TIM1_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM1_CR2_MMS_L -----------------------------------
// SVD Line: 6290
// - SFDITEM_FIELD__TIM1_CR2_MMS_L
// MMS_L
//
// [Bits 6..4] RW (@ 0x40012C04) MMS_L
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 6294
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) TI1S
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 6298
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) OIS1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 6302
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) OIS1N
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 6306
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) OIS2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 6310
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) OIS2N
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 6314
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) OIS3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 6318
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) OIS3N
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 6322
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) OIS4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS5 -----------------------------------
// SVD Line: 6326
// - SFDITEM_FIELD__TIM1_CR2_OIS5
// OIS5
//
// [Bit 16] RW (@ 0x40012C04) OIS5
//
// ( (unsigned int) TIM1_CR2 )
// OIS5
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS6 -----------------------------------
// SVD Line: 6330
// - SFDITEM_FIELD__TIM1_CR2_OIS6
// OIS6
//
// [Bit 18] RW (@ 0x40012C04) OIS6
//
// ( (unsigned int) TIM1_CR2 )
// OIS6
//
//
//
// ------------------------------- Field Item: TIM1_CR2_MMS_H -----------------------------------
// SVD Line: 6334
// - SFDITEM_FIELD__TIM1_CR2_MMS_H
// MMS_H
//
// [Bit 25] RW (@ 0x40012C04) MMS_H
//
// ( (unsigned int) TIM1_CR2 )
// MMS_H
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 6273
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) control register 2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x2057FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2057FFD) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_CCDS
// - SFDITEM_FIELD__TIM1_CR2_MMS_L
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// - SFDITEM_FIELD__TIM1_CR2_OIS5
// - SFDITEM_FIELD__TIM1_CR2_OIS6
// - SFDITEM_FIELD__TIM1_CR2_MMS_H
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 6340
unsigned int TIM1_SMCR __AT (0x40012C08);
// ------------------------------- Field Item: TIM1_SMCR_SMS_L ----------------------------------
// SVD Line: 6345
// - SFDITEM_FIELD__TIM1_SMCR_SMS_L
// SMS_L
//
// [Bits 2..0] RW (@ 0x40012C08) SMS_L
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 6349
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) OCCS
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_TS_L -----------------------------------
// SVD Line: 6353
// - SFDITEM_FIELD__TIM1_SMCR_TS_L
// TS_L
//
// [Bits 6..4] RW (@ 0x40012C08) TS_L
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 6357
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) MSM
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 6361
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) ETF
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 6365
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) ETPS
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 6369
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) ECE
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 6373
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) ETP
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_SMS_H ----------------------------------
// SVD Line: 6377
// - SFDITEM_FIELD__TIM1_SMCR_SMS_H
// SMS_H
//
// [Bit 16] RW (@ 0x40012C08) SMS_H
//
// ( (unsigned int) TIM1_SMCR )
// SMS_H
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_TS_H -----------------------------------
// SVD Line: 6381
// - SFDITEM_FIELD__TIM1_SMCR_TS_H
// TS_H
//
// [Bits 21..20] RW (@ 0x40012C08) TS_H
//
// ( (unsigned char)((TIM1_SMCR >> 20) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 6340
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) slave mode control register
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0x31FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x31FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS_L
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS_L
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// - SFDITEM_FIELD__TIM1_SMCR_SMS_H
// - SFDITEM_FIELD__TIM1_SMCR_TS_H
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 6387
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 6392
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) UIE
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 6396
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) CC1IE
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 6400
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) CC2IE
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 6404
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) CC3IE
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 6408
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) CC4IE
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 6412
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) COMIE
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 6416
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) TIE
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 6420
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) BIE
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_UDE -----------------------------------
// SVD Line: 6424
// - SFDITEM_FIELD__TIM1_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x40012C0C) UDE
//
// ( (unsigned int) TIM1_DIER )
// UDE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1DE ----------------------------------
// SVD Line: 6428
// - SFDITEM_FIELD__TIM1_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x40012C0C) CC1DE
//
// ( (unsigned int) TIM1_DIER )
// CC1DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2DE ----------------------------------
// SVD Line: 6432
// - SFDITEM_FIELD__TIM1_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x40012C0C) CC2DE
//
// ( (unsigned int) TIM1_DIER )
// CC2DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3DE ----------------------------------
// SVD Line: 6436
// - SFDITEM_FIELD__TIM1_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x40012C0C) CC3DE
//
// ( (unsigned int) TIM1_DIER )
// CC3DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4DE ----------------------------------
// SVD Line: 6440
// - SFDITEM_FIELD__TIM1_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x40012C0C) CC4DE
//
// ( (unsigned int) TIM1_DIER )
// CC4DE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMDE ----------------------------------
// SVD Line: 6444
// - SFDITEM_FIELD__TIM1_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x40012C0C) COMDE
//
// ( (unsigned int) TIM1_DIER )
// COMDE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TDE -----------------------------------
// SVD Line: 6448
// - SFDITEM_FIELD__TIM1_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x40012C0C) TDE
//
// ( (unsigned int) TIM1_DIER )
// TDE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 6387
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) DMA/Interrupt enable register
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
// - SFDITEM_FIELD__TIM1_DIER_UDE
// - SFDITEM_FIELD__TIM1_DIER_CC1DE
// - SFDITEM_FIELD__TIM1_DIER_CC2DE
// - SFDITEM_FIELD__TIM1_DIER_CC3DE
// - SFDITEM_FIELD__TIM1_DIER_CC4DE
// - SFDITEM_FIELD__TIM1_DIER_COMDE
// - SFDITEM_FIELD__TIM1_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 6454
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 6459
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) UIF
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 6463
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) CC1IF
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 6467
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) CC2IF
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 6471
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) CC3IF
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 6475
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) CC4IF
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 6479
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) COMIF
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 6483
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) TIF
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 6487
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) BIF
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_B2IF ------------------------------------
// SVD Line: 6491
// - SFDITEM_FIELD__TIM1_SR_B2IF
// B2IF
//
// [Bit 8] RW (@ 0x40012C10) B2IF
//
// ( (unsigned int) TIM1_SR )
// B2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 6495
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) CC1OF
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 6499
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) CC2OF
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 6503
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) CC3OF
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 6507
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) CC4OF
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_SBIF ------------------------------------
// SVD Line: 6511
// - SFDITEM_FIELD__TIM1_SR_SBIF
// SBIF
//
// [Bit 13] RW (@ 0x40012C10) SBIF
//
// ( (unsigned int) TIM1_SR )
// SBIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC5IF -----------------------------------
// SVD Line: 6515
// - SFDITEM_FIELD__TIM1_SR_CC5IF
// CC5IF
//
// [Bit 16] RW (@ 0x40012C10) CC5IF
//
// ( (unsigned int) TIM1_SR )
// CC5IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC6IF -----------------------------------
// SVD Line: 6519
// - SFDITEM_FIELD__TIM1_SR_CC6IF
// CC6IF
//
// [Bit 17] RW (@ 0x40012C10) CC6IF
//
// ( (unsigned int) TIM1_SR )
// CC6IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 6523
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 18] RW (@ 0x40012C10) IC1IR
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 6527
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 19] RW (@ 0x40012C10) IC2IR
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 6531
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 24] RW (@ 0x40012C10) IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 6535
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 25] RW (@ 0x40012C10) IC4IR
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 6539
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 26] RW (@ 0x40012C10) IC1IF
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 6543
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 27] RW (@ 0x40012C10) IC2IF
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 6547
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 28] RW (@ 0x40012C10) IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 6551
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 29] RW (@ 0x40012C10) IC4IF
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 6454
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) status register
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0x3F0F3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_B2IF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_SBIF
// - SFDITEM_FIELD__TIM1_SR_CC5IF
// - SFDITEM_FIELD__TIM1_SR_CC6IF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 6557
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 6562
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40012C14) UG
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 6566
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40012C14) CC1G
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 6570
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40012C14) CC2G
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 6574
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40012C14) CC3G
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 6578
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40012C14) CC4G
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 6582
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40012C14) COMG
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 6586
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40012C14) TG
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 6590
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40012C14) BG
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 6557
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40012C14) event generation register
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_OUTPUT ----------------------------
// SVD Line: 6596
unsigned int TIM1_CCMR1_OUTPUT __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 6600
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) CC1S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 0) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 6604
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) OC1FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 6608
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) OC1PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1PE
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M_L ------------------------------
// SVD Line: 6612
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_L
// OC1M_L
//
// [Bits 6..4] RW (@ 0x40012C18) OC1M_L
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 4) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 6616
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) OC1CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 6620
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) CC2S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 8) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 6624
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) OC2FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 6628
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) OC2PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2PE
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M_L ------------------------------
// SVD Line: 6632
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_L
// OC2M_L
//
// [Bits 14..12] RW (@ 0x40012C18) OC2M_L
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 12) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 6636
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) OC2CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M_H ------------------------------
// SVD Line: 6640
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_H
// OC1M_H
//
// [Bit 16] RW (@ 0x40012C18) OC1M_H
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1M_H
//
//
//
// -------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M_H ------------------------------
// SVD Line: 6644
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_H
// OC2M_H
//
// [Bit 24] RW (@ 0x40012C18) OC2M_H
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2M_H
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_OUTPUT -------------------------------
// SVD Line: 6596
// SFDITEM_REG__TIM1_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C18) CCMR1_OUTPUT
// ( (unsigned int)((TIM1_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_L
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_L
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M_H
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M_H
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_INPUT ----------------------------
// SVD Line: 6650
unsigned int TIM1_CCMR1_INPUT __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 6655
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) CC1S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 0) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 6659
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40012C18) IC1PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 2) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 6663
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) IC1F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 4) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 6667
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) CC2S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 8) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 6671
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) IC2PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 10) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 6675
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) IC2F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 12) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_INPUT --------------------------------
// SVD Line: 6650
// SFDITEM_REG__TIM1_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40012C18) CCMR1_INPUT
// ( (unsigned int)((TIM1_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_OUTPUT ----------------------------
// SVD Line: 6681
unsigned int TIM1_CCMR2_OUTPUT __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 6685
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) CC3S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 0) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 6689
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) OC3FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 6693
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) OC3PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3PE
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M_L ------------------------------
// SVD Line: 6697
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_L
// OC3M_L
//
// [Bits 6..4] RW (@ 0x40012C1C) OC3M_L
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 4) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 6701
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) OC3CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 6705
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) CC4S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 8) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 6709
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) OC4FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 6713
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) OC4PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4PE
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M_L ------------------------------
// SVD Line: 6717
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_L
// OC4M_L
//
// [Bits 14..12] RW (@ 0x40012C1C) OC4M_L
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 12) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 6721
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) OC4CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4CE
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M_H ------------------------------
// SVD Line: 6725
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_H
// OC3M_H
//
// [Bit 16] RW (@ 0x40012C1C) OC3M_H
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3M_H
//
//
//
// -------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M_H ------------------------------
// SVD Line: 6729
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_H
// OC4M_H
//
// [Bit 24] RW (@ 0x40012C1C) OC4M_H
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4M_H
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_OUTPUT -------------------------------
// SVD Line: 6681
// SFDITEM_REG__TIM1_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) CCMR2_OUTPUT
// ( (unsigned int)((TIM1_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_L
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_L
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M_H
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M_H
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_INPUT ----------------------------
// SVD Line: 6735
unsigned int TIM1_CCMR2_INPUT __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 6740
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) CC3S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 0) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 6744
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) IC3PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 2) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 6748
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) IC3F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 4) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 6752
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) CC4S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 8) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 6756
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) IC4PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 10) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 6760
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) IC4F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 12) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_INPUT --------------------------------
// SVD Line: 6735
// SFDITEM_REG__TIM1_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) CCMR2_INPUT
// ( (unsigned int)((TIM1_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 6766
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 6771
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) CC1E
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 6775
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) CC1P
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 6779
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) CC1NE
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 6783
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) CC1NP
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 6787
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) CC2E
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 6791
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) CC2P
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 6795
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) CC2NE
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 6799
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) CC2NP
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 6803
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) CC3E
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 6807
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) CC3P
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 6811
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) CC3NE
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 6815
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) CC3NP
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 6819
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) CC4E
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 6823
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) CC4P
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4NP ----------------------------------
// SVD Line: 6827
// - SFDITEM_FIELD__TIM1_CCER_CC4NP
// CC4NP
//
// [Bit 15] RW (@ 0x40012C20) CC4NP
//
// ( (unsigned int) TIM1_CCER )
// CC4NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC5E -----------------------------------
// SVD Line: 6831
// - SFDITEM_FIELD__TIM1_CCER_CC5E
// CC5E
//
// [Bit 16] RW (@ 0x40012C20) CC5E
//
// ( (unsigned int) TIM1_CCER )
// CC5E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC5P -----------------------------------
// SVD Line: 6835
// - SFDITEM_FIELD__TIM1_CCER_CC5P
// CC5P
//
// [Bit 17] RW (@ 0x40012C20) CC5P
//
// ( (unsigned int) TIM1_CCER )
// CC5P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC6E -----------------------------------
// SVD Line: 6839
// - SFDITEM_FIELD__TIM1_CCER_CC6E
// CC6E
//
// [Bit 20] RW (@ 0x40012C20) CC6E
//
// ( (unsigned int) TIM1_CCER )
// CC6E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC6P -----------------------------------
// SVD Line: 6843
// - SFDITEM_FIELD__TIM1_CCER_CC6P
// CC6P
//
// [Bit 21] RW (@ 0x40012C20) CC6P
//
// ( (unsigned int) TIM1_CCER )
// CC6P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 6766
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) capture/compare enableregister
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x33BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// - SFDITEM_FIELD__TIM1_CCER_CC4NP
// - SFDITEM_FIELD__TIM1_CCER_CC5E
// - SFDITEM_FIELD__TIM1_CCER_CC5P
// - SFDITEM_FIELD__TIM1_CCER_CC6E
// - SFDITEM_FIELD__TIM1_CCER_CC6P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 6849
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 6854
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) CNT
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 6849
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) counter
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 6860
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 6865
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) PSC
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 6860
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) prescaler
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 6871
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 6876
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) ARR
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 6871
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) auto-reload register
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 6882
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 6887
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) REP
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 6882
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) repetition counter register
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 6893
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 6898
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) CCR1
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR1_CCR1_H ----------------------------------
// SVD Line: 6902
// - SFDITEM_FIELD__TIM1_CCR1_CCR1_H
// CCR1_H
//
// [Bits 31..16] RW (@ 0x40012C34) CCR1_H
//
// ( (unsigned short)((TIM1_CCR1 >> 16) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 6893
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) capture/compare register 1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// - SFDITEM_FIELD__TIM1_CCR1_CCR1_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 6908
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 6913
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) CCR2
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR2_CCR2_H ----------------------------------
// SVD Line: 6917
// - SFDITEM_FIELD__TIM1_CCR2_CCR2_H
// CCR2_H
//
// [Bits 31..16] RW (@ 0x40012C38) CCR2_H
//
// ( (unsigned short)((TIM1_CCR2 >> 16) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 6908
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) capture/compare register 2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// - SFDITEM_FIELD__TIM1_CCR2_CCR2_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 6923
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 6928
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) CCR3
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCR3_CCR3_H ----------------------------------
// SVD Line: 6932
// - SFDITEM_FIELD__TIM1_CCR3_CCR3_H
// CCR3_H
//
// [Bits 31..16] RW (@ 0x40012C3C) CCR3_H
//
// ( (unsigned short)((TIM1_CCR3 >> 16) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 6923
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) capture/compare register 3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// - SFDITEM_FIELD__TIM1_CCR3_CCR3_H
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 6938
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 6943
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) CCR4
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 6938
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) capture/compare register 4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 6949
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 6954
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) DTG
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 6958
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) LOCK
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 6962
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) OSSI
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 6966
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) OSSR
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 6970
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) BKE
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 6974
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) BKP
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 6978
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) AOE
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 6982
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) MOE
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 6949
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) break and dead-time register
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ---------------------------- Register Item Address: TIM1_CCR5 --------------------------------
// SVD Line: 6988
unsigned int TIM1_CCR5 __AT (0x40012C48);
// ------------------------------- Field Item: TIM1_CCR5_CCR5 -----------------------------------
// SVD Line: 6992
// - SFDITEM_FIELD__TIM1_CCR5_CCR5
// CCR5
//
// [Bits 15..0] RW (@ 0x40012C48) CCR5
//
// ( (unsigned short)((TIM1_CCR5 >> 0) & 0xFFFF), ((TIM1_CCR5 = (TIM1_CCR5 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR5 -----------------------------------
// SVD Line: 6988
// SFDITEM_REG__TIM1_CCR5
// CCR5
//
// [Bits 31..0] RW (@ 0x40012C48) CCR5
// ( (unsigned int)((TIM1_CCR5 >> 0) & 0xFFFFFFFF), ((TIM1_CCR5 = (TIM1_CCR5 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR5_CCR5
//
//
// ---------------------------- Register Item Address: TIM1_CCR6 --------------------------------
// SVD Line: 6998
unsigned int TIM1_CCR6 __AT (0x40012C4C);
// ------------------------------- Field Item: TIM1_CCR6_CCR6 -----------------------------------
// SVD Line: 7002
// - SFDITEM_FIELD__TIM1_CCR6_CCR6
// CCR6
//
// [Bits 15..0] RW (@ 0x40012C4C) CCR6
//
// ( (unsigned short)((TIM1_CCR6 >> 0) & 0xFFFF), ((TIM1_CCR6 = (TIM1_CCR6 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR6 -----------------------------------
// SVD Line: 6998
// SFDITEM_REG__TIM1_CCR6
// CCR6
//
// [Bits 31..0] RW (@ 0x40012C4C) CCR6
// ( (unsigned int)((TIM1_CCR6 >> 0) & 0xFFFFFFFF), ((TIM1_CCR6 = (TIM1_CCR6 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR6_CCR6
//
//
// ---------------------------- Register Item Address: TIM1_CCMR3 -------------------------------
// SVD Line: 7008
unsigned int TIM1_CCMR3 __AT (0x40012C50);
// ------------------------------ Field Item: TIM1_CCMR3_OC5FE ----------------------------------
// SVD Line: 7012
// - SFDITEM_FIELD__TIM1_CCMR3_OC5FE
// OC5FE
//
// [Bit 2] RW (@ 0x40012C50) OC5FE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC5FE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC5PE ----------------------------------
// SVD Line: 7016
// - SFDITEM_FIELD__TIM1_CCMR3_OC5PE
// OC5PE
//
// [Bit 3] RW (@ 0x40012C50) OC5PE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC5PE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC5M_L ---------------------------------
// SVD Line: 7020
// - SFDITEM_FIELD__TIM1_CCMR3_OC5M_L
// OC5M_L
//
// [Bits 6..4] RW (@ 0x40012C50) OC5M_L
//
// ( (unsigned char)((TIM1_CCMR3 >> 4) & 0x7), ((TIM1_CCMR3 = (TIM1_CCMR3 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC5CE ----------------------------------
// SVD Line: 7024
// - SFDITEM_FIELD__TIM1_CCMR3_OC5CE
// OC5CE
//
// [Bit 7] RW (@ 0x40012C50) OC5CE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC5CE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC6FE ----------------------------------
// SVD Line: 7028
// - SFDITEM_FIELD__TIM1_CCMR3_OC6FE
// OC6FE
//
// [Bit 10] RW (@ 0x40012C50) OC6FE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC6FE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC6PE ----------------------------------
// SVD Line: 7032
// - SFDITEM_FIELD__TIM1_CCMR3_OC6PE
// OC6PE
//
// [Bit 11] RW (@ 0x40012C50) OC6PE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC6PE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC6M_L ---------------------------------
// SVD Line: 7036
// - SFDITEM_FIELD__TIM1_CCMR3_OC6M_L
// OC6M_L
//
// [Bits 14..12] RW (@ 0x40012C50) OC6M_L
//
// ( (unsigned char)((TIM1_CCMR3 >> 12) & 0x7), ((TIM1_CCMR3 = (TIM1_CCMR3 & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC6CE ----------------------------------
// SVD Line: 7040
// - SFDITEM_FIELD__TIM1_CCMR3_OC6CE
// OC6CE
//
// [Bit 15] RW (@ 0x40012C50) OC6CE
//
// ( (unsigned int) TIM1_CCMR3 )
// OC6CE
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC5M_H ---------------------------------
// SVD Line: 7044
// - SFDITEM_FIELD__TIM1_CCMR3_OC5M_H
// OC5M_H
//
// [Bit 16] RW (@ 0x40012C50) OC5M_H
//
// ( (unsigned int) TIM1_CCMR3 )
// OC5M_H
//
//
//
// ------------------------------ Field Item: TIM1_CCMR3_OC6M_H ---------------------------------
// SVD Line: 7048
// - SFDITEM_FIELD__TIM1_CCMR3_OC6M_H
// OC6M_H
//
// [Bit 24] RW (@ 0x40012C50) OC6M_H
//
// ( (unsigned int) TIM1_CCMR3 )
// OC6M_H
//
//
//
// ------------------------------- Register RTree: TIM1_CCMR3 -----------------------------------
// SVD Line: 7008
// SFDITEM_REG__TIM1_CCMR3
// CCMR3
//
// [Bits 31..0] RW (@ 0x40012C50) CCMR3
// ( (unsigned int)((TIM1_CCMR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCMR3 = (TIM1_CCMR3 & ~(0x101FCFCUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FCFC) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR3_OC5FE
// - SFDITEM_FIELD__TIM1_CCMR3_OC5PE
// - SFDITEM_FIELD__TIM1_CCMR3_OC5M_L
// - SFDITEM_FIELD__TIM1_CCMR3_OC5CE
// - SFDITEM_FIELD__TIM1_CCMR3_OC6FE
// - SFDITEM_FIELD__TIM1_CCMR3_OC6PE
// - SFDITEM_FIELD__TIM1_CCMR3_OC6M_L
// - SFDITEM_FIELD__TIM1_CCMR3_OC6CE
// - SFDITEM_FIELD__TIM1_CCMR3_OC5M_H
// - SFDITEM_FIELD__TIM1_CCMR3_OC6M_H
//
//
// ---------------------------- Register Item Address: TIM1_TISEL -------------------------------
// SVD Line: 7054
unsigned int TIM1_TISEL __AT (0x40012C5C);
// ------------------------------ Field Item: TIM1_TISEL_TI1SEL ---------------------------------
// SVD Line: 7058
// - SFDITEM_FIELD__TIM1_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x40012C5C) TI1SEL
//
// ( (unsigned char)((TIM1_TISEL >> 0) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI2SEL ---------------------------------
// SVD Line: 7062
// - SFDITEM_FIELD__TIM1_TISEL_TI2SEL
// TI2SEL
//
// [Bits 11..8] RW (@ 0x40012C5C) TI2SEL
//
// ( (unsigned char)((TIM1_TISEL >> 8) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI3SEL ---------------------------------
// SVD Line: 7066
// - SFDITEM_FIELD__TIM1_TISEL_TI3SEL
// TI3SEL
//
// [Bits 19..16] RW (@ 0x40012C5C) TI3SEL
//
// ( (unsigned char)((TIM1_TISEL >> 16) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_TISEL_TI4SEL ---------------------------------
// SVD Line: 7070
// - SFDITEM_FIELD__TIM1_TISEL_TI4SEL
// TI4SEL
//
// [Bits 27..24] RW (@ 0x40012C5C) TI4SEL
//
// ( (unsigned char)((TIM1_TISEL >> 24) & 0xF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM1_TISEL -----------------------------------
// SVD Line: 7054
// SFDITEM_REG__TIM1_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x40012C5C) TISEL
// ( (unsigned int)((TIM1_TISEL >> 0) & 0xFFFFFFFF), ((TIM1_TISEL = (TIM1_TISEL & ~(0xF0F0F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F0F0F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_TISEL_TI1SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI2SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI3SEL
// - SFDITEM_FIELD__TIM1_TISEL_TI4SEL
//
//
// ----------------------------- Register Item Address: TIM1_AF1 --------------------------------
// SVD Line: 7076
unsigned int TIM1_AF1 __AT (0x40012C60);
// ------------------------------- Field Item: TIM1_AF1_BKINE -----------------------------------
// SVD Line: 7080
// - SFDITEM_FIELD__TIM1_AF1_BKINE
// BKINE
//
// [Bit 0] RW (@ 0x40012C60) BKINE
//
// ( (unsigned int) TIM1_AF1 )
// BKINE
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP1E ----------------------------------
// SVD Line: 7084
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1E
// BKCMP1E
//
// [Bit 1] RW (@ 0x40012C60) BKCMP1E
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP1E
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP2E ----------------------------------
// SVD Line: 7088
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2E
// BKCMP2E
//
// [Bit 2] RW (@ 0x40012C60) BKCMP2E
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP2E
//
//
//
// ------------------------------- Field Item: TIM1_AF1_BKINP -----------------------------------
// SVD Line: 7092
// - SFDITEM_FIELD__TIM1_AF1_BKINP
// BKINP
//
// [Bit 9] RW (@ 0x40012C60) BKINP
//
// ( (unsigned int) TIM1_AF1 )
// BKINP
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP1P ----------------------------------
// SVD Line: 7096
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1P
// BKCMP1P
//
// [Bit 10] RW (@ 0x40012C60) BKCMP1P
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP1P
//
//
//
// ------------------------------ Field Item: TIM1_AF1_BKCMP2P ----------------------------------
// SVD Line: 7100
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2P
// BKCMP2P
//
// [Bit 11] RW (@ 0x40012C60) BKCMP2P
//
// ( (unsigned int) TIM1_AF1 )
// BKCMP2P
//
//
//
// ------------------------------- Field Item: TIM1_AF1_ETRSEL ----------------------------------
// SVD Line: 7104
// - SFDITEM_FIELD__TIM1_AF1_ETRSEL
// ETRSEL
//
// [Bits 17..14] RW (@ 0x40012C60) ETRSEL
//
// ( (unsigned char)((TIM1_AF1 >> 14) & 0xF), ((TIM1_AF1 = (TIM1_AF1 & ~(0xFUL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM1_AF1_INTR_SEL ---------------------------------
// SVD Line: 7108
// - SFDITEM_FIELD__TIM1_AF1_INTR_SEL
// INTR_SEL
//
// [Bits 19..18] RW (@ 0x40012C60) INTR_SEL
//
// ( (unsigned char)((TIM1_AF1 >> 18) & 0x3), ((TIM1_AF1 = (TIM1_AF1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM1_AF1_PWM_PHS_EN --------------------------------
// SVD Line: 7112
// - SFDITEM_FIELD__TIM1_AF1_PWM_PHS_EN
// PWM_PHS_EN
//
// [Bit 20] RW (@ 0x40012C60) PWM_PHS_EN
//
// ( (unsigned int) TIM1_AF1 )
// PWM_PHS_EN
//
//
//
// -------------------------------- Register RTree: TIM1_AF1 ------------------------------------
// SVD Line: 7076
// SFDITEM_REG__TIM1_AF1
// AF1
//
// [Bits 31..0] RW (@ 0x40012C60) AF1
// ( (unsigned int)((TIM1_AF1 >> 0) & 0xFFFFFFFF), ((TIM1_AF1 = (TIM1_AF1 & ~(0x1FCE07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FCE07) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_AF1_BKINE
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1E
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2E
// - SFDITEM_FIELD__TIM1_AF1_BKINP
// - SFDITEM_FIELD__TIM1_AF1_BKCMP1P
// - SFDITEM_FIELD__TIM1_AF1_BKCMP2P
// - SFDITEM_FIELD__TIM1_AF1_ETRSEL
// - SFDITEM_FIELD__TIM1_AF1_INTR_SEL
// - SFDITEM_FIELD__TIM1_AF1_PWM_PHS_EN
//
//
// ----------------------------- Register Item Address: TIM1_AF2 --------------------------------
// SVD Line: 7118
unsigned int TIM1_AF2 __AT (0x40012C64);
// ------------------------------- Field Item: TIM1_AF2_OCRSEL ----------------------------------
// SVD Line: 7122
// - SFDITEM_FIELD__TIM1_AF2_OCRSEL
// OCRSEL
//
// [Bits 18..16] RW (@ 0x40012C64) OCRSEL
//
// ( (unsigned char)((TIM1_AF2 >> 16) & 0x7), ((TIM1_AF2 = (TIM1_AF2 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_AF2 ------------------------------------
// SVD Line: 7118
// SFDITEM_REG__TIM1_AF2
// AF2
//
// [Bits 31..0] RW (@ 0x40012C64) AF2
// ( (unsigned int)((TIM1_AF2 >> 0) & 0xFFFFFFFF), ((TIM1_AF2 = (TIM1_AF2 & ~(0x70000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70000) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_AF2_OCRSEL
//
//
// ----------------------------- Register Item Address: TIM1_DCR --------------------------------
// SVD Line: 7128
unsigned int TIM1_DCR __AT (0x40012FDC);
// -------------------------------- Field Item: TIM1_DCR_DBA ------------------------------------
// SVD Line: 7133
// - SFDITEM_FIELD__TIM1_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40012FDC) DBA
//
// ( (unsigned char)((TIM1_DCR >> 0) & 0x1F), ((TIM1_DCR = (TIM1_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_DCR_DBL ------------------------------------
// SVD Line: 7137
// - SFDITEM_FIELD__TIM1_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40012FDC) DBL
//
// ( (unsigned char)((TIM1_DCR >> 8) & 0x1F), ((TIM1_DCR = (TIM1_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_DCR ------------------------------------
// SVD Line: 7128
// SFDITEM_REG__TIM1_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40012FDC) DMA control register
// ( (unsigned int)((TIM1_DCR >> 0) & 0xFFFFFFFF), ((TIM1_DCR = (TIM1_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DCR_DBA
// - SFDITEM_FIELD__TIM1_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM1_DMAR --------------------------------
// SVD Line: 7143
unsigned int TIM1_DMAR __AT (0x40012FE0);
// ------------------------------- Field Item: TIM1_DMAR_DMAB -----------------------------------
// SVD Line: 7148
// - SFDITEM_FIELD__TIM1_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x40012FE0) DMAB
//
// ( (unsigned int)((TIM1_DMAR >> 0) & 0xFFFFFFFF), ((TIM1_DMAR = (TIM1_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_DMAR -----------------------------------
// SVD Line: 7143
// SFDITEM_REG__TIM1_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x40012FE0) DMA address for full transfer
// ( (unsigned int)((TIM1_DMAR >> 0) & 0xFFFFFFFF), ((TIM1_DMAR = (TIM1_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DMAR_DMAB
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 6213
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_OUTPUT
// - SFDITEM_REG__TIM1_CCMR1_INPUT
// - SFDITEM_REG__TIM1_CCMR2_OUTPUT
// - SFDITEM_REG__TIM1_CCMR2_INPUT
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
// - SFDITEM_REG__TIM1_CCR5
// - SFDITEM_REG__TIM1_CCR6
// - SFDITEM_REG__TIM1_CCMR3
// - SFDITEM_REG__TIM1_TISEL
// - SFDITEM_REG__TIM1_AF1
// - SFDITEM_REG__TIM1_AF2
// - SFDITEM_REG__TIM1_DCR
// - SFDITEM_REG__TIM1_DMAR
//
//
// ----------------------------- Register Item Address: TIM3_CR1 --------------------------------
// SVD Line: 7171
unsigned int TIM3_CR1 __AT (0x40000400);
// -------------------------------- Field Item: TIM3_CR1_CEN ------------------------------------
// SVD Line: 7175
// - SFDITEM_FIELD__TIM3_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40000400) CEN
//
// ( (unsigned int) TIM3_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM3_CR1_UDIS -----------------------------------
// SVD Line: 7179
// - SFDITEM_FIELD__TIM3_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40000400) UDIS
//
// ( (unsigned int) TIM3_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM3_CR1_URS ------------------------------------
// SVD Line: 7183
// - SFDITEM_FIELD__TIM3_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40000400) URS
//
// ( (unsigned int) TIM3_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM3_CR1_OPM ------------------------------------
// SVD Line: 7187
// - SFDITEM_FIELD__TIM3_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40000400) OPM
//
// ( (unsigned int) TIM3_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM3_CR1_DIR ------------------------------------
// SVD Line: 7191
// - SFDITEM_FIELD__TIM3_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40000400) DIR
//
// ( (unsigned int) TIM3_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM3_CR1_CMS ------------------------------------
// SVD Line: 7195
// - SFDITEM_FIELD__TIM3_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40000400) CMS
//
// ( (unsigned char)((TIM3_CR1 >> 5) & 0x3), ((TIM3_CR1 = (TIM3_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM3_CR1_ARPE -----------------------------------
// SVD Line: 7199
// - SFDITEM_FIELD__TIM3_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40000400) ARPE
//
// ( (unsigned int) TIM3_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM3_CR1_CKD ------------------------------------
// SVD Line: 7203
// - SFDITEM_FIELD__TIM3_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40000400) CKD
//
// ( (unsigned char)((TIM3_CR1 >> 8) & 0x3), ((TIM3_CR1 = (TIM3_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CR1 ------------------------------------
// SVD Line: 7171
// SFDITEM_REG__TIM3_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40000400) CR1
// ( (unsigned int)((TIM3_CR1 >> 0) & 0xFFFFFFFF), ((TIM3_CR1 = (TIM3_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CR1_CEN
// - SFDITEM_FIELD__TIM3_CR1_UDIS
// - SFDITEM_FIELD__TIM3_CR1_URS
// - SFDITEM_FIELD__TIM3_CR1_OPM
// - SFDITEM_FIELD__TIM3_CR1_DIR
// - SFDITEM_FIELD__TIM3_CR1_CMS
// - SFDITEM_FIELD__TIM3_CR1_ARPE
// - SFDITEM_FIELD__TIM3_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM3_CR2 --------------------------------
// SVD Line: 7209
unsigned int TIM3_CR2 __AT (0x40000404);
// -------------------------------- Field Item: TIM3_CR2_CCPC -----------------------------------
// SVD Line: 7213
// - SFDITEM_FIELD__TIM3_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40000404) CCPC
//
// ( (unsigned int) TIM3_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM3_CR2_CCUS -----------------------------------
// SVD Line: 7217
// - SFDITEM_FIELD__TIM3_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40000404) CCUS
//
// ( (unsigned int) TIM3_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM3_CR2_CCDS -----------------------------------
// SVD Line: 7221
// - SFDITEM_FIELD__TIM3_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40000404) CCDS
//
// ( (unsigned int) TIM3_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM3_CR2_MMS_L -----------------------------------
// SVD Line: 7225
// - SFDITEM_FIELD__TIM3_CR2_MMS_L
// MMS_L
//
// [Bits 6..4] RW (@ 0x40000404) MMS_L
//
// ( (unsigned char)((TIM3_CR2 >> 4) & 0x7), ((TIM3_CR2 = (TIM3_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM3_CR2_TI1S -----------------------------------
// SVD Line: 7229
// - SFDITEM_FIELD__TIM3_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40000404) TI1S
//
// ( (unsigned int) TIM3_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS1 -----------------------------------
// SVD Line: 7233
// - SFDITEM_FIELD__TIM3_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40000404) OIS1
//
// ( (unsigned int) TIM3_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM3_CR2_OIS1N -----------------------------------
// SVD Line: 7237
// - SFDITEM_FIELD__TIM3_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40000404) OIS1N
//
// ( (unsigned int) TIM3_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS2 -----------------------------------
// SVD Line: 7241
// - SFDITEM_FIELD__TIM3_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40000404) OIS2
//
// ( (unsigned int) TIM3_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM3_CR2_OIS2N -----------------------------------
// SVD Line: 7245
// - SFDITEM_FIELD__TIM3_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40000404) OIS2N
//
// ( (unsigned int) TIM3_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS3 -----------------------------------
// SVD Line: 7249
// - SFDITEM_FIELD__TIM3_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40000404) OIS3
//
// ( (unsigned int) TIM3_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM3_CR2_OIS3N -----------------------------------
// SVD Line: 7253
// - SFDITEM_FIELD__TIM3_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40000404) OIS3N
//
// ( (unsigned int) TIM3_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS4 -----------------------------------
// SVD Line: 7257
// - SFDITEM_FIELD__TIM3_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40000404) OIS4
//
// ( (unsigned int) TIM3_CR2 )
// OIS4
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS5 -----------------------------------
// SVD Line: 7261
// - SFDITEM_FIELD__TIM3_CR2_OIS5
// OIS5
//
// [Bit 16] RW (@ 0x40000404) OIS5
//
// ( (unsigned int) TIM3_CR2 )
// OIS5
//
//
//
// -------------------------------- Field Item: TIM3_CR2_OIS6 -----------------------------------
// SVD Line: 7265
// - SFDITEM_FIELD__TIM3_CR2_OIS6
// OIS6
//
// [Bit 18] RW (@ 0x40000404) OIS6
//
// ( (unsigned int) TIM3_CR2 )
// OIS6
//
//
//
// ------------------------------- Field Item: TIM3_CR2_MMS_H -----------------------------------
// SVD Line: 7269
// - SFDITEM_FIELD__TIM3_CR2_MMS_H
// MMS_H
//
// [Bit 25] RW (@ 0x40000404) MMS_H
//
// ( (unsigned int) TIM3_CR2 )
// MMS_H
//
//
//
// -------------------------------- Register RTree: TIM3_CR2 ------------------------------------
// SVD Line: 7209
// SFDITEM_REG__TIM3_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40000404) CR2
// ( (unsigned int)((TIM3_CR2 >> 0) & 0xFFFFFFFF), ((TIM3_CR2 = (TIM3_CR2 & ~(0x2057FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2057FFD) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CR2_CCPC
// - SFDITEM_FIELD__TIM3_CR2_CCUS
// - SFDITEM_FIELD__TIM3_CR2_CCDS
// - SFDITEM_FIELD__TIM3_CR2_MMS_L
// - SFDITEM_FIELD__TIM3_CR2_TI1S
// - SFDITEM_FIELD__TIM3_CR2_OIS1
// - SFDITEM_FIELD__TIM3_CR2_OIS1N
// - SFDITEM_FIELD__TIM3_CR2_OIS2
// - SFDITEM_FIELD__TIM3_CR2_OIS2N
// - SFDITEM_FIELD__TIM3_CR2_OIS3
// - SFDITEM_FIELD__TIM3_CR2_OIS3N
// - SFDITEM_FIELD__TIM3_CR2_OIS4
// - SFDITEM_FIELD__TIM3_CR2_OIS5
// - SFDITEM_FIELD__TIM3_CR2_OIS6
// - SFDITEM_FIELD__TIM3_CR2_MMS_H
//
//
// ---------------------------- Register Item Address: TIM3_SMCR --------------------------------
// SVD Line: 7275
unsigned int TIM3_SMCR __AT (0x40000408);
// ------------------------------- Field Item: TIM3_SMCR_SMS_L ----------------------------------
// SVD Line: 7279
// - SFDITEM_FIELD__TIM3_SMCR_SMS_L
// SMS_L
//
// [Bits 2..0] RW (@ 0x40000408) SMS_L
//
// ( (unsigned char)((TIM3_SMCR >> 0) & 0x7), ((TIM3_SMCR = (TIM3_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM3_SMCR_OCCS -----------------------------------
// SVD Line: 7283
// - SFDITEM_FIELD__TIM3_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40000408) OCCS
//
// ( (unsigned int) TIM3_SMCR )
// OCCS
//
//
//
// ------------------------------- Field Item: TIM3_SMCR_TS_L -----------------------------------
// SVD Line: 7287
// - SFDITEM_FIELD__TIM3_SMCR_TS_L
// TS_L
//
// [Bits 6..4] RW (@ 0x40000408) TS_L
//
// ( (unsigned char)((TIM3_SMCR >> 4) & 0x7), ((TIM3_SMCR = (TIM3_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM3_SMCR_MSM -----------------------------------
// SVD Line: 7291
// - SFDITEM_FIELD__TIM3_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40000408) MSM
//
// ( (unsigned int) TIM3_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM3_SMCR_ETF -----------------------------------
// SVD Line: 7295
// - SFDITEM_FIELD__TIM3_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40000408) ETF
//
// ( (unsigned char)((TIM3_SMCR >> 8) & 0xF), ((TIM3_SMCR = (TIM3_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM3_SMCR_ETPS -----------------------------------
// SVD Line: 7299
// - SFDITEM_FIELD__TIM3_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40000408) ETPS
//
// ( (unsigned char)((TIM3_SMCR >> 12) & 0x3), ((TIM3_SMCR = (TIM3_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM3_SMCR_ECE -----------------------------------
// SVD Line: 7303
// - SFDITEM_FIELD__TIM3_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40000408) ECE
//
// ( (unsigned int) TIM3_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM3_SMCR_ETP -----------------------------------
// SVD Line: 7307
// - SFDITEM_FIELD__TIM3_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40000408) ETP
//
// ( (unsigned int) TIM3_SMCR )
// ETP
//
//
//
// ------------------------------- Field Item: TIM3_SMCR_SMS_H ----------------------------------
// SVD Line: 7311
// - SFDITEM_FIELD__TIM3_SMCR_SMS_H
// SMS_H
//
// [Bit 16] RW (@ 0x40000408) SMS_H
//
// ( (unsigned int) TIM3_SMCR )
// SMS_H
//
//
//
// ------------------------------- Field Item: TIM3_SMCR_TS_H -----------------------------------
// SVD Line: 7315
// - SFDITEM_FIELD__TIM3_SMCR_TS_H
// TS_H
//
// [Bits 21..20] RW (@ 0x40000408) TS_H
//
// ( (unsigned char)((TIM3_SMCR >> 20) & 0x3), ((TIM3_SMCR = (TIM3_SMCR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_SMCR -----------------------------------
// SVD Line: 7275
// SFDITEM_REG__TIM3_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40000408) SMCR
// ( (unsigned int)((TIM3_SMCR >> 0) & 0xFFFFFFFF), ((TIM3_SMCR = (TIM3_SMCR & ~(0x31FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x31FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_SMCR_SMS_L
// - SFDITEM_FIELD__TIM3_SMCR_OCCS
// - SFDITEM_FIELD__TIM3_SMCR_TS_L
// - SFDITEM_FIELD__TIM3_SMCR_MSM
// - SFDITEM_FIELD__TIM3_SMCR_ETF
// - SFDITEM_FIELD__TIM3_SMCR_ETPS
// - SFDITEM_FIELD__TIM3_SMCR_ECE
// - SFDITEM_FIELD__TIM3_SMCR_ETP
// - SFDITEM_FIELD__TIM3_SMCR_SMS_H
// - SFDITEM_FIELD__TIM3_SMCR_TS_H
//
//
// ---------------------------- Register Item Address: TIM3_DIER --------------------------------
// SVD Line: 7321
unsigned int TIM3_DIER __AT (0x4000040C);
// -------------------------------- Field Item: TIM3_DIER_UIE -----------------------------------
// SVD Line: 7325
// - SFDITEM_FIELD__TIM3_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000040C) UIE
//
// ( (unsigned int) TIM3_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC1IE ----------------------------------
// SVD Line: 7329
// - SFDITEM_FIELD__TIM3_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000040C) CC1IE
//
// ( (unsigned int) TIM3_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC2IE ----------------------------------
// SVD Line: 7333
// - SFDITEM_FIELD__TIM3_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x4000040C) CC2IE
//
// ( (unsigned int) TIM3_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC3IE ----------------------------------
// SVD Line: 7337
// - SFDITEM_FIELD__TIM3_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x4000040C) CC3IE
//
// ( (unsigned int) TIM3_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC4IE ----------------------------------
// SVD Line: 7341
// - SFDITEM_FIELD__TIM3_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x4000040C) CC4IE
//
// ( (unsigned int) TIM3_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_COMIE ----------------------------------
// SVD Line: 7345
// - SFDITEM_FIELD__TIM3_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4000040C) COMIE
//
// ( (unsigned int) TIM3_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM3_DIER_TIE -----------------------------------
// SVD Line: 7349
// - SFDITEM_FIELD__TIM3_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x4000040C) TIE
//
// ( (unsigned int) TIM3_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM3_DIER_BIE -----------------------------------
// SVD Line: 7353
// - SFDITEM_FIELD__TIM3_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4000040C) BIE
//
// ( (unsigned int) TIM3_DIER )
// BIE
//
//
//
// -------------------------------- Field Item: TIM3_DIER_UDE -----------------------------------
// SVD Line: 7357
// - SFDITEM_FIELD__TIM3_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4000040C) UDE
//
// ( (unsigned int) TIM3_DIER )
// UDE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC1DE ----------------------------------
// SVD Line: 7361
// - SFDITEM_FIELD__TIM3_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4000040C) CC1DE
//
// ( (unsigned int) TIM3_DIER )
// CC1DE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC2DE ----------------------------------
// SVD Line: 7365
// - SFDITEM_FIELD__TIM3_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x4000040C) CC2DE
//
// ( (unsigned int) TIM3_DIER )
// CC2DE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC3DE ----------------------------------
// SVD Line: 7369
// - SFDITEM_FIELD__TIM3_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x4000040C) CC3DE
//
// ( (unsigned int) TIM3_DIER )
// CC3DE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_CC4DE ----------------------------------
// SVD Line: 7373
// - SFDITEM_FIELD__TIM3_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x4000040C) CC4DE
//
// ( (unsigned int) TIM3_DIER )
// CC4DE
//
//
//
// ------------------------------- Field Item: TIM3_DIER_COMDE ----------------------------------
// SVD Line: 7377
// - SFDITEM_FIELD__TIM3_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x4000040C) COMDE
//
// ( (unsigned int) TIM3_DIER )
// COMDE
//
//
//
// -------------------------------- Field Item: TIM3_DIER_TDE -----------------------------------
// SVD Line: 7381
// - SFDITEM_FIELD__TIM3_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x4000040C) TDE
//
// ( (unsigned int) TIM3_DIER )
// TDE
//
//
//
// -------------------------------- Register RTree: TIM3_DIER -----------------------------------
// SVD Line: 7321
// SFDITEM_REG__TIM3_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000040C) DIER
// ( (unsigned int)((TIM3_DIER >> 0) & 0xFFFFFFFF), ((TIM3_DIER = (TIM3_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_DIER_UIE
// - SFDITEM_FIELD__TIM3_DIER_CC1IE
// - SFDITEM_FIELD__TIM3_DIER_CC2IE
// - SFDITEM_FIELD__TIM3_DIER_CC3IE
// - SFDITEM_FIELD__TIM3_DIER_CC4IE
// - SFDITEM_FIELD__TIM3_DIER_COMIE
// - SFDITEM_FIELD__TIM3_DIER_TIE
// - SFDITEM_FIELD__TIM3_DIER_BIE
// - SFDITEM_FIELD__TIM3_DIER_UDE
// - SFDITEM_FIELD__TIM3_DIER_CC1DE
// - SFDITEM_FIELD__TIM3_DIER_CC2DE
// - SFDITEM_FIELD__TIM3_DIER_CC3DE
// - SFDITEM_FIELD__TIM3_DIER_CC4DE
// - SFDITEM_FIELD__TIM3_DIER_COMDE
// - SFDITEM_FIELD__TIM3_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM3_SR ---------------------------------
// SVD Line: 7387
unsigned int TIM3_SR __AT (0x40000410);
// --------------------------------- Field Item: TIM3_SR_UIF ------------------------------------
// SVD Line: 7391
// - SFDITEM_FIELD__TIM3_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40000410) UIF
//
// ( (unsigned int) TIM3_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC1IF -----------------------------------
// SVD Line: 7395
// - SFDITEM_FIELD__TIM3_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40000410) CC1IF
//
// ( (unsigned int) TIM3_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC2IF -----------------------------------
// SVD Line: 7399
// - SFDITEM_FIELD__TIM3_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40000410) CC2IF
//
// ( (unsigned int) TIM3_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC3IF -----------------------------------
// SVD Line: 7403
// - SFDITEM_FIELD__TIM3_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40000410) CC3IF
//
// ( (unsigned int) TIM3_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC4IF -----------------------------------
// SVD Line: 7407
// - SFDITEM_FIELD__TIM3_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40000410) CC4IF
//
// ( (unsigned int) TIM3_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_COMIF -----------------------------------
// SVD Line: 7411
// - SFDITEM_FIELD__TIM3_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40000410) COMIF
//
// ( (unsigned int) TIM3_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM3_SR_TIF ------------------------------------
// SVD Line: 7415
// - SFDITEM_FIELD__TIM3_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40000410) TIF
//
// ( (unsigned int) TIM3_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM3_SR_BIF ------------------------------------
// SVD Line: 7419
// - SFDITEM_FIELD__TIM3_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40000410) BIF
//
// ( (unsigned int) TIM3_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM3_SR_B2IF ------------------------------------
// SVD Line: 7423
// - SFDITEM_FIELD__TIM3_SR_B2IF
// B2IF
//
// [Bit 8] RW (@ 0x40000410) B2IF
//
// ( (unsigned int) TIM3_SR )
// B2IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC1OF -----------------------------------
// SVD Line: 7427
// - SFDITEM_FIELD__TIM3_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40000410) CC1OF
//
// ( (unsigned int) TIM3_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC2OF -----------------------------------
// SVD Line: 7431
// - SFDITEM_FIELD__TIM3_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40000410) CC2OF
//
// ( (unsigned int) TIM3_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC3OF -----------------------------------
// SVD Line: 7435
// - SFDITEM_FIELD__TIM3_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40000410) CC3OF
//
// ( (unsigned int) TIM3_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC4OF -----------------------------------
// SVD Line: 7439
// - SFDITEM_FIELD__TIM3_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40000410) CC4OF
//
// ( (unsigned int) TIM3_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM3_SR_SBIF ------------------------------------
// SVD Line: 7443
// - SFDITEM_FIELD__TIM3_SR_SBIF
// SBIF
//
// [Bit 13] RW (@ 0x40000410) SBIF
//
// ( (unsigned int) TIM3_SR )
// SBIF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC5IF -----------------------------------
// SVD Line: 7447
// - SFDITEM_FIELD__TIM3_SR_CC5IF
// CC5IF
//
// [Bit 16] RW (@ 0x40000410) CC5IF
//
// ( (unsigned int) TIM3_SR )
// CC5IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_CC6IF -----------------------------------
// SVD Line: 7451
// - SFDITEM_FIELD__TIM3_SR_CC6IF
// CC6IF
//
// [Bit 17] RW (@ 0x40000410) CC6IF
//
// ( (unsigned int) TIM3_SR )
// CC6IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC1IR -----------------------------------
// SVD Line: 7455
// - SFDITEM_FIELD__TIM3_SR_IC1IR
// IC1IR
//
// [Bit 18] RW (@ 0x40000410) IC1IR
//
// ( (unsigned int) TIM3_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC2IR -----------------------------------
// SVD Line: 7459
// - SFDITEM_FIELD__TIM3_SR_IC2IR
// IC2IR
//
// [Bit 19] RW (@ 0x40000410) IC2IR
//
// ( (unsigned int) TIM3_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC3IR -----------------------------------
// SVD Line: 7463
// - SFDITEM_FIELD__TIM3_SR_IC3IR
// IC3IR
//
// [Bit 24] RW (@ 0x40000410) IC3IR
//
// ( (unsigned int) TIM3_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC4IR -----------------------------------
// SVD Line: 7467
// - SFDITEM_FIELD__TIM3_SR_IC4IR
// IC4IR
//
// [Bit 25] RW (@ 0x40000410) IC4IR
//
// ( (unsigned int) TIM3_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC1IF -----------------------------------
// SVD Line: 7471
// - SFDITEM_FIELD__TIM3_SR_IC1IF
// IC1IF
//
// [Bit 26] RW (@ 0x40000410) IC1IF
//
// ( (unsigned int) TIM3_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC2IF -----------------------------------
// SVD Line: 7475
// - SFDITEM_FIELD__TIM3_SR_IC2IF
// IC2IF
//
// [Bit 27] RW (@ 0x40000410) IC2IF
//
// ( (unsigned int) TIM3_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC3IF -----------------------------------
// SVD Line: 7479
// - SFDITEM_FIELD__TIM3_SR_IC3IF
// IC3IF
//
// [Bit 28] RW (@ 0x40000410) IC3IF
//
// ( (unsigned int) TIM3_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM3_SR_IC4IF -----------------------------------
// SVD Line: 7483
// - SFDITEM_FIELD__TIM3_SR_IC4IF
// IC4IF
//
// [Bit 29] RW (@ 0x40000410) IC4IF
//
// ( (unsigned int) TIM3_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM3_SR ------------------------------------
// SVD Line: 7387
// SFDITEM_REG__TIM3_SR
// SR
//
// [Bits 31..0] RW (@ 0x40000410) SR
// ( (unsigned int)((TIM3_SR >> 0) & 0xFFFFFFFF), ((TIM3_SR = (TIM3_SR & ~(0x3F0F3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_SR_UIF
// - SFDITEM_FIELD__TIM3_SR_CC1IF
// - SFDITEM_FIELD__TIM3_SR_CC2IF
// - SFDITEM_FIELD__TIM3_SR_CC3IF
// - SFDITEM_FIELD__TIM3_SR_CC4IF
// - SFDITEM_FIELD__TIM3_SR_COMIF
// - SFDITEM_FIELD__TIM3_SR_TIF
// - SFDITEM_FIELD__TIM3_SR_BIF
// - SFDITEM_FIELD__TIM3_SR_B2IF
// - SFDITEM_FIELD__TIM3_SR_CC1OF
// - SFDITEM_FIELD__TIM3_SR_CC2OF
// - SFDITEM_FIELD__TIM3_SR_CC3OF
// - SFDITEM_FIELD__TIM3_SR_CC4OF
// - SFDITEM_FIELD__TIM3_SR_SBIF
// - SFDITEM_FIELD__TIM3_SR_CC5IF
// - SFDITEM_FIELD__TIM3_SR_CC6IF
// - SFDITEM_FIELD__TIM3_SR_IC1IR
// - SFDITEM_FIELD__TIM3_SR_IC2IR
// - SFDITEM_FIELD__TIM3_SR_IC3IR
// - SFDITEM_FIELD__TIM3_SR_IC4IR
// - SFDITEM_FIELD__TIM3_SR_IC1IF
// - SFDITEM_FIELD__TIM3_SR_IC2IF
// - SFDITEM_FIELD__TIM3_SR_IC3IF
// - SFDITEM_FIELD__TIM3_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM3_EGR --------------------------------
// SVD Line: 7489
unsigned int TIM3_EGR __AT (0x40000414);
// --------------------------------- Field Item: TIM3_EGR_UG ------------------------------------
// SVD Line: 7493
// - SFDITEM_FIELD__TIM3_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40000414) UG
//
// ( (unsigned int) TIM3_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM3_EGR_CC1G -----------------------------------
// SVD Line: 7497
// - SFDITEM_FIELD__TIM3_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40000414) CC1G
//
// ( (unsigned int) TIM3_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM3_EGR_CC2G -----------------------------------
// SVD Line: 7501
// - SFDITEM_FIELD__TIM3_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40000414) CC2G
//
// ( (unsigned int) TIM3_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM3_EGR_CC3G -----------------------------------
// SVD Line: 7505
// - SFDITEM_FIELD__TIM3_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40000414) CC3G
//
// ( (unsigned int) TIM3_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM3_EGR_CC4G -----------------------------------
// SVD Line: 7509
// - SFDITEM_FIELD__TIM3_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40000414) CC4G
//
// ( (unsigned int) TIM3_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM3_EGR_COMG -----------------------------------
// SVD Line: 7513
// - SFDITEM_FIELD__TIM3_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40000414) COMG
//
// ( (unsigned int) TIM3_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM3_EGR_TG ------------------------------------
// SVD Line: 7517
// - SFDITEM_FIELD__TIM3_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40000414) TG
//
// ( (unsigned int) TIM3_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM3_EGR_BG ------------------------------------
// SVD Line: 7521
// - SFDITEM_FIELD__TIM3_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40000414) BG
//
// ( (unsigned int) TIM3_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM3_EGR ------------------------------------
// SVD Line: 7489
// SFDITEM_REG__TIM3_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40000414) EGR
// ( (unsigned int)((TIM3_EGR >> 0) & 0xFFFFFFFF), ((TIM3_EGR = (TIM3_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_EGR_UG
// - SFDITEM_FIELD__TIM3_EGR_CC1G
// - SFDITEM_FIELD__TIM3_EGR_CC2G
// - SFDITEM_FIELD__TIM3_EGR_CC3G
// - SFDITEM_FIELD__TIM3_EGR_CC4G
// - SFDITEM_FIELD__TIM3_EGR_COMG
// - SFDITEM_FIELD__TIM3_EGR_TG
// - SFDITEM_FIELD__TIM3_EGR_BG
//
//
// ------------------------ Register Item Address: TIM3_CCMR1_OUTPUT ----------------------------
// SVD Line: 7527
unsigned int TIM3_CCMR1_OUTPUT __AT (0x40000418);
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 7531
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40000418) CC1S
//
// ( (unsigned char)((TIM3_CCMR1_OUTPUT >> 0) & 0x3), ((TIM3_CCMR1_OUTPUT = (TIM3_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 7535
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40000418) OC1FE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 7539
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40000418) OC1PE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC1PE
//
//
//
// -------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC1M_L ------------------------------
// SVD Line: 7543
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1M_L
// OC1M_L
//
// [Bits 6..4] RW (@ 0x40000418) OC1M_L
//
// ( (unsigned char)((TIM3_CCMR1_OUTPUT >> 4) & 0x7), ((TIM3_CCMR1_OUTPUT = (TIM3_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 7547
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40000418) OC1CE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 7551
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40000418) CC2S
//
// ( (unsigned char)((TIM3_CCMR1_OUTPUT >> 8) & 0x3), ((TIM3_CCMR1_OUTPUT = (TIM3_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 7555
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40000418) OC2FE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 7559
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40000418) OC2PE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC2PE
//
//
//
// -------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC2M_L ------------------------------
// SVD Line: 7563
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2M_L
// OC2M_L
//
// [Bits 14..12] RW (@ 0x40000418) OC2M_L
//
// ( (unsigned char)((TIM3_CCMR1_OUTPUT >> 12) & 0x7), ((TIM3_CCMR1_OUTPUT = (TIM3_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 7567
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40000418) OC2CE
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC1M_H ------------------------------
// SVD Line: 7571
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1M_H
// OC1M_H
//
// [Bit 16] RW (@ 0x40000418) OC1M_H
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC1M_H
//
//
//
// -------------------------- Field Item: TIM3_CCMR1_OUTPUT_OC2M_H ------------------------------
// SVD Line: 7575
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2M_H
// OC2M_H
//
// [Bit 24] RW (@ 0x40000418) OC2M_H
//
// ( (unsigned int) TIM3_CCMR1_OUTPUT )
// OC2M_H
//
//
//
// ---------------------------- Register RTree: TIM3_CCMR1_OUTPUT -------------------------------
// SVD Line: 7527
// SFDITEM_REG__TIM3_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40000418) CCMR1_OUTPUT
// ( (unsigned int)((TIM3_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM3_CCMR1_OUTPUT = (TIM3_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1M_L
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2M_L
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC1M_H
// - SFDITEM_FIELD__TIM3_CCMR1_OUTPUT_OC2M_H
//
//
// ------------------------- Register Item Address: TIM3_CCMR1_INPUT ----------------------------
// SVD Line: 7581
unsigned int TIM3_CCMR1_INPUT __AT (0x40000418);
// ---------------------------- Field Item: TIM3_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 7586
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40000418) CC1S
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 0) & 0x3), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 7590
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40000418) IC1PSC
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 2) & 0x3), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 7594
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40000418) IC1F
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 4) & 0xF), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 7598
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40000418) CC2S
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 8) & 0x3), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 7602
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40000418) IC2PSC
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 10) & 0x3), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 7606
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40000418) IC2F
//
// ( (unsigned char)((TIM3_CCMR1_INPUT >> 12) & 0xF), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM3_CCMR1_INPUT --------------------------------
// SVD Line: 7581
// SFDITEM_REG__TIM3_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40000418) CCMR1_INPUT
// ( (unsigned int)((TIM3_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM3_CCMR1_INPUT = (TIM3_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM3_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM3_CCMR2_OUTPUT ----------------------------
// SVD Line: 7612
unsigned int TIM3_CCMR2_OUTPUT __AT (0x4000041C);
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 7616
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x4000041C) CC3S
//
// ( (unsigned char)((TIM3_CCMR2_OUTPUT >> 0) & 0x3), ((TIM3_CCMR2_OUTPUT = (TIM3_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 7620
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x4000041C) OC3FE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 7624
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x4000041C) OC3PE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC3PE
//
//
//
// -------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC3M_L ------------------------------
// SVD Line: 7628
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3M_L
// OC3M_L
//
// [Bits 6..4] RW (@ 0x4000041C) OC3M_L
//
// ( (unsigned char)((TIM3_CCMR2_OUTPUT >> 4) & 0x7), ((TIM3_CCMR2_OUTPUT = (TIM3_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 7632
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x4000041C) OC3CE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 7636
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x4000041C) CC4S
//
// ( (unsigned char)((TIM3_CCMR2_OUTPUT >> 8) & 0x3), ((TIM3_CCMR2_OUTPUT = (TIM3_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 7640
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x4000041C) OC4FE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 7644
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x4000041C) OC4PE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC4PE
//
//
//
// -------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC4M_L ------------------------------
// SVD Line: 7648
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4M_L
// OC4M_L
//
// [Bits 14..12] RW (@ 0x4000041C) OC4M_L
//
// ( (unsigned char)((TIM3_CCMR2_OUTPUT >> 12) & 0x7), ((TIM3_CCMR2_OUTPUT = (TIM3_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 7652
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x4000041C) OC4CE
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC4CE
//
//
//
// -------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC3M_H ------------------------------
// SVD Line: 7656
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3M_H
// OC3M_H
//
// [Bit 16] RW (@ 0x4000041C) OC3M_H
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC3M_H
//
//
//
// -------------------------- Field Item: TIM3_CCMR2_OUTPUT_OC4M_H ------------------------------
// SVD Line: 7660
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4M_H
// OC4M_H
//
// [Bit 24] RW (@ 0x4000041C) OC4M_H
//
// ( (unsigned int) TIM3_CCMR2_OUTPUT )
// OC4M_H
//
//
//
// ---------------------------- Register RTree: TIM3_CCMR2_OUTPUT -------------------------------
// SVD Line: 7612
// SFDITEM_REG__TIM3_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x4000041C) CCMR2_OUTPUT
// ( (unsigned int)((TIM3_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM3_CCMR2_OUTPUT = (TIM3_CCMR2_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3M_L
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4M_L
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4CE
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC3M_H
// - SFDITEM_FIELD__TIM3_CCMR2_OUTPUT_OC4M_H
//
//
// ------------------------- Register Item Address: TIM3_CCMR2_INPUT ----------------------------
// SVD Line: 7666
unsigned int TIM3_CCMR2_INPUT __AT (0x4000041C);
// ---------------------------- Field Item: TIM3_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 7671
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x4000041C) CC3S
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 0) & 0x3), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 7675
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x4000041C) IC3PSC
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 2) & 0x3), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 7679
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x4000041C) IC3F
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 4) & 0xF), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 7683
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x4000041C) CC4S
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 8) & 0x3), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM3_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 7687
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x4000041C) IC4PSC
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 10) & 0x3), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM3_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 7691
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x4000041C) IC4F
//
// ( (unsigned char)((TIM3_CCMR2_INPUT >> 12) & 0xF), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM3_CCMR2_INPUT --------------------------------
// SVD Line: 7666
// SFDITEM_REG__TIM3_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x4000041C) CCMR2_INPUT
// ( (unsigned int)((TIM3_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM3_CCMR2_INPUT = (TIM3_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM3_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM3_CCER --------------------------------
// SVD Line: 7697
unsigned int TIM3_CCER __AT (0x40000420);
// ------------------------------- Field Item: TIM3_CCER_CC1E -----------------------------------
// SVD Line: 7701
// - SFDITEM_FIELD__TIM3_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40000420) CC1E
//
// ( (unsigned int) TIM3_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC1P -----------------------------------
// SVD Line: 7705
// - SFDITEM_FIELD__TIM3_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40000420) CC1P
//
// ( (unsigned int) TIM3_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC1NE ----------------------------------
// SVD Line: 7709
// - SFDITEM_FIELD__TIM3_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40000420) CC1NE
//
// ( (unsigned int) TIM3_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC1NP ----------------------------------
// SVD Line: 7713
// - SFDITEM_FIELD__TIM3_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40000420) CC1NP
//
// ( (unsigned int) TIM3_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC2E -----------------------------------
// SVD Line: 7717
// - SFDITEM_FIELD__TIM3_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40000420) CC2E
//
// ( (unsigned int) TIM3_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC2P -----------------------------------
// SVD Line: 7721
// - SFDITEM_FIELD__TIM3_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40000420) CC2P
//
// ( (unsigned int) TIM3_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC2NE ----------------------------------
// SVD Line: 7725
// - SFDITEM_FIELD__TIM3_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40000420) CC2NE
//
// ( (unsigned int) TIM3_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC2NP ----------------------------------
// SVD Line: 7729
// - SFDITEM_FIELD__TIM3_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40000420) CC2NP
//
// ( (unsigned int) TIM3_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC3E -----------------------------------
// SVD Line: 7733
// - SFDITEM_FIELD__TIM3_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40000420) CC3E
//
// ( (unsigned int) TIM3_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC3P -----------------------------------
// SVD Line: 7737
// - SFDITEM_FIELD__TIM3_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40000420) CC3P
//
// ( (unsigned int) TIM3_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC3NE ----------------------------------
// SVD Line: 7741
// - SFDITEM_FIELD__TIM3_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40000420) CC3NE
//
// ( (unsigned int) TIM3_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC3NP ----------------------------------
// SVD Line: 7745
// - SFDITEM_FIELD__TIM3_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40000420) CC3NP
//
// ( (unsigned int) TIM3_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC4E -----------------------------------
// SVD Line: 7749
// - SFDITEM_FIELD__TIM3_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40000420) CC4E
//
// ( (unsigned int) TIM3_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC4P -----------------------------------
// SVD Line: 7753
// - SFDITEM_FIELD__TIM3_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40000420) CC4P
//
// ( (unsigned int) TIM3_CCER )
// CC4P
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC4NP ----------------------------------
// SVD Line: 7757
// - SFDITEM_FIELD__TIM3_CCER_CC4NP
// CC4NP
//
// [Bit 15] RW (@ 0x40000420) CC4NP
//
// ( (unsigned int) TIM3_CCER )
// CC4NP
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC5E -----------------------------------
// SVD Line: 7761
// - SFDITEM_FIELD__TIM3_CCER_CC5E
// CC5E
//
// [Bit 16] RW (@ 0x40000420) CC5E
//
// ( (unsigned int) TIM3_CCER )
// CC5E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC5P -----------------------------------
// SVD Line: 7765
// - SFDITEM_FIELD__TIM3_CCER_CC5P
// CC5P
//
// [Bit 17] RW (@ 0x40000420) CC5P
//
// ( (unsigned int) TIM3_CCER )
// CC5P
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC6E -----------------------------------
// SVD Line: 7769
// - SFDITEM_FIELD__TIM3_CCER_CC6E
// CC6E
//
// [Bit 20] RW (@ 0x40000420) CC6E
//
// ( (unsigned int) TIM3_CCER )
// CC6E
//
//
//
// ------------------------------- Field Item: TIM3_CCER_CC6P -----------------------------------
// SVD Line: 7773
// - SFDITEM_FIELD__TIM3_CCER_CC6P
// CC6P
//
// [Bit 21] RW (@ 0x40000420) CC6P
//
// ( (unsigned int) TIM3_CCER )
// CC6P
//
//
//
// -------------------------------- Register RTree: TIM3_CCER -----------------------------------
// SVD Line: 7697
// SFDITEM_REG__TIM3_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40000420) CCER
// ( (unsigned int)((TIM3_CCER >> 0) & 0xFFFFFFFF), ((TIM3_CCER = (TIM3_CCER & ~(0x33BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCER_CC1E
// - SFDITEM_FIELD__TIM3_CCER_CC1P
// - SFDITEM_FIELD__TIM3_CCER_CC1NE
// - SFDITEM_FIELD__TIM3_CCER_CC1NP
// - SFDITEM_FIELD__TIM3_CCER_CC2E
// - SFDITEM_FIELD__TIM3_CCER_CC2P
// - SFDITEM_FIELD__TIM3_CCER_CC2NE
// - SFDITEM_FIELD__TIM3_CCER_CC2NP
// - SFDITEM_FIELD__TIM3_CCER_CC3E
// - SFDITEM_FIELD__TIM3_CCER_CC3P
// - SFDITEM_FIELD__TIM3_CCER_CC3NE
// - SFDITEM_FIELD__TIM3_CCER_CC3NP
// - SFDITEM_FIELD__TIM3_CCER_CC4E
// - SFDITEM_FIELD__TIM3_CCER_CC4P
// - SFDITEM_FIELD__TIM3_CCER_CC4NP
// - SFDITEM_FIELD__TIM3_CCER_CC5E
// - SFDITEM_FIELD__TIM3_CCER_CC5P
// - SFDITEM_FIELD__TIM3_CCER_CC6E
// - SFDITEM_FIELD__TIM3_CCER_CC6P
//
//
// ----------------------------- Register Item Address: TIM3_CNT --------------------------------
// SVD Line: 7779
unsigned int TIM3_CNT __AT (0x40000424);
// -------------------------------- Field Item: TIM3_CNT_CNT ------------------------------------
// SVD Line: 7783
// - SFDITEM_FIELD__TIM3_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40000424) CNT
//
// ( (unsigned short)((TIM3_CNT >> 0) & 0xFFFF), ((TIM3_CNT = (TIM3_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CNT ------------------------------------
// SVD Line: 7779
// SFDITEM_REG__TIM3_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40000424) CNT
// ( (unsigned int)((TIM3_CNT >> 0) & 0xFFFFFFFF), ((TIM3_CNT = (TIM3_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM3_PSC --------------------------------
// SVD Line: 7789
unsigned int TIM3_PSC __AT (0x40000428);
// -------------------------------- Field Item: TIM3_PSC_PSC ------------------------------------
// SVD Line: 7793
// - SFDITEM_FIELD__TIM3_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40000428) PSC
//
// ( (unsigned short)((TIM3_PSC >> 0) & 0xFFFF), ((TIM3_PSC = (TIM3_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_PSC ------------------------------------
// SVD Line: 7789
// SFDITEM_REG__TIM3_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40000428) PSC
// ( (unsigned int)((TIM3_PSC >> 0) & 0xFFFFFFFF), ((TIM3_PSC = (TIM3_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM3_ARR --------------------------------
// SVD Line: 7799
unsigned int TIM3_ARR __AT (0x4000042C);
// -------------------------------- Field Item: TIM3_ARR_ARR ------------------------------------
// SVD Line: 7803
// - SFDITEM_FIELD__TIM3_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000042C) ARR
//
// ( (unsigned short)((TIM3_ARR >> 0) & 0xFFFF), ((TIM3_ARR = (TIM3_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_ARR ------------------------------------
// SVD Line: 7799
// SFDITEM_REG__TIM3_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000042C) ARR
// ( (unsigned int)((TIM3_ARR >> 0) & 0xFFFFFFFF), ((TIM3_ARR = (TIM3_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM3_CCR1 --------------------------------
// SVD Line: 7809
unsigned int TIM3_CCR1 __AT (0x40000434);
// ------------------------------- Field Item: TIM3_CCR1_CCR1 -----------------------------------
// SVD Line: 7813
// - SFDITEM_FIELD__TIM3_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40000434) CCR1
//
// ( (unsigned short)((TIM3_CCR1 >> 0) & 0xFFFF), ((TIM3_CCR1 = (TIM3_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CCR1 -----------------------------------
// SVD Line: 7809
// SFDITEM_REG__TIM3_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40000434) CCR1
// ( (unsigned int)((TIM3_CCR1 >> 0) & 0xFFFFFFFF), ((TIM3_CCR1 = (TIM3_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM3_CCR2 --------------------------------
// SVD Line: 7819
unsigned int TIM3_CCR2 __AT (0x40000438);
// ------------------------------- Field Item: TIM3_CCR2_CCR2 -----------------------------------
// SVD Line: 7823
// - SFDITEM_FIELD__TIM3_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40000438) CCR2
//
// ( (unsigned short)((TIM3_CCR2 >> 0) & 0xFFFF), ((TIM3_CCR2 = (TIM3_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CCR2 -----------------------------------
// SVD Line: 7819
// SFDITEM_REG__TIM3_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40000438) CCR2
// ( (unsigned int)((TIM3_CCR2 >> 0) & 0xFFFFFFFF), ((TIM3_CCR2 = (TIM3_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM3_CCR3 --------------------------------
// SVD Line: 7829
unsigned int TIM3_CCR3 __AT (0x4000043C);
// ------------------------------- Field Item: TIM3_CCR3_CCR3 -----------------------------------
// SVD Line: 7833
// - SFDITEM_FIELD__TIM3_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x4000043C) CCR3
//
// ( (unsigned short)((TIM3_CCR3 >> 0) & 0xFFFF), ((TIM3_CCR3 = (TIM3_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CCR3 -----------------------------------
// SVD Line: 7829
// SFDITEM_REG__TIM3_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x4000043C) CCR3
// ( (unsigned int)((TIM3_CCR3 >> 0) & 0xFFFFFFFF), ((TIM3_CCR3 = (TIM3_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM3_CCR4 --------------------------------
// SVD Line: 7839
unsigned int TIM3_CCR4 __AT (0x40000440);
// ------------------------------- Field Item: TIM3_CCR4_CCR4 -----------------------------------
// SVD Line: 7843
// - SFDITEM_FIELD__TIM3_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40000440) CCR4
//
// ( (unsigned short)((TIM3_CCR4 >> 0) & 0xFFFF), ((TIM3_CCR4 = (TIM3_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_CCR4 -----------------------------------
// SVD Line: 7839
// SFDITEM_REG__TIM3_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40000440) CCR4
// ( (unsigned int)((TIM3_CCR4 >> 0) & 0xFFFFFFFF), ((TIM3_CCR4 = (TIM3_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM3_TISEL -------------------------------
// SVD Line: 7849
unsigned int TIM3_TISEL __AT (0x4000045C);
// ------------------------------ Field Item: TIM3_TISEL_TI1SEL ---------------------------------
// SVD Line: 7853
// - SFDITEM_FIELD__TIM3_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x4000045C) TI1SEL
//
// ( (unsigned char)((TIM3_TISEL >> 0) & 0xF), ((TIM3_TISEL = (TIM3_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM3_TISEL_TI2SEL ---------------------------------
// SVD Line: 7857
// - SFDITEM_FIELD__TIM3_TISEL_TI2SEL
// TI2SEL
//
// [Bits 11..8] RW (@ 0x4000045C) TI2SEL
//
// ( (unsigned char)((TIM3_TISEL >> 8) & 0xF), ((TIM3_TISEL = (TIM3_TISEL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM3_TISEL_TI3SEL ---------------------------------
// SVD Line: 7861
// - SFDITEM_FIELD__TIM3_TISEL_TI3SEL
// TI3SEL
//
// [Bits 19..16] RW (@ 0x4000045C) TI3SEL
//
// ( (unsigned char)((TIM3_TISEL >> 16) & 0xF), ((TIM3_TISEL = (TIM3_TISEL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM3_TISEL_TI4SEL ---------------------------------
// SVD Line: 7865
// - SFDITEM_FIELD__TIM3_TISEL_TI4SEL
// TI4SEL
//
// [Bits 27..24] RW (@ 0x4000045C) TI4SEL
//
// ( (unsigned char)((TIM3_TISEL >> 24) & 0xF), ((TIM3_TISEL = (TIM3_TISEL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM3_TISEL -----------------------------------
// SVD Line: 7849
// SFDITEM_REG__TIM3_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x4000045C) TISEL
// ( (unsigned int)((TIM3_TISEL >> 0) & 0xFFFFFFFF), ((TIM3_TISEL = (TIM3_TISEL & ~(0xF0F0F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F0F0F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_TISEL_TI1SEL
// - SFDITEM_FIELD__TIM3_TISEL_TI2SEL
// - SFDITEM_FIELD__TIM3_TISEL_TI3SEL
// - SFDITEM_FIELD__TIM3_TISEL_TI4SEL
//
//
// ----------------------------- Register Item Address: TIM3_AF1 --------------------------------
// SVD Line: 7871
unsigned int TIM3_AF1 __AT (0x40000460);
// ------------------------------- Field Item: TIM3_AF1_BKINE -----------------------------------
// SVD Line: 7875
// - SFDITEM_FIELD__TIM3_AF1_BKINE
// BKINE
//
// [Bit 0] RW (@ 0x40000460) BKINE
//
// ( (unsigned int) TIM3_AF1 )
// BKINE
//
//
//
// ------------------------------ Field Item: TIM3_AF1_BKCMP1E ----------------------------------
// SVD Line: 7879
// - SFDITEM_FIELD__TIM3_AF1_BKCMP1E
// BKCMP1E
//
// [Bit 1] RW (@ 0x40000460) BKCMP1E
//
// ( (unsigned int) TIM3_AF1 )
// BKCMP1E
//
//
//
// ------------------------------ Field Item: TIM3_AF1_BKCMP2E ----------------------------------
// SVD Line: 7883
// - SFDITEM_FIELD__TIM3_AF1_BKCMP2E
// BKCMP2E
//
// [Bit 2] RW (@ 0x40000460) BKCMP2E
//
// ( (unsigned int) TIM3_AF1 )
// BKCMP2E
//
//
//
// ------------------------------- Field Item: TIM3_AF1_BKINP -----------------------------------
// SVD Line: 7887
// - SFDITEM_FIELD__TIM3_AF1_BKINP
// BKINP
//
// [Bit 9] RW (@ 0x40000460) BKINP
//
// ( (unsigned int) TIM3_AF1 )
// BKINP
//
//
//
// ------------------------------ Field Item: TIM3_AF1_BKCMP1P ----------------------------------
// SVD Line: 7891
// - SFDITEM_FIELD__TIM3_AF1_BKCMP1P
// BKCMP1P
//
// [Bit 10] RW (@ 0x40000460) BKCMP1P
//
// ( (unsigned int) TIM3_AF1 )
// BKCMP1P
//
//
//
// ------------------------------ Field Item: TIM3_AF1_BKCMP2P ----------------------------------
// SVD Line: 7895
// - SFDITEM_FIELD__TIM3_AF1_BKCMP2P
// BKCMP2P
//
// [Bit 11] RW (@ 0x40000460) BKCMP2P
//
// ( (unsigned int) TIM3_AF1 )
// BKCMP2P
//
//
//
// ------------------------------- Field Item: TIM3_AF1_ETRSEL ----------------------------------
// SVD Line: 7899
// - SFDITEM_FIELD__TIM3_AF1_ETRSEL
// ETRSEL
//
// [Bits 17..14] RW (@ 0x40000460) ETRSEL
//
// ( (unsigned char)((TIM3_AF1 >> 14) & 0xF), ((TIM3_AF1 = (TIM3_AF1 & ~(0xFUL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: TIM3_AF1_INTR_SEL ---------------------------------
// SVD Line: 7903
// - SFDITEM_FIELD__TIM3_AF1_INTR_SEL
// INTR_SEL
//
// [Bits 19..18] RW (@ 0x40000460) INTR_SEL
//
// ( (unsigned char)((TIM3_AF1 >> 18) & 0x3), ((TIM3_AF1 = (TIM3_AF1 & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM3_AF1_PWM_PHS_EN --------------------------------
// SVD Line: 7907
// - SFDITEM_FIELD__TIM3_AF1_PWM_PHS_EN
// PWM_PHS_EN
//
// [Bit 20] RW (@ 0x40000460) PWM_PHS_EN
//
// ( (unsigned int) TIM3_AF1 )
// PWM_PHS_EN
//
//
//
// -------------------------------- Register RTree: TIM3_AF1 ------------------------------------
// SVD Line: 7871
// SFDITEM_REG__TIM3_AF1
// AF1
//
// [Bits 31..0] RW (@ 0x40000460) AF1
// ( (unsigned int)((TIM3_AF1 >> 0) & 0xFFFFFFFF), ((TIM3_AF1 = (TIM3_AF1 & ~(0x1FCE07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FCE07) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_AF1_BKINE
// - SFDITEM_FIELD__TIM3_AF1_BKCMP1E
// - SFDITEM_FIELD__TIM3_AF1_BKCMP2E
// - SFDITEM_FIELD__TIM3_AF1_BKINP
// - SFDITEM_FIELD__TIM3_AF1_BKCMP1P
// - SFDITEM_FIELD__TIM3_AF1_BKCMP2P
// - SFDITEM_FIELD__TIM3_AF1_ETRSEL
// - SFDITEM_FIELD__TIM3_AF1_INTR_SEL
// - SFDITEM_FIELD__TIM3_AF1_PWM_PHS_EN
//
//
// ----------------------------- Register Item Address: TIM3_AF2 --------------------------------
// SVD Line: 7913
unsigned int TIM3_AF2 __AT (0x40000464);
// ------------------------------- Field Item: TIM3_AF2_OCRSEL ----------------------------------
// SVD Line: 7917
// - SFDITEM_FIELD__TIM3_AF2_OCRSEL
// OCRSEL
//
// [Bits 18..16] RW (@ 0x40000464) OCRSEL
//
// ( (unsigned char)((TIM3_AF2 >> 16) & 0x7), ((TIM3_AF2 = (TIM3_AF2 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_AF2 ------------------------------------
// SVD Line: 7913
// SFDITEM_REG__TIM3_AF2
// AF2
//
// [Bits 31..0] RW (@ 0x40000464) AF2
// ( (unsigned int)((TIM3_AF2 >> 0) & 0xFFFFFFFF), ((TIM3_AF2 = (TIM3_AF2 & ~(0x70000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x70000) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_AF2_OCRSEL
//
//
// ----------------------------- Register Item Address: TIM3_DCR --------------------------------
// SVD Line: 7923
unsigned int TIM3_DCR __AT (0x400007DC);
// -------------------------------- Field Item: TIM3_DCR_DBA ------------------------------------
// SVD Line: 7927
// - SFDITEM_FIELD__TIM3_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x400007DC) DBA
//
// ( (unsigned char)((TIM3_DCR >> 0) & 0x1F), ((TIM3_DCR = (TIM3_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM3_DCR_DBL ------------------------------------
// SVD Line: 7931
// - SFDITEM_FIELD__TIM3_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x400007DC) DBL
//
// ( (unsigned char)((TIM3_DCR >> 8) & 0x1F), ((TIM3_DCR = (TIM3_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_DCR ------------------------------------
// SVD Line: 7923
// SFDITEM_REG__TIM3_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x400007DC) DCR
// ( (unsigned int)((TIM3_DCR >> 0) & 0xFFFFFFFF), ((TIM3_DCR = (TIM3_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_DCR_DBA
// - SFDITEM_FIELD__TIM3_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM3_DMAR --------------------------------
// SVD Line: 7937
unsigned int TIM3_DMAR __AT (0x400007E0);
// ------------------------------- Field Item: TIM3_DMAR_DMAB -----------------------------------
// SVD Line: 7941
// - SFDITEM_FIELD__TIM3_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x400007E0) DMAB
//
// ( (unsigned int)((TIM3_DMAR >> 0) & 0xFFFFFFFF), ((TIM3_DMAR = (TIM3_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM3_DMAR -----------------------------------
// SVD Line: 7937
// SFDITEM_REG__TIM3_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x400007E0) DMAR
// ( (unsigned int)((TIM3_DMAR >> 0) & 0xFFFFFFFF), ((TIM3_DMAR = (TIM3_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM3_DMAR_DMAB
//
//
// ---------------------------------- Peripheral View: TIM3 -------------------------------------
// SVD Line: 7156
// TIM3
// TIM3
// - SFDITEM_REG__TIM3_CR1
// - SFDITEM_REG__TIM3_CR2
// - SFDITEM_REG__TIM3_SMCR
// - SFDITEM_REG__TIM3_DIER
// - SFDITEM_REG__TIM3_SR
// - SFDITEM_REG__TIM3_EGR
// - SFDITEM_REG__TIM3_CCMR1_OUTPUT
// - SFDITEM_REG__TIM3_CCMR1_INPUT
// - SFDITEM_REG__TIM3_CCMR2_OUTPUT
// - SFDITEM_REG__TIM3_CCMR2_INPUT
// - SFDITEM_REG__TIM3_CCER
// - SFDITEM_REG__TIM3_CNT
// - SFDITEM_REG__TIM3_PSC
// - SFDITEM_REG__TIM3_ARR
// - SFDITEM_REG__TIM3_CCR1
// - SFDITEM_REG__TIM3_CCR2
// - SFDITEM_REG__TIM3_CCR3
// - SFDITEM_REG__TIM3_CCR4
// - SFDITEM_REG__TIM3_TISEL
// - SFDITEM_REG__TIM3_AF1
// - SFDITEM_REG__TIM3_AF2
// - SFDITEM_REG__TIM3_DCR
// - SFDITEM_REG__TIM3_DMAR
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 7965
unsigned int TIM14_CR1 __AT (0x40002000);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 7970
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002000) CEN
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 7974
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002000) UDIS
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 7978
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002000) URS
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_OPM -----------------------------------
// SVD Line: 7982
// - SFDITEM_FIELD__TIM14_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40002000) OPM
//
// ( (unsigned int) TIM14_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM14_CR1_DIR -----------------------------------
// SVD Line: 7986
// - SFDITEM_FIELD__TIM14_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40002000) DIR
//
// ( (unsigned int) TIM14_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CMS -----------------------------------
// SVD Line: 7990
// - SFDITEM_FIELD__TIM14_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40002000) CMS
//
// ( (unsigned char)((TIM14_CR1 >> 5) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 7994
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002000) ARPE
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 7998
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002000) CKD
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 7965
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002000) TIM14 control register1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_OPM
// - SFDITEM_FIELD__TIM14_CR1_DIR
// - SFDITEM_FIELD__TIM14_CR1_CMS
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 8004
unsigned int TIM14_DIER __AT (0x4000200C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 8009
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000200C) UIE
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 8013
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000200C) CC1IE
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC2IE ----------------------------------
// SVD Line: 8017
// - SFDITEM_FIELD__TIM14_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x4000200C) CC2IE
//
// ( (unsigned int) TIM14_DIER )
// CC2IE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC3IE ----------------------------------
// SVD Line: 8021
// - SFDITEM_FIELD__TIM14_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x4000200C) CC3IE
//
// ( (unsigned int) TIM14_DIER )
// CC3IE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC4IE ----------------------------------
// SVD Line: 8025
// - SFDITEM_FIELD__TIM14_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x4000200C) CC4IE
//
// ( (unsigned int) TIM14_DIER )
// CC4IE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_COMIE ----------------------------------
// SVD Line: 8029
// - SFDITEM_FIELD__TIM14_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4000200C) COMIE
//
// ( (unsigned int) TIM14_DIER )
// COMIE
//
//
//
// ------------------------------- Field Item: TIM14_DIER_TIE -----------------------------------
// SVD Line: 8033
// - SFDITEM_FIELD__TIM14_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x4000200C) TIE
//
// ( (unsigned int) TIM14_DIER )
// TIE
//
//
//
// ------------------------------- Field Item: TIM14_DIER_BIE -----------------------------------
// SVD Line: 8037
// - SFDITEM_FIELD__TIM14_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4000200C) BIE
//
// ( (unsigned int) TIM14_DIER )
// BIE
//
//
//
// ------------------------------- Field Item: TIM14_DIER_UDE -----------------------------------
// SVD Line: 8041
// - SFDITEM_FIELD__TIM14_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4000200C) UDE
//
// ( (unsigned int) TIM14_DIER )
// UDE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1DE ----------------------------------
// SVD Line: 8045
// - SFDITEM_FIELD__TIM14_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4000200C) CC1DE
//
// ( (unsigned int) TIM14_DIER )
// CC1DE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC2DE ----------------------------------
// SVD Line: 8049
// - SFDITEM_FIELD__TIM14_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x4000200C) CC2DE
//
// ( (unsigned int) TIM14_DIER )
// CC2DE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC3DE ----------------------------------
// SVD Line: 8053
// - SFDITEM_FIELD__TIM14_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x4000200C) CC3DE
//
// ( (unsigned int) TIM14_DIER )
// CC3DE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC4DE ----------------------------------
// SVD Line: 8057
// - SFDITEM_FIELD__TIM14_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x4000200C) CC4DE
//
// ( (unsigned int) TIM14_DIER )
// CC4DE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_COMDE ----------------------------------
// SVD Line: 8061
// - SFDITEM_FIELD__TIM14_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x4000200C) COMDE
//
// ( (unsigned int) TIM14_DIER )
// COMDE
//
//
//
// ------------------------------- Field Item: TIM14_DIER_TDE -----------------------------------
// SVD Line: 8065
// - SFDITEM_FIELD__TIM14_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x4000200C) TDE
//
// ( (unsigned int) TIM14_DIER )
// TDE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 8004
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000200C) DMA/Interrupt enable register
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// - SFDITEM_FIELD__TIM14_DIER_CC2IE
// - SFDITEM_FIELD__TIM14_DIER_CC3IE
// - SFDITEM_FIELD__TIM14_DIER_CC4IE
// - SFDITEM_FIELD__TIM14_DIER_COMIE
// - SFDITEM_FIELD__TIM14_DIER_TIE
// - SFDITEM_FIELD__TIM14_DIER_BIE
// - SFDITEM_FIELD__TIM14_DIER_UDE
// - SFDITEM_FIELD__TIM14_DIER_CC1DE
// - SFDITEM_FIELD__TIM14_DIER_CC2DE
// - SFDITEM_FIELD__TIM14_DIER_CC3DE
// - SFDITEM_FIELD__TIM14_DIER_CC4DE
// - SFDITEM_FIELD__TIM14_DIER_COMDE
// - SFDITEM_FIELD__TIM14_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 8071
unsigned int TIM14_SR __AT (0x40002010);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 8076
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002010) UIF
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 8080
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002010) CC1IF
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC2IF -----------------------------------
// SVD Line: 8084
// - SFDITEM_FIELD__TIM14_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40002010) CC2IF
//
// ( (unsigned int) TIM14_SR )
// CC2IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC3IF -----------------------------------
// SVD Line: 8088
// - SFDITEM_FIELD__TIM14_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40002010) CC3IF
//
// ( (unsigned int) TIM14_SR )
// CC3IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC4IF -----------------------------------
// SVD Line: 8092
// - SFDITEM_FIELD__TIM14_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40002010) CC4IF
//
// ( (unsigned int) TIM14_SR )
// CC4IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_COMIF -----------------------------------
// SVD Line: 8096
// - SFDITEM_FIELD__TIM14_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40002010) COMIF
//
// ( (unsigned int) TIM14_SR )
// COMIF
//
//
//
// -------------------------------- Field Item: TIM14_SR_TIF ------------------------------------
// SVD Line: 8100
// - SFDITEM_FIELD__TIM14_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40002010) TIF
//
// ( (unsigned int) TIM14_SR )
// TIF
//
//
//
// -------------------------------- Field Item: TIM14_SR_BIF ------------------------------------
// SVD Line: 8104
// - SFDITEM_FIELD__TIM14_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40002010) BIF
//
// ( (unsigned int) TIM14_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM14_SR_B2IF -----------------------------------
// SVD Line: 8108
// - SFDITEM_FIELD__TIM14_SR_B2IF
// B2IF
//
// [Bit 8] RW (@ 0x40002010) B2IF
//
// ( (unsigned int) TIM14_SR )
// B2IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 8112
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002010) CC1OF
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC2OF -----------------------------------
// SVD Line: 8116
// - SFDITEM_FIELD__TIM14_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40002010) CC2OF
//
// ( (unsigned int) TIM14_SR )
// CC2OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC3OF -----------------------------------
// SVD Line: 8120
// - SFDITEM_FIELD__TIM14_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40002010) CC3OF
//
// ( (unsigned int) TIM14_SR )
// CC3OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC4OF -----------------------------------
// SVD Line: 8124
// - SFDITEM_FIELD__TIM14_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40002010) CC4OF
//
// ( (unsigned int) TIM14_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM14_SR_SBIF -----------------------------------
// SVD Line: 8128
// - SFDITEM_FIELD__TIM14_SR_SBIF
// SBIF
//
// [Bit 13] RW (@ 0x40002010) SBIF
//
// ( (unsigned int) TIM14_SR )
// SBIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC5IF -----------------------------------
// SVD Line: 8132
// - SFDITEM_FIELD__TIM14_SR_CC5IF
// CC5IF
//
// [Bit 16] RW (@ 0x40002010) CC5IF
//
// ( (unsigned int) TIM14_SR )
// CC5IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC6IF -----------------------------------
// SVD Line: 8136
// - SFDITEM_FIELD__TIM14_SR_CC6IF
// CC6IF
//
// [Bit 17] RW (@ 0x40002010) CC6IF
//
// ( (unsigned int) TIM14_SR )
// CC6IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IR -----------------------------------
// SVD Line: 8140
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// IC1IR
//
// [Bit 18] RW (@ 0x40002010) IC1IR
//
// ( (unsigned int) TIM14_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC2IR -----------------------------------
// SVD Line: 8144
// - SFDITEM_FIELD__TIM14_SR_IC2IR
// IC2IR
//
// [Bit 19] RW (@ 0x40002010) IC2IR
//
// ( (unsigned int) TIM14_SR )
// IC2IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC3IR -----------------------------------
// SVD Line: 8148
// - SFDITEM_FIELD__TIM14_SR_IC3IR
// IC3IR
//
// [Bit 24] RW (@ 0x40002010) IC3IR
//
// ( (unsigned int) TIM14_SR )
// IC3IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC4IR -----------------------------------
// SVD Line: 8152
// - SFDITEM_FIELD__TIM14_SR_IC4IR
// IC4IR
//
// [Bit 25] RW (@ 0x40002010) IC4IR
//
// ( (unsigned int) TIM14_SR )
// IC4IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IF -----------------------------------
// SVD Line: 8156
// - SFDITEM_FIELD__TIM14_SR_IC1IF
// IC1IF
//
// [Bit 26] RW (@ 0x40002010) IC1IF
//
// ( (unsigned int) TIM14_SR )
// IC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC2IF -----------------------------------
// SVD Line: 8160
// - SFDITEM_FIELD__TIM14_SR_IC2IF
// IC2IF
//
// [Bit 27] RW (@ 0x40002010) IC2IF
//
// ( (unsigned int) TIM14_SR )
// IC2IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC3IF -----------------------------------
// SVD Line: 8164
// - SFDITEM_FIELD__TIM14_SR_IC3IF
// IC3IF
//
// [Bit 28] RW (@ 0x40002010) IC3IF
//
// ( (unsigned int) TIM14_SR )
// IC3IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC4IF -----------------------------------
// SVD Line: 8168
// - SFDITEM_FIELD__TIM14_SR_IC4IF
// IC4IF
//
// [Bit 29] RW (@ 0x40002010) IC4IF
//
// ( (unsigned int) TIM14_SR )
// IC4IF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 8071
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002010) status register
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x3F0F3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC2IF
// - SFDITEM_FIELD__TIM14_SR_CC3IF
// - SFDITEM_FIELD__TIM14_SR_CC4IF
// - SFDITEM_FIELD__TIM14_SR_COMIF
// - SFDITEM_FIELD__TIM14_SR_TIF
// - SFDITEM_FIELD__TIM14_SR_BIF
// - SFDITEM_FIELD__TIM14_SR_B2IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// - SFDITEM_FIELD__TIM14_SR_CC2OF
// - SFDITEM_FIELD__TIM14_SR_CC3OF
// - SFDITEM_FIELD__TIM14_SR_CC4OF
// - SFDITEM_FIELD__TIM14_SR_SBIF
// - SFDITEM_FIELD__TIM14_SR_CC5IF
// - SFDITEM_FIELD__TIM14_SR_CC6IF
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// - SFDITEM_FIELD__TIM14_SR_IC2IR
// - SFDITEM_FIELD__TIM14_SR_IC3IR
// - SFDITEM_FIELD__TIM14_SR_IC4IR
// - SFDITEM_FIELD__TIM14_SR_IC1IF
// - SFDITEM_FIELD__TIM14_SR_IC2IF
// - SFDITEM_FIELD__TIM14_SR_IC3IF
// - SFDITEM_FIELD__TIM14_SR_IC4IF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 8174
unsigned int TIM14_EGR __AT (0x40002014);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 8179
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40002014) UG
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 8183
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40002014) CC1G
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC2G -----------------------------------
// SVD Line: 8187
// - SFDITEM_FIELD__TIM14_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40002014) CC2G
//
// ( (unsigned int) TIM14_EGR )
// CC2G
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC3G -----------------------------------
// SVD Line: 8191
// - SFDITEM_FIELD__TIM14_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40002014) CC3G
//
// ( (unsigned int) TIM14_EGR )
// CC3G
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC4G -----------------------------------
// SVD Line: 8195
// - SFDITEM_FIELD__TIM14_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40002014) CC4G
//
// ( (unsigned int) TIM14_EGR )
// CC4G
//
//
//
// ------------------------------- Field Item: TIM14_EGR_COMG -----------------------------------
// SVD Line: 8199
// - SFDITEM_FIELD__TIM14_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40002014) COMG
//
// ( (unsigned int) TIM14_EGR )
// COMG
//
//
//
// -------------------------------- Field Item: TIM14_EGR_TG ------------------------------------
// SVD Line: 8203
// - SFDITEM_FIELD__TIM14_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40002014) TG
//
// ( (unsigned int) TIM14_EGR )
// TG
//
//
//
// -------------------------------- Field Item: TIM14_EGR_BG ------------------------------------
// SVD Line: 8207
// - SFDITEM_FIELD__TIM14_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40002014) BG
//
// ( (unsigned int) TIM14_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 8174
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40002014) event generation register
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// - SFDITEM_FIELD__TIM14_EGR_CC2G
// - SFDITEM_FIELD__TIM14_EGR_CC3G
// - SFDITEM_FIELD__TIM14_EGR_CC4G
// - SFDITEM_FIELD__TIM14_EGR_COMG
// - SFDITEM_FIELD__TIM14_EGR_TG
// - SFDITEM_FIELD__TIM14_EGR_BG
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_OUTPUT ---------------------------
// SVD Line: 8213
unsigned int TIM14_CCMR1_OUTPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 8217
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) CC1S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 0) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 8221
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40002018) OC1FE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 8225
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002018) OC1PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1PE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M_L -----------------------------
// SVD Line: 8229
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M_L
// OC1M_L
//
// [Bits 6..4] RW (@ 0x40002018) OC1M_L
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 4) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 8233
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40002018) OC1CE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC2S ------------------------------
// SVD Line: 8237
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40002018) CC2S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 8) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 8241
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40002018) OC2FE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC2FE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 8245
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40002018) OC2PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC2PE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC2M_L -----------------------------
// SVD Line: 8249
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2M_L
// OC2M_L
//
// [Bits 14..12] RW (@ 0x40002018) OC2M_L
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 12) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 8253
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40002018) OC2CE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M_H -----------------------------
// SVD Line: 8257
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M_H
// OC1M_H
//
// [Bit 16] RW (@ 0x40002018) OC1M_H
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1M_H
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC2M_H -----------------------------
// SVD Line: 8261
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2M_H
// OC2M_H
//
// [Bit 24] RW (@ 0x40002018) OC2M_H
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC2M_H
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_OUTPUT -------------------------------
// SVD Line: 8213
// SFDITEM_REG__TIM14_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40002018) CCMR1_OUTPUT
// ( (unsigned int)((TIM14_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M_L
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2M_L
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M_H
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC2M_H
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_INPUT ----------------------------
// SVD Line: 8267
unsigned int TIM14_CCMR1_INPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 8272
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) CC1S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 0) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 8276
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002018) IC1PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 2) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 8280
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002018) IC1F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 4) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 8284
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40002018) CC2S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 8) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 8288
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40002018) IC2PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 10) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 8292
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40002018) IC2F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 12) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_INPUT -------------------------------
// SVD Line: 8267
// SFDITEM_REG__TIM14_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40002018) CCMR1_INPUT
// ( (unsigned int)((TIM14_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC2F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 8298
unsigned int TIM14_CCER __AT (0x40002020);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 8303
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002020) CC1E
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 8307
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002020) CC1P
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NE ----------------------------------
// SVD Line: 8311
// - SFDITEM_FIELD__TIM14_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40002020) CC1NE
//
// ( (unsigned int) TIM14_CCER )
// CC1NE
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 8315
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002020) CC1NP
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC2E ----------------------------------
// SVD Line: 8319
// - SFDITEM_FIELD__TIM14_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40002020) CC2E
//
// ( (unsigned int) TIM14_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC2P ----------------------------------
// SVD Line: 8323
// - SFDITEM_FIELD__TIM14_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40002020) CC2P
//
// ( (unsigned int) TIM14_CCER )
// CC2P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC2NE ----------------------------------
// SVD Line: 8327
// - SFDITEM_FIELD__TIM14_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40002020) CC2NE
//
// ( (unsigned int) TIM14_CCER )
// CC2NE
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC2NP ----------------------------------
// SVD Line: 8331
// - SFDITEM_FIELD__TIM14_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40002020) CC2NP
//
// ( (unsigned int) TIM14_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC3E ----------------------------------
// SVD Line: 8335
// - SFDITEM_FIELD__TIM14_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40002020) CC3E
//
// ( (unsigned int) TIM14_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC3P ----------------------------------
// SVD Line: 8339
// - SFDITEM_FIELD__TIM14_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40002020) CC3P
//
// ( (unsigned int) TIM14_CCER )
// CC3P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC3NE ----------------------------------
// SVD Line: 8343
// - SFDITEM_FIELD__TIM14_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40002020) CC3NE
//
// ( (unsigned int) TIM14_CCER )
// CC3NE
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC3NP ----------------------------------
// SVD Line: 8347
// - SFDITEM_FIELD__TIM14_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40002020) CC3NP
//
// ( (unsigned int) TIM14_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC4E ----------------------------------
// SVD Line: 8351
// - SFDITEM_FIELD__TIM14_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40002020) CC4E
//
// ( (unsigned int) TIM14_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC4P ----------------------------------
// SVD Line: 8355
// - SFDITEM_FIELD__TIM14_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40002020) CC4P
//
// ( (unsigned int) TIM14_CCER )
// CC4P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC4NP ----------------------------------
// SVD Line: 8359
// - SFDITEM_FIELD__TIM14_CCER_CC4NP
// CC4NP
//
// [Bit 15] RW (@ 0x40002020) CC4NP
//
// ( (unsigned int) TIM14_CCER )
// CC4NP
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC5E ----------------------------------
// SVD Line: 8363
// - SFDITEM_FIELD__TIM14_CCER_CC5E
// CC5E
//
// [Bit 16] RW (@ 0x40002020) CC5E
//
// ( (unsigned int) TIM14_CCER )
// CC5E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC5P ----------------------------------
// SVD Line: 8367
// - SFDITEM_FIELD__TIM14_CCER_CC5P
// CC5P
//
// [Bit 17] RW (@ 0x40002020) CC5P
//
// ( (unsigned int) TIM14_CCER )
// CC5P
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC6E ----------------------------------
// SVD Line: 8371
// - SFDITEM_FIELD__TIM14_CCER_CC6E
// CC6E
//
// [Bit 20] RW (@ 0x40002020) CC6E
//
// ( (unsigned int) TIM14_CCER )
// CC6E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC6P ----------------------------------
// SVD Line: 8375
// - SFDITEM_FIELD__TIM14_CCER_CC6P
// CC6P
//
// [Bit 21] RW (@ 0x40002020) CC6P
//
// ( (unsigned int) TIM14_CCER )
// CC6P
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 8298
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002020) capture/compare enableregister
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0x33BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NE
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// - SFDITEM_FIELD__TIM14_CCER_CC2E
// - SFDITEM_FIELD__TIM14_CCER_CC2P
// - SFDITEM_FIELD__TIM14_CCER_CC2NE
// - SFDITEM_FIELD__TIM14_CCER_CC2NP
// - SFDITEM_FIELD__TIM14_CCER_CC3E
// - SFDITEM_FIELD__TIM14_CCER_CC3P
// - SFDITEM_FIELD__TIM14_CCER_CC3NE
// - SFDITEM_FIELD__TIM14_CCER_CC3NP
// - SFDITEM_FIELD__TIM14_CCER_CC4E
// - SFDITEM_FIELD__TIM14_CCER_CC4P
// - SFDITEM_FIELD__TIM14_CCER_CC4NP
// - SFDITEM_FIELD__TIM14_CCER_CC5E
// - SFDITEM_FIELD__TIM14_CCER_CC5P
// - SFDITEM_FIELD__TIM14_CCER_CC6E
// - SFDITEM_FIELD__TIM14_CCER_CC6P
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 8381
unsigned int TIM14_CNT __AT (0x40002024);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 8386
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002024) CNT
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 8381
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002024) counter
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 8392
unsigned int TIM14_PSC __AT (0x40002028);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 8397
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002028) PSC
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 8392
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002028) prescaler
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 8403
unsigned int TIM14_ARR __AT (0x4000202C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 8408
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000202C) ARR
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 8403
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000202C) auto-reload register
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 8414
unsigned int TIM14_CCR1 __AT (0x40002034);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 8419
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002034) CCR1
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 8414
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002034) capture/compare register 1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// --------------------------- Register Item Address: TIM14_TISEL -------------------------------
// SVD Line: 8425
unsigned int TIM14_TISEL __AT (0x4000205C);
// ----------------------------- Field Item: TIM14_TISEL_TI1SEL ---------------------------------
// SVD Line: 8429
// - SFDITEM_FIELD__TIM14_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x4000205C) TI1SEL
//
// ( (unsigned char)((TIM14_TISEL >> 0) & 0xF), ((TIM14_TISEL = (TIM14_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_TISEL ----------------------------------
// SVD Line: 8425
// SFDITEM_REG__TIM14_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x4000205C) TISEL
// ( (unsigned int)((TIM14_TISEL >> 0) & 0xFFFFFFFF), ((TIM14_TISEL = (TIM14_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_TISEL_TI1SEL
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 7949
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_OUTPUT
// - SFDITEM_REG__TIM14_CCMR1_INPUT
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_TISEL
//
//
// ---------------------------- Register Item Address: TIM16_CR1 --------------------------------
// SVD Line: 8453
unsigned int TIM16_CR1 __AT (0x40014400);
// -------------------------------- Field Item: TIM16_CR1_CEN -----------------------------------
// SVD Line: 8458
// - SFDITEM_FIELD__TIM16_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40014400) CEN
//
// ( (unsigned int) TIM16_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM16_CR1_UDIS -----------------------------------
// SVD Line: 8462
// - SFDITEM_FIELD__TIM16_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40014400) UDIS
//
// ( (unsigned int) TIM16_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM16_CR1_URS -----------------------------------
// SVD Line: 8466
// - SFDITEM_FIELD__TIM16_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40014400) URS
//
// ( (unsigned int) TIM16_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM16_CR1_OPM -----------------------------------
// SVD Line: 8470
// - SFDITEM_FIELD__TIM16_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40014400) OPM
//
// ( (unsigned int) TIM16_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM16_CR1_DIR -----------------------------------
// SVD Line: 8474
// - SFDITEM_FIELD__TIM16_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40014400) DIR
//
// ( (unsigned int) TIM16_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM16_CR1_CMS -----------------------------------
// SVD Line: 8478
// - SFDITEM_FIELD__TIM16_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40014400) CMS
//
// ( (unsigned char)((TIM16_CR1 >> 5) & 0x3), ((TIM16_CR1 = (TIM16_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_CR1_ARPE -----------------------------------
// SVD Line: 8482
// - SFDITEM_FIELD__TIM16_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40014400) ARPE
//
// ( (unsigned int) TIM16_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM16_CR1_CKD -----------------------------------
// SVD Line: 8486
// - SFDITEM_FIELD__TIM16_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40014400) CKD
//
// ( (unsigned char)((TIM16_CR1 >> 8) & 0x3), ((TIM16_CR1 = (TIM16_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_CR1 -----------------------------------
// SVD Line: 8453
// SFDITEM_REG__TIM16_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40014400) TIM16 control register1
// ( (unsigned int)((TIM16_CR1 >> 0) & 0xFFFFFFFF), ((TIM16_CR1 = (TIM16_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CR1_CEN
// - SFDITEM_FIELD__TIM16_CR1_UDIS
// - SFDITEM_FIELD__TIM16_CR1_URS
// - SFDITEM_FIELD__TIM16_CR1_OPM
// - SFDITEM_FIELD__TIM16_CR1_DIR
// - SFDITEM_FIELD__TIM16_CR1_CMS
// - SFDITEM_FIELD__TIM16_CR1_ARPE
// - SFDITEM_FIELD__TIM16_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM16_CR2 --------------------------------
// SVD Line: 8492
unsigned int TIM16_CR2 __AT (0x40014404);
// ------------------------------- Field Item: TIM16_CR2_CCPC -----------------------------------
// SVD Line: 8497
// - SFDITEM_FIELD__TIM16_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40014404) CCPC
//
// ( (unsigned int) TIM16_CR2 )
// CCPC
//
//
//
// ------------------------------- Field Item: TIM16_CR2_CCUS -----------------------------------
// SVD Line: 8501
// - SFDITEM_FIELD__TIM16_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40014404) CCUS
//
// ( (unsigned int) TIM16_CR2 )
// CCUS
//
//
//
// ------------------------------- Field Item: TIM16_CR2_CCDS -----------------------------------
// SVD Line: 8505
// - SFDITEM_FIELD__TIM16_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40014404) CCDS
//
// ( (unsigned int) TIM16_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM16_CR2_MMS_L ----------------------------------
// SVD Line: 8509
// - SFDITEM_FIELD__TIM16_CR2_MMS_L
// MMS_L
//
// [Bits 6..4] RW (@ 0x40014404) MMS_L
//
// ( (unsigned char)((TIM16_CR2 >> 4) & 0x7), ((TIM16_CR2 = (TIM16_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_CR2_TI1S -----------------------------------
// SVD Line: 8513
// - SFDITEM_FIELD__TIM16_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40014404) TI1S
//
// ( (unsigned int) TIM16_CR2 )
// TI1S
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS1 -----------------------------------
// SVD Line: 8517
// - SFDITEM_FIELD__TIM16_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40014404) OIS1
//
// ( (unsigned int) TIM16_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS1N ----------------------------------
// SVD Line: 8521
// - SFDITEM_FIELD__TIM16_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40014404) OIS1N
//
// ( (unsigned int) TIM16_CR2 )
// OIS1N
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS2 -----------------------------------
// SVD Line: 8525
// - SFDITEM_FIELD__TIM16_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40014404) OIS2
//
// ( (unsigned int) TIM16_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS2N ----------------------------------
// SVD Line: 8529
// - SFDITEM_FIELD__TIM16_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40014404) OIS2N
//
// ( (unsigned int) TIM16_CR2 )
// OIS2N
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS3 -----------------------------------
// SVD Line: 8533
// - SFDITEM_FIELD__TIM16_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40014404) OIS3
//
// ( (unsigned int) TIM16_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS3N ----------------------------------
// SVD Line: 8537
// - SFDITEM_FIELD__TIM16_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40014404) OIS3N
//
// ( (unsigned int) TIM16_CR2 )
// OIS3N
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS4 -----------------------------------
// SVD Line: 8541
// - SFDITEM_FIELD__TIM16_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40014404) OIS4
//
// ( (unsigned int) TIM16_CR2 )
// OIS4
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS5 -----------------------------------
// SVD Line: 8545
// - SFDITEM_FIELD__TIM16_CR2_OIS5
// OIS5
//
// [Bit 16] RW (@ 0x40014404) OIS5
//
// ( (unsigned int) TIM16_CR2 )
// OIS5
//
//
//
// ------------------------------- Field Item: TIM16_CR2_OIS6 -----------------------------------
// SVD Line: 8549
// - SFDITEM_FIELD__TIM16_CR2_OIS6
// OIS6
//
// [Bit 18] RW (@ 0x40014404) OIS6
//
// ( (unsigned int) TIM16_CR2 )
// OIS6
//
//
//
// ------------------------------- Field Item: TIM16_CR2_MMS_H ----------------------------------
// SVD Line: 8553
// - SFDITEM_FIELD__TIM16_CR2_MMS_H
// MMS_H
//
// [Bit 25] RW (@ 0x40014404) MMS_H
//
// ( (unsigned int) TIM16_CR2 )
// MMS_H
//
//
//
// -------------------------------- Register RTree: TIM16_CR2 -----------------------------------
// SVD Line: 8492
// SFDITEM_REG__TIM16_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40014404) control register 2
// ( (unsigned int)((TIM16_CR2 >> 0) & 0xFFFFFFFF), ((TIM16_CR2 = (TIM16_CR2 & ~(0x2057FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2057FFD) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CR2_CCPC
// - SFDITEM_FIELD__TIM16_CR2_CCUS
// - SFDITEM_FIELD__TIM16_CR2_CCDS
// - SFDITEM_FIELD__TIM16_CR2_MMS_L
// - SFDITEM_FIELD__TIM16_CR2_TI1S
// - SFDITEM_FIELD__TIM16_CR2_OIS1
// - SFDITEM_FIELD__TIM16_CR2_OIS1N
// - SFDITEM_FIELD__TIM16_CR2_OIS2
// - SFDITEM_FIELD__TIM16_CR2_OIS2N
// - SFDITEM_FIELD__TIM16_CR2_OIS3
// - SFDITEM_FIELD__TIM16_CR2_OIS3N
// - SFDITEM_FIELD__TIM16_CR2_OIS4
// - SFDITEM_FIELD__TIM16_CR2_OIS5
// - SFDITEM_FIELD__TIM16_CR2_OIS6
// - SFDITEM_FIELD__TIM16_CR2_MMS_H
//
//
// ---------------------------- Register Item Address: TIM16_DIER -------------------------------
// SVD Line: 8559
unsigned int TIM16_DIER __AT (0x4001440C);
// ------------------------------- Field Item: TIM16_DIER_UIE -----------------------------------
// SVD Line: 8564
// - SFDITEM_FIELD__TIM16_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4001440C) UIE
//
// ( (unsigned int) TIM16_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC1IE ----------------------------------
// SVD Line: 8568
// - SFDITEM_FIELD__TIM16_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4001440C) CC1IE
//
// ( (unsigned int) TIM16_DIER )
// CC1IE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC2IE ----------------------------------
// SVD Line: 8572
// - SFDITEM_FIELD__TIM16_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x4001440C) CC2IE
//
// ( (unsigned int) TIM16_DIER )
// CC2IE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC3IE ----------------------------------
// SVD Line: 8576
// - SFDITEM_FIELD__TIM16_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x4001440C) CC3IE
//
// ( (unsigned int) TIM16_DIER )
// CC3IE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC4IE ----------------------------------
// SVD Line: 8580
// - SFDITEM_FIELD__TIM16_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x4001440C) CC4IE
//
// ( (unsigned int) TIM16_DIER )
// CC4IE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_COMIE ----------------------------------
// SVD Line: 8584
// - SFDITEM_FIELD__TIM16_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4001440C) COMIE
//
// ( (unsigned int) TIM16_DIER )
// COMIE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_TIE -----------------------------------
// SVD Line: 8588
// - SFDITEM_FIELD__TIM16_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x4001440C) TIE
//
// ( (unsigned int) TIM16_DIER )
// TIE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_BIE -----------------------------------
// SVD Line: 8592
// - SFDITEM_FIELD__TIM16_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4001440C) BIE
//
// ( (unsigned int) TIM16_DIER )
// BIE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_UDE -----------------------------------
// SVD Line: 8596
// - SFDITEM_FIELD__TIM16_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4001440C) UDE
//
// ( (unsigned int) TIM16_DIER )
// UDE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC1DE ----------------------------------
// SVD Line: 8600
// - SFDITEM_FIELD__TIM16_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4001440C) CC1DE
//
// ( (unsigned int) TIM16_DIER )
// CC1DE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC2DE ----------------------------------
// SVD Line: 8604
// - SFDITEM_FIELD__TIM16_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x4001440C) CC2DE
//
// ( (unsigned int) TIM16_DIER )
// CC2DE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC3DE ----------------------------------
// SVD Line: 8608
// - SFDITEM_FIELD__TIM16_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x4001440C) CC3DE
//
// ( (unsigned int) TIM16_DIER )
// CC3DE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_CC4DE ----------------------------------
// SVD Line: 8612
// - SFDITEM_FIELD__TIM16_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x4001440C) CC4DE
//
// ( (unsigned int) TIM16_DIER )
// CC4DE
//
//
//
// ------------------------------ Field Item: TIM16_DIER_COMDE ----------------------------------
// SVD Line: 8616
// - SFDITEM_FIELD__TIM16_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x4001440C) COMDE
//
// ( (unsigned int) TIM16_DIER )
// COMDE
//
//
//
// ------------------------------- Field Item: TIM16_DIER_TDE -----------------------------------
// SVD Line: 8620
// - SFDITEM_FIELD__TIM16_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x4001440C) TDE
//
// ( (unsigned int) TIM16_DIER )
// TDE
//
//
//
// ------------------------------- Register RTree: TIM16_DIER -----------------------------------
// SVD Line: 8559
// SFDITEM_REG__TIM16_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4001440C) DMA/Interrupt enable register
// ( (unsigned int)((TIM16_DIER >> 0) & 0xFFFFFFFF), ((TIM16_DIER = (TIM16_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DIER_UIE
// - SFDITEM_FIELD__TIM16_DIER_CC1IE
// - SFDITEM_FIELD__TIM16_DIER_CC2IE
// - SFDITEM_FIELD__TIM16_DIER_CC3IE
// - SFDITEM_FIELD__TIM16_DIER_CC4IE
// - SFDITEM_FIELD__TIM16_DIER_COMIE
// - SFDITEM_FIELD__TIM16_DIER_TIE
// - SFDITEM_FIELD__TIM16_DIER_BIE
// - SFDITEM_FIELD__TIM16_DIER_UDE
// - SFDITEM_FIELD__TIM16_DIER_CC1DE
// - SFDITEM_FIELD__TIM16_DIER_CC2DE
// - SFDITEM_FIELD__TIM16_DIER_CC3DE
// - SFDITEM_FIELD__TIM16_DIER_CC4DE
// - SFDITEM_FIELD__TIM16_DIER_COMDE
// - SFDITEM_FIELD__TIM16_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM16_SR --------------------------------
// SVD Line: 8626
unsigned int TIM16_SR __AT (0x40014410);
// -------------------------------- Field Item: TIM16_SR_UIF ------------------------------------
// SVD Line: 8631
// - SFDITEM_FIELD__TIM16_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40014410) UIF
//
// ( (unsigned int) TIM16_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC1IF -----------------------------------
// SVD Line: 8635
// - SFDITEM_FIELD__TIM16_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40014410) CC1IF
//
// ( (unsigned int) TIM16_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC2IF -----------------------------------
// SVD Line: 8639
// - SFDITEM_FIELD__TIM16_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40014410) CC2IF
//
// ( (unsigned int) TIM16_SR )
// CC2IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC3IF -----------------------------------
// SVD Line: 8643
// - SFDITEM_FIELD__TIM16_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40014410) CC3IF
//
// ( (unsigned int) TIM16_SR )
// CC3IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC4IF -----------------------------------
// SVD Line: 8647
// - SFDITEM_FIELD__TIM16_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40014410) CC4IF
//
// ( (unsigned int) TIM16_SR )
// CC4IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_COMIF -----------------------------------
// SVD Line: 8651
// - SFDITEM_FIELD__TIM16_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40014410) COMIF
//
// ( (unsigned int) TIM16_SR )
// COMIF
//
//
//
// -------------------------------- Field Item: TIM16_SR_TIF ------------------------------------
// SVD Line: 8655
// - SFDITEM_FIELD__TIM16_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40014410) TIF
//
// ( (unsigned int) TIM16_SR )
// TIF
//
//
//
// -------------------------------- Field Item: TIM16_SR_BIF ------------------------------------
// SVD Line: 8659
// - SFDITEM_FIELD__TIM16_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40014410) BIF
//
// ( (unsigned int) TIM16_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM16_SR_B2IF -----------------------------------
// SVD Line: 8663
// - SFDITEM_FIELD__TIM16_SR_B2IF
// B2IF
//
// [Bit 8] RW (@ 0x40014410) B2IF
//
// ( (unsigned int) TIM16_SR )
// B2IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC1OF -----------------------------------
// SVD Line: 8667
// - SFDITEM_FIELD__TIM16_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40014410) CC1OF
//
// ( (unsigned int) TIM16_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC2OF -----------------------------------
// SVD Line: 8671
// - SFDITEM_FIELD__TIM16_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40014410) CC2OF
//
// ( (unsigned int) TIM16_SR )
// CC2OF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC3OF -----------------------------------
// SVD Line: 8675
// - SFDITEM_FIELD__TIM16_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40014410) CC3OF
//
// ( (unsigned int) TIM16_SR )
// CC3OF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC4OF -----------------------------------
// SVD Line: 8679
// - SFDITEM_FIELD__TIM16_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40014410) CC4OF
//
// ( (unsigned int) TIM16_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM16_SR_SBIF -----------------------------------
// SVD Line: 8683
// - SFDITEM_FIELD__TIM16_SR_SBIF
// SBIF
//
// [Bit 13] RW (@ 0x40014410) SBIF
//
// ( (unsigned int) TIM16_SR )
// SBIF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC5IF -----------------------------------
// SVD Line: 8687
// - SFDITEM_FIELD__TIM16_SR_CC5IF
// CC5IF
//
// [Bit 16] RW (@ 0x40014410) CC5IF
//
// ( (unsigned int) TIM16_SR )
// CC5IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_CC6IF -----------------------------------
// SVD Line: 8691
// - SFDITEM_FIELD__TIM16_SR_CC6IF
// CC6IF
//
// [Bit 17] RW (@ 0x40014410) CC6IF
//
// ( (unsigned int) TIM16_SR )
// CC6IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC1IR -----------------------------------
// SVD Line: 8695
// - SFDITEM_FIELD__TIM16_SR_IC1IR
// IC1IR
//
// [Bit 18] RW (@ 0x40014410) IC1IR
//
// ( (unsigned int) TIM16_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC2IR -----------------------------------
// SVD Line: 8699
// - SFDITEM_FIELD__TIM16_SR_IC2IR
// IC2IR
//
// [Bit 19] RW (@ 0x40014410) IC2IR
//
// ( (unsigned int) TIM16_SR )
// IC2IR
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC3IR -----------------------------------
// SVD Line: 8703
// - SFDITEM_FIELD__TIM16_SR_IC3IR
// IC3IR
//
// [Bit 24] RW (@ 0x40014410) IC3IR
//
// ( (unsigned int) TIM16_SR )
// IC3IR
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC4IR -----------------------------------
// SVD Line: 8707
// - SFDITEM_FIELD__TIM16_SR_IC4IR
// IC4IR
//
// [Bit 25] RW (@ 0x40014410) IC4IR
//
// ( (unsigned int) TIM16_SR )
// IC4IR
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC1IF -----------------------------------
// SVD Line: 8711
// - SFDITEM_FIELD__TIM16_SR_IC1IF
// IC1IF
//
// [Bit 26] RW (@ 0x40014410) IC1IF
//
// ( (unsigned int) TIM16_SR )
// IC1IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC2IF -----------------------------------
// SVD Line: 8715
// - SFDITEM_FIELD__TIM16_SR_IC2IF
// IC2IF
//
// [Bit 27] RW (@ 0x40014410) IC2IF
//
// ( (unsigned int) TIM16_SR )
// IC2IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC3IF -----------------------------------
// SVD Line: 8719
// - SFDITEM_FIELD__TIM16_SR_IC3IF
// IC3IF
//
// [Bit 28] RW (@ 0x40014410) IC3IF
//
// ( (unsigned int) TIM16_SR )
// IC3IF
//
//
//
// ------------------------------- Field Item: TIM16_SR_IC4IF -----------------------------------
// SVD Line: 8723
// - SFDITEM_FIELD__TIM16_SR_IC4IF
// IC4IF
//
// [Bit 29] RW (@ 0x40014410) IC4IF
//
// ( (unsigned int) TIM16_SR )
// IC4IF
//
//
//
// -------------------------------- Register RTree: TIM16_SR ------------------------------------
// SVD Line: 8626
// SFDITEM_REG__TIM16_SR
// SR
//
// [Bits 31..0] RW (@ 0x40014410) status register
// ( (unsigned int)((TIM16_SR >> 0) & 0xFFFFFFFF), ((TIM16_SR = (TIM16_SR & ~(0x3F0F3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_SR_UIF
// - SFDITEM_FIELD__TIM16_SR_CC1IF
// - SFDITEM_FIELD__TIM16_SR_CC2IF
// - SFDITEM_FIELD__TIM16_SR_CC3IF
// - SFDITEM_FIELD__TIM16_SR_CC4IF
// - SFDITEM_FIELD__TIM16_SR_COMIF
// - SFDITEM_FIELD__TIM16_SR_TIF
// - SFDITEM_FIELD__TIM16_SR_BIF
// - SFDITEM_FIELD__TIM16_SR_B2IF
// - SFDITEM_FIELD__TIM16_SR_CC1OF
// - SFDITEM_FIELD__TIM16_SR_CC2OF
// - SFDITEM_FIELD__TIM16_SR_CC3OF
// - SFDITEM_FIELD__TIM16_SR_CC4OF
// - SFDITEM_FIELD__TIM16_SR_SBIF
// - SFDITEM_FIELD__TIM16_SR_CC5IF
// - SFDITEM_FIELD__TIM16_SR_CC6IF
// - SFDITEM_FIELD__TIM16_SR_IC1IR
// - SFDITEM_FIELD__TIM16_SR_IC2IR
// - SFDITEM_FIELD__TIM16_SR_IC3IR
// - SFDITEM_FIELD__TIM16_SR_IC4IR
// - SFDITEM_FIELD__TIM16_SR_IC1IF
// - SFDITEM_FIELD__TIM16_SR_IC2IF
// - SFDITEM_FIELD__TIM16_SR_IC3IF
// - SFDITEM_FIELD__TIM16_SR_IC4IF
//
//
// ---------------------------- Register Item Address: TIM16_EGR --------------------------------
// SVD Line: 8729
unsigned int TIM16_EGR __AT (0x40014414);
// -------------------------------- Field Item: TIM16_EGR_UG ------------------------------------
// SVD Line: 8734
// - SFDITEM_FIELD__TIM16_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40014414) UG
//
// ( (unsigned int) TIM16_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM16_EGR_CC1G -----------------------------------
// SVD Line: 8738
// - SFDITEM_FIELD__TIM16_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40014414) CC1G
//
// ( (unsigned int) TIM16_EGR )
// CC1G
//
//
//
// ------------------------------- Field Item: TIM16_EGR_CC2G -----------------------------------
// SVD Line: 8742
// - SFDITEM_FIELD__TIM16_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40014414) CC2G
//
// ( (unsigned int) TIM16_EGR )
// CC2G
//
//
//
// ------------------------------- Field Item: TIM16_EGR_CC3G -----------------------------------
// SVD Line: 8746
// - SFDITEM_FIELD__TIM16_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40014414) CC3G
//
// ( (unsigned int) TIM16_EGR )
// CC3G
//
//
//
// ------------------------------- Field Item: TIM16_EGR_CC4G -----------------------------------
// SVD Line: 8750
// - SFDITEM_FIELD__TIM16_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40014414) CC4G
//
// ( (unsigned int) TIM16_EGR )
// CC4G
//
//
//
// ------------------------------- Field Item: TIM16_EGR_COMG -----------------------------------
// SVD Line: 8754
// - SFDITEM_FIELD__TIM16_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40014414) COMG
//
// ( (unsigned int) TIM16_EGR )
// COMG
//
//
//
// -------------------------------- Field Item: TIM16_EGR_TG ------------------------------------
// SVD Line: 8758
// - SFDITEM_FIELD__TIM16_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40014414) TG
//
// ( (unsigned int) TIM16_EGR )
// TG
//
//
//
// -------------------------------- Field Item: TIM16_EGR_BG ------------------------------------
// SVD Line: 8762
// - SFDITEM_FIELD__TIM16_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40014414) BG
//
// ( (unsigned int) TIM16_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM16_EGR -----------------------------------
// SVD Line: 8729
// SFDITEM_REG__TIM16_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40014414) event generation register
// ( (unsigned int)((TIM16_EGR >> 0) & 0xFFFFFFFF), ((TIM16_EGR = (TIM16_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_EGR_UG
// - SFDITEM_FIELD__TIM16_EGR_CC1G
// - SFDITEM_FIELD__TIM16_EGR_CC2G
// - SFDITEM_FIELD__TIM16_EGR_CC3G
// - SFDITEM_FIELD__TIM16_EGR_CC4G
// - SFDITEM_FIELD__TIM16_EGR_COMG
// - SFDITEM_FIELD__TIM16_EGR_TG
// - SFDITEM_FIELD__TIM16_EGR_BG
//
//
// ------------------------ Register Item Address: TIM16_CCMR1_OUTPUT ---------------------------
// SVD Line: 8768
unsigned int TIM16_CCMR1_OUTPUT __AT (0x40014418);
// --------------------------- Field Item: TIM16_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 8772
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014418) CC1S
//
// ( (unsigned char)((TIM16_CCMR1_OUTPUT >> 0) & 0x3), ((TIM16_CCMR1_OUTPUT = (TIM16_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 8776
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40014418) OC1FE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 8780
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40014418) OC1PE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC1PE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC1M_L -----------------------------
// SVD Line: 8784
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1M_L
// OC1M_L
//
// [Bits 6..4] RW (@ 0x40014418) OC1M_L
//
// ( (unsigned char)((TIM16_CCMR1_OUTPUT >> 4) & 0x7), ((TIM16_CCMR1_OUTPUT = (TIM16_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 8788
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40014418) OC1CE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_OUTPUT_CC2S ------------------------------
// SVD Line: 8792
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40014418) CC2S
//
// ( (unsigned char)((TIM16_CCMR1_OUTPUT >> 8) & 0x3), ((TIM16_CCMR1_OUTPUT = (TIM16_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 8796
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40014418) OC2FE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC2FE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 8800
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40014418) OC2PE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC2PE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC2M_L -----------------------------
// SVD Line: 8804
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2M_L
// OC2M_L
//
// [Bits 14..12] RW (@ 0x40014418) OC2M_L
//
// ( (unsigned char)((TIM16_CCMR1_OUTPUT >> 12) & 0x7), ((TIM16_CCMR1_OUTPUT = (TIM16_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 8808
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40014418) OC2CE
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC1M_H -----------------------------
// SVD Line: 8812
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1M_H
// OC1M_H
//
// [Bit 16] RW (@ 0x40014418) OC1M_H
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC1M_H
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_OUTPUT_OC2M_H -----------------------------
// SVD Line: 8816
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2M_H
// OC2M_H
//
// [Bit 24] RW (@ 0x40014418) OC2M_H
//
// ( (unsigned int) TIM16_CCMR1_OUTPUT )
// OC2M_H
//
//
//
// --------------------------- Register RTree: TIM16_CCMR1_OUTPUT -------------------------------
// SVD Line: 8768
// SFDITEM_REG__TIM16_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40014418) CCMR1_OUTPUT
// ( (unsigned int)((TIM16_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM16_CCMR1_OUTPUT = (TIM16_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1M_L
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2M_L
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC1M_H
// - SFDITEM_FIELD__TIM16_CCMR1_OUTPUT_OC2M_H
//
//
// ------------------------ Register Item Address: TIM16_CCMR1_INPUT ----------------------------
// SVD Line: 8822
unsigned int TIM16_CCMR1_INPUT __AT (0x40014418);
// --------------------------- Field Item: TIM16_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 8827
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014418) CC1S
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 0) & 0x3), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 8831
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40014418) IC1PSC
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 2) & 0x3), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 8835
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40014418) IC1F
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 4) & 0xF), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 8839
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40014418) CC2S
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 8) & 0x3), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM16_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 8843
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40014418) IC2PSC
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 10) & 0x3), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------- Field Item: TIM16_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 8847
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40014418) IC2F
//
// ( (unsigned char)((TIM16_CCMR1_INPUT >> 12) & 0xF), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM16_CCMR1_INPUT -------------------------------
// SVD Line: 8822
// SFDITEM_REG__TIM16_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40014418) CCMR1_INPUT
// ( (unsigned int)((TIM16_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM16_CCMR1_INPUT = (TIM16_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM16_CCMR1_INPUT_IC2F
//
//
// ---------------------------- Register Item Address: TIM16_CCER -------------------------------
// SVD Line: 8853
unsigned int TIM16_CCER __AT (0x40014420);
// ------------------------------- Field Item: TIM16_CCER_CC1E ----------------------------------
// SVD Line: 8858
// - SFDITEM_FIELD__TIM16_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40014420) CC1E
//
// ( (unsigned int) TIM16_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC1P ----------------------------------
// SVD Line: 8862
// - SFDITEM_FIELD__TIM16_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40014420) CC1P
//
// ( (unsigned int) TIM16_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC1NE ----------------------------------
// SVD Line: 8866
// - SFDITEM_FIELD__TIM16_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40014420) CC1NE
//
// ( (unsigned int) TIM16_CCER )
// CC1NE
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC1NP ----------------------------------
// SVD Line: 8870
// - SFDITEM_FIELD__TIM16_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40014420) CC1NP
//
// ( (unsigned int) TIM16_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC2E ----------------------------------
// SVD Line: 8874
// - SFDITEM_FIELD__TIM16_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40014420) CC2E
//
// ( (unsigned int) TIM16_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC2P ----------------------------------
// SVD Line: 8878
// - SFDITEM_FIELD__TIM16_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40014420) CC2P
//
// ( (unsigned int) TIM16_CCER )
// CC2P
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC2NE ----------------------------------
// SVD Line: 8882
// - SFDITEM_FIELD__TIM16_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40014420) CC2NE
//
// ( (unsigned int) TIM16_CCER )
// CC2NE
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC2NP ----------------------------------
// SVD Line: 8886
// - SFDITEM_FIELD__TIM16_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40014420) CC2NP
//
// ( (unsigned int) TIM16_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC3E ----------------------------------
// SVD Line: 8890
// - SFDITEM_FIELD__TIM16_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40014420) CC3E
//
// ( (unsigned int) TIM16_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC3P ----------------------------------
// SVD Line: 8894
// - SFDITEM_FIELD__TIM16_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40014420) CC3P
//
// ( (unsigned int) TIM16_CCER )
// CC3P
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC3NE ----------------------------------
// SVD Line: 8898
// - SFDITEM_FIELD__TIM16_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40014420) CC3NE
//
// ( (unsigned int) TIM16_CCER )
// CC3NE
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC3NP ----------------------------------
// SVD Line: 8902
// - SFDITEM_FIELD__TIM16_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40014420) CC3NP
//
// ( (unsigned int) TIM16_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC4E ----------------------------------
// SVD Line: 8906
// - SFDITEM_FIELD__TIM16_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40014420) CC4E
//
// ( (unsigned int) TIM16_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC4P ----------------------------------
// SVD Line: 8910
// - SFDITEM_FIELD__TIM16_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40014420) CC4P
//
// ( (unsigned int) TIM16_CCER )
// CC4P
//
//
//
// ------------------------------ Field Item: TIM16_CCER_CC4NP ----------------------------------
// SVD Line: 8914
// - SFDITEM_FIELD__TIM16_CCER_CC4NP
// CC4NP
//
// [Bit 15] RW (@ 0x40014420) CC4NP
//
// ( (unsigned int) TIM16_CCER )
// CC4NP
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC5E ----------------------------------
// SVD Line: 8918
// - SFDITEM_FIELD__TIM16_CCER_CC5E
// CC5E
//
// [Bit 16] RW (@ 0x40014420) CC5E
//
// ( (unsigned int) TIM16_CCER )
// CC5E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC5P ----------------------------------
// SVD Line: 8922
// - SFDITEM_FIELD__TIM16_CCER_CC5P
// CC5P
//
// [Bit 17] RW (@ 0x40014420) CC5P
//
// ( (unsigned int) TIM16_CCER )
// CC5P
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC6E ----------------------------------
// SVD Line: 8926
// - SFDITEM_FIELD__TIM16_CCER_CC6E
// CC6E
//
// [Bit 20] RW (@ 0x40014420) CC6E
//
// ( (unsigned int) TIM16_CCER )
// CC6E
//
//
//
// ------------------------------- Field Item: TIM16_CCER_CC6P ----------------------------------
// SVD Line: 8930
// - SFDITEM_FIELD__TIM16_CCER_CC6P
// CC6P
//
// [Bit 21] RW (@ 0x40014420) CC6P
//
// ( (unsigned int) TIM16_CCER )
// CC6P
//
//
//
// ------------------------------- Register RTree: TIM16_CCER -----------------------------------
// SVD Line: 8853
// SFDITEM_REG__TIM16_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40014420) capture/compare enableregister
// ( (unsigned int)((TIM16_CCER >> 0) & 0xFFFFFFFF), ((TIM16_CCER = (TIM16_CCER & ~(0x33BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCER_CC1E
// - SFDITEM_FIELD__TIM16_CCER_CC1P
// - SFDITEM_FIELD__TIM16_CCER_CC1NE
// - SFDITEM_FIELD__TIM16_CCER_CC1NP
// - SFDITEM_FIELD__TIM16_CCER_CC2E
// - SFDITEM_FIELD__TIM16_CCER_CC2P
// - SFDITEM_FIELD__TIM16_CCER_CC2NE
// - SFDITEM_FIELD__TIM16_CCER_CC2NP
// - SFDITEM_FIELD__TIM16_CCER_CC3E
// - SFDITEM_FIELD__TIM16_CCER_CC3P
// - SFDITEM_FIELD__TIM16_CCER_CC3NE
// - SFDITEM_FIELD__TIM16_CCER_CC3NP
// - SFDITEM_FIELD__TIM16_CCER_CC4E
// - SFDITEM_FIELD__TIM16_CCER_CC4P
// - SFDITEM_FIELD__TIM16_CCER_CC4NP
// - SFDITEM_FIELD__TIM16_CCER_CC5E
// - SFDITEM_FIELD__TIM16_CCER_CC5P
// - SFDITEM_FIELD__TIM16_CCER_CC6E
// - SFDITEM_FIELD__TIM16_CCER_CC6P
//
//
// ---------------------------- Register Item Address: TIM16_CNT --------------------------------
// SVD Line: 8936
unsigned int TIM16_CNT __AT (0x40014424);
// -------------------------------- Field Item: TIM16_CNT_CNT -----------------------------------
// SVD Line: 8941
// - SFDITEM_FIELD__TIM16_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40014424) CNT
//
// ( (unsigned short)((TIM16_CNT >> 0) & 0xFFFF), ((TIM16_CNT = (TIM16_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_CNT -----------------------------------
// SVD Line: 8936
// SFDITEM_REG__TIM16_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40014424) counter
// ( (unsigned int)((TIM16_CNT >> 0) & 0xFFFFFFFF), ((TIM16_CNT = (TIM16_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM16_PSC --------------------------------
// SVD Line: 8947
unsigned int TIM16_PSC __AT (0x40014428);
// -------------------------------- Field Item: TIM16_PSC_PSC -----------------------------------
// SVD Line: 8952
// - SFDITEM_FIELD__TIM16_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40014428) PSC
//
// ( (unsigned short)((TIM16_PSC >> 0) & 0xFFFF), ((TIM16_PSC = (TIM16_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_PSC -----------------------------------
// SVD Line: 8947
// SFDITEM_REG__TIM16_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40014428) prescaler
// ( (unsigned int)((TIM16_PSC >> 0) & 0xFFFFFFFF), ((TIM16_PSC = (TIM16_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM16_ARR --------------------------------
// SVD Line: 8958
unsigned int TIM16_ARR __AT (0x4001442C);
// -------------------------------- Field Item: TIM16_ARR_ARR -----------------------------------
// SVD Line: 8963
// - SFDITEM_FIELD__TIM16_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4001442C) ARR
//
// ( (unsigned short)((TIM16_ARR >> 0) & 0xFFFF), ((TIM16_ARR = (TIM16_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_ARR -----------------------------------
// SVD Line: 8958
// SFDITEM_REG__TIM16_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4001442C) auto-reload register
// ( (unsigned int)((TIM16_ARR >> 0) & 0xFFFFFFFF), ((TIM16_ARR = (TIM16_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM16_RCR --------------------------------
// SVD Line: 8969
unsigned int TIM16_RCR __AT (0x40014430);
// -------------------------------- Field Item: TIM16_RCR_REP -----------------------------------
// SVD Line: 8974
// - SFDITEM_FIELD__TIM16_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40014430) REP
//
// ( (unsigned char)((TIM16_RCR >> 0) & 0xFF), ((TIM16_RCR = (TIM16_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_RCR -----------------------------------
// SVD Line: 8969
// SFDITEM_REG__TIM16_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40014430) repetition counter register
// ( (unsigned int)((TIM16_RCR >> 0) & 0xFFFFFFFF), ((TIM16_RCR = (TIM16_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM16_CCR1 -------------------------------
// SVD Line: 8980
unsigned int TIM16_CCR1 __AT (0x40014434);
// ------------------------------- Field Item: TIM16_CCR1_CCR1 ----------------------------------
// SVD Line: 8985
// - SFDITEM_FIELD__TIM16_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40014434) CCR1
//
// ( (unsigned short)((TIM16_CCR1 >> 0) & 0xFFFF), ((TIM16_CCR1 = (TIM16_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM16_CCR1 -----------------------------------
// SVD Line: 8980
// SFDITEM_REG__TIM16_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40014434) capture/compare register 1
// ( (unsigned int)((TIM16_CCR1 >> 0) & 0xFFFFFFFF), ((TIM16_CCR1 = (TIM16_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM16_BDTR -------------------------------
// SVD Line: 8991
unsigned int TIM16_BDTR __AT (0x40014444);
// ------------------------------- Field Item: TIM16_BDTR_DTG -----------------------------------
// SVD Line: 8996
// - SFDITEM_FIELD__TIM16_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40014444) DTG
//
// ( (unsigned char)((TIM16_BDTR >> 0) & 0xFF), ((TIM16_BDTR = (TIM16_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_LOCK ----------------------------------
// SVD Line: 9000
// - SFDITEM_FIELD__TIM16_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40014444) LOCK
//
// ( (unsigned char)((TIM16_BDTR >> 8) & 0x3), ((TIM16_BDTR = (TIM16_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_OSSI ----------------------------------
// SVD Line: 9004
// - SFDITEM_FIELD__TIM16_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40014444) OSSI
//
// ( (unsigned int) TIM16_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_OSSR ----------------------------------
// SVD Line: 9008
// - SFDITEM_FIELD__TIM16_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40014444) OSSR
//
// ( (unsigned int) TIM16_BDTR )
// OSSR
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_BKE -----------------------------------
// SVD Line: 9012
// - SFDITEM_FIELD__TIM16_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40014444) BKE
//
// ( (unsigned int) TIM16_BDTR )
// BKE
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_BKP -----------------------------------
// SVD Line: 9016
// - SFDITEM_FIELD__TIM16_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40014444) BKP
//
// ( (unsigned int) TIM16_BDTR )
// BKP
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_AOE -----------------------------------
// SVD Line: 9020
// - SFDITEM_FIELD__TIM16_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40014444) AOE
//
// ( (unsigned int) TIM16_BDTR )
// AOE
//
//
//
// ------------------------------- Field Item: TIM16_BDTR_MOE -----------------------------------
// SVD Line: 9024
// - SFDITEM_FIELD__TIM16_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40014444) MOE
//
// ( (unsigned int) TIM16_BDTR )
// MOE
//
//
//
// ------------------------------- Register RTree: TIM16_BDTR -----------------------------------
// SVD Line: 8991
// SFDITEM_REG__TIM16_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40014444) break and dead-time register
// ( (unsigned int)((TIM16_BDTR >> 0) & 0xFFFFFFFF), ((TIM16_BDTR = (TIM16_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_BDTR_DTG
// - SFDITEM_FIELD__TIM16_BDTR_LOCK
// - SFDITEM_FIELD__TIM16_BDTR_OSSI
// - SFDITEM_FIELD__TIM16_BDTR_OSSR
// - SFDITEM_FIELD__TIM16_BDTR_BKE
// - SFDITEM_FIELD__TIM16_BDTR_BKP
// - SFDITEM_FIELD__TIM16_BDTR_AOE
// - SFDITEM_FIELD__TIM16_BDTR_MOE
//
//
// --------------------------- Register Item Address: TIM16_TISEL -------------------------------
// SVD Line: 9030
unsigned int TIM16_TISEL __AT (0x4001445C);
// ----------------------------- Field Item: TIM16_TISEL_TI1SEL ---------------------------------
// SVD Line: 9034
// - SFDITEM_FIELD__TIM16_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x4001445C) TI1SEL
//
// ( (unsigned char)((TIM16_TISEL >> 0) & 0xF), ((TIM16_TISEL = (TIM16_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM16_TISEL_TI2SEL ---------------------------------
// SVD Line: 9038
// - SFDITEM_FIELD__TIM16_TISEL_TI2SEL
// TI2SEL
//
// [Bits 11..8] RW (@ 0x4001445C) TI2SEL
//
// ( (unsigned char)((TIM16_TISEL >> 8) & 0xF), ((TIM16_TISEL = (TIM16_TISEL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM16_TISEL_TI3SEL ---------------------------------
// SVD Line: 9042
// - SFDITEM_FIELD__TIM16_TISEL_TI3SEL
// TI3SEL
//
// [Bits 19..16] RW (@ 0x4001445C) TI3SEL
//
// ( (unsigned char)((TIM16_TISEL >> 16) & 0xF), ((TIM16_TISEL = (TIM16_TISEL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM16_TISEL_TI4SEL ---------------------------------
// SVD Line: 9046
// - SFDITEM_FIELD__TIM16_TISEL_TI4SEL
// TI4SEL
//
// [Bits 27..24] RW (@ 0x4001445C) TI4SEL
//
// ( (unsigned char)((TIM16_TISEL >> 24) & 0xF), ((TIM16_TISEL = (TIM16_TISEL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM16_TISEL ----------------------------------
// SVD Line: 9030
// SFDITEM_REG__TIM16_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x4001445C) TISEL
// ( (unsigned int)((TIM16_TISEL >> 0) & 0xFFFFFFFF), ((TIM16_TISEL = (TIM16_TISEL & ~(0xF0F0F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F0F0F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_TISEL_TI1SEL
// - SFDITEM_FIELD__TIM16_TISEL_TI2SEL
// - SFDITEM_FIELD__TIM16_TISEL_TI3SEL
// - SFDITEM_FIELD__TIM16_TISEL_TI4SEL
//
//
// ---------------------------- Register Item Address: TIM16_AF1 --------------------------------
// SVD Line: 9052
unsigned int TIM16_AF1 __AT (0x40014460);
// ------------------------------- Field Item: TIM16_AF1_BKINE ----------------------------------
// SVD Line: 9056
// - SFDITEM_FIELD__TIM16_AF1_BKINE
// BKINE
//
// [Bit 0] RW (@ 0x40014460) BKINE
//
// ( (unsigned int) TIM16_AF1 )
// BKINE
//
//
//
// ------------------------------ Field Item: TIM16_AF1_BKCMP1E ---------------------------------
// SVD Line: 9060
// - SFDITEM_FIELD__TIM16_AF1_BKCMP1E
// BKCMP1E
//
// [Bit 1] RW (@ 0x40014460) BKCMP1E
//
// ( (unsigned int) TIM16_AF1 )
// BKCMP1E
//
//
//
// ------------------------------ Field Item: TIM16_AF1_BKCMP2E ---------------------------------
// SVD Line: 9064
// - SFDITEM_FIELD__TIM16_AF1_BKCMP2E
// BKCMP2E
//
// [Bit 2] RW (@ 0x40014460) BKCMP2E
//
// ( (unsigned int) TIM16_AF1 )
// BKCMP2E
//
//
//
// ------------------------------- Field Item: TIM16_AF1_BKINP ----------------------------------
// SVD Line: 9068
// - SFDITEM_FIELD__TIM16_AF1_BKINP
// BKINP
//
// [Bit 9] RW (@ 0x40014460) BKINP
//
// ( (unsigned int) TIM16_AF1 )
// BKINP
//
//
//
// ------------------------------ Field Item: TIM16_AF1_BKCMP1P ---------------------------------
// SVD Line: 9072
// - SFDITEM_FIELD__TIM16_AF1_BKCMP1P
// BKCMP1P
//
// [Bit 10] RW (@ 0x40014460) BKCMP1P
//
// ( (unsigned int) TIM16_AF1 )
// BKCMP1P
//
//
//
// ------------------------------ Field Item: TIM16_AF1_BKCMP2P ---------------------------------
// SVD Line: 9076
// - SFDITEM_FIELD__TIM16_AF1_BKCMP2P
// BKCMP2P
//
// [Bit 11] RW (@ 0x40014460) BKCMP2P
//
// ( (unsigned int) TIM16_AF1 )
// BKCMP2P
//
//
//
// -------------------------------- Register RTree: TIM16_AF1 -----------------------------------
// SVD Line: 9052
// SFDITEM_REG__TIM16_AF1
// AF1
//
// [Bits 31..0] RW (@ 0x40014460) AF1
// ( (unsigned int)((TIM16_AF1 >> 0) & 0xFFFFFFFF), ((TIM16_AF1 = (TIM16_AF1 & ~(0xE07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xE07) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_AF1_BKINE
// - SFDITEM_FIELD__TIM16_AF1_BKCMP1E
// - SFDITEM_FIELD__TIM16_AF1_BKCMP2E
// - SFDITEM_FIELD__TIM16_AF1_BKINP
// - SFDITEM_FIELD__TIM16_AF1_BKCMP1P
// - SFDITEM_FIELD__TIM16_AF1_BKCMP2P
//
//
// ---------------------------- Register Item Address: TIM16_DCR --------------------------------
// SVD Line: 9082
unsigned int TIM16_DCR __AT (0x400147DC);
// -------------------------------- Field Item: TIM16_DCR_DBA -----------------------------------
// SVD Line: 9087
// - SFDITEM_FIELD__TIM16_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x400147DC) DBA
//
// ( (unsigned char)((TIM16_DCR >> 0) & 0x1F), ((TIM16_DCR = (TIM16_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM16_DCR_DBL -----------------------------------
// SVD Line: 9091
// - SFDITEM_FIELD__TIM16_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x400147DC) DBL
//
// ( (unsigned char)((TIM16_DCR >> 8) & 0x1F), ((TIM16_DCR = (TIM16_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM16_DCR -----------------------------------
// SVD Line: 9082
// SFDITEM_REG__TIM16_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x400147DC) DMA control register
// ( (unsigned int)((TIM16_DCR >> 0) & 0xFFFFFFFF), ((TIM16_DCR = (TIM16_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DCR_DBA
// - SFDITEM_FIELD__TIM16_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM16_DMAR -------------------------------
// SVD Line: 9097
unsigned int TIM16_DMAR __AT (0x400147E0);
// ------------------------------- Field Item: TIM16_DMAR_DMAB ----------------------------------
// SVD Line: 9102
// - SFDITEM_FIELD__TIM16_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x400147E0) DMAB
//
// ( (unsigned int)((TIM16_DMAR >> 0) & 0xFFFFFFFF), ((TIM16_DMAR = (TIM16_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM16_DMAR -----------------------------------
// SVD Line: 9097
// SFDITEM_REG__TIM16_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x400147E0) DMA address for full transfer
// ( (unsigned int)((TIM16_DMAR >> 0) & 0xFFFFFFFF), ((TIM16_DMAR = (TIM16_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM16_DMAR_DMAB
//
//
// --------------------------------- Peripheral View: TIM16 -------------------------------------
// SVD Line: 8437
// TIM16
// TIM16
// - SFDITEM_REG__TIM16_CR1
// - SFDITEM_REG__TIM16_CR2
// - SFDITEM_REG__TIM16_DIER
// - SFDITEM_REG__TIM16_SR
// - SFDITEM_REG__TIM16_EGR
// - SFDITEM_REG__TIM16_CCMR1_OUTPUT
// - SFDITEM_REG__TIM16_CCMR1_INPUT
// - SFDITEM_REG__TIM16_CCER
// - SFDITEM_REG__TIM16_CNT
// - SFDITEM_REG__TIM16_PSC
// - SFDITEM_REG__TIM16_ARR
// - SFDITEM_REG__TIM16_RCR
// - SFDITEM_REG__TIM16_CCR1
// - SFDITEM_REG__TIM16_BDTR
// - SFDITEM_REG__TIM16_TISEL
// - SFDITEM_REG__TIM16_AF1
// - SFDITEM_REG__TIM16_DCR
// - SFDITEM_REG__TIM16_DMAR
//
//
// ---------------------------- Register Item Address: TIM17_CR1 --------------------------------
// SVD Line: 8453
unsigned int TIM17_CR1 __AT (0x40014800);
// -------------------------------- Field Item: TIM17_CR1_CEN -----------------------------------
// SVD Line: 8458
// - SFDITEM_FIELD__TIM17_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40014800) CEN
//
// ( (unsigned int) TIM17_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM17_CR1_UDIS -----------------------------------
// SVD Line: 8462
// - SFDITEM_FIELD__TIM17_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40014800) UDIS
//
// ( (unsigned int) TIM17_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM17_CR1_URS -----------------------------------
// SVD Line: 8466
// - SFDITEM_FIELD__TIM17_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40014800) URS
//
// ( (unsigned int) TIM17_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM17_CR1_OPM -----------------------------------
// SVD Line: 8470
// - SFDITEM_FIELD__TIM17_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40014800) OPM
//
// ( (unsigned int) TIM17_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM17_CR1_DIR -----------------------------------
// SVD Line: 8474
// - SFDITEM_FIELD__TIM17_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40014800) DIR
//
// ( (unsigned int) TIM17_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM17_CR1_CMS -----------------------------------
// SVD Line: 8478
// - SFDITEM_FIELD__TIM17_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40014800) CMS
//
// ( (unsigned char)((TIM17_CR1 >> 5) & 0x3), ((TIM17_CR1 = (TIM17_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_CR1_ARPE -----------------------------------
// SVD Line: 8482
// - SFDITEM_FIELD__TIM17_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40014800) ARPE
//
// ( (unsigned int) TIM17_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM17_CR1_CKD -----------------------------------
// SVD Line: 8486
// - SFDITEM_FIELD__TIM17_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40014800) CKD
//
// ( (unsigned char)((TIM17_CR1 >> 8) & 0x3), ((TIM17_CR1 = (TIM17_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_CR1 -----------------------------------
// SVD Line: 8453
// SFDITEM_REG__TIM17_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40014800) TIM16 control register1
// ( (unsigned int)((TIM17_CR1 >> 0) & 0xFFFFFFFF), ((TIM17_CR1 = (TIM17_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CR1_CEN
// - SFDITEM_FIELD__TIM17_CR1_UDIS
// - SFDITEM_FIELD__TIM17_CR1_URS
// - SFDITEM_FIELD__TIM17_CR1_OPM
// - SFDITEM_FIELD__TIM17_CR1_DIR
// - SFDITEM_FIELD__TIM17_CR1_CMS
// - SFDITEM_FIELD__TIM17_CR1_ARPE
// - SFDITEM_FIELD__TIM17_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM17_CR2 --------------------------------
// SVD Line: 8492
unsigned int TIM17_CR2 __AT (0x40014804);
// ------------------------------- Field Item: TIM17_CR2_CCPC -----------------------------------
// SVD Line: 8497
// - SFDITEM_FIELD__TIM17_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40014804) CCPC
//
// ( (unsigned int) TIM17_CR2 )
// CCPC
//
//
//
// ------------------------------- Field Item: TIM17_CR2_CCUS -----------------------------------
// SVD Line: 8501
// - SFDITEM_FIELD__TIM17_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40014804) CCUS
//
// ( (unsigned int) TIM17_CR2 )
// CCUS
//
//
//
// ------------------------------- Field Item: TIM17_CR2_CCDS -----------------------------------
// SVD Line: 8505
// - SFDITEM_FIELD__TIM17_CR2_CCDS
// CCDS
//
// [Bit 3] RW (@ 0x40014804) CCDS
//
// ( (unsigned int) TIM17_CR2 )
// CCDS
//
//
//
// ------------------------------- Field Item: TIM17_CR2_MMS_L ----------------------------------
// SVD Line: 8509
// - SFDITEM_FIELD__TIM17_CR2_MMS_L
// MMS_L
//
// [Bits 6..4] RW (@ 0x40014804) MMS_L
//
// ( (unsigned char)((TIM17_CR2 >> 4) & 0x7), ((TIM17_CR2 = (TIM17_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_CR2_TI1S -----------------------------------
// SVD Line: 8513
// - SFDITEM_FIELD__TIM17_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40014804) TI1S
//
// ( (unsigned int) TIM17_CR2 )
// TI1S
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS1 -----------------------------------
// SVD Line: 8517
// - SFDITEM_FIELD__TIM17_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40014804) OIS1
//
// ( (unsigned int) TIM17_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS1N ----------------------------------
// SVD Line: 8521
// - SFDITEM_FIELD__TIM17_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40014804) OIS1N
//
// ( (unsigned int) TIM17_CR2 )
// OIS1N
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS2 -----------------------------------
// SVD Line: 8525
// - SFDITEM_FIELD__TIM17_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40014804) OIS2
//
// ( (unsigned int) TIM17_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS2N ----------------------------------
// SVD Line: 8529
// - SFDITEM_FIELD__TIM17_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40014804) OIS2N
//
// ( (unsigned int) TIM17_CR2 )
// OIS2N
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS3 -----------------------------------
// SVD Line: 8533
// - SFDITEM_FIELD__TIM17_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40014804) OIS3
//
// ( (unsigned int) TIM17_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS3N ----------------------------------
// SVD Line: 8537
// - SFDITEM_FIELD__TIM17_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40014804) OIS3N
//
// ( (unsigned int) TIM17_CR2 )
// OIS3N
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS4 -----------------------------------
// SVD Line: 8541
// - SFDITEM_FIELD__TIM17_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40014804) OIS4
//
// ( (unsigned int) TIM17_CR2 )
// OIS4
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS5 -----------------------------------
// SVD Line: 8545
// - SFDITEM_FIELD__TIM17_CR2_OIS5
// OIS5
//
// [Bit 16] RW (@ 0x40014804) OIS5
//
// ( (unsigned int) TIM17_CR2 )
// OIS5
//
//
//
// ------------------------------- Field Item: TIM17_CR2_OIS6 -----------------------------------
// SVD Line: 8549
// - SFDITEM_FIELD__TIM17_CR2_OIS6
// OIS6
//
// [Bit 18] RW (@ 0x40014804) OIS6
//
// ( (unsigned int) TIM17_CR2 )
// OIS6
//
//
//
// ------------------------------- Field Item: TIM17_CR2_MMS_H ----------------------------------
// SVD Line: 8553
// - SFDITEM_FIELD__TIM17_CR2_MMS_H
// MMS_H
//
// [Bit 25] RW (@ 0x40014804) MMS_H
//
// ( (unsigned int) TIM17_CR2 )
// MMS_H
//
//
//
// -------------------------------- Register RTree: TIM17_CR2 -----------------------------------
// SVD Line: 8492
// SFDITEM_REG__TIM17_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40014804) control register 2
// ( (unsigned int)((TIM17_CR2 >> 0) & 0xFFFFFFFF), ((TIM17_CR2 = (TIM17_CR2 & ~(0x2057FFDUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2057FFD) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CR2_CCPC
// - SFDITEM_FIELD__TIM17_CR2_CCUS
// - SFDITEM_FIELD__TIM17_CR2_CCDS
// - SFDITEM_FIELD__TIM17_CR2_MMS_L
// - SFDITEM_FIELD__TIM17_CR2_TI1S
// - SFDITEM_FIELD__TIM17_CR2_OIS1
// - SFDITEM_FIELD__TIM17_CR2_OIS1N
// - SFDITEM_FIELD__TIM17_CR2_OIS2
// - SFDITEM_FIELD__TIM17_CR2_OIS2N
// - SFDITEM_FIELD__TIM17_CR2_OIS3
// - SFDITEM_FIELD__TIM17_CR2_OIS3N
// - SFDITEM_FIELD__TIM17_CR2_OIS4
// - SFDITEM_FIELD__TIM17_CR2_OIS5
// - SFDITEM_FIELD__TIM17_CR2_OIS6
// - SFDITEM_FIELD__TIM17_CR2_MMS_H
//
//
// ---------------------------- Register Item Address: TIM17_DIER -------------------------------
// SVD Line: 8559
unsigned int TIM17_DIER __AT (0x4001480C);
// ------------------------------- Field Item: TIM17_DIER_UIE -----------------------------------
// SVD Line: 8564
// - SFDITEM_FIELD__TIM17_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4001480C) UIE
//
// ( (unsigned int) TIM17_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC1IE ----------------------------------
// SVD Line: 8568
// - SFDITEM_FIELD__TIM17_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4001480C) CC1IE
//
// ( (unsigned int) TIM17_DIER )
// CC1IE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC2IE ----------------------------------
// SVD Line: 8572
// - SFDITEM_FIELD__TIM17_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x4001480C) CC2IE
//
// ( (unsigned int) TIM17_DIER )
// CC2IE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC3IE ----------------------------------
// SVD Line: 8576
// - SFDITEM_FIELD__TIM17_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x4001480C) CC3IE
//
// ( (unsigned int) TIM17_DIER )
// CC3IE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC4IE ----------------------------------
// SVD Line: 8580
// - SFDITEM_FIELD__TIM17_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x4001480C) CC4IE
//
// ( (unsigned int) TIM17_DIER )
// CC4IE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_COMIE ----------------------------------
// SVD Line: 8584
// - SFDITEM_FIELD__TIM17_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x4001480C) COMIE
//
// ( (unsigned int) TIM17_DIER )
// COMIE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_TIE -----------------------------------
// SVD Line: 8588
// - SFDITEM_FIELD__TIM17_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x4001480C) TIE
//
// ( (unsigned int) TIM17_DIER )
// TIE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_BIE -----------------------------------
// SVD Line: 8592
// - SFDITEM_FIELD__TIM17_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x4001480C) BIE
//
// ( (unsigned int) TIM17_DIER )
// BIE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_UDE -----------------------------------
// SVD Line: 8596
// - SFDITEM_FIELD__TIM17_DIER_UDE
// UDE
//
// [Bit 8] RW (@ 0x4001480C) UDE
//
// ( (unsigned int) TIM17_DIER )
// UDE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC1DE ----------------------------------
// SVD Line: 8600
// - SFDITEM_FIELD__TIM17_DIER_CC1DE
// CC1DE
//
// [Bit 9] RW (@ 0x4001480C) CC1DE
//
// ( (unsigned int) TIM17_DIER )
// CC1DE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC2DE ----------------------------------
// SVD Line: 8604
// - SFDITEM_FIELD__TIM17_DIER_CC2DE
// CC2DE
//
// [Bit 10] RW (@ 0x4001480C) CC2DE
//
// ( (unsigned int) TIM17_DIER )
// CC2DE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC3DE ----------------------------------
// SVD Line: 8608
// - SFDITEM_FIELD__TIM17_DIER_CC3DE
// CC3DE
//
// [Bit 11] RW (@ 0x4001480C) CC3DE
//
// ( (unsigned int) TIM17_DIER )
// CC3DE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_CC4DE ----------------------------------
// SVD Line: 8612
// - SFDITEM_FIELD__TIM17_DIER_CC4DE
// CC4DE
//
// [Bit 12] RW (@ 0x4001480C) CC4DE
//
// ( (unsigned int) TIM17_DIER )
// CC4DE
//
//
//
// ------------------------------ Field Item: TIM17_DIER_COMDE ----------------------------------
// SVD Line: 8616
// - SFDITEM_FIELD__TIM17_DIER_COMDE
// COMDE
//
// [Bit 13] RW (@ 0x4001480C) COMDE
//
// ( (unsigned int) TIM17_DIER )
// COMDE
//
//
//
// ------------------------------- Field Item: TIM17_DIER_TDE -----------------------------------
// SVD Line: 8620
// - SFDITEM_FIELD__TIM17_DIER_TDE
// TDE
//
// [Bit 14] RW (@ 0x4001480C) TDE
//
// ( (unsigned int) TIM17_DIER )
// TDE
//
//
//
// ------------------------------- Register RTree: TIM17_DIER -----------------------------------
// SVD Line: 8559
// SFDITEM_REG__TIM17_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4001480C) DMA/Interrupt enable register
// ( (unsigned int)((TIM17_DIER >> 0) & 0xFFFFFFFF), ((TIM17_DIER = (TIM17_DIER & ~(0x7FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DIER_UIE
// - SFDITEM_FIELD__TIM17_DIER_CC1IE
// - SFDITEM_FIELD__TIM17_DIER_CC2IE
// - SFDITEM_FIELD__TIM17_DIER_CC3IE
// - SFDITEM_FIELD__TIM17_DIER_CC4IE
// - SFDITEM_FIELD__TIM17_DIER_COMIE
// - SFDITEM_FIELD__TIM17_DIER_TIE
// - SFDITEM_FIELD__TIM17_DIER_BIE
// - SFDITEM_FIELD__TIM17_DIER_UDE
// - SFDITEM_FIELD__TIM17_DIER_CC1DE
// - SFDITEM_FIELD__TIM17_DIER_CC2DE
// - SFDITEM_FIELD__TIM17_DIER_CC3DE
// - SFDITEM_FIELD__TIM17_DIER_CC4DE
// - SFDITEM_FIELD__TIM17_DIER_COMDE
// - SFDITEM_FIELD__TIM17_DIER_TDE
//
//
// ----------------------------- Register Item Address: TIM17_SR --------------------------------
// SVD Line: 8626
unsigned int TIM17_SR __AT (0x40014810);
// -------------------------------- Field Item: TIM17_SR_UIF ------------------------------------
// SVD Line: 8631
// - SFDITEM_FIELD__TIM17_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40014810) UIF
//
// ( (unsigned int) TIM17_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC1IF -----------------------------------
// SVD Line: 8635
// - SFDITEM_FIELD__TIM17_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40014810) CC1IF
//
// ( (unsigned int) TIM17_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC2IF -----------------------------------
// SVD Line: 8639
// - SFDITEM_FIELD__TIM17_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40014810) CC2IF
//
// ( (unsigned int) TIM17_SR )
// CC2IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC3IF -----------------------------------
// SVD Line: 8643
// - SFDITEM_FIELD__TIM17_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40014810) CC3IF
//
// ( (unsigned int) TIM17_SR )
// CC3IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC4IF -----------------------------------
// SVD Line: 8647
// - SFDITEM_FIELD__TIM17_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40014810) CC4IF
//
// ( (unsigned int) TIM17_SR )
// CC4IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_COMIF -----------------------------------
// SVD Line: 8651
// - SFDITEM_FIELD__TIM17_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40014810) COMIF
//
// ( (unsigned int) TIM17_SR )
// COMIF
//
//
//
// -------------------------------- Field Item: TIM17_SR_TIF ------------------------------------
// SVD Line: 8655
// - SFDITEM_FIELD__TIM17_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40014810) TIF
//
// ( (unsigned int) TIM17_SR )
// TIF
//
//
//
// -------------------------------- Field Item: TIM17_SR_BIF ------------------------------------
// SVD Line: 8659
// - SFDITEM_FIELD__TIM17_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40014810) BIF
//
// ( (unsigned int) TIM17_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM17_SR_B2IF -----------------------------------
// SVD Line: 8663
// - SFDITEM_FIELD__TIM17_SR_B2IF
// B2IF
//
// [Bit 8] RW (@ 0x40014810) B2IF
//
// ( (unsigned int) TIM17_SR )
// B2IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC1OF -----------------------------------
// SVD Line: 8667
// - SFDITEM_FIELD__TIM17_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40014810) CC1OF
//
// ( (unsigned int) TIM17_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC2OF -----------------------------------
// SVD Line: 8671
// - SFDITEM_FIELD__TIM17_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40014810) CC2OF
//
// ( (unsigned int) TIM17_SR )
// CC2OF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC3OF -----------------------------------
// SVD Line: 8675
// - SFDITEM_FIELD__TIM17_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40014810) CC3OF
//
// ( (unsigned int) TIM17_SR )
// CC3OF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC4OF -----------------------------------
// SVD Line: 8679
// - SFDITEM_FIELD__TIM17_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40014810) CC4OF
//
// ( (unsigned int) TIM17_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM17_SR_SBIF -----------------------------------
// SVD Line: 8683
// - SFDITEM_FIELD__TIM17_SR_SBIF
// SBIF
//
// [Bit 13] RW (@ 0x40014810) SBIF
//
// ( (unsigned int) TIM17_SR )
// SBIF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC5IF -----------------------------------
// SVD Line: 8687
// - SFDITEM_FIELD__TIM17_SR_CC5IF
// CC5IF
//
// [Bit 16] RW (@ 0x40014810) CC5IF
//
// ( (unsigned int) TIM17_SR )
// CC5IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_CC6IF -----------------------------------
// SVD Line: 8691
// - SFDITEM_FIELD__TIM17_SR_CC6IF
// CC6IF
//
// [Bit 17] RW (@ 0x40014810) CC6IF
//
// ( (unsigned int) TIM17_SR )
// CC6IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC1IR -----------------------------------
// SVD Line: 8695
// - SFDITEM_FIELD__TIM17_SR_IC1IR
// IC1IR
//
// [Bit 18] RW (@ 0x40014810) IC1IR
//
// ( (unsigned int) TIM17_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC2IR -----------------------------------
// SVD Line: 8699
// - SFDITEM_FIELD__TIM17_SR_IC2IR
// IC2IR
//
// [Bit 19] RW (@ 0x40014810) IC2IR
//
// ( (unsigned int) TIM17_SR )
// IC2IR
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC3IR -----------------------------------
// SVD Line: 8703
// - SFDITEM_FIELD__TIM17_SR_IC3IR
// IC3IR
//
// [Bit 24] RW (@ 0x40014810) IC3IR
//
// ( (unsigned int) TIM17_SR )
// IC3IR
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC4IR -----------------------------------
// SVD Line: 8707
// - SFDITEM_FIELD__TIM17_SR_IC4IR
// IC4IR
//
// [Bit 25] RW (@ 0x40014810) IC4IR
//
// ( (unsigned int) TIM17_SR )
// IC4IR
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC1IF -----------------------------------
// SVD Line: 8711
// - SFDITEM_FIELD__TIM17_SR_IC1IF
// IC1IF
//
// [Bit 26] RW (@ 0x40014810) IC1IF
//
// ( (unsigned int) TIM17_SR )
// IC1IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC2IF -----------------------------------
// SVD Line: 8715
// - SFDITEM_FIELD__TIM17_SR_IC2IF
// IC2IF
//
// [Bit 27] RW (@ 0x40014810) IC2IF
//
// ( (unsigned int) TIM17_SR )
// IC2IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC3IF -----------------------------------
// SVD Line: 8719
// - SFDITEM_FIELD__TIM17_SR_IC3IF
// IC3IF
//
// [Bit 28] RW (@ 0x40014810) IC3IF
//
// ( (unsigned int) TIM17_SR )
// IC3IF
//
//
//
// ------------------------------- Field Item: TIM17_SR_IC4IF -----------------------------------
// SVD Line: 8723
// - SFDITEM_FIELD__TIM17_SR_IC4IF
// IC4IF
//
// [Bit 29] RW (@ 0x40014810) IC4IF
//
// ( (unsigned int) TIM17_SR )
// IC4IF
//
//
//
// -------------------------------- Register RTree: TIM17_SR ------------------------------------
// SVD Line: 8626
// SFDITEM_REG__TIM17_SR
// SR
//
// [Bits 31..0] RW (@ 0x40014810) status register
// ( (unsigned int)((TIM17_SR >> 0) & 0xFFFFFFFF), ((TIM17_SR = (TIM17_SR & ~(0x3F0F3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F0F3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_SR_UIF
// - SFDITEM_FIELD__TIM17_SR_CC1IF
// - SFDITEM_FIELD__TIM17_SR_CC2IF
// - SFDITEM_FIELD__TIM17_SR_CC3IF
// - SFDITEM_FIELD__TIM17_SR_CC4IF
// - SFDITEM_FIELD__TIM17_SR_COMIF
// - SFDITEM_FIELD__TIM17_SR_TIF
// - SFDITEM_FIELD__TIM17_SR_BIF
// - SFDITEM_FIELD__TIM17_SR_B2IF
// - SFDITEM_FIELD__TIM17_SR_CC1OF
// - SFDITEM_FIELD__TIM17_SR_CC2OF
// - SFDITEM_FIELD__TIM17_SR_CC3OF
// - SFDITEM_FIELD__TIM17_SR_CC4OF
// - SFDITEM_FIELD__TIM17_SR_SBIF
// - SFDITEM_FIELD__TIM17_SR_CC5IF
// - SFDITEM_FIELD__TIM17_SR_CC6IF
// - SFDITEM_FIELD__TIM17_SR_IC1IR
// - SFDITEM_FIELD__TIM17_SR_IC2IR
// - SFDITEM_FIELD__TIM17_SR_IC3IR
// - SFDITEM_FIELD__TIM17_SR_IC4IR
// - SFDITEM_FIELD__TIM17_SR_IC1IF
// - SFDITEM_FIELD__TIM17_SR_IC2IF
// - SFDITEM_FIELD__TIM17_SR_IC3IF
// - SFDITEM_FIELD__TIM17_SR_IC4IF
//
//
// ---------------------------- Register Item Address: TIM17_EGR --------------------------------
// SVD Line: 8729
unsigned int TIM17_EGR __AT (0x40014814);
// -------------------------------- Field Item: TIM17_EGR_UG ------------------------------------
// SVD Line: 8734
// - SFDITEM_FIELD__TIM17_EGR_UG
// UG
//
// [Bit 0] RW (@ 0x40014814) UG
//
// ( (unsigned int) TIM17_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM17_EGR_CC1G -----------------------------------
// SVD Line: 8738
// - SFDITEM_FIELD__TIM17_EGR_CC1G
// CC1G
//
// [Bit 1] RW (@ 0x40014814) CC1G
//
// ( (unsigned int) TIM17_EGR )
// CC1G
//
//
//
// ------------------------------- Field Item: TIM17_EGR_CC2G -----------------------------------
// SVD Line: 8742
// - SFDITEM_FIELD__TIM17_EGR_CC2G
// CC2G
//
// [Bit 2] RW (@ 0x40014814) CC2G
//
// ( (unsigned int) TIM17_EGR )
// CC2G
//
//
//
// ------------------------------- Field Item: TIM17_EGR_CC3G -----------------------------------
// SVD Line: 8746
// - SFDITEM_FIELD__TIM17_EGR_CC3G
// CC3G
//
// [Bit 3] RW (@ 0x40014814) CC3G
//
// ( (unsigned int) TIM17_EGR )
// CC3G
//
//
//
// ------------------------------- Field Item: TIM17_EGR_CC4G -----------------------------------
// SVD Line: 8750
// - SFDITEM_FIELD__TIM17_EGR_CC4G
// CC4G
//
// [Bit 4] RW (@ 0x40014814) CC4G
//
// ( (unsigned int) TIM17_EGR )
// CC4G
//
//
//
// ------------------------------- Field Item: TIM17_EGR_COMG -----------------------------------
// SVD Line: 8754
// - SFDITEM_FIELD__TIM17_EGR_COMG
// COMG
//
// [Bit 5] RW (@ 0x40014814) COMG
//
// ( (unsigned int) TIM17_EGR )
// COMG
//
//
//
// -------------------------------- Field Item: TIM17_EGR_TG ------------------------------------
// SVD Line: 8758
// - SFDITEM_FIELD__TIM17_EGR_TG
// TG
//
// [Bit 6] RW (@ 0x40014814) TG
//
// ( (unsigned int) TIM17_EGR )
// TG
//
//
//
// -------------------------------- Field Item: TIM17_EGR_BG ------------------------------------
// SVD Line: 8762
// - SFDITEM_FIELD__TIM17_EGR_BG
// BG
//
// [Bit 7] RW (@ 0x40014814) BG
//
// ( (unsigned int) TIM17_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM17_EGR -----------------------------------
// SVD Line: 8729
// SFDITEM_REG__TIM17_EGR
// EGR
//
// [Bits 31..0] RW (@ 0x40014814) event generation register
// ( (unsigned int)((TIM17_EGR >> 0) & 0xFFFFFFFF), ((TIM17_EGR = (TIM17_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_EGR_UG
// - SFDITEM_FIELD__TIM17_EGR_CC1G
// - SFDITEM_FIELD__TIM17_EGR_CC2G
// - SFDITEM_FIELD__TIM17_EGR_CC3G
// - SFDITEM_FIELD__TIM17_EGR_CC4G
// - SFDITEM_FIELD__TIM17_EGR_COMG
// - SFDITEM_FIELD__TIM17_EGR_TG
// - SFDITEM_FIELD__TIM17_EGR_BG
//
//
// ------------------------ Register Item Address: TIM17_CCMR1_OUTPUT ---------------------------
// SVD Line: 8768
unsigned int TIM17_CCMR1_OUTPUT __AT (0x40014818);
// --------------------------- Field Item: TIM17_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 8772
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014818) CC1S
//
// ( (unsigned char)((TIM17_CCMR1_OUTPUT >> 0) & 0x3), ((TIM17_CCMR1_OUTPUT = (TIM17_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 8776
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40014818) OC1FE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC1FE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 8780
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40014818) OC1PE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC1PE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC1M_L -----------------------------
// SVD Line: 8784
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1M_L
// OC1M_L
//
// [Bits 6..4] RW (@ 0x40014818) OC1M_L
//
// ( (unsigned char)((TIM17_CCMR1_OUTPUT >> 4) & 0x7), ((TIM17_CCMR1_OUTPUT = (TIM17_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 8788
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40014818) OC1CE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_OUTPUT_CC2S ------------------------------
// SVD Line: 8792
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40014818) CC2S
//
// ( (unsigned char)((TIM17_CCMR1_OUTPUT >> 8) & 0x3), ((TIM17_CCMR1_OUTPUT = (TIM17_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 8796
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40014818) OC2FE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC2FE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 8800
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40014818) OC2PE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC2PE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC2M_L -----------------------------
// SVD Line: 8804
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2M_L
// OC2M_L
//
// [Bits 14..12] RW (@ 0x40014818) OC2M_L
//
// ( (unsigned char)((TIM17_CCMR1_OUTPUT >> 12) & 0x7), ((TIM17_CCMR1_OUTPUT = (TIM17_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 8808
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40014818) OC2CE
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC2CE
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC1M_H -----------------------------
// SVD Line: 8812
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1M_H
// OC1M_H
//
// [Bit 16] RW (@ 0x40014818) OC1M_H
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC1M_H
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_OUTPUT_OC2M_H -----------------------------
// SVD Line: 8816
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2M_H
// OC2M_H
//
// [Bit 24] RW (@ 0x40014818) OC2M_H
//
// ( (unsigned int) TIM17_CCMR1_OUTPUT )
// OC2M_H
//
//
//
// --------------------------- Register RTree: TIM17_CCMR1_OUTPUT -------------------------------
// SVD Line: 8768
// SFDITEM_REG__TIM17_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40014818) CCMR1_OUTPUT
// ( (unsigned int)((TIM17_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM17_CCMR1_OUTPUT = (TIM17_CCMR1_OUTPUT & ~(0x101FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1M_L
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2M_L
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2CE
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC1M_H
// - SFDITEM_FIELD__TIM17_CCMR1_OUTPUT_OC2M_H
//
//
// ------------------------ Register Item Address: TIM17_CCMR1_INPUT ----------------------------
// SVD Line: 8822
unsigned int TIM17_CCMR1_INPUT __AT (0x40014818);
// --------------------------- Field Item: TIM17_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 8827
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40014818) CC1S
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 0) & 0x3), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 8831
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40014818) IC1PSC
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 2) & 0x3), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 8835
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40014818) IC1F
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 4) & 0xF), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 8839
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40014818) CC2S
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 8) & 0x3), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------- Field Item: TIM17_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 8843
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40014818) IC2PSC
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 10) & 0x3), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// --------------------------- Field Item: TIM17_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 8847
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40014818) IC2F
//
// ( (unsigned char)((TIM17_CCMR1_INPUT >> 12) & 0xF), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM17_CCMR1_INPUT -------------------------------
// SVD Line: 8822
// SFDITEM_REG__TIM17_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40014818) CCMR1_INPUT
// ( (unsigned int)((TIM17_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM17_CCMR1_INPUT = (TIM17_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM17_CCMR1_INPUT_IC2F
//
//
// ---------------------------- Register Item Address: TIM17_CCER -------------------------------
// SVD Line: 8853
unsigned int TIM17_CCER __AT (0x40014820);
// ------------------------------- Field Item: TIM17_CCER_CC1E ----------------------------------
// SVD Line: 8858
// - SFDITEM_FIELD__TIM17_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40014820) CC1E
//
// ( (unsigned int) TIM17_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC1P ----------------------------------
// SVD Line: 8862
// - SFDITEM_FIELD__TIM17_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40014820) CC1P
//
// ( (unsigned int) TIM17_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC1NE ----------------------------------
// SVD Line: 8866
// - SFDITEM_FIELD__TIM17_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40014820) CC1NE
//
// ( (unsigned int) TIM17_CCER )
// CC1NE
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC1NP ----------------------------------
// SVD Line: 8870
// - SFDITEM_FIELD__TIM17_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40014820) CC1NP
//
// ( (unsigned int) TIM17_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC2E ----------------------------------
// SVD Line: 8874
// - SFDITEM_FIELD__TIM17_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40014820) CC2E
//
// ( (unsigned int) TIM17_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC2P ----------------------------------
// SVD Line: 8878
// - SFDITEM_FIELD__TIM17_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40014820) CC2P
//
// ( (unsigned int) TIM17_CCER )
// CC2P
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC2NE ----------------------------------
// SVD Line: 8882
// - SFDITEM_FIELD__TIM17_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40014820) CC2NE
//
// ( (unsigned int) TIM17_CCER )
// CC2NE
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC2NP ----------------------------------
// SVD Line: 8886
// - SFDITEM_FIELD__TIM17_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40014820) CC2NP
//
// ( (unsigned int) TIM17_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC3E ----------------------------------
// SVD Line: 8890
// - SFDITEM_FIELD__TIM17_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40014820) CC3E
//
// ( (unsigned int) TIM17_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC3P ----------------------------------
// SVD Line: 8894
// - SFDITEM_FIELD__TIM17_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40014820) CC3P
//
// ( (unsigned int) TIM17_CCER )
// CC3P
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC3NE ----------------------------------
// SVD Line: 8898
// - SFDITEM_FIELD__TIM17_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40014820) CC3NE
//
// ( (unsigned int) TIM17_CCER )
// CC3NE
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC3NP ----------------------------------
// SVD Line: 8902
// - SFDITEM_FIELD__TIM17_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40014820) CC3NP
//
// ( (unsigned int) TIM17_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC4E ----------------------------------
// SVD Line: 8906
// - SFDITEM_FIELD__TIM17_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40014820) CC4E
//
// ( (unsigned int) TIM17_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC4P ----------------------------------
// SVD Line: 8910
// - SFDITEM_FIELD__TIM17_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40014820) CC4P
//
// ( (unsigned int) TIM17_CCER )
// CC4P
//
//
//
// ------------------------------ Field Item: TIM17_CCER_CC4NP ----------------------------------
// SVD Line: 8914
// - SFDITEM_FIELD__TIM17_CCER_CC4NP
// CC4NP
//
// [Bit 15] RW (@ 0x40014820) CC4NP
//
// ( (unsigned int) TIM17_CCER )
// CC4NP
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC5E ----------------------------------
// SVD Line: 8918
// - SFDITEM_FIELD__TIM17_CCER_CC5E
// CC5E
//
// [Bit 16] RW (@ 0x40014820) CC5E
//
// ( (unsigned int) TIM17_CCER )
// CC5E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC5P ----------------------------------
// SVD Line: 8922
// - SFDITEM_FIELD__TIM17_CCER_CC5P
// CC5P
//
// [Bit 17] RW (@ 0x40014820) CC5P
//
// ( (unsigned int) TIM17_CCER )
// CC5P
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC6E ----------------------------------
// SVD Line: 8926
// - SFDITEM_FIELD__TIM17_CCER_CC6E
// CC6E
//
// [Bit 20] RW (@ 0x40014820) CC6E
//
// ( (unsigned int) TIM17_CCER )
// CC6E
//
//
//
// ------------------------------- Field Item: TIM17_CCER_CC6P ----------------------------------
// SVD Line: 8930
// - SFDITEM_FIELD__TIM17_CCER_CC6P
// CC6P
//
// [Bit 21] RW (@ 0x40014820) CC6P
//
// ( (unsigned int) TIM17_CCER )
// CC6P
//
//
//
// ------------------------------- Register RTree: TIM17_CCER -----------------------------------
// SVD Line: 8853
// SFDITEM_REG__TIM17_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40014820) capture/compare enableregister
// ( (unsigned int)((TIM17_CCER >> 0) & 0xFFFFFFFF), ((TIM17_CCER = (TIM17_CCER & ~(0x33BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x33BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCER_CC1E
// - SFDITEM_FIELD__TIM17_CCER_CC1P
// - SFDITEM_FIELD__TIM17_CCER_CC1NE
// - SFDITEM_FIELD__TIM17_CCER_CC1NP
// - SFDITEM_FIELD__TIM17_CCER_CC2E
// - SFDITEM_FIELD__TIM17_CCER_CC2P
// - SFDITEM_FIELD__TIM17_CCER_CC2NE
// - SFDITEM_FIELD__TIM17_CCER_CC2NP
// - SFDITEM_FIELD__TIM17_CCER_CC3E
// - SFDITEM_FIELD__TIM17_CCER_CC3P
// - SFDITEM_FIELD__TIM17_CCER_CC3NE
// - SFDITEM_FIELD__TIM17_CCER_CC3NP
// - SFDITEM_FIELD__TIM17_CCER_CC4E
// - SFDITEM_FIELD__TIM17_CCER_CC4P
// - SFDITEM_FIELD__TIM17_CCER_CC4NP
// - SFDITEM_FIELD__TIM17_CCER_CC5E
// - SFDITEM_FIELD__TIM17_CCER_CC5P
// - SFDITEM_FIELD__TIM17_CCER_CC6E
// - SFDITEM_FIELD__TIM17_CCER_CC6P
//
//
// ---------------------------- Register Item Address: TIM17_CNT --------------------------------
// SVD Line: 8936
unsigned int TIM17_CNT __AT (0x40014824);
// -------------------------------- Field Item: TIM17_CNT_CNT -----------------------------------
// SVD Line: 8941
// - SFDITEM_FIELD__TIM17_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40014824) CNT
//
// ( (unsigned short)((TIM17_CNT >> 0) & 0xFFFF), ((TIM17_CNT = (TIM17_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_CNT -----------------------------------
// SVD Line: 8936
// SFDITEM_REG__TIM17_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40014824) counter
// ( (unsigned int)((TIM17_CNT >> 0) & 0xFFFFFFFF), ((TIM17_CNT = (TIM17_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM17_PSC --------------------------------
// SVD Line: 8947
unsigned int TIM17_PSC __AT (0x40014828);
// -------------------------------- Field Item: TIM17_PSC_PSC -----------------------------------
// SVD Line: 8952
// - SFDITEM_FIELD__TIM17_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40014828) PSC
//
// ( (unsigned short)((TIM17_PSC >> 0) & 0xFFFF), ((TIM17_PSC = (TIM17_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_PSC -----------------------------------
// SVD Line: 8947
// SFDITEM_REG__TIM17_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40014828) prescaler
// ( (unsigned int)((TIM17_PSC >> 0) & 0xFFFFFFFF), ((TIM17_PSC = (TIM17_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM17_ARR --------------------------------
// SVD Line: 8958
unsigned int TIM17_ARR __AT (0x4001482C);
// -------------------------------- Field Item: TIM17_ARR_ARR -----------------------------------
// SVD Line: 8963
// - SFDITEM_FIELD__TIM17_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4001482C) ARR
//
// ( (unsigned short)((TIM17_ARR >> 0) & 0xFFFF), ((TIM17_ARR = (TIM17_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_ARR -----------------------------------
// SVD Line: 8958
// SFDITEM_REG__TIM17_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4001482C) auto-reload register
// ( (unsigned int)((TIM17_ARR >> 0) & 0xFFFFFFFF), ((TIM17_ARR = (TIM17_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM17_RCR --------------------------------
// SVD Line: 8969
unsigned int TIM17_RCR __AT (0x40014830);
// -------------------------------- Field Item: TIM17_RCR_REP -----------------------------------
// SVD Line: 8974
// - SFDITEM_FIELD__TIM17_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40014830) REP
//
// ( (unsigned char)((TIM17_RCR >> 0) & 0xFF), ((TIM17_RCR = (TIM17_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_RCR -----------------------------------
// SVD Line: 8969
// SFDITEM_REG__TIM17_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40014830) repetition counter register
// ( (unsigned int)((TIM17_RCR >> 0) & 0xFFFFFFFF), ((TIM17_RCR = (TIM17_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM17_CCR1 -------------------------------
// SVD Line: 8980
unsigned int TIM17_CCR1 __AT (0x40014834);
// ------------------------------- Field Item: TIM17_CCR1_CCR1 ----------------------------------
// SVD Line: 8985
// - SFDITEM_FIELD__TIM17_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40014834) CCR1
//
// ( (unsigned short)((TIM17_CCR1 >> 0) & 0xFFFF), ((TIM17_CCR1 = (TIM17_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM17_CCR1 -----------------------------------
// SVD Line: 8980
// SFDITEM_REG__TIM17_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40014834) capture/compare register 1
// ( (unsigned int)((TIM17_CCR1 >> 0) & 0xFFFFFFFF), ((TIM17_CCR1 = (TIM17_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM17_BDTR -------------------------------
// SVD Line: 8991
unsigned int TIM17_BDTR __AT (0x40014844);
// ------------------------------- Field Item: TIM17_BDTR_DTG -----------------------------------
// SVD Line: 8996
// - SFDITEM_FIELD__TIM17_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40014844) DTG
//
// ( (unsigned char)((TIM17_BDTR >> 0) & 0xFF), ((TIM17_BDTR = (TIM17_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_LOCK ----------------------------------
// SVD Line: 9000
// - SFDITEM_FIELD__TIM17_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40014844) LOCK
//
// ( (unsigned char)((TIM17_BDTR >> 8) & 0x3), ((TIM17_BDTR = (TIM17_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_OSSI ----------------------------------
// SVD Line: 9004
// - SFDITEM_FIELD__TIM17_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40014844) OSSI
//
// ( (unsigned int) TIM17_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_OSSR ----------------------------------
// SVD Line: 9008
// - SFDITEM_FIELD__TIM17_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40014844) OSSR
//
// ( (unsigned int) TIM17_BDTR )
// OSSR
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_BKE -----------------------------------
// SVD Line: 9012
// - SFDITEM_FIELD__TIM17_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40014844) BKE
//
// ( (unsigned int) TIM17_BDTR )
// BKE
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_BKP -----------------------------------
// SVD Line: 9016
// - SFDITEM_FIELD__TIM17_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40014844) BKP
//
// ( (unsigned int) TIM17_BDTR )
// BKP
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_AOE -----------------------------------
// SVD Line: 9020
// - SFDITEM_FIELD__TIM17_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40014844) AOE
//
// ( (unsigned int) TIM17_BDTR )
// AOE
//
//
//
// ------------------------------- Field Item: TIM17_BDTR_MOE -----------------------------------
// SVD Line: 9024
// - SFDITEM_FIELD__TIM17_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40014844) MOE
//
// ( (unsigned int) TIM17_BDTR )
// MOE
//
//
//
// ------------------------------- Register RTree: TIM17_BDTR -----------------------------------
// SVD Line: 8991
// SFDITEM_REG__TIM17_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40014844) break and dead-time register
// ( (unsigned int)((TIM17_BDTR >> 0) & 0xFFFFFFFF), ((TIM17_BDTR = (TIM17_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_BDTR_DTG
// - SFDITEM_FIELD__TIM17_BDTR_LOCK
// - SFDITEM_FIELD__TIM17_BDTR_OSSI
// - SFDITEM_FIELD__TIM17_BDTR_OSSR
// - SFDITEM_FIELD__TIM17_BDTR_BKE
// - SFDITEM_FIELD__TIM17_BDTR_BKP
// - SFDITEM_FIELD__TIM17_BDTR_AOE
// - SFDITEM_FIELD__TIM17_BDTR_MOE
//
//
// --------------------------- Register Item Address: TIM17_TISEL -------------------------------
// SVD Line: 9030
unsigned int TIM17_TISEL __AT (0x4001485C);
// ----------------------------- Field Item: TIM17_TISEL_TI1SEL ---------------------------------
// SVD Line: 9034
// - SFDITEM_FIELD__TIM17_TISEL_TI1SEL
// TI1SEL
//
// [Bits 3..0] RW (@ 0x4001485C) TI1SEL
//
// ( (unsigned char)((TIM17_TISEL >> 0) & 0xF), ((TIM17_TISEL = (TIM17_TISEL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM17_TISEL_TI2SEL ---------------------------------
// SVD Line: 9038
// - SFDITEM_FIELD__TIM17_TISEL_TI2SEL
// TI2SEL
//
// [Bits 11..8] RW (@ 0x4001485C) TI2SEL
//
// ( (unsigned char)((TIM17_TISEL >> 8) & 0xF), ((TIM17_TISEL = (TIM17_TISEL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM17_TISEL_TI3SEL ---------------------------------
// SVD Line: 9042
// - SFDITEM_FIELD__TIM17_TISEL_TI3SEL
// TI3SEL
//
// [Bits 19..16] RW (@ 0x4001485C) TI3SEL
//
// ( (unsigned char)((TIM17_TISEL >> 16) & 0xF), ((TIM17_TISEL = (TIM17_TISEL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: TIM17_TISEL_TI4SEL ---------------------------------
// SVD Line: 9046
// - SFDITEM_FIELD__TIM17_TISEL_TI4SEL
// TI4SEL
//
// [Bits 27..24] RW (@ 0x4001485C) TI4SEL
//
// ( (unsigned char)((TIM17_TISEL >> 24) & 0xF), ((TIM17_TISEL = (TIM17_TISEL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM17_TISEL ----------------------------------
// SVD Line: 9030
// SFDITEM_REG__TIM17_TISEL
// TISEL
//
// [Bits 31..0] RW (@ 0x4001485C) TISEL
// ( (unsigned int)((TIM17_TISEL >> 0) & 0xFFFFFFFF), ((TIM17_TISEL = (TIM17_TISEL & ~(0xF0F0F0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F0F0F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_TISEL_TI1SEL
// - SFDITEM_FIELD__TIM17_TISEL_TI2SEL
// - SFDITEM_FIELD__TIM17_TISEL_TI3SEL
// - SFDITEM_FIELD__TIM17_TISEL_TI4SEL
//
//
// ---------------------------- Register Item Address: TIM17_AF1 --------------------------------
// SVD Line: 9052
unsigned int TIM17_AF1 __AT (0x40014860);
// ------------------------------- Field Item: TIM17_AF1_BKINE ----------------------------------
// SVD Line: 9056
// - SFDITEM_FIELD__TIM17_AF1_BKINE
// BKINE
//
// [Bit 0] RW (@ 0x40014860) BKINE
//
// ( (unsigned int) TIM17_AF1 )
// BKINE
//
//
//
// ------------------------------ Field Item: TIM17_AF1_BKCMP1E ---------------------------------
// SVD Line: 9060
// - SFDITEM_FIELD__TIM17_AF1_BKCMP1E
// BKCMP1E
//
// [Bit 1] RW (@ 0x40014860) BKCMP1E
//
// ( (unsigned int) TIM17_AF1 )
// BKCMP1E
//
//
//
// ------------------------------ Field Item: TIM17_AF1_BKCMP2E ---------------------------------
// SVD Line: 9064
// - SFDITEM_FIELD__TIM17_AF1_BKCMP2E
// BKCMP2E
//
// [Bit 2] RW (@ 0x40014860) BKCMP2E
//
// ( (unsigned int) TIM17_AF1 )
// BKCMP2E
//
//
//
// ------------------------------- Field Item: TIM17_AF1_BKINP ----------------------------------
// SVD Line: 9068
// - SFDITEM_FIELD__TIM17_AF1_BKINP
// BKINP
//
// [Bit 9] RW (@ 0x40014860) BKINP
//
// ( (unsigned int) TIM17_AF1 )
// BKINP
//
//
//
// ------------------------------ Field Item: TIM17_AF1_BKCMP1P ---------------------------------
// SVD Line: 9072
// - SFDITEM_FIELD__TIM17_AF1_BKCMP1P
// BKCMP1P
//
// [Bit 10] RW (@ 0x40014860) BKCMP1P
//
// ( (unsigned int) TIM17_AF1 )
// BKCMP1P
//
//
//
// ------------------------------ Field Item: TIM17_AF1_BKCMP2P ---------------------------------
// SVD Line: 9076
// - SFDITEM_FIELD__TIM17_AF1_BKCMP2P
// BKCMP2P
//
// [Bit 11] RW (@ 0x40014860) BKCMP2P
//
// ( (unsigned int) TIM17_AF1 )
// BKCMP2P
//
//
//
// -------------------------------- Register RTree: TIM17_AF1 -----------------------------------
// SVD Line: 9052
// SFDITEM_REG__TIM17_AF1
// AF1
//
// [Bits 31..0] RW (@ 0x40014860) AF1
// ( (unsigned int)((TIM17_AF1 >> 0) & 0xFFFFFFFF), ((TIM17_AF1 = (TIM17_AF1 & ~(0xE07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xE07) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_AF1_BKINE
// - SFDITEM_FIELD__TIM17_AF1_BKCMP1E
// - SFDITEM_FIELD__TIM17_AF1_BKCMP2E
// - SFDITEM_FIELD__TIM17_AF1_BKINP
// - SFDITEM_FIELD__TIM17_AF1_BKCMP1P
// - SFDITEM_FIELD__TIM17_AF1_BKCMP2P
//
//
// ---------------------------- Register Item Address: TIM17_DCR --------------------------------
// SVD Line: 9082
unsigned int TIM17_DCR __AT (0x40014BDC);
// -------------------------------- Field Item: TIM17_DCR_DBA -----------------------------------
// SVD Line: 9087
// - SFDITEM_FIELD__TIM17_DCR_DBA
// DBA
//
// [Bits 4..0] RW (@ 0x40014BDC) DBA
//
// ( (unsigned char)((TIM17_DCR >> 0) & 0x1F), ((TIM17_DCR = (TIM17_DCR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM17_DCR_DBL -----------------------------------
// SVD Line: 9091
// - SFDITEM_FIELD__TIM17_DCR_DBL
// DBL
//
// [Bits 12..8] RW (@ 0x40014BDC) DBL
//
// ( (unsigned char)((TIM17_DCR >> 8) & 0x1F), ((TIM17_DCR = (TIM17_DCR & ~(0x1FUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x1F) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM17_DCR -----------------------------------
// SVD Line: 9082
// SFDITEM_REG__TIM17_DCR
// DCR
//
// [Bits 31..0] RW (@ 0x40014BDC) DMA control register
// ( (unsigned int)((TIM17_DCR >> 0) & 0xFFFFFFFF), ((TIM17_DCR = (TIM17_DCR & ~(0x1F1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F1F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DCR_DBA
// - SFDITEM_FIELD__TIM17_DCR_DBL
//
//
// ---------------------------- Register Item Address: TIM17_DMAR -------------------------------
// SVD Line: 9097
unsigned int TIM17_DMAR __AT (0x40014BE0);
// ------------------------------- Field Item: TIM17_DMAR_DMAB ----------------------------------
// SVD Line: 9102
// - SFDITEM_FIELD__TIM17_DMAR_DMAB
// DMAB
//
// [Bits 31..0] RW (@ 0x40014BE0) DMAB
//
// ( (unsigned int)((TIM17_DMAR >> 0) & 0xFFFFFFFF), ((TIM17_DMAR = (TIM17_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM17_DMAR -----------------------------------
// SVD Line: 9097
// SFDITEM_REG__TIM17_DMAR
// DMAR
//
// [Bits 31..0] RW (@ 0x40014BE0) DMA address for full transfer
// ( (unsigned int)((TIM17_DMAR >> 0) & 0xFFFFFFFF), ((TIM17_DMAR = (TIM17_DMAR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM17_DMAR_DMAB
//
//
// --------------------------------- Peripheral View: TIM17 -------------------------------------
// SVD Line: 9110
// TIM17
// TIM17
// - SFDITEM_REG__TIM17_CR1
// - SFDITEM_REG__TIM17_CR2
// - SFDITEM_REG__TIM17_DIER
// - SFDITEM_REG__TIM17_SR
// - SFDITEM_REG__TIM17_EGR
// - SFDITEM_REG__TIM17_CCMR1_OUTPUT
// - SFDITEM_REG__TIM17_CCMR1_INPUT
// - SFDITEM_REG__TIM17_CCER
// - SFDITEM_REG__TIM17_CNT
// - SFDITEM_REG__TIM17_PSC
// - SFDITEM_REG__TIM17_ARR
// - SFDITEM_REG__TIM17_RCR
// - SFDITEM_REG__TIM17_CCR1
// - SFDITEM_REG__TIM17_BDTR
// - SFDITEM_REG__TIM17_TISEL
// - SFDITEM_REG__TIM17_AF1
// - SFDITEM_REG__TIM17_DCR
// - SFDITEM_REG__TIM17_DMAR
//
//
// ----------------------------- Register Item Address: UART1_DR --------------------------------
// SVD Line: 9129
unsigned int UART1_DR __AT (0x40004800);
// --------------------------------- Field Item: UART1_DR_DR ------------------------------------
// SVD Line: 9133
// - SFDITEM_FIELD__UART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004800) Receive/send data register
//
// ( (unsigned short)((UART1_DR >> 0) & 0x1FF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_DR ------------------------------------
// SVD Line: 9129
// SFDITEM_REG__UART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004800) DR
// ( (unsigned int)((UART1_DR >> 0) & 0xFFFFFFFF), ((UART1_DR = (UART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_DR_DR
//
//
// ---------------------------- Register Item Address: UART1_BRR --------------------------------
// SVD Line: 9140
unsigned int UART1_BRR __AT (0x40004804);
// -------------------------------- Field Item: UART1_BRR_BRR -----------------------------------
// SVD Line: 9144
// - SFDITEM_FIELD__UART1_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40004804) Baud rate register
//
// ( (unsigned short)((UART1_BRR >> 0) & 0xFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_BRR -----------------------------------
// SVD Line: 9140
// SFDITEM_REG__UART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004804) BRR
// ( (unsigned int)((UART1_BRR >> 0) & 0xFFFFFFFF), ((UART1_BRR = (UART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART1_SR --------------------------------
// SVD Line: 9151
unsigned int UART1_SR __AT (0x40004810);
// -------------------------------- Field Item: UART1_SR_RXNE -----------------------------------
// SVD Line: 9155
// - SFDITEM_FIELD__UART1_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40004810) Receive register not empty
//
// ( (unsigned int) UART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART1_SR_ORE ------------------------------------
// SVD Line: 9161
// - SFDITEM_FIELD__UART1_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40004810) Overrun error bit
//
// ( (unsigned int) UART1_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART1_SR_PE ------------------------------------
// SVD Line: 9166
// - SFDITEM_FIELD__UART1_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40004810) Parity Error bit
//
// ( (unsigned int) UART1_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART1_SR_FE ------------------------------------
// SVD Line: 9171
// - SFDITEM_FIELD__UART1_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40004810) Framing Error bit
//
// ( (unsigned int) UART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART1_SR_BRI ------------------------------------
// SVD Line: 9176
// - SFDITEM_FIELD__UART1_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40004810) Break Interrupt bit
//
// ( (unsigned int) UART1_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART1_SR_TDRE -----------------------------------
// SVD Line: 9181
// - SFDITEM_FIELD__UART1_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40004810) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART1_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART1_SR_TXE ------------------------------------
// SVD Line: 9187
// - SFDITEM_FIELD__UART1_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40004810) Transmitter Empty bit
//
// ( (unsigned int) UART1_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART1_SR_ADDR_RCVD ---------------------------------
// SVD Line: 9193
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40004810) Address Received Bit
//
// ( (unsigned int) UART1_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART1_SR_BUSY -----------------------------------
// SVD Line: 9198
// - SFDITEM_FIELD__UART1_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40004810) UART Busy
//
// ( (unsigned int) UART1_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART1_SR_BUSY_ERR ---------------------------------
// SVD Line: 9204
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40004810) Busy Detect Error
//
// ( (unsigned int) UART1_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART1_SR ------------------------------------
// SVD Line: 9151
// SFDITEM_REG__UART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004810) SR
// ( (unsigned int)((UART1_SR >> 0) & 0xFFFFFFFF), ((UART1_SR = (UART1_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_SR_RXNE
// - SFDITEM_FIELD__UART1_SR_ORE
// - SFDITEM_FIELD__UART1_SR_PE
// - SFDITEM_FIELD__UART1_SR_FE
// - SFDITEM_FIELD__UART1_SR_BRI
// - SFDITEM_FIELD__UART1_SR_TDRE
// - SFDITEM_FIELD__UART1_SR_TXE
// - SFDITEM_FIELD__UART1_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART1_SR_BUSY
// - SFDITEM_FIELD__UART1_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART1_CR1 --------------------------------
// SVD Line: 9211
unsigned int UART1_CR1 __AT (0x40004814);
// --------------------------------- Field Item: UART1_CR1_M ------------------------------------
// SVD Line: 9215
// - SFDITEM_FIELD__UART1_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40004814) Data Length Select
//
// ( (unsigned char)((UART1_CR1 >> 0) & 0x3), ((UART1_CR1 = (UART1_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART1_CR1_STOP -----------------------------------
// SVD Line: 9220
// - SFDITEM_FIELD__UART1_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40004814) Number of stop bits
//
// ( (unsigned int) UART1_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART1_CR1_PCE -----------------------------------
// SVD Line: 9225
// - SFDITEM_FIELD__UART1_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40004814) Parity Enable
//
// ( (unsigned int) UART1_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART1_CR1_PS ------------------------------------
// SVD Line: 9230
// - SFDITEM_FIELD__UART1_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40004814) Even Parity Select
//
// ( (unsigned int) UART1_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART1_CR1_SP ------------------------------------
// SVD Line: 9235
// - SFDITEM_FIELD__UART1_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40004814) Stick Parity
//
// ( (unsigned int) UART1_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART1_CR1_SBK -----------------------------------
// SVD Line: 9240
// - SFDITEM_FIELD__UART1_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40004814) Send Break
//
// ( (unsigned int) UART1_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART1_CR1_SWAP -----------------------------------
// SVD Line: 9245
// - SFDITEM_FIELD__UART1_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40004814) TX/RX pin swap
//
// ( (unsigned int) UART1_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART1_CR1_MSBFIRST ---------------------------------
// SVD Line: 9250
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40004814) MSB first mode
//
// ( (unsigned int) UART1_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART1_CR1 -----------------------------------
// SVD Line: 9211
// SFDITEM_REG__UART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40004814) CR1
// ( (unsigned int)((UART1_CR1 >> 0) & 0xFFFFFFFF), ((UART1_CR1 = (UART1_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR1_M
// - SFDITEM_FIELD__UART1_CR1_STOP
// - SFDITEM_FIELD__UART1_CR1_PCE
// - SFDITEM_FIELD__UART1_CR1_PS
// - SFDITEM_FIELD__UART1_CR1_SP
// - SFDITEM_FIELD__UART1_CR1_SBK
// - SFDITEM_FIELD__UART1_CR1_SWAP
// - SFDITEM_FIELD__UART1_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART1_CR2 --------------------------------
// SVD Line: 9257
unsigned int UART1_CR2 __AT (0x40004818);
// ------------------------------ Field Item: UART1_CR2_RXNEIE ----------------------------------
// SVD Line: 9261
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40004818) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART1_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART1_CR2_TDREIE ----------------------------------
// SVD Line: 9266
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40004818) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART1_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART1_CR2_LSIE -----------------------------------
// SVD Line: 9271
// - SFDITEM_FIELD__UART1_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40004818) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART1_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART1_CR2_BUSYERRIE --------------------------------
// SVD Line: 9276
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40004818) Enable Busyerr state interruption
//
// ( (unsigned int) UART1_CR2 )
// BUSYERRIE
//
//
//
// ------------------------------- Field Item: UART1_CR2_TXEIE ----------------------------------
// SVD Line: 9281
// - SFDITEM_FIELD__UART1_CR2_TXEIE
// TXEIE
//
// [Bit 4] RW (@ 0x40004818) Enable tx empty interruption
//
// ( (unsigned int) UART1_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: UART1_CR2 -----------------------------------
// SVD Line: 9257
// SFDITEM_REG__UART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004818) CR2
// ( (unsigned int)((UART1_CR2 >> 0) & 0xFFFFFFFF), ((UART1_CR2 = (UART1_CR2 & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR2_RXNEIE
// - SFDITEM_FIELD__UART1_CR2_TDREIE
// - SFDITEM_FIELD__UART1_CR2_LSIE
// - SFDITEM_FIELD__UART1_CR2_BUSYERRIE
// - SFDITEM_FIELD__UART1_CR2_TXEIE
//
//
// ---------------------------- Register Item Address: UART1_CR3 --------------------------------
// SVD Line: 9288
unsigned int UART1_CR3 __AT (0x4000481C);
// -------------------------------- Field Item: UART1_CR3_M_E -----------------------------------
// SVD Line: 9292
// - SFDITEM_FIELD__UART1_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x4000481C) Extension for DLS
//
// ( (unsigned int) UART1_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART1_CR3_ADDR_MATCH --------------------------------
// SVD Line: 9297
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x4000481C) Address Match Mode
//
// ( (unsigned int) UART1_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART1_CR3_SEND_ADDR --------------------------------
// SVD Line: 9302
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x4000481C) Send address control bit
//
// ( (unsigned int) UART1_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART1_CR3_TX_MODE ---------------------------------
// SVD Line: 9307
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x4000481C) Transmit mode control bit
//
// ( (unsigned int) UART1_CR3 )
// TX_MODE
//
//
//
// ------------------------------- Field Item: UART1_CR3_DMAR -----------------------------------
// SVD Line: 9312
// - SFDITEM_FIELD__UART1_CR3_DMAR
// DMAR
//
// [Bit 4] RW (@ 0x4000481C) DMA receive enable
//
// ( (unsigned int) UART1_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: UART1_CR3_DMAT -----------------------------------
// SVD Line: 9317
// - SFDITEM_FIELD__UART1_CR3_DMAT
// DMAT
//
// [Bit 5] RW (@ 0x4000481C) DMA transmit enable
//
// ( (unsigned int) UART1_CR3 )
// DMAT
//
//
//
// --------------------------- Field Item: UART1_CR3_DMA_SOFT_ACK -------------------------------
// SVD Line: 9322
// - SFDITEM_FIELD__UART1_CR3_DMA_SOFT_ACK
// DMA_SOFT_ACK
//
// [Bit 6] RW (@ 0x4000481C) DMA software ack
//
// ( (unsigned int) UART1_CR3 )
// DMA_SOFT_ACK
//
//
//
// -------------------------------- Register RTree: UART1_CR3 -----------------------------------
// SVD Line: 9288
// SFDITEM_REG__UART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x4000481C) CR3
// ( (unsigned int)((UART1_CR3 >> 0) & 0xFFFFFFFF), ((UART1_CR3 = (UART1_CR3 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_CR3_M_E
// - SFDITEM_FIELD__UART1_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART1_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART1_CR3_TX_MODE
// - SFDITEM_FIELD__UART1_CR3_DMAR
// - SFDITEM_FIELD__UART1_CR3_DMAT
// - SFDITEM_FIELD__UART1_CR3_DMA_SOFT_ACK
//
//
// ---------------------------- Register Item Address: UART1_RAR --------------------------------
// SVD Line: 9329
unsigned int UART1_RAR __AT (0x40004820);
// -------------------------------- Field Item: UART1_RAR_RAR -----------------------------------
// SVD Line: 9333
// - SFDITEM_FIELD__UART1_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40004820) Receive address matching register
//
// ( (unsigned char)((UART1_RAR >> 0) & 0xFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_RAR -----------------------------------
// SVD Line: 9329
// SFDITEM_REG__UART1_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40004820) RAR
// ( (unsigned int)((UART1_RAR >> 0) & 0xFFFFFFFF), ((UART1_RAR = (UART1_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART1_TAR --------------------------------
// SVD Line: 9340
unsigned int UART1_TAR __AT (0x40004824);
// -------------------------------- Field Item: UART1_TAR_TAR -----------------------------------
// SVD Line: 9344
// - SFDITEM_FIELD__UART1_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40004824) Transmit address matching register
//
// ( (unsigned char)((UART1_TAR >> 0) & 0xFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART1_TAR -----------------------------------
// SVD Line: 9340
// SFDITEM_REG__UART1_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40004824) TAR
// ( (unsigned int)((UART1_TAR >> 0) & 0xFFFFFFFF), ((UART1_TAR = (UART1_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_TAR_TAR
//
//
// ---------------------------- Register Item Address: UART1_BRRF -------------------------------
// SVD Line: 9351
unsigned int UART1_BRRF __AT (0x40004828);
// ------------------------------- Field Item: UART1_BRRF_BRRF ----------------------------------
// SVD Line: 9355
// - SFDITEM_FIELD__UART1_BRRF_BRRF
// BRRF
//
// [Bits 3..0] RW (@ 0x40004828) Baud rate fractional register
//
// ( (unsigned char)((UART1_BRRF >> 0) & 0xF), ((UART1_BRRF = (UART1_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: UART1_BRRF -----------------------------------
// SVD Line: 9351
// SFDITEM_REG__UART1_BRRF
// BRRF
//
// [Bits 31..0] RW (@ 0x40004828) BRRF
// ( (unsigned int)((UART1_BRRF >> 0) & 0xFFFFFFFF), ((UART1_BRRF = (UART1_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART1_BRRF_BRRF
//
//
// --------------------------------- Peripheral View: UART1 -------------------------------------
// SVD Line: 9119
// UART1
// UART1
// - SFDITEM_REG__UART1_DR
// - SFDITEM_REG__UART1_BRR
// - SFDITEM_REG__UART1_SR
// - SFDITEM_REG__UART1_CR1
// - SFDITEM_REG__UART1_CR2
// - SFDITEM_REG__UART1_CR3
// - SFDITEM_REG__UART1_RAR
// - SFDITEM_REG__UART1_TAR
// - SFDITEM_REG__UART1_BRRF
//
//
// ----------------------------- Register Item Address: UART2_DR --------------------------------
// SVD Line: 9129
unsigned int UART2_DR __AT (0x40004C00);
// --------------------------------- Field Item: UART2_DR_DR ------------------------------------
// SVD Line: 9133
// - SFDITEM_FIELD__UART2_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004C00) Receive/send data register
//
// ( (unsigned short)((UART2_DR >> 0) & 0x1FF), ((UART2_DR = (UART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_DR ------------------------------------
// SVD Line: 9129
// SFDITEM_REG__UART2_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004C00) DR
// ( (unsigned int)((UART2_DR >> 0) & 0xFFFFFFFF), ((UART2_DR = (UART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_DR_DR
//
//
// ---------------------------- Register Item Address: UART2_BRR --------------------------------
// SVD Line: 9140
unsigned int UART2_BRR __AT (0x40004C04);
// -------------------------------- Field Item: UART2_BRR_BRR -----------------------------------
// SVD Line: 9144
// - SFDITEM_FIELD__UART2_BRR_BRR
// BRR
//
// [Bits 15..0] RW (@ 0x40004C04) Baud rate register
//
// ( (unsigned short)((UART2_BRR >> 0) & 0xFFFF), ((UART2_BRR = (UART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_BRR -----------------------------------
// SVD Line: 9140
// SFDITEM_REG__UART2_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004C04) BRR
// ( (unsigned int)((UART2_BRR >> 0) & 0xFFFFFFFF), ((UART2_BRR = (UART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_BRR_BRR
//
//
// ----------------------------- Register Item Address: UART2_SR --------------------------------
// SVD Line: 9151
unsigned int UART2_SR __AT (0x40004C10);
// -------------------------------- Field Item: UART2_SR_RXNE -----------------------------------
// SVD Line: 9155
// - SFDITEM_FIELD__UART2_SR_RXNE
// RXNE
//
// [Bit 0] RO (@ 0x40004C10) Receive register not empty
//
// ( (unsigned int) UART2_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: UART2_SR_ORE ------------------------------------
// SVD Line: 9161
// - SFDITEM_FIELD__UART2_SR_ORE
// ORE
//
// [Bit 1] RW (@ 0x40004C10) Overrun error bit
//
// ( (unsigned int) UART2_SR )
// ORE
//
//
//
// --------------------------------- Field Item: UART2_SR_PE ------------------------------------
// SVD Line: 9166
// - SFDITEM_FIELD__UART2_SR_PE
// PE
//
// [Bit 2] RW (@ 0x40004C10) Parity Error bit
//
// ( (unsigned int) UART2_SR )
// PE
//
//
//
// --------------------------------- Field Item: UART2_SR_FE ------------------------------------
// SVD Line: 9171
// - SFDITEM_FIELD__UART2_SR_FE
// FE
//
// [Bit 3] RW (@ 0x40004C10) Framing Error bit
//
// ( (unsigned int) UART2_SR )
// FE
//
//
//
// -------------------------------- Field Item: UART2_SR_BRI ------------------------------------
// SVD Line: 9176
// - SFDITEM_FIELD__UART2_SR_BRI
// BRI
//
// [Bit 4] RW (@ 0x40004C10) Break Interrupt bit
//
// ( (unsigned int) UART2_SR )
// BRI
//
//
//
// -------------------------------- Field Item: UART2_SR_TDRE -----------------------------------
// SVD Line: 9181
// - SFDITEM_FIELD__UART2_SR_TDRE
// TDRE
//
// [Bit 5] RO (@ 0x40004C10) Transmit Holding Register Empty bit
//
// ( (unsigned int) UART2_SR )
// TDRE
//
//
//
// -------------------------------- Field Item: UART2_SR_TXE ------------------------------------
// SVD Line: 9187
// - SFDITEM_FIELD__UART2_SR_TXE
// TXE
//
// [Bit 6] RO (@ 0x40004C10) Transmitter Empty bit
//
// ( (unsigned int) UART2_SR )
// TXE
//
//
//
// ----------------------------- Field Item: UART2_SR_ADDR_RCVD ---------------------------------
// SVD Line: 9193
// - SFDITEM_FIELD__UART2_SR_ADDR_RCVD
// ADDR_RCVD
//
// [Bit 8] RW (@ 0x40004C10) Address Received Bit
//
// ( (unsigned int) UART2_SR )
// ADDR_RCVD
//
//
//
// -------------------------------- Field Item: UART2_SR_BUSY -----------------------------------
// SVD Line: 9198
// - SFDITEM_FIELD__UART2_SR_BUSY
// BUSY
//
// [Bit 9] RO (@ 0x40004C10) UART Busy
//
// ( (unsigned int) UART2_SR )
// BUSY
//
//
//
// ------------------------------ Field Item: UART2_SR_BUSY_ERR ---------------------------------
// SVD Line: 9204
// - SFDITEM_FIELD__UART2_SR_BUSY_ERR
// BUSY_ERR
//
// [Bit 10] RW (@ 0x40004C10) Busy Detect Error
//
// ( (unsigned int) UART2_SR )
// BUSY_ERR
//
//
//
// -------------------------------- Register RTree: UART2_SR ------------------------------------
// SVD Line: 9151
// SFDITEM_REG__UART2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004C10) SR
// ( (unsigned int)((UART2_SR >> 0) & 0xFFFFFFFF), ((UART2_SR = (UART2_SR & ~(0x51EUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x51E) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_SR_RXNE
// - SFDITEM_FIELD__UART2_SR_ORE
// - SFDITEM_FIELD__UART2_SR_PE
// - SFDITEM_FIELD__UART2_SR_FE
// - SFDITEM_FIELD__UART2_SR_BRI
// - SFDITEM_FIELD__UART2_SR_TDRE
// - SFDITEM_FIELD__UART2_SR_TXE
// - SFDITEM_FIELD__UART2_SR_ADDR_RCVD
// - SFDITEM_FIELD__UART2_SR_BUSY
// - SFDITEM_FIELD__UART2_SR_BUSY_ERR
//
//
// ---------------------------- Register Item Address: UART2_CR1 --------------------------------
// SVD Line: 9211
unsigned int UART2_CR1 __AT (0x40004C14);
// --------------------------------- Field Item: UART2_CR1_M ------------------------------------
// SVD Line: 9215
// - SFDITEM_FIELD__UART2_CR1_M
// M
//
// [Bits 1..0] RW (@ 0x40004C14) Data Length Select
//
// ( (unsigned char)((UART2_CR1 >> 0) & 0x3), ((UART2_CR1 = (UART2_CR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: UART2_CR1_STOP -----------------------------------
// SVD Line: 9220
// - SFDITEM_FIELD__UART2_CR1_STOP
// STOP
//
// [Bit 2] RW (@ 0x40004C14) Number of stop bits
//
// ( (unsigned int) UART2_CR1 )
// STOP
//
//
//
// -------------------------------- Field Item: UART2_CR1_PCE -----------------------------------
// SVD Line: 9225
// - SFDITEM_FIELD__UART2_CR1_PCE
// PCE
//
// [Bit 3] RW (@ 0x40004C14) Parity Enable
//
// ( (unsigned int) UART2_CR1 )
// PCE
//
//
//
// -------------------------------- Field Item: UART2_CR1_PS ------------------------------------
// SVD Line: 9230
// - SFDITEM_FIELD__UART2_CR1_PS
// PS
//
// [Bit 4] RW (@ 0x40004C14) Even Parity Select
//
// ( (unsigned int) UART2_CR1 )
// PS
//
//
//
// -------------------------------- Field Item: UART2_CR1_SP ------------------------------------
// SVD Line: 9235
// - SFDITEM_FIELD__UART2_CR1_SP
// SP
//
// [Bit 5] RW (@ 0x40004C14) Stick Parity
//
// ( (unsigned int) UART2_CR1 )
// SP
//
//
//
// -------------------------------- Field Item: UART2_CR1_SBK -----------------------------------
// SVD Line: 9240
// - SFDITEM_FIELD__UART2_CR1_SBK
// SBK
//
// [Bit 6] RW (@ 0x40004C14) Send Break
//
// ( (unsigned int) UART2_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: UART2_CR1_SWAP -----------------------------------
// SVD Line: 9245
// - SFDITEM_FIELD__UART2_CR1_SWAP
// SWAP
//
// [Bit 8] RW (@ 0x40004C14) TX/RX pin swap
//
// ( (unsigned int) UART2_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: UART2_CR1_MSBFIRST ---------------------------------
// SVD Line: 9250
// - SFDITEM_FIELD__UART2_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 9] RW (@ 0x40004C14) MSB first mode
//
// ( (unsigned int) UART2_CR1 )
// MSBFIRST
//
//
//
// -------------------------------- Register RTree: UART2_CR1 -----------------------------------
// SVD Line: 9211
// SFDITEM_REG__UART2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40004C14) CR1
// ( (unsigned int)((UART2_CR1 >> 0) & 0xFFFFFFFF), ((UART2_CR1 = (UART2_CR1 & ~(0x37FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x37F) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR1_M
// - SFDITEM_FIELD__UART2_CR1_STOP
// - SFDITEM_FIELD__UART2_CR1_PCE
// - SFDITEM_FIELD__UART2_CR1_PS
// - SFDITEM_FIELD__UART2_CR1_SP
// - SFDITEM_FIELD__UART2_CR1_SBK
// - SFDITEM_FIELD__UART2_CR1_SWAP
// - SFDITEM_FIELD__UART2_CR1_MSBFIRST
//
//
// ---------------------------- Register Item Address: UART2_CR2 --------------------------------
// SVD Line: 9257
unsigned int UART2_CR2 __AT (0x40004C18);
// ------------------------------ Field Item: UART2_CR2_RXNEIE ----------------------------------
// SVD Line: 9261
// - SFDITEM_FIELD__UART2_CR2_RXNEIE
// RXNEIE
//
// [Bit 0] RW (@ 0x40004C18) Enable Received Data Available Interrupt
//
// ( (unsigned int) UART2_CR2 )
// RXNEIE
//
//
//
// ------------------------------ Field Item: UART2_CR2_TDREIE ----------------------------------
// SVD Line: 9266
// - SFDITEM_FIELD__UART2_CR2_TDREIE
// TDREIE
//
// [Bit 1] RW (@ 0x40004C18) Enable Transmit Holding Register Empty Interrupt
//
// ( (unsigned int) UART2_CR2 )
// TDREIE
//
//
//
// ------------------------------- Field Item: UART2_CR2_LSIE -----------------------------------
// SVD Line: 9271
// - SFDITEM_FIELD__UART2_CR2_LSIE
// LSIE
//
// [Bit 2] RW (@ 0x40004C18) Enable Receiver Line Status Interrupt
//
// ( (unsigned int) UART2_CR2 )
// LSIE
//
//
//
// ----------------------------- Field Item: UART2_CR2_BUSYERRIE --------------------------------
// SVD Line: 9276
// - SFDITEM_FIELD__UART2_CR2_BUSYERRIE
// BUSYERRIE
//
// [Bit 3] RW (@ 0x40004C18) Enable Busyerr state interruption
//
// ( (unsigned int) UART2_CR2 )
// BUSYERRIE
//
//
//
// ------------------------------- Field Item: UART2_CR2_TXEIE ----------------------------------
// SVD Line: 9281
// - SFDITEM_FIELD__UART2_CR2_TXEIE
// TXEIE
//
// [Bit 4] RW (@ 0x40004C18) Enable tx empty interruption
//
// ( (unsigned int) UART2_CR2 )
// TXEIE
//
//
//
// -------------------------------- Register RTree: UART2_CR2 -----------------------------------
// SVD Line: 9257
// SFDITEM_REG__UART2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004C18) CR2
// ( (unsigned int)((UART2_CR2 >> 0) & 0xFFFFFFFF), ((UART2_CR2 = (UART2_CR2 & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR2_RXNEIE
// - SFDITEM_FIELD__UART2_CR2_TDREIE
// - SFDITEM_FIELD__UART2_CR2_LSIE
// - SFDITEM_FIELD__UART2_CR2_BUSYERRIE
// - SFDITEM_FIELD__UART2_CR2_TXEIE
//
//
// ---------------------------- Register Item Address: UART2_CR3 --------------------------------
// SVD Line: 9288
unsigned int UART2_CR3 __AT (0x40004C1C);
// -------------------------------- Field Item: UART2_CR3_M_E -----------------------------------
// SVD Line: 9292
// - SFDITEM_FIELD__UART2_CR3_M_E
// M_E
//
// [Bit 0] RW (@ 0x40004C1C) Extension for DLS
//
// ( (unsigned int) UART2_CR3 )
// M_E
//
//
//
// ---------------------------- Field Item: UART2_CR3_ADDR_MATCH --------------------------------
// SVD Line: 9297
// - SFDITEM_FIELD__UART2_CR3_ADDR_MATCH
// ADDR_MATCH
//
// [Bit 1] RW (@ 0x40004C1C) Address Match Mode
//
// ( (unsigned int) UART2_CR3 )
// ADDR_MATCH
//
//
//
// ----------------------------- Field Item: UART2_CR3_SEND_ADDR --------------------------------
// SVD Line: 9302
// - SFDITEM_FIELD__UART2_CR3_SEND_ADDR
// SEND_ADDR
//
// [Bit 2] RW (@ 0x40004C1C) Send address control bit
//
// ( (unsigned int) UART2_CR3 )
// SEND_ADDR
//
//
//
// ------------------------------ Field Item: UART2_CR3_TX_MODE ---------------------------------
// SVD Line: 9307
// - SFDITEM_FIELD__UART2_CR3_TX_MODE
// TX_MODE
//
// [Bit 3] RW (@ 0x40004C1C) Transmit mode control bit
//
// ( (unsigned int) UART2_CR3 )
// TX_MODE
//
//
//
// ------------------------------- Field Item: UART2_CR3_DMAR -----------------------------------
// SVD Line: 9312
// - SFDITEM_FIELD__UART2_CR3_DMAR
// DMAR
//
// [Bit 4] RW (@ 0x40004C1C) DMA receive enable
//
// ( (unsigned int) UART2_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: UART2_CR3_DMAT -----------------------------------
// SVD Line: 9317
// - SFDITEM_FIELD__UART2_CR3_DMAT
// DMAT
//
// [Bit 5] RW (@ 0x40004C1C) DMA transmit enable
//
// ( (unsigned int) UART2_CR3 )
// DMAT
//
//
//
// --------------------------- Field Item: UART2_CR3_DMA_SOFT_ACK -------------------------------
// SVD Line: 9322
// - SFDITEM_FIELD__UART2_CR3_DMA_SOFT_ACK
// DMA_SOFT_ACK
//
// [Bit 6] RW (@ 0x40004C1C) DMA software ack
//
// ( (unsigned int) UART2_CR3 )
// DMA_SOFT_ACK
//
//
//
// -------------------------------- Register RTree: UART2_CR3 -----------------------------------
// SVD Line: 9288
// SFDITEM_REG__UART2_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40004C1C) CR3
// ( (unsigned int)((UART2_CR3 >> 0) & 0xFFFFFFFF), ((UART2_CR3 = (UART2_CR3 & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7F) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_CR3_M_E
// - SFDITEM_FIELD__UART2_CR3_ADDR_MATCH
// - SFDITEM_FIELD__UART2_CR3_SEND_ADDR
// - SFDITEM_FIELD__UART2_CR3_TX_MODE
// - SFDITEM_FIELD__UART2_CR3_DMAR
// - SFDITEM_FIELD__UART2_CR3_DMAT
// - SFDITEM_FIELD__UART2_CR3_DMA_SOFT_ACK
//
//
// ---------------------------- Register Item Address: UART2_RAR --------------------------------
// SVD Line: 9329
unsigned int UART2_RAR __AT (0x40004C20);
// -------------------------------- Field Item: UART2_RAR_RAR -----------------------------------
// SVD Line: 9333
// - SFDITEM_FIELD__UART2_RAR_RAR
// RAR
//
// [Bits 7..0] RW (@ 0x40004C20) Receive address matching register
//
// ( (unsigned char)((UART2_RAR >> 0) & 0xFF), ((UART2_RAR = (UART2_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_RAR -----------------------------------
// SVD Line: 9329
// SFDITEM_REG__UART2_RAR
// RAR
//
// [Bits 31..0] RW (@ 0x40004C20) RAR
// ( (unsigned int)((UART2_RAR >> 0) & 0xFFFFFFFF), ((UART2_RAR = (UART2_RAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_RAR_RAR
//
//
// ---------------------------- Register Item Address: UART2_TAR --------------------------------
// SVD Line: 9340
unsigned int UART2_TAR __AT (0x40004C24);
// -------------------------------- Field Item: UART2_TAR_TAR -----------------------------------
// SVD Line: 9344
// - SFDITEM_FIELD__UART2_TAR_TAR
// TAR
//
// [Bits 7..0] RW (@ 0x40004C24) Transmit address matching register
//
// ( (unsigned char)((UART2_TAR >> 0) & 0xFF), ((UART2_TAR = (UART2_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: UART2_TAR -----------------------------------
// SVD Line: 9340
// SFDITEM_REG__UART2_TAR
// TAR
//
// [Bits 31..0] RW (@ 0x40004C24) TAR
// ( (unsigned int)((UART2_TAR >> 0) & 0xFFFFFFFF), ((UART2_TAR = (UART2_TAR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_TAR_TAR
//
//
// ---------------------------- Register Item Address: UART2_BRRF -------------------------------
// SVD Line: 9351
unsigned int UART2_BRRF __AT (0x40004C28);
// ------------------------------- Field Item: UART2_BRRF_BRRF ----------------------------------
// SVD Line: 9355
// - SFDITEM_FIELD__UART2_BRRF_BRRF
// BRRF
//
// [Bits 3..0] RW (@ 0x40004C28) Baud rate fractional register
//
// ( (unsigned char)((UART2_BRRF >> 0) & 0xF), ((UART2_BRRF = (UART2_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: UART2_BRRF -----------------------------------
// SVD Line: 9351
// SFDITEM_REG__UART2_BRRF
// BRRF
//
// [Bits 31..0] RW (@ 0x40004C28) BRRF
// ( (unsigned int)((UART2_BRRF >> 0) & 0xFFFFFFFF), ((UART2_BRRF = (UART2_BRRF & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF) << 0 ) ) ))
// - SFDITEM_FIELD__UART2_BRRF_BRRF
//
//
// --------------------------------- Peripheral View: UART2 -------------------------------------
// SVD Line: 9364
// UART2
// UART2
// - SFDITEM_REG__UART2_DR
// - SFDITEM_REG__UART2_BRR
// - SFDITEM_REG__UART2_SR
// - SFDITEM_REG__UART2_CR1
// - SFDITEM_REG__UART2_CR2
// - SFDITEM_REG__UART2_CR3
// - SFDITEM_REG__UART2_RAR
// - SFDITEM_REG__UART2_TAR
// - SFDITEM_REG__UART2_BRRF
//
//
// ---------------------------- Register Item Address: USART1_SR --------------------------------
// SVD Line: 9384
unsigned int USART1_SR __AT (0x40013800);
// -------------------------------- Field Item: USART1_SR_PE ------------------------------------
// SVD Line: 9389
// - SFDITEM_FIELD__USART1_SR_PE
// PE
//
// [Bit 0] RO (@ 0x40013800) Parity error
//
// ( (unsigned int) USART1_SR )
// PE
//
//
//
// -------------------------------- Field Item: USART1_SR_FE ------------------------------------
// SVD Line: 9395
// - SFDITEM_FIELD__USART1_SR_FE
// FE
//
// [Bit 1] RO (@ 0x40013800) Framing error
//
// ( (unsigned int) USART1_SR )
// FE
//
//
//
// -------------------------------- Field Item: USART1_SR_NE ------------------------------------
// SVD Line: 9401
// - SFDITEM_FIELD__USART1_SR_NE
// NE
//
// [Bit 2] RO (@ 0x40013800) Noise error flag
//
// ( (unsigned int) USART1_SR )
// NE
//
//
//
// -------------------------------- Field Item: USART1_SR_ORE -----------------------------------
// SVD Line: 9407
// - SFDITEM_FIELD__USART1_SR_ORE
// ORE
//
// [Bit 3] RO (@ 0x40013800) overrun error
//
// ( (unsigned int) USART1_SR )
// ORE
//
//
//
// ------------------------------- Field Item: USART1_SR_IDLE -----------------------------------
// SVD Line: 9413
// - SFDITEM_FIELD__USART1_SR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x40013800) idle
//
// ( (unsigned int) USART1_SR )
// IDLE
//
//
//
// ------------------------------- Field Item: USART1_SR_RXNE -----------------------------------
// SVD Line: 9419
// - SFDITEM_FIELD__USART1_SR_RXNE
// RXNE
//
// [Bit 5] RW (@ 0x40013800) Read data register not empty
//
// ( (unsigned int) USART1_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: USART1_SR_TC ------------------------------------
// SVD Line: 9424
// - SFDITEM_FIELD__USART1_SR_TC
// TC
//
// [Bit 6] RW (@ 0x40013800) Transmission complete
//
// ( (unsigned int) USART1_SR )
// TC
//
//
//
// -------------------------------- Field Item: USART1_SR_TXE -----------------------------------
// SVD Line: 9429
// - SFDITEM_FIELD__USART1_SR_TXE
// TXE
//
// [Bit 7] RO (@ 0x40013800) Transmit data register empty
//
// ( (unsigned int) USART1_SR )
// TXE
//
//
//
// -------------------------------- Field Item: USART1_SR_LBD -----------------------------------
// SVD Line: 9435
// - SFDITEM_FIELD__USART1_SR_LBD
// LBD
//
// [Bit 8] RW (@ 0x40013800) LIN break detection flag
//
// ( (unsigned int) USART1_SR )
// LBD
//
//
//
// -------------------------------- Field Item: USART1_SR_CTS -----------------------------------
// SVD Line: 9440
// - SFDITEM_FIELD__USART1_SR_CTS
// CTS
//
// [Bit 9] RW (@ 0x40013800) cts flag
//
// ( (unsigned int) USART1_SR )
// CTS
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRF -----------------------------------
// SVD Line: 9445
// - SFDITEM_FIELD__USART1_SR_ABRF
// ABRF
//
// [Bit 10] RO (@ 0x40013800) auto baud rate flag
//
// ( (unsigned int) USART1_SR )
// ABRF
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRE -----------------------------------
// SVD Line: 9451
// - SFDITEM_FIELD__USART1_SR_ABRE
// ABRE
//
// [Bit 11] RO (@ 0x40013800) auto baud rateerror
//
// ( (unsigned int) USART1_SR )
// ABRE
//
//
//
// ------------------------------- Field Item: USART1_SR_ABRRQ ----------------------------------
// SVD Line: 9457
// - SFDITEM_FIELD__USART1_SR_ABRRQ
// ABRRQ
//
// [Bit 12] RO (@ 0x40013800) auto baud rate req
//
// ( (unsigned int) USART1_SR )
// ABRRQ
//
//
//
// ------------------------------- Field Item: USART1_SR_RTOF -----------------------------------
// SVD Line: 9463
// - SFDITEM_FIELD__USART1_SR_RTOF
// RTOF
//
// [Bit 19] RW (@ 0x40013800) rto flag
//
// ( (unsigned int) USART1_SR )
// RTOF
//
//
//
// ------------------------------- Field Item: USART1_SR_TXPE -----------------------------------
// SVD Line: 9468
// - SFDITEM_FIELD__USART1_SR_TXPE
// TXPE
//
// [Bit 20] RW (@ 0x40013800) TXPE
//
// ( (unsigned int) USART1_SR )
// TXPE
//
//
//
// ------------------------------ Field Item: USART1_SR_RXBUSY ----------------------------------
// SVD Line: 9472
// - SFDITEM_FIELD__USART1_SR_RXBUSY
// RXBUSY
//
// [Bit 21] RO (@ 0x40013800) RXBUSY
//
// ( (unsigned int) USART1_SR )
// RXBUSY
//
//
//
// ------------------------------ Field Item: USART1_SR_TXBUSY ----------------------------------
// SVD Line: 9477
// - SFDITEM_FIELD__USART1_SR_TXBUSY
// TXBUSY
//
// [Bit 22] RO (@ 0x40013800) TXBUSY
//
// ( (unsigned int) USART1_SR )
// TXBUSY
//
//
//
// -------------------------------- Register RTree: USART1_SR -----------------------------------
// SVD Line: 9384
// SFDITEM_REG__USART1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40013800) Status register
// ( (unsigned int)((USART1_SR >> 0) & 0xFFFFFFFF), ((USART1_SR = (USART1_SR & ~(0x180360UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x180360) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_SR_PE
// - SFDITEM_FIELD__USART1_SR_FE
// - SFDITEM_FIELD__USART1_SR_NE
// - SFDITEM_FIELD__USART1_SR_ORE
// - SFDITEM_FIELD__USART1_SR_IDLE
// - SFDITEM_FIELD__USART1_SR_RXNE
// - SFDITEM_FIELD__USART1_SR_TC
// - SFDITEM_FIELD__USART1_SR_TXE
// - SFDITEM_FIELD__USART1_SR_LBD
// - SFDITEM_FIELD__USART1_SR_CTS
// - SFDITEM_FIELD__USART1_SR_ABRF
// - SFDITEM_FIELD__USART1_SR_ABRE
// - SFDITEM_FIELD__USART1_SR_ABRRQ
// - SFDITEM_FIELD__USART1_SR_RTOF
// - SFDITEM_FIELD__USART1_SR_TXPE
// - SFDITEM_FIELD__USART1_SR_RXBUSY
// - SFDITEM_FIELD__USART1_SR_TXBUSY
//
//
// ---------------------------- Register Item Address: USART1_DR --------------------------------
// SVD Line: 9484
unsigned int USART1_DR __AT (0x40013804);
// -------------------------------- Field Item: USART1_DR_DR ------------------------------------
// SVD Line: 9489
// - SFDITEM_FIELD__USART1_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40013804) dr
//
// ( (unsigned short)((USART1_DR >> 0) & 0x1FF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: USART1_DR -----------------------------------
// SVD Line: 9484
// SFDITEM_REG__USART1_DR
// DR
//
// [Bits 31..0] RW (@ 0x40013804) Data register
// ( (unsigned int)((USART1_DR >> 0) & 0xFFFFFFFF), ((USART1_DR = (USART1_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_DR_DR
//
//
// ---------------------------- Register Item Address: USART1_BRR -------------------------------
// SVD Line: 9496
unsigned int USART1_BRR __AT (0x40013808);
// --------------------------- Field Item: USART1_BRR_DIV_FRACTION ------------------------------
// SVD Line: 9501
// - SFDITEM_FIELD__USART1_BRR_DIV_FRACTION
// DIV_FRACTION
//
// [Bits 3..0] RW (@ 0x40013808) DIV_Fraction
//
// ( (unsigned char)((USART1_BRR >> 0) & 0xF), ((USART1_BRR = (USART1_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: USART1_BRR_DIV_MANTISSA ------------------------------
// SVD Line: 9506
// - SFDITEM_FIELD__USART1_BRR_DIV_MANTISSA
// DIV_MANTISSA
//
// [Bits 15..4] RW (@ 0x40013808) DIV_Mantissa
//
// ( (unsigned short)((USART1_BRR >> 4) & 0xFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFUL << 4 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_BRR -----------------------------------
// SVD Line: 9496
// SFDITEM_REG__USART1_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40013808) Baud rate register
// ( (unsigned int)((USART1_BRR >> 0) & 0xFFFFFFFF), ((USART1_BRR = (USART1_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_BRR_DIV_FRACTION
// - SFDITEM_FIELD__USART1_BRR_DIV_MANTISSA
//
//
// ---------------------------- Register Item Address: USART1_CR1 -------------------------------
// SVD Line: 9513
unsigned int USART1_CR1 __AT (0x4001380C);
// ------------------------------- Field Item: USART1_CR1_SBK -----------------------------------
// SVD Line: 9518
// - SFDITEM_FIELD__USART1_CR1_SBK
// SBK
//
// [Bit 0] RW (@ 0x4001380C) Send break
//
// ( (unsigned int) USART1_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: USART1_CR1_RWU -----------------------------------
// SVD Line: 9523
// - SFDITEM_FIELD__USART1_CR1_RWU
// RWU
//
// [Bit 1] RW (@ 0x4001380C) Receiver wakeup
//
// ( (unsigned int) USART1_CR1 )
// RWU
//
//
//
// -------------------------------- Field Item: USART1_CR1_RE -----------------------------------
// SVD Line: 9528
// - SFDITEM_FIELD__USART1_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x4001380C) Receiver enable
//
// ( (unsigned int) USART1_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: USART1_CR1_TE -----------------------------------
// SVD Line: 9533
// - SFDITEM_FIELD__USART1_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x4001380C) Transmitter enable
//
// ( (unsigned int) USART1_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: USART1_CR1_IDLEIE ---------------------------------
// SVD Line: 9538
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x4001380C) IDLE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_RXNEIE ---------------------------------
// SVD Line: 9543
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x4001380C) RXNE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_TCIE ----------------------------------
// SVD Line: 9548
// - SFDITEM_FIELD__USART1_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x4001380C) send complete int enable
//
// ( (unsigned int) USART1_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: USART1_CR1_TXEIE ----------------------------------
// SVD Line: 9553
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x4001380C) txe
//
// ( (unsigned int) USART1_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: USART1_CR1_PEIE ----------------------------------
// SVD Line: 9558
// - SFDITEM_FIELD__USART1_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x4001380C) PE interrupt enable
//
// ( (unsigned int) USART1_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: USART1_CR1_PS -----------------------------------
// SVD Line: 9563
// - SFDITEM_FIELD__USART1_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x4001380C) Parity selection
//
// ( (unsigned int) USART1_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: USART1_CR1_PCE -----------------------------------
// SVD Line: 9568
// - SFDITEM_FIELD__USART1_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x4001380C) Parity control enable
//
// ( (unsigned int) USART1_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: USART1_CR1_WAKE ----------------------------------
// SVD Line: 9573
// - SFDITEM_FIELD__USART1_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x4001380C) Wakeup method
//
// ( (unsigned int) USART1_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: USART1_CR1_M ------------------------------------
// SVD Line: 9578
// - SFDITEM_FIELD__USART1_CR1_M
// M
//
// [Bit 12] RW (@ 0x4001380C) word length
//
// ( (unsigned int) USART1_CR1 )
// M
//
//
//
// -------------------------------- Field Item: USART1_CR1_UE -----------------------------------
// SVD Line: 9583
// - SFDITEM_FIELD__USART1_CR1_UE
// UE
//
// [Bit 13] RW (@ 0x4001380C) uesart enable
//
// ( (unsigned int) USART1_CR1 )
// UE
//
//
//
// ----------------------------- Field Item: USART1_CR1_MSBFIRST --------------------------------
// SVD Line: 9588
// - SFDITEM_FIELD__USART1_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 15] RW (@ 0x4001380C) msbfirst
//
// ( (unsigned int) USART1_CR1 )
// MSBFIRST
//
//
//
// ------------------------------- Field Item: USART1_CR1_SWAP ----------------------------------
// SVD Line: 9593
// - SFDITEM_FIELD__USART1_CR1_SWAP
// SWAP
//
// [Bit 18] RW (@ 0x4001380C) swap
//
// ( (unsigned int) USART1_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: USART1_CR1_DATAINV ---------------------------------
// SVD Line: 9598
// - SFDITEM_FIELD__USART1_CR1_DATAINV
// DATAINV
//
// [Bit 27] RW (@ 0x4001380C) data inverse
//
// ( (unsigned int) USART1_CR1 )
// DATAINV
//
//
//
// ------------------------------- Register RTree: USART1_CR1 -----------------------------------
// SVD Line: 9513
// SFDITEM_REG__USART1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x4001380C) Control register 1
// ( (unsigned int)((USART1_CR1 >> 0) & 0xFFFFFFFF), ((USART1_CR1 = (USART1_CR1 & ~(0x804BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x804BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR1_SBK
// - SFDITEM_FIELD__USART1_CR1_RWU
// - SFDITEM_FIELD__USART1_CR1_RE
// - SFDITEM_FIELD__USART1_CR1_TE
// - SFDITEM_FIELD__USART1_CR1_IDLEIE
// - SFDITEM_FIELD__USART1_CR1_RXNEIE
// - SFDITEM_FIELD__USART1_CR1_TCIE
// - SFDITEM_FIELD__USART1_CR1_TXEIE
// - SFDITEM_FIELD__USART1_CR1_PEIE
// - SFDITEM_FIELD__USART1_CR1_PS
// - SFDITEM_FIELD__USART1_CR1_PCE
// - SFDITEM_FIELD__USART1_CR1_WAKE
// - SFDITEM_FIELD__USART1_CR1_M
// - SFDITEM_FIELD__USART1_CR1_UE
// - SFDITEM_FIELD__USART1_CR1_MSBFIRST
// - SFDITEM_FIELD__USART1_CR1_SWAP
// - SFDITEM_FIELD__USART1_CR1_DATAINV
//
//
// ---------------------------- Register Item Address: USART1_CR2 -------------------------------
// SVD Line: 9605
unsigned int USART1_CR2 __AT (0x40013810);
// ------------------------------- Field Item: USART1_CR2_ADD -----------------------------------
// SVD Line: 9610
// - SFDITEM_FIELD__USART1_CR2_ADD
// ADD
//
// [Bits 3..0] RW (@ 0x40013810) mute addr
//
// ( (unsigned char)((USART1_CR2 >> 0) & 0xF), ((USART1_CR2 = (USART1_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART1_CR2_LBDL ----------------------------------
// SVD Line: 9615
// - SFDITEM_FIELD__USART1_CR2_LBDL
// LBDL
//
// [Bit 5] RW (@ 0x40013810) LIN break detection length
//
// ( (unsigned int) USART1_CR2 )
// LBDL
//
//
//
// ------------------------------ Field Item: USART1_CR2_LBDIE ----------------------------------
// SVD Line: 9620
// - SFDITEM_FIELD__USART1_CR2_LBDIE
// LBDIE
//
// [Bit 6] RW (@ 0x40013810) lin break enable
//
// ( (unsigned int) USART1_CR2 )
// LBDIE
//
//
//
// ------------------------------- Field Item: USART1_CR2_LBCL ----------------------------------
// SVD Line: 9625
// - SFDITEM_FIELD__USART1_CR2_LBCL
// LBCL
//
// [Bit 8] RW (@ 0x40013810) lbcl
//
// ( (unsigned int) USART1_CR2 )
// LBCL
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPHA ----------------------------------
// SVD Line: 9630
// - SFDITEM_FIELD__USART1_CR2_CPHA
// CPHA
//
// [Bit 9] RW (@ 0x40013810) cpha
//
// ( (unsigned int) USART1_CR2 )
// CPHA
//
//
//
// ------------------------------- Field Item: USART1_CR2_CPOL ----------------------------------
// SVD Line: 9635
// - SFDITEM_FIELD__USART1_CR2_CPOL
// CPOL
//
// [Bit 10] RW (@ 0x40013810) cpol
//
// ( (unsigned int) USART1_CR2 )
// CPOL
//
//
//
// ------------------------------ Field Item: USART1_CR2_CLKEN ----------------------------------
// SVD Line: 9640
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// CLKEN
//
// [Bit 11] RW (@ 0x40013810) clk en
//
// ( (unsigned int) USART1_CR2 )
// CLKEN
//
//
//
// ------------------------------- Field Item: USART1_CR2_STOP ----------------------------------
// SVD Line: 9645
// - SFDITEM_FIELD__USART1_CR2_STOP
// STOP
//
// [Bits 13..12] RW (@ 0x40013810) stop bit
//
// ( (unsigned char)((USART1_CR2 >> 12) & 0x3), ((USART1_CR2 = (USART1_CR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: USART1_CR2_LINEN ----------------------------------
// SVD Line: 9650
// - SFDITEM_FIELD__USART1_CR2_LINEN
// LINEN
//
// [Bit 14] RW (@ 0x40013810) lin enable
//
// ( (unsigned int) USART1_CR2 )
// LINEN
//
//
//
// ------------------------------ Field Item: USART1_CR2_RTOEN ----------------------------------
// SVD Line: 9655
// - SFDITEM_FIELD__USART1_CR2_RTOEN
// RTOEN
//
// [Bit 25] RW (@ 0x40013810) Receiver timeout enable
//
// ( (unsigned int) USART1_CR2 )
// RTOEN
//
//
//
// ------------------------------- Register RTree: USART1_CR2 -----------------------------------
// SVD Line: 9605
// SFDITEM_REG__USART1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40013810) Control register 2
// ( (unsigned int)((USART1_CR2 >> 0) & 0xFFFFFFFF), ((USART1_CR2 = (USART1_CR2 & ~(0x2007F6FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2007F6F) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR2_ADD
// - SFDITEM_FIELD__USART1_CR2_LBDL
// - SFDITEM_FIELD__USART1_CR2_LBDIE
// - SFDITEM_FIELD__USART1_CR2_LBCL
// - SFDITEM_FIELD__USART1_CR2_CPHA
// - SFDITEM_FIELD__USART1_CR2_CPOL
// - SFDITEM_FIELD__USART1_CR2_CLKEN
// - SFDITEM_FIELD__USART1_CR2_STOP
// - SFDITEM_FIELD__USART1_CR2_LINEN
// - SFDITEM_FIELD__USART1_CR2_RTOEN
//
//
// ---------------------------- Register Item Address: USART1_CR3 -------------------------------
// SVD Line: 9662
unsigned int USART1_CR3 __AT (0x40013814);
// ------------------------------- Field Item: USART1_CR3_EIE -----------------------------------
// SVD Line: 9667
// - SFDITEM_FIELD__USART1_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40013814) error int enable
//
// ( (unsigned int) USART1_CR3 )
// EIE
//
//
//
// ------------------------------ Field Item: USART1_CR3_HDSEL ----------------------------------
// SVD Line: 9672
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40013814) hdsel
//
// ( (unsigned int) USART1_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: USART1_CR3_DMAR ----------------------------------
// SVD Line: 9677
// - SFDITEM_FIELD__USART1_CR3_DMAR
// DMAR
//
// [Bit 6] RW (@ 0x40013814) dma rx enable
//
// ( (unsigned int) USART1_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: USART1_CR3_DMAT ----------------------------------
// SVD Line: 9682
// - SFDITEM_FIELD__USART1_CR3_DMAT
// DMAT
//
// [Bit 7] RW (@ 0x40013814) dma tx enable
//
// ( (unsigned int) USART1_CR3 )
// DMAT
//
//
//
// ------------------------------- Field Item: USART1_CR3_RTSE ----------------------------------
// SVD Line: 9687
// - SFDITEM_FIELD__USART1_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40013814) rts enable
//
// ( (unsigned int) USART1_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: USART1_CR3_CTSE ----------------------------------
// SVD Line: 9692
// - SFDITEM_FIELD__USART1_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40013814) cts enable
//
// ( (unsigned int) USART1_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: USART1_CR3_CTSIE ----------------------------------
// SVD Line: 9697
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40013814) cts int enable
//
// ( (unsigned int) USART1_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: USART1_CR3_OVER8 ----------------------------------
// SVD Line: 9702
// - SFDITEM_FIELD__USART1_CR3_OVER8
// OVER8
//
// [Bit 11] RW (@ 0x40013814) oversampling
//
// ( (unsigned int) USART1_CR3 )
// OVER8
//
//
//
// ------------------------------ Field Item: USART1_CR3_ABREN ----------------------------------
// SVD Line: 9707
// - SFDITEM_FIELD__USART1_CR3_ABREN
// ABREN
//
// [Bit 12] RW (@ 0x40013814) autobaud enable
//
// ( (unsigned int) USART1_CR3 )
// ABREN
//
//
//
// ------------------------------ Field Item: USART1_CR3_ABRMOD ---------------------------------
// SVD Line: 9712
// - SFDITEM_FIELD__USART1_CR3_ABRMOD
// ABRMOD
//
// [Bits 14..13] RW (@ 0x40013814) auto baud mod
//
// ( (unsigned char)((USART1_CR3 >> 13) & 0x3), ((USART1_CR3 = (USART1_CR3 & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ------------------------------ Field Item: USART1_CR3_RTOIE ----------------------------------
// SVD Line: 9717
// - SFDITEM_FIELD__USART1_CR3_RTOIE
// RTOIE
//
// [Bit 29] RW (@ 0x40013814) rto int enable
//
// ( (unsigned int) USART1_CR3 )
// RTOIE
//
//
//
// ----------------------------- Field Item: USART1_CR3_TXLSEIE ---------------------------------
// SVD Line: 9722
// - SFDITEM_FIELD__USART1_CR3_TXLSEIE
// TXLSEIE
//
// [Bit 31] RW (@ 0x40013814) tx register empty int enable
//
// ( (unsigned int) USART1_CR3 )
// TXLSEIE
//
//
//
// ------------------------------- Register RTree: USART1_CR3 -----------------------------------
// SVD Line: 9662
// SFDITEM_REG__USART1_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40013814) Control register 3
// ( (unsigned int)((USART1_CR3 >> 0) & 0xFFFFFFFF), ((USART1_CR3 = (USART1_CR3 & ~(0xA0007FC9UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA0007FC9) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_CR3_EIE
// - SFDITEM_FIELD__USART1_CR3_HDSEL
// - SFDITEM_FIELD__USART1_CR3_DMAR
// - SFDITEM_FIELD__USART1_CR3_DMAT
// - SFDITEM_FIELD__USART1_CR3_RTSE
// - SFDITEM_FIELD__USART1_CR3_CTSE
// - SFDITEM_FIELD__USART1_CR3_CTSIE
// - SFDITEM_FIELD__USART1_CR3_OVER8
// - SFDITEM_FIELD__USART1_CR3_ABREN
// - SFDITEM_FIELD__USART1_CR3_ABRMOD
// - SFDITEM_FIELD__USART1_CR3_RTOIE
// - SFDITEM_FIELD__USART1_CR3_TXLSEIE
//
//
// --------------------------- Register Item Address: USART1_RTOR -------------------------------
// SVD Line: 9729
unsigned int USART1_RTOR __AT (0x4001381C);
// ------------------------------- Field Item: USART1_RTOR_RTO ----------------------------------
// SVD Line: 9733
// - SFDITEM_FIELD__USART1_RTOR_RTO
// RTO
//
// [Bits 23..0] RW (@ 0x4001381C) receive timeout
//
// ( (unsigned int)((USART1_RTOR >> 0) & 0xFFFFFF), ((USART1_RTOR = (USART1_RTOR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART1_RTOR ----------------------------------
// SVD Line: 9729
// SFDITEM_REG__USART1_RTOR
// RTOR
//
// [Bits 31..0] RW (@ 0x4001381C) RTOR
// ( (unsigned int)((USART1_RTOR >> 0) & 0xFFFFFFFF), ((USART1_RTOR = (USART1_RTOR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART1_RTOR_RTO
//
//
// --------------------------------- Peripheral View: USART1 ------------------------------------
// SVD Line: 9368
// USART1
// USART1
// - SFDITEM_REG__USART1_SR
// - SFDITEM_REG__USART1_DR
// - SFDITEM_REG__USART1_BRR
// - SFDITEM_REG__USART1_CR1
// - SFDITEM_REG__USART1_CR2
// - SFDITEM_REG__USART1_CR3
// - SFDITEM_REG__USART1_RTOR
//
//
// ---------------------------- Register Item Address: USART2_SR --------------------------------
// SVD Line: 9384
unsigned int USART2_SR __AT (0x40004400);
// -------------------------------- Field Item: USART2_SR_PE ------------------------------------
// SVD Line: 9389
// - SFDITEM_FIELD__USART2_SR_PE
// PE
//
// [Bit 0] RO (@ 0x40004400) Parity error
//
// ( (unsigned int) USART2_SR )
// PE
//
//
//
// -------------------------------- Field Item: USART2_SR_FE ------------------------------------
// SVD Line: 9395
// - SFDITEM_FIELD__USART2_SR_FE
// FE
//
// [Bit 1] RO (@ 0x40004400) Framing error
//
// ( (unsigned int) USART2_SR )
// FE
//
//
//
// -------------------------------- Field Item: USART2_SR_NE ------------------------------------
// SVD Line: 9401
// - SFDITEM_FIELD__USART2_SR_NE
// NE
//
// [Bit 2] RO (@ 0x40004400) Noise error flag
//
// ( (unsigned int) USART2_SR )
// NE
//
//
//
// -------------------------------- Field Item: USART2_SR_ORE -----------------------------------
// SVD Line: 9407
// - SFDITEM_FIELD__USART2_SR_ORE
// ORE
//
// [Bit 3] RO (@ 0x40004400) overrun error
//
// ( (unsigned int) USART2_SR )
// ORE
//
//
//
// ------------------------------- Field Item: USART2_SR_IDLE -----------------------------------
// SVD Line: 9413
// - SFDITEM_FIELD__USART2_SR_IDLE
// IDLE
//
// [Bit 4] RO (@ 0x40004400) idle
//
// ( (unsigned int) USART2_SR )
// IDLE
//
//
//
// ------------------------------- Field Item: USART2_SR_RXNE -----------------------------------
// SVD Line: 9419
// - SFDITEM_FIELD__USART2_SR_RXNE
// RXNE
//
// [Bit 5] RW (@ 0x40004400) Read data register not empty
//
// ( (unsigned int) USART2_SR )
// RXNE
//
//
//
// -------------------------------- Field Item: USART2_SR_TC ------------------------------------
// SVD Line: 9424
// - SFDITEM_FIELD__USART2_SR_TC
// TC
//
// [Bit 6] RW (@ 0x40004400) Transmission complete
//
// ( (unsigned int) USART2_SR )
// TC
//
//
//
// -------------------------------- Field Item: USART2_SR_TXE -----------------------------------
// SVD Line: 9429
// - SFDITEM_FIELD__USART2_SR_TXE
// TXE
//
// [Bit 7] RO (@ 0x40004400) Transmit data register empty
//
// ( (unsigned int) USART2_SR )
// TXE
//
//
//
// -------------------------------- Field Item: USART2_SR_LBD -----------------------------------
// SVD Line: 9435
// - SFDITEM_FIELD__USART2_SR_LBD
// LBD
//
// [Bit 8] RW (@ 0x40004400) LIN break detection flag
//
// ( (unsigned int) USART2_SR )
// LBD
//
//
//
// -------------------------------- Field Item: USART2_SR_CTS -----------------------------------
// SVD Line: 9440
// - SFDITEM_FIELD__USART2_SR_CTS
// CTS
//
// [Bit 9] RW (@ 0x40004400) cts flag
//
// ( (unsigned int) USART2_SR )
// CTS
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRF -----------------------------------
// SVD Line: 9445
// - SFDITEM_FIELD__USART2_SR_ABRF
// ABRF
//
// [Bit 10] RO (@ 0x40004400) auto baud rate flag
//
// ( (unsigned int) USART2_SR )
// ABRF
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRE -----------------------------------
// SVD Line: 9451
// - SFDITEM_FIELD__USART2_SR_ABRE
// ABRE
//
// [Bit 11] RO (@ 0x40004400) auto baud rateerror
//
// ( (unsigned int) USART2_SR )
// ABRE
//
//
//
// ------------------------------- Field Item: USART2_SR_ABRRQ ----------------------------------
// SVD Line: 9457
// - SFDITEM_FIELD__USART2_SR_ABRRQ
// ABRRQ
//
// [Bit 12] RO (@ 0x40004400) auto baud rate req
//
// ( (unsigned int) USART2_SR )
// ABRRQ
//
//
//
// ------------------------------- Field Item: USART2_SR_RTOF -----------------------------------
// SVD Line: 9463
// - SFDITEM_FIELD__USART2_SR_RTOF
// RTOF
//
// [Bit 19] RW (@ 0x40004400) rto flag
//
// ( (unsigned int) USART2_SR )
// RTOF
//
//
//
// ------------------------------- Field Item: USART2_SR_TXPE -----------------------------------
// SVD Line: 9468
// - SFDITEM_FIELD__USART2_SR_TXPE
// TXPE
//
// [Bit 20] RW (@ 0x40004400) TXPE
//
// ( (unsigned int) USART2_SR )
// TXPE
//
//
//
// ------------------------------ Field Item: USART2_SR_RXBUSY ----------------------------------
// SVD Line: 9472
// - SFDITEM_FIELD__USART2_SR_RXBUSY
// RXBUSY
//
// [Bit 21] RO (@ 0x40004400) RXBUSY
//
// ( (unsigned int) USART2_SR )
// RXBUSY
//
//
//
// ------------------------------ Field Item: USART2_SR_TXBUSY ----------------------------------
// SVD Line: 9477
// - SFDITEM_FIELD__USART2_SR_TXBUSY
// TXBUSY
//
// [Bit 22] RO (@ 0x40004400) TXBUSY
//
// ( (unsigned int) USART2_SR )
// TXBUSY
//
//
//
// -------------------------------- Register RTree: USART2_SR -----------------------------------
// SVD Line: 9384
// SFDITEM_REG__USART2_SR
// SR
//
// [Bits 31..0] RW (@ 0x40004400) Status register
// ( (unsigned int)((USART2_SR >> 0) & 0xFFFFFFFF), ((USART2_SR = (USART2_SR & ~(0x180360UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x180360) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_SR_PE
// - SFDITEM_FIELD__USART2_SR_FE
// - SFDITEM_FIELD__USART2_SR_NE
// - SFDITEM_FIELD__USART2_SR_ORE
// - SFDITEM_FIELD__USART2_SR_IDLE
// - SFDITEM_FIELD__USART2_SR_RXNE
// - SFDITEM_FIELD__USART2_SR_TC
// - SFDITEM_FIELD__USART2_SR_TXE
// - SFDITEM_FIELD__USART2_SR_LBD
// - SFDITEM_FIELD__USART2_SR_CTS
// - SFDITEM_FIELD__USART2_SR_ABRF
// - SFDITEM_FIELD__USART2_SR_ABRE
// - SFDITEM_FIELD__USART2_SR_ABRRQ
// - SFDITEM_FIELD__USART2_SR_RTOF
// - SFDITEM_FIELD__USART2_SR_TXPE
// - SFDITEM_FIELD__USART2_SR_RXBUSY
// - SFDITEM_FIELD__USART2_SR_TXBUSY
//
//
// ---------------------------- Register Item Address: USART2_DR --------------------------------
// SVD Line: 9484
unsigned int USART2_DR __AT (0x40004404);
// -------------------------------- Field Item: USART2_DR_DR ------------------------------------
// SVD Line: 9489
// - SFDITEM_FIELD__USART2_DR_DR
// DR
//
// [Bits 8..0] RW (@ 0x40004404) dr
//
// ( (unsigned short)((USART2_DR >> 0) & 0x1FF), ((USART2_DR = (USART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: USART2_DR -----------------------------------
// SVD Line: 9484
// SFDITEM_REG__USART2_DR
// DR
//
// [Bits 31..0] RW (@ 0x40004404) Data register
// ( (unsigned int)((USART2_DR >> 0) & 0xFFFFFFFF), ((USART2_DR = (USART2_DR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_DR_DR
//
//
// ---------------------------- Register Item Address: USART2_BRR -------------------------------
// SVD Line: 9496
unsigned int USART2_BRR __AT (0x40004408);
// --------------------------- Field Item: USART2_BRR_DIV_FRACTION ------------------------------
// SVD Line: 9501
// - SFDITEM_FIELD__USART2_BRR_DIV_FRACTION
// DIV_FRACTION
//
// [Bits 3..0] RW (@ 0x40004408) DIV_Fraction
//
// ( (unsigned char)((USART2_BRR >> 0) & 0xF), ((USART2_BRR = (USART2_BRR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: USART2_BRR_DIV_MANTISSA ------------------------------
// SVD Line: 9506
// - SFDITEM_FIELD__USART2_BRR_DIV_MANTISSA
// DIV_MANTISSA
//
// [Bits 15..4] RW (@ 0x40004408) DIV_Mantissa
//
// ( (unsigned short)((USART2_BRR >> 4) & 0xFFF), ((USART2_BRR = (USART2_BRR & ~(0xFFFUL << 4 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 4 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART2_BRR -----------------------------------
// SVD Line: 9496
// SFDITEM_REG__USART2_BRR
// BRR
//
// [Bits 31..0] RW (@ 0x40004408) Baud rate register
// ( (unsigned int)((USART2_BRR >> 0) & 0xFFFFFFFF), ((USART2_BRR = (USART2_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_BRR_DIV_FRACTION
// - SFDITEM_FIELD__USART2_BRR_DIV_MANTISSA
//
//
// ---------------------------- Register Item Address: USART2_CR1 -------------------------------
// SVD Line: 9513
unsigned int USART2_CR1 __AT (0x4000440C);
// ------------------------------- Field Item: USART2_CR1_SBK -----------------------------------
// SVD Line: 9518
// - SFDITEM_FIELD__USART2_CR1_SBK
// SBK
//
// [Bit 0] RW (@ 0x4000440C) Send break
//
// ( (unsigned int) USART2_CR1 )
// SBK
//
//
//
// ------------------------------- Field Item: USART2_CR1_RWU -----------------------------------
// SVD Line: 9523
// - SFDITEM_FIELD__USART2_CR1_RWU
// RWU
//
// [Bit 1] RW (@ 0x4000440C) Receiver wakeup
//
// ( (unsigned int) USART2_CR1 )
// RWU
//
//
//
// -------------------------------- Field Item: USART2_CR1_RE -----------------------------------
// SVD Line: 9528
// - SFDITEM_FIELD__USART2_CR1_RE
// RE
//
// [Bit 2] RW (@ 0x4000440C) Receiver enable
//
// ( (unsigned int) USART2_CR1 )
// RE
//
//
//
// -------------------------------- Field Item: USART2_CR1_TE -----------------------------------
// SVD Line: 9533
// - SFDITEM_FIELD__USART2_CR1_TE
// TE
//
// [Bit 3] RW (@ 0x4000440C) Transmitter enable
//
// ( (unsigned int) USART2_CR1 )
// TE
//
//
//
// ------------------------------ Field Item: USART2_CR1_IDLEIE ---------------------------------
// SVD Line: 9538
// - SFDITEM_FIELD__USART2_CR1_IDLEIE
// IDLEIE
//
// [Bit 4] RW (@ 0x4000440C) IDLE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// IDLEIE
//
//
//
// ------------------------------ Field Item: USART2_CR1_RXNEIE ---------------------------------
// SVD Line: 9543
// - SFDITEM_FIELD__USART2_CR1_RXNEIE
// RXNEIE
//
// [Bit 5] RW (@ 0x4000440C) RXNE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// RXNEIE
//
//
//
// ------------------------------- Field Item: USART2_CR1_TCIE ----------------------------------
// SVD Line: 9548
// - SFDITEM_FIELD__USART2_CR1_TCIE
// TCIE
//
// [Bit 6] RW (@ 0x4000440C) send complete int enable
//
// ( (unsigned int) USART2_CR1 )
// TCIE
//
//
//
// ------------------------------ Field Item: USART2_CR1_TXEIE ----------------------------------
// SVD Line: 9553
// - SFDITEM_FIELD__USART2_CR1_TXEIE
// TXEIE
//
// [Bit 7] RW (@ 0x4000440C) txe
//
// ( (unsigned int) USART2_CR1 )
// TXEIE
//
//
//
// ------------------------------- Field Item: USART2_CR1_PEIE ----------------------------------
// SVD Line: 9558
// - SFDITEM_FIELD__USART2_CR1_PEIE
// PEIE
//
// [Bit 8] RW (@ 0x4000440C) PE interrupt enable
//
// ( (unsigned int) USART2_CR1 )
// PEIE
//
//
//
// -------------------------------- Field Item: USART2_CR1_PS -----------------------------------
// SVD Line: 9563
// - SFDITEM_FIELD__USART2_CR1_PS
// PS
//
// [Bit 9] RW (@ 0x4000440C) Parity selection
//
// ( (unsigned int) USART2_CR1 )
// PS
//
//
//
// ------------------------------- Field Item: USART2_CR1_PCE -----------------------------------
// SVD Line: 9568
// - SFDITEM_FIELD__USART2_CR1_PCE
// PCE
//
// [Bit 10] RW (@ 0x4000440C) Parity control enable
//
// ( (unsigned int) USART2_CR1 )
// PCE
//
//
//
// ------------------------------- Field Item: USART2_CR1_WAKE ----------------------------------
// SVD Line: 9573
// - SFDITEM_FIELD__USART2_CR1_WAKE
// WAKE
//
// [Bit 11] RW (@ 0x4000440C) Wakeup method
//
// ( (unsigned int) USART2_CR1 )
// WAKE
//
//
//
// -------------------------------- Field Item: USART2_CR1_M ------------------------------------
// SVD Line: 9578
// - SFDITEM_FIELD__USART2_CR1_M
// M
//
// [Bit 12] RW (@ 0x4000440C) word length
//
// ( (unsigned int) USART2_CR1 )
// M
//
//
//
// -------------------------------- Field Item: USART2_CR1_UE -----------------------------------
// SVD Line: 9583
// - SFDITEM_FIELD__USART2_CR1_UE
// UE
//
// [Bit 13] RW (@ 0x4000440C) uesart enable
//
// ( (unsigned int) USART2_CR1 )
// UE
//
//
//
// ----------------------------- Field Item: USART2_CR1_MSBFIRST --------------------------------
// SVD Line: 9588
// - SFDITEM_FIELD__USART2_CR1_MSBFIRST
// MSBFIRST
//
// [Bit 15] RW (@ 0x4000440C) msbfirst
//
// ( (unsigned int) USART2_CR1 )
// MSBFIRST
//
//
//
// ------------------------------- Field Item: USART2_CR1_SWAP ----------------------------------
// SVD Line: 9593
// - SFDITEM_FIELD__USART2_CR1_SWAP
// SWAP
//
// [Bit 18] RW (@ 0x4000440C) swap
//
// ( (unsigned int) USART2_CR1 )
// SWAP
//
//
//
// ----------------------------- Field Item: USART2_CR1_DATAINV ---------------------------------
// SVD Line: 9598
// - SFDITEM_FIELD__USART2_CR1_DATAINV
// DATAINV
//
// [Bit 27] RW (@ 0x4000440C) data inverse
//
// ( (unsigned int) USART2_CR1 )
// DATAINV
//
//
//
// ------------------------------- Register RTree: USART2_CR1 -----------------------------------
// SVD Line: 9513
// SFDITEM_REG__USART2_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x4000440C) Control register 1
// ( (unsigned int)((USART2_CR1 >> 0) & 0xFFFFFFFF), ((USART2_CR1 = (USART2_CR1 & ~(0x804BFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x804BFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR1_SBK
// - SFDITEM_FIELD__USART2_CR1_RWU
// - SFDITEM_FIELD__USART2_CR1_RE
// - SFDITEM_FIELD__USART2_CR1_TE
// - SFDITEM_FIELD__USART2_CR1_IDLEIE
// - SFDITEM_FIELD__USART2_CR1_RXNEIE
// - SFDITEM_FIELD__USART2_CR1_TCIE
// - SFDITEM_FIELD__USART2_CR1_TXEIE
// - SFDITEM_FIELD__USART2_CR1_PEIE
// - SFDITEM_FIELD__USART2_CR1_PS
// - SFDITEM_FIELD__USART2_CR1_PCE
// - SFDITEM_FIELD__USART2_CR1_WAKE
// - SFDITEM_FIELD__USART2_CR1_M
// - SFDITEM_FIELD__USART2_CR1_UE
// - SFDITEM_FIELD__USART2_CR1_MSBFIRST
// - SFDITEM_FIELD__USART2_CR1_SWAP
// - SFDITEM_FIELD__USART2_CR1_DATAINV
//
//
// ---------------------------- Register Item Address: USART2_CR2 -------------------------------
// SVD Line: 9605
unsigned int USART2_CR2 __AT (0x40004410);
// ------------------------------- Field Item: USART2_CR2_ADD -----------------------------------
// SVD Line: 9610
// - SFDITEM_FIELD__USART2_CR2_ADD
// ADD
//
// [Bits 3..0] RW (@ 0x40004410) mute addr
//
// ( (unsigned char)((USART2_CR2 >> 0) & 0xF), ((USART2_CR2 = (USART2_CR2 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: USART2_CR2_LBDL ----------------------------------
// SVD Line: 9615
// - SFDITEM_FIELD__USART2_CR2_LBDL
// LBDL
//
// [Bit 5] RW (@ 0x40004410) LIN break detection length
//
// ( (unsigned int) USART2_CR2 )
// LBDL
//
//
//
// ------------------------------ Field Item: USART2_CR2_LBDIE ----------------------------------
// SVD Line: 9620
// - SFDITEM_FIELD__USART2_CR2_LBDIE
// LBDIE
//
// [Bit 6] RW (@ 0x40004410) lin break enable
//
// ( (unsigned int) USART2_CR2 )
// LBDIE
//
//
//
// ------------------------------- Field Item: USART2_CR2_LBCL ----------------------------------
// SVD Line: 9625
// - SFDITEM_FIELD__USART2_CR2_LBCL
// LBCL
//
// [Bit 8] RW (@ 0x40004410) lbcl
//
// ( (unsigned int) USART2_CR2 )
// LBCL
//
//
//
// ------------------------------- Field Item: USART2_CR2_CPHA ----------------------------------
// SVD Line: 9630
// - SFDITEM_FIELD__USART2_CR2_CPHA
// CPHA
//
// [Bit 9] RW (@ 0x40004410) cpha
//
// ( (unsigned int) USART2_CR2 )
// CPHA
//
//
//
// ------------------------------- Field Item: USART2_CR2_CPOL ----------------------------------
// SVD Line: 9635
// - SFDITEM_FIELD__USART2_CR2_CPOL
// CPOL
//
// [Bit 10] RW (@ 0x40004410) cpol
//
// ( (unsigned int) USART2_CR2 )
// CPOL
//
//
//
// ------------------------------ Field Item: USART2_CR2_CLKEN ----------------------------------
// SVD Line: 9640
// - SFDITEM_FIELD__USART2_CR2_CLKEN
// CLKEN
//
// [Bit 11] RW (@ 0x40004410) clk en
//
// ( (unsigned int) USART2_CR2 )
// CLKEN
//
//
//
// ------------------------------- Field Item: USART2_CR2_STOP ----------------------------------
// SVD Line: 9645
// - SFDITEM_FIELD__USART2_CR2_STOP
// STOP
//
// [Bits 13..12] RW (@ 0x40004410) stop bit
//
// ( (unsigned char)((USART2_CR2 >> 12) & 0x3), ((USART2_CR2 = (USART2_CR2 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: USART2_CR2_LINEN ----------------------------------
// SVD Line: 9650
// - SFDITEM_FIELD__USART2_CR2_LINEN
// LINEN
//
// [Bit 14] RW (@ 0x40004410) lin enable
//
// ( (unsigned int) USART2_CR2 )
// LINEN
//
//
//
// ------------------------------ Field Item: USART2_CR2_RTOEN ----------------------------------
// SVD Line: 9655
// - SFDITEM_FIELD__USART2_CR2_RTOEN
// RTOEN
//
// [Bit 25] RW (@ 0x40004410) Receiver timeout enable
//
// ( (unsigned int) USART2_CR2 )
// RTOEN
//
//
//
// ------------------------------- Register RTree: USART2_CR2 -----------------------------------
// SVD Line: 9605
// SFDITEM_REG__USART2_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40004410) Control register 2
// ( (unsigned int)((USART2_CR2 >> 0) & 0xFFFFFFFF), ((USART2_CR2 = (USART2_CR2 & ~(0x2007F6FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x2007F6F) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR2_ADD
// - SFDITEM_FIELD__USART2_CR2_LBDL
// - SFDITEM_FIELD__USART2_CR2_LBDIE
// - SFDITEM_FIELD__USART2_CR2_LBCL
// - SFDITEM_FIELD__USART2_CR2_CPHA
// - SFDITEM_FIELD__USART2_CR2_CPOL
// - SFDITEM_FIELD__USART2_CR2_CLKEN
// - SFDITEM_FIELD__USART2_CR2_STOP
// - SFDITEM_FIELD__USART2_CR2_LINEN
// - SFDITEM_FIELD__USART2_CR2_RTOEN
//
//
// ---------------------------- Register Item Address: USART2_CR3 -------------------------------
// SVD Line: 9662
unsigned int USART2_CR3 __AT (0x40004414);
// ------------------------------- Field Item: USART2_CR3_EIE -----------------------------------
// SVD Line: 9667
// - SFDITEM_FIELD__USART2_CR3_EIE
// EIE
//
// [Bit 0] RW (@ 0x40004414) error int enable
//
// ( (unsigned int) USART2_CR3 )
// EIE
//
//
//
// ------------------------------ Field Item: USART2_CR3_HDSEL ----------------------------------
// SVD Line: 9672
// - SFDITEM_FIELD__USART2_CR3_HDSEL
// HDSEL
//
// [Bit 3] RW (@ 0x40004414) hdsel
//
// ( (unsigned int) USART2_CR3 )
// HDSEL
//
//
//
// ------------------------------- Field Item: USART2_CR3_DMAR ----------------------------------
// SVD Line: 9677
// - SFDITEM_FIELD__USART2_CR3_DMAR
// DMAR
//
// [Bit 6] RW (@ 0x40004414) dma rx enable
//
// ( (unsigned int) USART2_CR3 )
// DMAR
//
//
//
// ------------------------------- Field Item: USART2_CR3_DMAT ----------------------------------
// SVD Line: 9682
// - SFDITEM_FIELD__USART2_CR3_DMAT
// DMAT
//
// [Bit 7] RW (@ 0x40004414) dma tx enable
//
// ( (unsigned int) USART2_CR3 )
// DMAT
//
//
//
// ------------------------------- Field Item: USART2_CR3_RTSE ----------------------------------
// SVD Line: 9687
// - SFDITEM_FIELD__USART2_CR3_RTSE
// RTSE
//
// [Bit 8] RW (@ 0x40004414) rts enable
//
// ( (unsigned int) USART2_CR3 )
// RTSE
//
//
//
// ------------------------------- Field Item: USART2_CR3_CTSE ----------------------------------
// SVD Line: 9692
// - SFDITEM_FIELD__USART2_CR3_CTSE
// CTSE
//
// [Bit 9] RW (@ 0x40004414) cts enable
//
// ( (unsigned int) USART2_CR3 )
// CTSE
//
//
//
// ------------------------------ Field Item: USART2_CR3_CTSIE ----------------------------------
// SVD Line: 9697
// - SFDITEM_FIELD__USART2_CR3_CTSIE
// CTSIE
//
// [Bit 10] RW (@ 0x40004414) cts int enable
//
// ( (unsigned int) USART2_CR3 )
// CTSIE
//
//
//
// ------------------------------ Field Item: USART2_CR3_OVER8 ----------------------------------
// SVD Line: 9702
// - SFDITEM_FIELD__USART2_CR3_OVER8
// OVER8
//
// [Bit 11] RW (@ 0x40004414) oversampling
//
// ( (unsigned int) USART2_CR3 )
// OVER8
//
//
//
// ------------------------------ Field Item: USART2_CR3_ABREN ----------------------------------
// SVD Line: 9707
// - SFDITEM_FIELD__USART2_CR3_ABREN
// ABREN
//
// [Bit 12] RW (@ 0x40004414) autobaud enable
//
// ( (unsigned int) USART2_CR3 )
// ABREN
//
//
//
// ------------------------------ Field Item: USART2_CR3_ABRMOD ---------------------------------
// SVD Line: 9712
// - SFDITEM_FIELD__USART2_CR3_ABRMOD
// ABRMOD
//
// [Bits 14..13] RW (@ 0x40004414) auto baud mod
//
// ( (unsigned char)((USART2_CR3 >> 13) & 0x3), ((USART2_CR3 = (USART2_CR3 & ~(0x3UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 13 ) ) ))
//
//
//
// ------------------------------ Field Item: USART2_CR3_RTOIE ----------------------------------
// SVD Line: 9717
// - SFDITEM_FIELD__USART2_CR3_RTOIE
// RTOIE
//
// [Bit 29] RW (@ 0x40004414) rto int enable
//
// ( (unsigned int) USART2_CR3 )
// RTOIE
//
//
//
// ----------------------------- Field Item: USART2_CR3_TXLSEIE ---------------------------------
// SVD Line: 9722
// - SFDITEM_FIELD__USART2_CR3_TXLSEIE
// TXLSEIE
//
// [Bit 31] RW (@ 0x40004414) tx register empty int enable
//
// ( (unsigned int) USART2_CR3 )
// TXLSEIE
//
//
//
// ------------------------------- Register RTree: USART2_CR3 -----------------------------------
// SVD Line: 9662
// SFDITEM_REG__USART2_CR3
// CR3
//
// [Bits 31..0] RW (@ 0x40004414) Control register 3
// ( (unsigned int)((USART2_CR3 >> 0) & 0xFFFFFFFF), ((USART2_CR3 = (USART2_CR3 & ~(0xA0007FC9UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xA0007FC9) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_CR3_EIE
// - SFDITEM_FIELD__USART2_CR3_HDSEL
// - SFDITEM_FIELD__USART2_CR3_DMAR
// - SFDITEM_FIELD__USART2_CR3_DMAT
// - SFDITEM_FIELD__USART2_CR3_RTSE
// - SFDITEM_FIELD__USART2_CR3_CTSE
// - SFDITEM_FIELD__USART2_CR3_CTSIE
// - SFDITEM_FIELD__USART2_CR3_OVER8
// - SFDITEM_FIELD__USART2_CR3_ABREN
// - SFDITEM_FIELD__USART2_CR3_ABRMOD
// - SFDITEM_FIELD__USART2_CR3_RTOIE
// - SFDITEM_FIELD__USART2_CR3_TXLSEIE
//
//
// --------------------------- Register Item Address: USART2_RTOR -------------------------------
// SVD Line: 9729
unsigned int USART2_RTOR __AT (0x4000441C);
// ------------------------------- Field Item: USART2_RTOR_RTO ----------------------------------
// SVD Line: 9733
// - SFDITEM_FIELD__USART2_RTOR_RTO
// RTO
//
// [Bits 23..0] RW (@ 0x4000441C) receive timeout
//
// ( (unsigned int)((USART2_RTOR >> 0) & 0xFFFFFF), ((USART2_RTOR = (USART2_RTOR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: USART2_RTOR ----------------------------------
// SVD Line: 9729
// SFDITEM_REG__USART2_RTOR
// RTOR
//
// [Bits 31..0] RW (@ 0x4000441C) RTOR
// ( (unsigned int)((USART2_RTOR >> 0) & 0xFFFFFFFF), ((USART2_RTOR = (USART2_RTOR & ~(0xFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__USART2_RTOR_RTO
//
//
// --------------------------------- Peripheral View: USART2 ------------------------------------
// SVD Line: 9742
// USART2
// USART2
// - SFDITEM_REG__USART2_SR
// - SFDITEM_REG__USART2_DR
// - SFDITEM_REG__USART2_BRR
// - SFDITEM_REG__USART2_CR1
// - SFDITEM_REG__USART2_CR2
// - SFDITEM_REG__USART2_CR3
// - SFDITEM_REG__USART2_RTOR
//
//
// ----------------------------- Register Item Address: WWDG_CR ---------------------------------
// SVD Line: 9766
unsigned int WWDG_CR __AT (0x40002C00);
// ---------------------------------- Field Item: WWDG_CR_T -------------------------------------
// SVD Line: 9771
// - SFDITEM_FIELD__WWDG_CR_T
// T
//
// [Bits 6..0] RW (@ 0x40002C00) wwdg counter bit
//
// ( (unsigned char)((WWDG_CR >> 0) & 0x7F), ((WWDG_CR = (WWDG_CR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: WWDG_CR_WDGA ------------------------------------
// SVD Line: 9776
// - SFDITEM_FIELD__WWDG_CR_WDGA
// WDGA
//
// [Bit 7] RW (@ 0x40002C00) WWDG Activation
//
// ( (unsigned int) WWDG_CR )
// WDGA
//
//
//
// --------------------------------- Register RTree: WWDG_CR ------------------------------------
// SVD Line: 9766
// SFDITEM_REG__WWDG_CR
// CR
//
// [Bits 31..0] RW (@ 0x40002C00) Control register (WWDG_CR)
// ( (unsigned int)((WWDG_CR >> 0) & 0xFFFFFFFF), ((WWDG_CR = (WWDG_CR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_CR_T
// - SFDITEM_FIELD__WWDG_CR_WDGA
//
//
// ----------------------------- Register Item Address: WWDG_CFR --------------------------------
// SVD Line: 9783
unsigned int WWDG_CFR __AT (0x40002C04);
// --------------------------------- Field Item: WWDG_CFR_W -------------------------------------
// SVD Line: 9788
// - SFDITEM_FIELD__WWDG_CFR_W
// W
//
// [Bits 6..0] RW (@ 0x40002C04) window value bit
//
// ( (unsigned char)((WWDG_CFR >> 0) & 0x7F), ((WWDG_CFR = (WWDG_CFR & ~(0x7FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7F) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: WWDG_CFR_WDGTB -----------------------------------
// SVD Line: 9793
// - SFDITEM_FIELD__WWDG_CFR_WDGTB
// WDGTB
//
// [Bits 8..7] RW (@ 0x40002C04) time base bit
//
// ( (unsigned char)((WWDG_CFR >> 7) & 0x3), ((WWDG_CFR = (WWDG_CFR & ~(0x3UL << 7 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 7 ) ) ))
//
//
//
// -------------------------------- Field Item: WWDG_CFR_EWI ------------------------------------
// SVD Line: 9798
// - SFDITEM_FIELD__WWDG_CFR_EWI
// EWI
//
// [Bit 9] RW (@ 0x40002C04) Early wakeup interrupt
//
// ( (unsigned int) WWDG_CFR )
// EWI
//
//
//
// -------------------------------- Register RTree: WWDG_CFR ------------------------------------
// SVD Line: 9783
// SFDITEM_REG__WWDG_CFR
// CFR
//
// [Bits 31..0] RW (@ 0x40002C04) Configuration register(WWDG_CFR)
// ( (unsigned int)((WWDG_CFR >> 0) & 0xFFFFFFFF), ((WWDG_CFR = (WWDG_CFR & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_CFR_W
// - SFDITEM_FIELD__WWDG_CFR_WDGTB
// - SFDITEM_FIELD__WWDG_CFR_EWI
//
//
// ----------------------------- Register Item Address: WWDG_SR ---------------------------------
// SVD Line: 9805
unsigned int WWDG_SR __AT (0x40002C08);
// -------------------------------- Field Item: WWDG_SR_EWIF ------------------------------------
// SVD Line: 9810
// - SFDITEM_FIELD__WWDG_SR_EWIF
// EWIF
//
// [Bit 0] RW (@ 0x40002C08) Early wakeup interrupt flag
//
// ( (unsigned int) WWDG_SR )
// EWIF
//
//
//
// --------------------------------- Register RTree: WWDG_SR ------------------------------------
// SVD Line: 9805
// SFDITEM_REG__WWDG_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002C08) Status register (WWDG_SR)
// ( (unsigned int)((WWDG_SR >> 0) & 0xFFFFFFFF), ((WWDG_SR = (WWDG_SR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__WWDG_SR_EWIF
//
//
// ---------------------------------- Peripheral View: WWDG -------------------------------------
// SVD Line: 9751
// WWDG
// WWDG
// - SFDITEM_REG__WWDG_CR
// - SFDITEM_REG__WWDG_CFR
// - SFDITEM_REG__WWDG_SR
//
//
// ----------------------------- IRQ Num definition: PY32F033xx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// -------------------------- PY32F033xx Specific Interrupt Numbers -----------------------------
// WWDG_IRQ
// WWDG
// Window WatchDog Interrupt
// 16
//
//
// PVD_IRQ
// PVD
// PVD Interrupt through EXTI Lines 16
// 17
//
//
// RTC_IRQ
// RTC
// RTC Interrupt through EXTI Lines 19
// 18
//
//
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 19
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 20
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 21
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 22
//
//
// EXTI4_15_IRQ
// EXTI4_15
// EXTI Line 4 to 15 Interrupt
// 23
//
//
// ADC_IRQ
// ADC
// ADC Interrupt
// 24
//
//
// DMA_Channel1_IRQ
// DMA_Channel1
// DMA Channel 1 Interrupt
// 25
//
//
// DMA_Channel2_IRQ
// DMA_Channel2
// DMA Channel 2 Interrupt
// 26
//
//
// DMA_Channel3_IRQ
// DMA_Channel3
// DMA Channel 3 Interrupt
// 27
//
//
// COMP1_2_IRQ
// COMP1_2
// COMP1 and 2 Interrupts
// 28
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 29
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 30
//
//
// TIM3_IRQ
// TIM3
// TIM3 global Interrupt
// 32
//
//
// LPTIM_IRQ
// LPTIM
// LPTIM global Interrupt
// 33
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupt
// 35
//
//
// TIM16_IRQ
// TIM16
// TIM16 global Interrupt
// 37
//
//
// TIM17_IRQ
// TIM17
// TIM17 global Interrupt
// 38
//
//
// I2C1_EV_IRQ
// I2C1_EV
// I2C1 Event global Interrupt
// 39
//
//
// I2C1_ER_IRQ
// I2C1_ER
// I2C1 Error global Interrupt
// 40
//
//
// SPI1_IRQ
// SPI1
// SPI1 global Interrupt
// 41
//
//
// SPI2_IRQ
// SPI2
// SPI2 global Interrupt
// 42
//
//
// USART1_IRQ
// USART1
// USART1 global Interrupt
// 43
//
//
// USART2_IRQ
// USART2
// USART2 global Interrupt
// 44
//
//
// LPUART_IRQ
// LPUART
// LPUART global Interrupt
// 45
//
//
// PY32F033xx_IRQTable
// PY32F033xx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// WWDG_IRQ
// PVD_IRQ
// RTC_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_15_IRQ
// ADC_IRQ
// DMA_Channel1_IRQ
// DMA_Channel2_IRQ
// DMA_Channel3_IRQ
// COMP1_2_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// TIM3_IRQ
// LPTIM_IRQ
// TIM14_IRQ
// TIM16_IRQ
// TIM17_IRQ
// I2C1_EV_IRQ
// I2C1_ER_IRQ
// SPI1_IRQ
// SPI2_IRQ
// USART1_IRQ
// USART2_IRQ
// LPUART_IRQ
//
// ------------------------------------ Menu: PY32F033xx ---------------------------------------
// SVD Line: 2
// ------------------------------ Peripheral Menu: 'PY32F033xx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// ADC
// ADC
//
//
// COMP
// COMP
//
//
// CRC
// CRC
//
//
// DBGMCU
// DBGMCU
//
//
// DMA
// DMA
//
//
// EXTI
// EXTI
//
//
// FLASH
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOF
//
//
// I2C
// I2C1
//
//
// IWDG
// IWDG
//
//
// LPTIM
// LPTIM
//
//
// LPUART
// LPUART
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// RTC
// RTC
//
//
// SPI
// SPI1
// SPI2
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM3
// TIM14
// TIM16
// TIM17
//
//
// UART
// UART1
// UART2
//
//
// USART
// USART1
// USART2
//
//
// WWDG
// WWDG
//
//