/*
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* @file E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F001xx.sfd
* @brief CMSIS-SVD SFD File
* @version 1.0.0
* @date Wed May 6 12:14:55 2026
* @note Generated by SVDConv V3.3.47
* from File 'E:/SVN/PT061/A15_MCU_tools/B01_PY_PACK/MDK/MDK Pack Source/MDK Pack F0 Series/01_Basic_Pack/Files/CMSIS/SVD/PY32F001xx.svd',
* last modified on Sat Oct 11 17:45:43 2025
*/
// ---------------------------- Register Item Address: COMP1_CSR --------------------------------
// SVD Line: 41
unsigned int COMP1_CSR __AT (0x40010200);
// -------------------------------- Field Item: COMP1_CSR_EN ------------------------------------
// SVD Line: 47
// - SFDITEM_FIELD__COMP1_CSR_EN
// EN
//
// [Bit 0] RW (@ 0x40010200) COMP enable bit
//
// ( (unsigned int) COMP1_CSR )
// EN
//
//
//
// ------------------------------ Field Item: COMP1_CSR_INNSEL ----------------------------------
// SVD Line: 52
// - SFDITEM_FIELD__COMP1_CSR_INNSEL
// INNSEL
//
// [Bit 5] RW (@ 0x40010200) desc INNSEL
//
// ( (unsigned int) COMP1_CSR )
// INNSEL
//
//
//
// ------------------------------ Field Item: COMP1_CSR_WINMODE ---------------------------------
// SVD Line: 57
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// WINMODE
//
// [Bit 11] RW (@ 0x40010200) Comparator non-inverting input selector for window mode
//
// ( (unsigned int) COMP1_CSR )
// WINMODE
//
//
//
// ----------------------------- Field Item: COMP1_CSR_POLARITY ---------------------------------
// SVD Line: 62
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010200) Comparator polarity selector
//
// ( (unsigned int) COMP1_CSR )
// POLARITY
//
//
//
// ------------------------------- Field Item: COMP1_CSR_VCDIV ----------------------------------
// SVD Line: 67
// - SFDITEM_FIELD__COMP1_CSR_VCDIV
// VCDIV
//
// [Bits 25..22] RW (@ 0x40010200) VCDIV
//
// ( (unsigned char)((COMP1_CSR >> 22) & 0xF), ((COMP1_CSR = (COMP1_CSR & ~(0xFUL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 22 ) ) ))
//
//
//
// ------------------------------- Field Item: COMP1_CSR_VCSEL ----------------------------------
// SVD Line: 72
// - SFDITEM_FIELD__COMP1_CSR_VCSEL
// VCSEL
//
// [Bit 27] RW (@ 0x40010200) VCSEL
//
// ( (unsigned int) COMP1_CSR )
// VCSEL
//
//
//
// ----------------------------- Field Item: COMP1_CSR_COMP_OUT ---------------------------------
// SVD Line: 77
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RW (@ 0x40010200) Comparator output status
//
// ( (unsigned int) COMP1_CSR )
// COMP_OUT
//
//
//
// -------------------------------- Register RTree: COMP1_CSR -----------------------------------
// SVD Line: 41
// SFDITEM_REG__COMP1_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010200) COMP control and status register
// ( (unsigned int)((COMP1_CSR >> 0) & 0xFFFFFFFF), ((COMP1_CSR = (COMP1_CSR & ~(0x4BC08821UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x4BC08821) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_CSR_EN
// - SFDITEM_FIELD__COMP1_CSR_INNSEL
// - SFDITEM_FIELD__COMP1_CSR_WINMODE
// - SFDITEM_FIELD__COMP1_CSR_POLARITY
// - SFDITEM_FIELD__COMP1_CSR_VCDIV
// - SFDITEM_FIELD__COMP1_CSR_VCSEL
// - SFDITEM_FIELD__COMP1_CSR_COMP_OUT
//
//
// ----------------------------- Register Item Address: COMP1_FR --------------------------------
// SVD Line: 84
unsigned int COMP1_FR __AT (0x40010204);
// ------------------------------- Field Item: COMP1_FR_FLTEN1 ----------------------------------
// SVD Line: 90
// - SFDITEM_FIELD__COMP1_FR_FLTEN1
// FLTEN1
//
// [Bit 0] RW (@ 0x40010204) Filter enable bit
//
// ( (unsigned int) COMP1_FR )
// FLTEN1
//
//
//
// ------------------------------ Field Item: COMP1_FR_FLTCNT1 ----------------------------------
// SVD Line: 95
// - SFDITEM_FIELD__COMP1_FR_FLTCNT1
// FLTCNT1
//
// [Bits 31..16] RW (@ 0x40010204) Comparator filter and counter
//
// ( (unsigned short)((COMP1_FR >> 16) & 0xFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP1_FR ------------------------------------
// SVD Line: 84
// SFDITEM_REG__COMP1_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010204) Comparator Filter register
// ( (unsigned int)((COMP1_FR >> 0) & 0xFFFFFFFF), ((COMP1_FR = (COMP1_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP1_FR_FLTEN1
// - SFDITEM_FIELD__COMP1_FR_FLTCNT1
//
//
// --------------------------------- Peripheral View: COMP1 -------------------------------------
// SVD Line: 25
// COMP1
// COMP1
// - SFDITEM_REG__COMP1_CSR
// - SFDITEM_REG__COMP1_FR
//
//
// ---------------------------- Register Item Address: COMP2_CSR --------------------------------
// SVD Line: 120
unsigned int COMP2_CSR __AT (0x40010210);
// -------------------------------- Field Item: COMP2_CSR_EN ------------------------------------
// SVD Line: 126
// - SFDITEM_FIELD__COMP2_CSR_EN
// EN
//
// [Bit 0] RW (@ 0x40010210) COMP enable bit
//
// ( (unsigned int) COMP2_CSR )
// EN
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INMSEL ----------------------------------
// SVD Line: 131
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// INMSEL
//
// [Bit 5] RW (@ 0x40010210) Comparator signal selector for inverting input INM
//
// ( (unsigned int) COMP2_CSR )
// INMSEL
//
//
//
// ------------------------------ Field Item: COMP2_CSR_INPSEL ----------------------------------
// SVD Line: 136
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// INPSEL
//
// [Bit 9] RW (@ 0x40010210) Comparator signal selector for non-inverting input
//
// ( (unsigned int) COMP2_CSR )
// INPSEL
//
//
//
// ----------------------------- Field Item: COMP2_CSR_POLARITY ---------------------------------
// SVD Line: 141
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// POLARITY
//
// [Bit 15] RW (@ 0x40010210) Comparator polarity selector
//
// ( (unsigned int) COMP2_CSR )
// POLARITY
//
//
//
// ----------------------------- Field Item: COMP2_CSR_COMP_OUT ---------------------------------
// SVD Line: 146
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
// COMP_OUT
//
// [Bit 30] RW (@ 0x40010210) Comparator output status
//
// ( (unsigned int) COMP2_CSR )
// COMP_OUT
//
//
//
// -------------------------------- Register RTree: COMP2_CSR -----------------------------------
// SVD Line: 120
// SFDITEM_REG__COMP2_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40010210) COMP control and status register
// ( (unsigned int)((COMP2_CSR >> 0) & 0xFFFFFFFF), ((COMP2_CSR = (COMP2_CSR & ~(0x40008221UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x40008221) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_CSR_EN
// - SFDITEM_FIELD__COMP2_CSR_INMSEL
// - SFDITEM_FIELD__COMP2_CSR_INPSEL
// - SFDITEM_FIELD__COMP2_CSR_POLARITY
// - SFDITEM_FIELD__COMP2_CSR_COMP_OUT
//
//
// ----------------------------- Register Item Address: COMP2_FR --------------------------------
// SVD Line: 153
unsigned int COMP2_FR __AT (0x40010214);
// ------------------------------- Field Item: COMP2_FR_FLTEN2 ----------------------------------
// SVD Line: 159
// - SFDITEM_FIELD__COMP2_FR_FLTEN2
// FLTEN2
//
// [Bit 0] RW (@ 0x40010214) Filter enable bit
//
// ( (unsigned int) COMP2_FR )
// FLTEN2
//
//
//
// ------------------------------ Field Item: COMP2_FR_FLTCNT2 ----------------------------------
// SVD Line: 164
// - SFDITEM_FIELD__COMP2_FR_FLTCNT2
// FLTCNT2
//
// [Bits 31..16] RW (@ 0x40010214) Comparator filter and counter
//
// ( (unsigned short)((COMP2_FR >> 16) & 0xFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: COMP2_FR ------------------------------------
// SVD Line: 153
// SFDITEM_REG__COMP2_FR
// FR
//
// [Bits 31..0] RW (@ 0x40010214) Comparator Filter register
// ( (unsigned int)((COMP2_FR >> 0) & 0xFFFFFFFF), ((COMP2_FR = (COMP2_FR & ~(0xFFFF0001UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF0001) << 0 ) ) ))
// - SFDITEM_FIELD__COMP2_FR_FLTEN2
// - SFDITEM_FIELD__COMP2_FR_FLTCNT2
//
//
// --------------------------------- Peripheral View: COMP2 -------------------------------------
// SVD Line: 104
// COMP2
// COMP2
// - SFDITEM_REG__COMP2_CSR
// - SFDITEM_REG__COMP2_FR
//
//
// ------------------------------ Register Item Address: CRC_DR ---------------------------------
// SVD Line: 184
unsigned int CRC_DR __AT (0x40023000);
// ---------------------------------- Field Item: CRC_DR_DR -------------------------------------
// SVD Line: 191
// - SFDITEM_FIELD__CRC_DR_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data Register
//
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_DR -------------------------------------
// SVD Line: 184
// SFDITEM_REG__CRC_DR
// DR
//
// [Bits 31..0] RW (@ 0x40023000) Data register
// ( (unsigned int)((CRC_DR >> 0) & 0xFFFFFFFF), ((CRC_DR = (CRC_DR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_DR_DR
//
//
// ----------------------------- Register Item Address: CRC_IDR ---------------------------------
// SVD Line: 198
unsigned int CRC_IDR __AT (0x40023004);
// --------------------------------- Field Item: CRC_IDR_IDR ------------------------------------
// SVD Line: 204
// - SFDITEM_FIELD__CRC_IDR_IDR
// IDR
//
// [Bits 7..0] RW (@ 0x40023004) Independent Data register
//
// ( (unsigned char)((CRC_IDR >> 0) & 0xFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: CRC_IDR ------------------------------------
// SVD Line: 198
// SFDITEM_REG__CRC_IDR
// IDR
//
// [Bits 31..0] RW (@ 0x40023004) Independent Data register
// ( (unsigned int)((CRC_IDR >> 0) & 0xFFFFFFFF), ((CRC_IDR = (CRC_IDR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_IDR_IDR
//
//
// ------------------------------ Register Item Address: CRC_CR ---------------------------------
// SVD Line: 211
unsigned int CRC_CR __AT (0x40023008);
// -------------------------------- Field Item: CRC_CR_RESET ------------------------------------
// SVD Line: 218
// - SFDITEM_FIELD__CRC_CR_RESET
// RESET
//
// [Bit 0] WO (@ 0x40023008) Reset bit
//
// ( (unsigned int) CRC_CR )
// RESET
//
//
//
// --------------------------------- Register RTree: CRC_CR -------------------------------------
// SVD Line: 211
// SFDITEM_REG__CRC_CR
// CR
//
// [Bits 31..0] WO (@ 0x40023008) Control register
// ( (unsigned int)((CRC_CR >> 0) & 0xFFFFFFFF), ((CRC_CR = (CRC_CR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__CRC_CR_RESET
//
//
// ---------------------------------- Peripheral View: CRC --------------------------------------
// SVD Line: 173
// CRC
// CRC
// - SFDITEM_REG__CRC_DR
// - SFDITEM_REG__CRC_IDR
// - SFDITEM_REG__CRC_CR
//
//
// -------------------------- Register Item Address: DBGMCU_IDCODE ------------------------------
// SVD Line: 238
unsigned int DBGMCU_IDCODE __AT (0x40015800);
// ---------------------------- Field Item: DBGMCU_IDCODE_REV_ID --------------------------------
// SVD Line: 245
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
// REV_ID
//
// [Bits 31..0] RO (@ 0x40015800) REV_ID
//
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
//
//
//
// ------------------------------ Register RTree: DBGMCU_IDCODE ---------------------------------
// SVD Line: 238
// SFDITEM_REG__DBGMCU_IDCODE
// IDCODE
//
// [Bits 31..0] RO (@ 0x40015800) MCU Device ID Code Register
// ( (unsigned int)((DBGMCU_IDCODE >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__DBGMCU_IDCODE_REV_ID
//
//
// ---------------------------- Register Item Address: DBGMCU_CR --------------------------------
// SVD Line: 252
unsigned int DBGMCU_CR __AT (0x40015804);
// ----------------------------- Field Item: DBGMCU_CR_DBG_SLEEP --------------------------------
// SVD Line: 258
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// DBG_SLEEP
//
// [Bit 0] RW (@ 0x40015804) Debug Sleep Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_SLEEP
//
//
//
// ----------------------------- Field Item: DBGMCU_CR_DBG_STOP ---------------------------------
// SVD Line: 263
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
// DBG_STOP
//
// [Bit 1] RW (@ 0x40015804) Debug Stop Mode
//
// ( (unsigned int) DBGMCU_CR )
// DBG_STOP
//
//
//
// -------------------------------- Register RTree: DBGMCU_CR -----------------------------------
// SVD Line: 252
// SFDITEM_REG__DBGMCU_CR
// CR
//
// [Bits 31..0] RW (@ 0x40015804) Debug MCU Configuration Register
// ( (unsigned int)((DBGMCU_CR >> 0) & 0xFFFFFFFF), ((DBGMCU_CR = (DBGMCU_CR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_CR_DBG_SLEEP
// - SFDITEM_FIELD__DBGMCU_CR_DBG_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ1 -----------------------------
// SVD Line: 270
unsigned int DBGMCU_APB_FZ1 __AT (0x40015808);
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_IWDG_STOP ----------------------------
// SVD Line: 276
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
// DBG_IWDG_STOP
//
// [Bit 12] RW (@ 0x40015808) Debug Independent Wachdog stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_IWDG_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ1_DBG_LPTIM_STOP ---------------------------
// SVD Line: 281
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
// DBG_LPTIM_STOP
//
// [Bit 31] RW (@ 0x40015808) Debug LPTIM stopped when Core ishalted
//
// ( (unsigned int) DBGMCU_APB_FZ1 )
// DBG_LPTIM_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ1 ---------------------------------
// SVD Line: 270
// SFDITEM_REG__DBGMCU_APB_FZ1
// APB_FZ1
//
// [Bits 31..0] RW (@ 0x40015808) APB Freeze Register1
// ( (unsigned int)((DBGMCU_APB_FZ1 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ1 = (DBGMCU_APB_FZ1 & ~(0x80001000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x80001000) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_IWDG_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ1_DBG_LPTIM_STOP
//
//
// -------------------------- Register Item Address: DBGMCU_APB_FZ2 -----------------------------
// SVD Line: 288
unsigned int DBGMCU_APB_FZ2 __AT (0x4001580C);
// ----------------------- Field Item: DBGMCU_APB_FZ2_DBG_TIMER1_STOP ---------------------------
// SVD Line: 294
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// DBG_TIMER1_STOP
//
// [Bit 11] RW (@ 0x4001580C) Debug Timer 1 stopped when Core ishalted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIMER1_STOP
//
//
//
// ------------------------ Field Item: DBGMCU_APB_FZ2_DBG_TIM14_STOP ---------------------------
// SVD Line: 299
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
// DBG_TIM14_STOP
//
// [Bit 15] RW (@ 0x4001580C) Debug TIM 14 stopped whenCore is halted
//
// ( (unsigned int) DBGMCU_APB_FZ2 )
// DBG_TIM14_STOP
//
//
//
// ----------------------------- Register RTree: DBGMCU_APB_FZ2 ---------------------------------
// SVD Line: 288
// SFDITEM_REG__DBGMCU_APB_FZ2
// APB_FZ2
//
// [Bits 31..0] RW (@ 0x4001580C) APB Freeze Register2
// ( (unsigned int)((DBGMCU_APB_FZ2 >> 0) & 0xFFFFFFFF), ((DBGMCU_APB_FZ2 = (DBGMCU_APB_FZ2 & ~(0x8800UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8800) << 0 ) ) ))
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIMER1_STOP
// - SFDITEM_FIELD__DBGMCU_APB_FZ2_DBG_TIM14_STOP
//
//
// --------------------------------- Peripheral View: DBGMCU ------------------------------------
// SVD Line: 227
// DBGMCU
// DBGMCU
// - SFDITEM_REG__DBGMCU_IDCODE
// - SFDITEM_REG__DBGMCU_CR
// - SFDITEM_REG__DBGMCU_APB_FZ1
// - SFDITEM_REG__DBGMCU_APB_FZ2
//
//
// ---------------------------- Register Item Address: EXTI_RTSR --------------------------------
// SVD Line: 334
unsigned int EXTI_RTSR __AT (0x40021800);
// -------------------------------- Field Item: EXTI_RTSR_RT0 -----------------------------------
// SVD Line: 340
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// RT0
//
// [Bit 0] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT0
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT1 -----------------------------------
// SVD Line: 345
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// RT1
//
// [Bit 1] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT1
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT2 -----------------------------------
// SVD Line: 350
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// RT2
//
// [Bit 2] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT2
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT3 -----------------------------------
// SVD Line: 355
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// RT3
//
// [Bit 3] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT3
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT4 -----------------------------------
// SVD Line: 360
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// RT4
//
// [Bit 4] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT4
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT5 -----------------------------------
// SVD Line: 365
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// RT5
//
// [Bit 5] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT5
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT6 -----------------------------------
// SVD Line: 370
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// RT6
//
// [Bit 6] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT6
//
//
//
// -------------------------------- Field Item: EXTI_RTSR_RT7 -----------------------------------
// SVD Line: 375
// - SFDITEM_FIELD__EXTI_RTSR_RT7
// RT7
//
// [Bit 7] RW (@ 0x40021800) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_RTSR )
// RT7
//
//
//
// -------------------------------- Register RTree: EXTI_RTSR -----------------------------------
// SVD Line: 334
// SFDITEM_REG__EXTI_RTSR
// RTSR
//
// [Bits 31..0] RW (@ 0x40021800) EXTI rising trigger selection register
// ( (unsigned int)((EXTI_RTSR >> 0) & 0xFFFFFFFF), ((EXTI_RTSR = (EXTI_RTSR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_RTSR_RT0
// - SFDITEM_FIELD__EXTI_RTSR_RT1
// - SFDITEM_FIELD__EXTI_RTSR_RT2
// - SFDITEM_FIELD__EXTI_RTSR_RT3
// - SFDITEM_FIELD__EXTI_RTSR_RT4
// - SFDITEM_FIELD__EXTI_RTSR_RT5
// - SFDITEM_FIELD__EXTI_RTSR_RT6
// - SFDITEM_FIELD__EXTI_RTSR_RT7
//
//
// ---------------------------- Register Item Address: EXTI_FTSR --------------------------------
// SVD Line: 382
unsigned int EXTI_FTSR __AT (0x40021804);
// -------------------------------- Field Item: EXTI_FTSR_FT0 -----------------------------------
// SVD Line: 388
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// FT0
//
// [Bit 0] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT0
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT1 -----------------------------------
// SVD Line: 393
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// FT1
//
// [Bit 1] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT1
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT2 -----------------------------------
// SVD Line: 398
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// FT2
//
// [Bit 2] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT2
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT3 -----------------------------------
// SVD Line: 403
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// FT3
//
// [Bit 3] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT3
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT4 -----------------------------------
// SVD Line: 408
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// FT4
//
// [Bit 4] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT4
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT5 -----------------------------------
// SVD Line: 413
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// FT5
//
// [Bit 5] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT5
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT6 -----------------------------------
// SVD Line: 418
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// FT6
//
// [Bit 6] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT6
//
//
//
// -------------------------------- Field Item: EXTI_FTSR_FT7 -----------------------------------
// SVD Line: 423
// - SFDITEM_FIELD__EXTI_FTSR_FT7
// FT7
//
// [Bit 7] RW (@ 0x40021804) Falling trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_FTSR )
// FT7
//
//
//
// -------------------------------- Register RTree: EXTI_FTSR -----------------------------------
// SVD Line: 382
// SFDITEM_REG__EXTI_FTSR
// FTSR
//
// [Bits 31..0] RW (@ 0x40021804) EXTI falling trigger selection register
// ( (unsigned int)((EXTI_FTSR >> 0) & 0xFFFFFFFF), ((EXTI_FTSR = (EXTI_FTSR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_FTSR_FT0
// - SFDITEM_FIELD__EXTI_FTSR_FT1
// - SFDITEM_FIELD__EXTI_FTSR_FT2
// - SFDITEM_FIELD__EXTI_FTSR_FT3
// - SFDITEM_FIELD__EXTI_FTSR_FT4
// - SFDITEM_FIELD__EXTI_FTSR_FT5
// - SFDITEM_FIELD__EXTI_FTSR_FT6
// - SFDITEM_FIELD__EXTI_FTSR_FT7
//
//
// ---------------------------- Register Item Address: EXTI_SWIER -------------------------------
// SVD Line: 430
unsigned int EXTI_SWIER __AT (0x40021808);
// ------------------------------- Field Item: EXTI_SWIER_SWI0 ----------------------------------
// SVD Line: 436
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// SWI0
//
// [Bit 0] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI0
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI1 ----------------------------------
// SVD Line: 441
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// SWI1
//
// [Bit 1] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI1
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI2 ----------------------------------
// SVD Line: 446
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// SWI2
//
// [Bit 2] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI2
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI3 ----------------------------------
// SVD Line: 451
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// SWI3
//
// [Bit 3] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI3
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI4 ----------------------------------
// SVD Line: 456
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// SWI4
//
// [Bit 4] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI4
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI5 ----------------------------------
// SVD Line: 461
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// SWI5
//
// [Bit 5] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI5
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI6 ----------------------------------
// SVD Line: 466
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// SWI6
//
// [Bit 6] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI6
//
//
//
// ------------------------------- Field Item: EXTI_SWIER_SWI7 ----------------------------------
// SVD Line: 471
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
// SWI7
//
// [Bit 7] RW (@ 0x40021808) Rising trigger event configuration bit of Configurable Event input
//
// ( (unsigned int) EXTI_SWIER )
// SWI7
//
//
//
// ------------------------------- Register RTree: EXTI_SWIER -----------------------------------
// SVD Line: 430
// SFDITEM_REG__EXTI_SWIER
// SWIER
//
// [Bits 31..0] RW (@ 0x40021808) EXTI software interrupt event register
// ( (unsigned int)((EXTI_SWIER >> 0) & 0xFFFFFFFF), ((EXTI_SWIER = (EXTI_SWIER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_SWIER_SWI0
// - SFDITEM_FIELD__EXTI_SWIER_SWI1
// - SFDITEM_FIELD__EXTI_SWIER_SWI2
// - SFDITEM_FIELD__EXTI_SWIER_SWI3
// - SFDITEM_FIELD__EXTI_SWIER_SWI4
// - SFDITEM_FIELD__EXTI_SWIER_SWI5
// - SFDITEM_FIELD__EXTI_SWIER_SWI6
// - SFDITEM_FIELD__EXTI_SWIER_SWI7
//
//
// ----------------------------- Register Item Address: EXTI_PR ---------------------------------
// SVD Line: 478
unsigned int EXTI_PR __AT (0x4002180C);
// --------------------------------- Field Item: EXTI_PR_PR0 ------------------------------------
// SVD Line: 484
// - SFDITEM_FIELD__EXTI_PR_PR0
// PR0
//
// [Bit 0] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR0
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR1 ------------------------------------
// SVD Line: 489
// - SFDITEM_FIELD__EXTI_PR_PR1
// PR1
//
// [Bit 1] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR1
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR2 ------------------------------------
// SVD Line: 494
// - SFDITEM_FIELD__EXTI_PR_PR2
// PR2
//
// [Bit 2] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR2
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR3 ------------------------------------
// SVD Line: 499
// - SFDITEM_FIELD__EXTI_PR_PR3
// PR3
//
// [Bit 3] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR3
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR4 ------------------------------------
// SVD Line: 504
// - SFDITEM_FIELD__EXTI_PR_PR4
// PR4
//
// [Bit 4] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR4
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR5 ------------------------------------
// SVD Line: 509
// - SFDITEM_FIELD__EXTI_PR_PR5
// PR5
//
// [Bit 5] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR5
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR6 ------------------------------------
// SVD Line: 514
// - SFDITEM_FIELD__EXTI_PR_PR6
// PR6
//
// [Bit 6] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR6
//
//
//
// --------------------------------- Field Item: EXTI_PR_PR7 ------------------------------------
// SVD Line: 519
// - SFDITEM_FIELD__EXTI_PR_PR7
// PR7
//
// [Bit 7] RW (@ 0x4002180C) configurable event inputs x rising edge Pending bit.
//
// ( (unsigned int) EXTI_PR )
// PR7
//
//
//
// --------------------------------- Register RTree: EXTI_PR ------------------------------------
// SVD Line: 478
// SFDITEM_REG__EXTI_PR
// PR
//
// [Bits 31..0] RW (@ 0x4002180C) EXTI pending register
// ( (unsigned int)((EXTI_PR >> 0) & 0xFFFFFFFF), ((EXTI_PR = (EXTI_PR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_PR_PR0
// - SFDITEM_FIELD__EXTI_PR_PR1
// - SFDITEM_FIELD__EXTI_PR_PR2
// - SFDITEM_FIELD__EXTI_PR_PR3
// - SFDITEM_FIELD__EXTI_PR_PR4
// - SFDITEM_FIELD__EXTI_PR_PR5
// - SFDITEM_FIELD__EXTI_PR_PR6
// - SFDITEM_FIELD__EXTI_PR_PR7
//
//
// --------------------------- Register Item Address: EXTI_EXTICR1 ------------------------------
// SVD Line: 526
unsigned int EXTI_EXTICR1 __AT (0x40021860);
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI0 ---------------------------------
// SVD Line: 532
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// EXTI0
//
// [Bits 1..0] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 0) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI1 ---------------------------------
// SVD Line: 537
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// EXTI1
//
// [Bits 9..8] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 8) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI2 ---------------------------------
// SVD Line: 542
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// EXTI2
//
// [Bits 17..16] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 16) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR1_EXTI3 ---------------------------------
// SVD Line: 547
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
// EXTI3
//
// [Bits 25..24] RW (@ 0x40021860) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR1 >> 24) & 0x3), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR1 ----------------------------------
// SVD Line: 526
// SFDITEM_REG__EXTI_EXTICR1
// EXTICR1
//
// [Bits 31..0] RW (@ 0x40021860) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR1 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR1 = (EXTI_EXTICR1 & ~(0x3030303UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3030303) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI0
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI1
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI2
// - SFDITEM_FIELD__EXTI_EXTICR1_EXTI3
//
//
// --------------------------- Register Item Address: EXTI_EXTICR2 ------------------------------
// SVD Line: 554
unsigned int EXTI_EXTICR2 __AT (0x40021864);
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI4 ---------------------------------
// SVD Line: 560
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// EXTI4
//
// [Bits 1..0] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned char)((EXTI_EXTICR2 >> 0) & 0x3), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI5 ---------------------------------
// SVD Line: 565
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// EXTI5
//
// [Bit 8] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI5
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI6 ---------------------------------
// SVD Line: 570
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// EXTI6
//
// [Bit 16] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI6
//
//
//
// ----------------------------- Field Item: EXTI_EXTICR2_EXTI7 ---------------------------------
// SVD Line: 575
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
// EXTI7
//
// [Bit 24] RW (@ 0x40021864) GPIO port selection
//
// ( (unsigned int) EXTI_EXTICR2 )
// EXTI7
//
//
//
// ------------------------------ Register RTree: EXTI_EXTICR2 ----------------------------------
// SVD Line: 554
// SFDITEM_REG__EXTI_EXTICR2
// EXTICR2
//
// [Bits 31..0] RW (@ 0x40021864) EXTI external interrupt selection register
// ( (unsigned int)((EXTI_EXTICR2 >> 0) & 0xFFFFFFFF), ((EXTI_EXTICR2 = (EXTI_EXTICR2 & ~(0x1010103UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1010103) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI4
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI5
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI6
// - SFDITEM_FIELD__EXTI_EXTICR2_EXTI7
//
//
// ----------------------------- Register Item Address: EXTI_IMR --------------------------------
// SVD Line: 582
unsigned int EXTI_IMR __AT (0x40021880);
// -------------------------------- Field Item: EXTI_IMR_IM0 ------------------------------------
// SVD Line: 589
// - SFDITEM_FIELD__EXTI_IMR_IM0
// IM0
//
// [Bit 0] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM0
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM1 ------------------------------------
// SVD Line: 594
// - SFDITEM_FIELD__EXTI_IMR_IM1
// IM1
//
// [Bit 1] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM1
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM2 ------------------------------------
// SVD Line: 599
// - SFDITEM_FIELD__EXTI_IMR_IM2
// IM2
//
// [Bit 2] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM2
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM3 ------------------------------------
// SVD Line: 604
// - SFDITEM_FIELD__EXTI_IMR_IM3
// IM3
//
// [Bit 3] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM3
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM4 ------------------------------------
// SVD Line: 609
// - SFDITEM_FIELD__EXTI_IMR_IM4
// IM4
//
// [Bit 4] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM4
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM5 ------------------------------------
// SVD Line: 614
// - SFDITEM_FIELD__EXTI_IMR_IM5
// IM5
//
// [Bit 5] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM5
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM6 ------------------------------------
// SVD Line: 619
// - SFDITEM_FIELD__EXTI_IMR_IM6
// IM6
//
// [Bit 6] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM6
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM7 ------------------------------------
// SVD Line: 624
// - SFDITEM_FIELD__EXTI_IMR_IM7
// IM7
//
// [Bit 7] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM7
//
//
//
// -------------------------------- Field Item: EXTI_IMR_IM29 -----------------------------------
// SVD Line: 629
// - SFDITEM_FIELD__EXTI_IMR_IM29
// IM29
//
// [Bit 29] RW (@ 0x40021880) CPU wakeup with interrupt mask on event input
//
// ( (unsigned int) EXTI_IMR )
// IM29
//
//
//
// -------------------------------- Register RTree: EXTI_IMR ------------------------------------
// SVD Line: 582
// SFDITEM_REG__EXTI_IMR
// IMR
//
// [Bits 31..0] RW (@ 0x40021880) EXTI CPU wakeup with interrupt mask register
// ( (unsigned int)((EXTI_IMR >> 0) & 0xFFFFFFFF), ((EXTI_IMR = (EXTI_IMR & ~(0x200000FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200000FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_IMR_IM0
// - SFDITEM_FIELD__EXTI_IMR_IM1
// - SFDITEM_FIELD__EXTI_IMR_IM2
// - SFDITEM_FIELD__EXTI_IMR_IM3
// - SFDITEM_FIELD__EXTI_IMR_IM4
// - SFDITEM_FIELD__EXTI_IMR_IM5
// - SFDITEM_FIELD__EXTI_IMR_IM6
// - SFDITEM_FIELD__EXTI_IMR_IM7
// - SFDITEM_FIELD__EXTI_IMR_IM29
//
//
// ----------------------------- Register Item Address: EXTI_EMR --------------------------------
// SVD Line: 636
unsigned int EXTI_EMR __AT (0x40021884);
// -------------------------------- Field Item: EXTI_EMR_EM0 ------------------------------------
// SVD Line: 642
// - SFDITEM_FIELD__EXTI_EMR_EM0
// EM0
//
// [Bit 0] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM0
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM1 ------------------------------------
// SVD Line: 647
// - SFDITEM_FIELD__EXTI_EMR_EM1
// EM1
//
// [Bit 1] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM1
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM2 ------------------------------------
// SVD Line: 652
// - SFDITEM_FIELD__EXTI_EMR_EM2
// EM2
//
// [Bit 2] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM2
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM3 ------------------------------------
// SVD Line: 657
// - SFDITEM_FIELD__EXTI_EMR_EM3
// EM3
//
// [Bit 3] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM3
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM4 ------------------------------------
// SVD Line: 662
// - SFDITEM_FIELD__EXTI_EMR_EM4
// EM4
//
// [Bit 4] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM4
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM5 ------------------------------------
// SVD Line: 667
// - SFDITEM_FIELD__EXTI_EMR_EM5
// EM5
//
// [Bit 5] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM5
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM6 ------------------------------------
// SVD Line: 672
// - SFDITEM_FIELD__EXTI_EMR_EM6
// EM6
//
// [Bit 6] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM6
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM7 ------------------------------------
// SVD Line: 677
// - SFDITEM_FIELD__EXTI_EMR_EM7
// EM7
//
// [Bit 7] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM7
//
//
//
// -------------------------------- Field Item: EXTI_EMR_EM29 -----------------------------------
// SVD Line: 682
// - SFDITEM_FIELD__EXTI_EMR_EM29
// EM29
//
// [Bit 29] RW (@ 0x40021884) CPU wakeup with event mask on event input
//
// ( (unsigned int) EXTI_EMR )
// EM29
//
//
//
// -------------------------------- Register RTree: EXTI_EMR ------------------------------------
// SVD Line: 636
// SFDITEM_REG__EXTI_EMR
// EMR
//
// [Bits 31..0] RW (@ 0x40021884) EXTI CPU wakeup with event mask register
// ( (unsigned int)((EXTI_EMR >> 0) & 0xFFFFFFFF), ((EXTI_EMR = (EXTI_EMR & ~(0x200000FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x200000FF) << 0 ) ) ))
// - SFDITEM_FIELD__EXTI_EMR_EM0
// - SFDITEM_FIELD__EXTI_EMR_EM1
// - SFDITEM_FIELD__EXTI_EMR_EM2
// - SFDITEM_FIELD__EXTI_EMR_EM3
// - SFDITEM_FIELD__EXTI_EMR_EM4
// - SFDITEM_FIELD__EXTI_EMR_EM5
// - SFDITEM_FIELD__EXTI_EMR_EM6
// - SFDITEM_FIELD__EXTI_EMR_EM7
// - SFDITEM_FIELD__EXTI_EMR_EM29
//
//
// ---------------------------------- Peripheral View: EXTI -------------------------------------
// SVD Line: 308
// EXTI
// EXTI
// - SFDITEM_REG__EXTI_RTSR
// - SFDITEM_REG__EXTI_FTSR
// - SFDITEM_REG__EXTI_SWIER
// - SFDITEM_REG__EXTI_PR
// - SFDITEM_REG__EXTI_EXTICR1
// - SFDITEM_REG__EXTI_EXTICR2
// - SFDITEM_REG__EXTI_IMR
// - SFDITEM_REG__EXTI_EMR
//
//
// ---------------------------- Register Item Address: FLASH_ACR --------------------------------
// SVD Line: 707
unsigned int FLASH_ACR __AT (0x40022000);
// ------------------------------ Field Item: FLASH_ACR_LATENCY ---------------------------------
// SVD Line: 714
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
// LATENCY
//
// [Bit 0] RW (@ 0x40022000) Latency
//
// ( (unsigned int) FLASH_ACR )
// LATENCY
//
//
//
// -------------------------------- Register RTree: FLASH_ACR -----------------------------------
// SVD Line: 707
// SFDITEM_REG__FLASH_ACR
// ACR
//
// [Bits 31..0] RW (@ 0x40022000) Access control register
// ( (unsigned int)((FLASH_ACR >> 0) & 0xFFFFFFFF), ((FLASH_ACR = (FLASH_ACR & ~(0x1UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_ACR_LATENCY
//
//
// ---------------------------- Register Item Address: FLASH_KEYR -------------------------------
// SVD Line: 721
unsigned int FLASH_KEYR __AT (0x40022008);
// ------------------------------- Field Item: FLASH_KEYR_KEY -----------------------------------
// SVD Line: 728
// - SFDITEM_FIELD__FLASH_KEYR_KEY
// KEY
//
// [Bits 31..0] WO (@ 0x40022008) Flash key
//
// ( (unsigned int)((FLASH_KEYR >> 0) & 0x0), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_KEYR -----------------------------------
// SVD Line: 721
// SFDITEM_REG__FLASH_KEYR
// KEYR
//
// [Bits 31..0] WO (@ 0x40022008) Flash key register
// ( (unsigned int)((FLASH_KEYR >> 0) & 0xFFFFFFFF), ((FLASH_KEYR = (FLASH_KEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_KEYR_KEY
//
//
// -------------------------- Register Item Address: FLASH_OPTKEYR ------------------------------
// SVD Line: 735
unsigned int FLASH_OPTKEYR __AT (0x4002200C);
// ---------------------------- Field Item: FLASH_OPTKEYR_OPTKEY --------------------------------
// SVD Line: 742
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
// OPTKEY
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key
//
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0x0), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_OPTKEYR ---------------------------------
// SVD Line: 735
// SFDITEM_REG__FLASH_OPTKEYR
// OPTKEYR
//
// [Bits 31..0] WO (@ 0x4002200C) Option byte key register
// ( (unsigned int)((FLASH_OPTKEYR >> 0) & 0xFFFFFFFF), ((FLASH_OPTKEYR = (FLASH_OPTKEYR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTKEYR_OPTKEY
//
//
// ----------------------------- Register Item Address: FLASH_SR --------------------------------
// SVD Line: 749
unsigned int FLASH_SR __AT (0x40022010);
// -------------------------------- Field Item: FLASH_SR_EOP ------------------------------------
// SVD Line: 755
// - SFDITEM_FIELD__FLASH_SR_EOP
// EOP
//
// [Bit 0] RW (@ 0x40022010) End of operation
//
// ( (unsigned int) FLASH_SR )
// EOP
//
//
//
// ------------------------------- Field Item: FLASH_SR_WRPERR ----------------------------------
// SVD Line: 760
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// WRPERR
//
// [Bit 4] RW (@ 0x40022010) Write protected error
//
// ( (unsigned int) FLASH_SR )
// WRPERR
//
//
//
// ------------------------------ Field Item: FLASH_SR_OPTVERR ----------------------------------
// SVD Line: 765
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// OPTVERR
//
// [Bit 15] RW (@ 0x40022010) Option and Engineering bits loading validity error
//
// ( (unsigned int) FLASH_SR )
// OPTVERR
//
//
//
// -------------------------------- Field Item: FLASH_SR_BSY ------------------------------------
// SVD Line: 770
// - SFDITEM_FIELD__FLASH_SR_BSY
// BSY
//
// [Bit 16] RW (@ 0x40022010) Busy
//
// ( (unsigned int) FLASH_SR )
// BSY
//
//
//
// -------------------------------- Register RTree: FLASH_SR ------------------------------------
// SVD Line: 749
// SFDITEM_REG__FLASH_SR
// SR
//
// [Bits 31..0] RW (@ 0x40022010) Status register
// ( (unsigned int)((FLASH_SR >> 0) & 0xFFFFFFFF), ((FLASH_SR = (FLASH_SR & ~(0x18011UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x18011) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SR_EOP
// - SFDITEM_FIELD__FLASH_SR_WRPERR
// - SFDITEM_FIELD__FLASH_SR_OPTVERR
// - SFDITEM_FIELD__FLASH_SR_BSY
//
//
// ----------------------------- Register Item Address: FLASH_CR --------------------------------
// SVD Line: 777
unsigned int FLASH_CR __AT (0x40022014);
// --------------------------------- Field Item: FLASH_CR_PG ------------------------------------
// SVD Line: 784
// - SFDITEM_FIELD__FLASH_CR_PG
// PG
//
// [Bit 0] RW (@ 0x40022014) Programming
//
// ( (unsigned int) FLASH_CR )
// PG
//
//
//
// -------------------------------- Field Item: FLASH_CR_PER ------------------------------------
// SVD Line: 789
// - SFDITEM_FIELD__FLASH_CR_PER
// PER
//
// [Bit 1] RW (@ 0x40022014) Page erase
//
// ( (unsigned int) FLASH_CR )
// PER
//
//
//
// -------------------------------- Field Item: FLASH_CR_MER ------------------------------------
// SVD Line: 794
// - SFDITEM_FIELD__FLASH_CR_MER
// MER
//
// [Bit 2] RW (@ 0x40022014) Mass erase
//
// ( (unsigned int) FLASH_CR )
// MER
//
//
//
// -------------------------------- Field Item: FLASH_CR_SER ------------------------------------
// SVD Line: 799
// - SFDITEM_FIELD__FLASH_CR_SER
// SER
//
// [Bit 11] RW (@ 0x40022014) Sector erase
//
// ( (unsigned int) FLASH_CR )
// SER
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTSTRT ----------------------------------
// SVD Line: 804
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// OPTSTRT
//
// [Bit 17] RW (@ 0x40022014) Option byte program start
//
// ( (unsigned int) FLASH_CR )
// OPTSTRT
//
//
//
// ------------------------------ Field Item: FLASH_CR_PGTSTRT ----------------------------------
// SVD Line: 809
// - SFDITEM_FIELD__FLASH_CR_PGTSTRT
// PGTSTRT
//
// [Bit 19] RW (@ 0x40022014) Flash main memory program start
//
// ( (unsigned int) FLASH_CR )
// PGTSTRT
//
//
//
// ------------------------------- Field Item: FLASH_CR_EOPIE -----------------------------------
// SVD Line: 814
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// EOPIE
//
// [Bit 24] RW (@ 0x40022014) End of operation interrupt enable
//
// ( (unsigned int) FLASH_CR )
// EOPIE
//
//
//
// ------------------------------- Field Item: FLASH_CR_ERRIE -----------------------------------
// SVD Line: 819
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// ERRIE
//
// [Bit 25] RW (@ 0x40022014) Error interrupt enable
//
// ( (unsigned int) FLASH_CR )
// ERRIE
//
//
//
// ----------------------------- Field Item: FLASH_CR_OBL_LAUNCH --------------------------------
// SVD Line: 824
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// OBL_LAUNCH
//
// [Bit 27] RW (@ 0x40022014) Force the option byte loading
//
// ( (unsigned int) FLASH_CR )
// OBL_LAUNCH
//
//
//
// ------------------------------ Field Item: FLASH_CR_OPTLOCK ----------------------------------
// SVD Line: 829
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// OPTLOCK
//
// [Bit 30] RW (@ 0x40022014) Options Lock
//
// ( (unsigned int) FLASH_CR )
// OPTLOCK
//
//
//
// -------------------------------- Field Item: FLASH_CR_LOCK -----------------------------------
// SVD Line: 834
// - SFDITEM_FIELD__FLASH_CR_LOCK
// LOCK
//
// [Bit 31] RW (@ 0x40022014) FLASH_CR Lock
//
// ( (unsigned int) FLASH_CR )
// LOCK
//
//
//
// -------------------------------- Register RTree: FLASH_CR ------------------------------------
// SVD Line: 777
// SFDITEM_REG__FLASH_CR
// CR
//
// [Bits 31..0] RW (@ 0x40022014) Flash control register
// ( (unsigned int)((FLASH_CR >> 0) & 0xFFFFFFFF), ((FLASH_CR = (FLASH_CR & ~(0xCB0A0807UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xCB0A0807) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_CR_PG
// - SFDITEM_FIELD__FLASH_CR_PER
// - SFDITEM_FIELD__FLASH_CR_MER
// - SFDITEM_FIELD__FLASH_CR_SER
// - SFDITEM_FIELD__FLASH_CR_OPTSTRT
// - SFDITEM_FIELD__FLASH_CR_PGTSTRT
// - SFDITEM_FIELD__FLASH_CR_EOPIE
// - SFDITEM_FIELD__FLASH_CR_ERRIE
// - SFDITEM_FIELD__FLASH_CR_OBL_LAUNCH
// - SFDITEM_FIELD__FLASH_CR_OPTLOCK
// - SFDITEM_FIELD__FLASH_CR_LOCK
//
//
// ---------------------------- Register Item Address: FLASH_OPTR -------------------------------
// SVD Line: 841
unsigned int FLASH_OPTR __AT (0x40022020);
// ------------------------------- Field Item: FLASH_OPTR_RDP -----------------------------------
// SVD Line: 848
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// RDP
//
// [Bits 7..0] RW (@ 0x40022020) Read Protection
//
// ( (unsigned char)((FLASH_OPTR >> 0) & 0xFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_OPTR_BOREN ----------------------------------
// SVD Line: 853
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// BOREN
//
// [Bit 8] RW (@ 0x40022020) BOR reset Level
//
// ( (unsigned int) FLASH_OPTR )
// BOREN
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_BORF_LEV --------------------------------
// SVD Line: 858
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
// BORF_LEV
//
// [Bits 11..9] RW (@ 0x40022020) These bits contain the VDD supply level threshold that activates the reset
//
// ( (unsigned char)((FLASH_OPTR >> 9) & 0x7), ((FLASH_OPTR = (FLASH_OPTR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_IWDG_SW ---------------------------------
// SVD Line: 863
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// IWDG_SW
//
// [Bit 12] RW (@ 0x40022020) Independent watchdog selection
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_SW
//
//
//
// ----------------------------- Field Item: FLASH_OPTR_SWD_MODE --------------------------------
// SVD Line: 868
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
// SWD_MODE
//
// [Bit 13] RW (@ 0x40022020) SWD_MODE
//
// ( (unsigned int) FLASH_OPTR )
// SWD_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_NRST_MODE --------------------------------
// SVD Line: 873
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// NRST_MODE
//
// [Bit 14] RW (@ 0x40022020) NRST_MODE
//
// ( (unsigned int) FLASH_OPTR )
// NRST_MODE
//
//
//
// ---------------------------- Field Item: FLASH_OPTR_IWDG_STOP --------------------------------
// SVD Line: 878
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
// IWDG_STOP
//
// [Bit 15] RW (@ 0x40022020) IWDG_STOP
//
// ( (unsigned int) FLASH_OPTR )
// IWDG_STOP
//
//
//
// ------------------------------- Register RTree: FLASH_OPTR -----------------------------------
// SVD Line: 841
// SFDITEM_REG__FLASH_OPTR
// OPTR
//
// [Bits 31..0] RW (@ 0x40022020) Flash option register
// ( (unsigned int)((FLASH_OPTR >> 0) & 0xFFFFFFFF), ((FLASH_OPTR = (FLASH_OPTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_OPTR_RDP
// - SFDITEM_FIELD__FLASH_OPTR_BOREN
// - SFDITEM_FIELD__FLASH_OPTR_BORF_LEV
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_SW
// - SFDITEM_FIELD__FLASH_OPTR_SWD_MODE
// - SFDITEM_FIELD__FLASH_OPTR_NRST_MODE
// - SFDITEM_FIELD__FLASH_OPTR_IWDG_STOP
//
//
// ---------------------------- Register Item Address: FLASH_SDKR -------------------------------
// SVD Line: 885
unsigned int FLASH_SDKR __AT (0x40022024);
// ----------------------------- Field Item: FLASH_SDKR_SDK_STRT --------------------------------
// SVD Line: 892
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// SDK_STRT
//
// [Bits 3..0] RW (@ 0x40022024) SDK area start address
//
// ( (unsigned char)((FLASH_SDKR >> 0) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: FLASH_SDKR_SDK_END ---------------------------------
// SVD Line: 897
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
// SDK_END
//
// [Bits 11..8] RW (@ 0x40022024) SDK area end address
//
// ( (unsigned char)((FLASH_SDKR >> 8) & 0xF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_SDKR -----------------------------------
// SVD Line: 885
// SFDITEM_REG__FLASH_SDKR
// SDKR
//
// [Bits 31..0] RW (@ 0x40022024) Flash SDK address register
// ( (unsigned int)((FLASH_SDKR >> 0) & 0xFFFFFFFF), ((FLASH_SDKR = (FLASH_SDKR & ~(0xF0FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF0F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SDKR_SDK_STRT
// - SFDITEM_FIELD__FLASH_SDKR_SDK_END
//
//
// ---------------------------- Register Item Address: FLASH_BTCR -------------------------------
// SVD Line: 904
unsigned int FLASH_BTCR __AT (0x40022028);
// ---------------------------- Field Item: FLASH_BTCR_BOOT_SIZE --------------------------------
// SVD Line: 910
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// BOOT_SIZE
//
// [Bits 2..0] RW (@ 0x40022028) desc BOOT_SIZE
//
// ( (unsigned char)((FLASH_BTCR >> 0) & 0x7), ((FLASH_BTCR = (FLASH_BTCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_BOOT0 ----------------------------------
// SVD Line: 915
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// BOOT0
//
// [Bit 14] RW (@ 0x40022028) desc BOOT0
//
// ( (unsigned int) FLASH_BTCR )
// BOOT0
//
//
//
// ------------------------------ Field Item: FLASH_BTCR_NBOOT1 ---------------------------------
// SVD Line: 920
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
// NBOOT1
//
// [Bit 15] RW (@ 0x40022028) desc NBOOT1
//
// ( (unsigned int) FLASH_BTCR )
// NBOOT1
//
//
//
// ------------------------------- Register RTree: FLASH_BTCR -----------------------------------
// SVD Line: 904
// SFDITEM_REG__FLASH_BTCR
// BTCR
//
// [Bits 31..0] RW (@ 0x40022028) FLASH boot control register
// ( (unsigned int)((FLASH_BTCR >> 0) & 0xFFFFFFFF), ((FLASH_BTCR = (FLASH_BTCR & ~(0xC007UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC007) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_BTCR_BOOT_SIZE
// - SFDITEM_FIELD__FLASH_BTCR_BOOT0
// - SFDITEM_FIELD__FLASH_BTCR_NBOOT1
//
//
// ---------------------------- Register Item Address: FLASH_WRPR -------------------------------
// SVD Line: 927
unsigned int FLASH_WRPR __AT (0x4002202C);
// ------------------------------- Field Item: FLASH_WRPR_WRP -----------------------------------
// SVD Line: 934
// - SFDITEM_FIELD__FLASH_WRPR_WRP
// WRP
//
// [Bits 5..0] RW (@ 0x4002202C) WRP address
//
// ( (unsigned char)((FLASH_WRPR >> 0) & 0x3F), ((FLASH_WRPR = (FLASH_WRPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3F) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_WRPR -----------------------------------
// SVD Line: 927
// SFDITEM_REG__FLASH_WRPR
// WRPR
//
// [Bits 31..0] RW (@ 0x4002202C) Flash WRP address register
// ( (unsigned int)((FLASH_WRPR >> 0) & 0xFFFFFFFF), ((FLASH_WRPR = (FLASH_WRPR & ~(0x3FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3F) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_WRPR_WRP
//
//
// ---------------------------- Register Item Address: FLASH_STCR -------------------------------
// SVD Line: 941
unsigned int FLASH_STCR __AT (0x40022090);
// ----------------------------- Field Item: FLASH_STCR_SLEEP_EN --------------------------------
// SVD Line: 948
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// SLEEP_EN
//
// [Bit 0] RW (@ 0x40022090) FLash sleep enable
//
// ( (unsigned int) FLASH_STCR )
// SLEEP_EN
//
//
//
// ---------------------------- Field Item: FLASH_STCR_SLEEP_TIME -------------------------------
// SVD Line: 953
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
// SLEEP_TIME
//
// [Bits 15..8] RW (@ 0x40022090) FLash sleep time configuration(counter based on HSI_10M)
//
// ( (unsigned char)((FLASH_STCR >> 8) & 0xFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_STCR -----------------------------------
// SVD Line: 941
// SFDITEM_REG__FLASH_STCR
// STCR
//
// [Bits 31..0] RW (@ 0x40022090) Flash sleep time config register
// ( (unsigned int)((FLASH_STCR >> 0) & 0xFFFFFFFF), ((FLASH_STCR = (FLASH_STCR & ~(0xFF01UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF01) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_EN
// - SFDITEM_FIELD__FLASH_STCR_SLEEP_TIME
//
//
// ---------------------------- Register Item Address: FLASH_TS0 --------------------------------
// SVD Line: 960
unsigned int FLASH_TS0 __AT (0x40022100);
// -------------------------------- Field Item: FLASH_TS0_TS0 -----------------------------------
// SVD Line: 967
// - SFDITEM_FIELD__FLASH_TS0_TS0
// TS0
//
// [Bits 8..0] RW (@ 0x40022100) FLash TS0 register
//
// ( (unsigned short)((FLASH_TS0 >> 0) & 0x1FF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS0 -----------------------------------
// SVD Line: 960
// SFDITEM_REG__FLASH_TS0
// TS0
//
// [Bits 31..0] RW (@ 0x40022100) Flash TS0 register
// ( (unsigned int)((FLASH_TS0 >> 0) & 0xFFFFFFFF), ((FLASH_TS0 = (FLASH_TS0 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS0_TS0
//
//
// ---------------------------- Register Item Address: FLASH_TS1 --------------------------------
// SVD Line: 974
unsigned int FLASH_TS1 __AT (0x40022104);
// -------------------------------- Field Item: FLASH_TS1_TS1 -----------------------------------
// SVD Line: 981
// - SFDITEM_FIELD__FLASH_TS1_TS1
// TS1
//
// [Bits 9..0] RW (@ 0x40022104) FLash TS1 register
//
// ( (unsigned short)((FLASH_TS1 >> 0) & 0x3FF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS1 -----------------------------------
// SVD Line: 974
// SFDITEM_REG__FLASH_TS1
// TS1
//
// [Bits 31..0] RW (@ 0x40022104) Flash TS1 register
// ( (unsigned int)((FLASH_TS1 >> 0) & 0xFFFFFFFF), ((FLASH_TS1 = (FLASH_TS1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS1_TS1
//
//
// ---------------------------- Register Item Address: FLASH_TS2P -------------------------------
// SVD Line: 988
unsigned int FLASH_TS2P __AT (0x40022108);
// ------------------------------- Field Item: FLASH_TS2P_TS2P ----------------------------------
// SVD Line: 995
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
// TS2P
//
// [Bits 8..0] RW (@ 0x40022108) FLash TS2P register
//
// ( (unsigned short)((FLASH_TS2P >> 0) & 0x1FF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TS2P -----------------------------------
// SVD Line: 988
// SFDITEM_REG__FLASH_TS2P
// TS2P
//
// [Bits 31..0] RW (@ 0x40022108) Flash TS2P register
// ( (unsigned int)((FLASH_TS2P >> 0) & 0xFFFFFFFF), ((FLASH_TS2P = (FLASH_TS2P & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS2P_TS2P
//
//
// ---------------------------- Register Item Address: FLASH_TPS3 -------------------------------
// SVD Line: 1002
unsigned int FLASH_TPS3 __AT (0x4002210C);
// ------------------------------- Field Item: FLASH_TPS3_TPS3 ----------------------------------
// SVD Line: 1009
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
// TPS3
//
// [Bits 11..0] RW (@ 0x4002210C) FLash TPS3 register
//
// ( (unsigned short)((FLASH_TPS3 >> 0) & 0xFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: FLASH_TPS3 -----------------------------------
// SVD Line: 1002
// SFDITEM_REG__FLASH_TPS3
// TPS3
//
// [Bits 31..0] RW (@ 0x4002210C) Flash TPS3 register
// ( (unsigned int)((FLASH_TPS3 >> 0) & 0xFFFFFFFF), ((FLASH_TPS3 = (FLASH_TPS3 & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TPS3_TPS3
//
//
// ---------------------------- Register Item Address: FLASH_TS3 --------------------------------
// SVD Line: 1016
unsigned int FLASH_TS3 __AT (0x40022110);
// -------------------------------- Field Item: FLASH_TS3_TS3 -----------------------------------
// SVD Line: 1023
// - SFDITEM_FIELD__FLASH_TS3_TS3
// TS3
//
// [Bits 8..0] RW (@ 0x40022110) FLash TS3 register
//
// ( (unsigned short)((FLASH_TS3 >> 0) & 0x1FF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: FLASH_TS3 -----------------------------------
// SVD Line: 1016
// SFDITEM_REG__FLASH_TS3
// TS3
//
// [Bits 31..0] RW (@ 0x40022110) Flash TS3 register
// ( (unsigned int)((FLASH_TS3 >> 0) & 0xFFFFFFFF), ((FLASH_TS3 = (FLASH_TS3 & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_TS3_TS3
//
//
// --------------------------- Register Item Address: FLASH_PERTPE ------------------------------
// SVD Line: 1030
unsigned int FLASH_PERTPE __AT (0x40022114);
// ----------------------------- Field Item: FLASH_PERTPE_PERTPE --------------------------------
// SVD Line: 1037
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
// PERTPE
//
// [Bits 17..0] RW (@ 0x40022114) FLash PERTPE register
//
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0x3FFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PERTPE ----------------------------------
// SVD Line: 1030
// SFDITEM_REG__FLASH_PERTPE
// PERTPE
//
// [Bits 31..0] RW (@ 0x40022114) Flash PERTPE register
// ( (unsigned int)((FLASH_PERTPE >> 0) & 0xFFFFFFFF), ((FLASH_PERTPE = (FLASH_PERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PERTPE_PERTPE
//
//
// -------------------------- Register Item Address: FLASH_SMERTPE ------------------------------
// SVD Line: 1044
unsigned int FLASH_SMERTPE __AT (0x40022118);
// ---------------------------- Field Item: FLASH_SMERTPE_SMERTPE -------------------------------
// SVD Line: 1051
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
// SMERTPE
//
// [Bits 17..0] RW (@ 0x40022118) FLash SMERTPE register
//
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0x3FFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_SMERTPE ---------------------------------
// SVD Line: 1044
// SFDITEM_REG__FLASH_SMERTPE
// SMERTPE
//
// [Bits 31..0] RW (@ 0x40022118) Flash SMERTPE register
// ( (unsigned int)((FLASH_SMERTPE >> 0) & 0xFFFFFFFF), ((FLASH_SMERTPE = (FLASH_SMERTPE & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_SMERTPE_SMERTPE
//
//
// --------------------------- Register Item Address: FLASH_PRGTPE ------------------------------
// SVD Line: 1058
unsigned int FLASH_PRGTPE __AT (0x4002211C);
// ----------------------------- Field Item: FLASH_PRGTPE_PRGTPE --------------------------------
// SVD Line: 1065
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
// PRGTPE
//
// [Bits 15..0] RW (@ 0x4002211C) FLash PRGTPE register
//
// ( (unsigned short)((FLASH_PRGTPE >> 0) & 0xFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRGTPE ----------------------------------
// SVD Line: 1058
// SFDITEM_REG__FLASH_PRGTPE
// PRGTPE
//
// [Bits 31..0] RW (@ 0x4002211C) Flash PRGTPE register
// ( (unsigned int)((FLASH_PRGTPE >> 0) & 0xFFFFFFFF), ((FLASH_PRGTPE = (FLASH_PRGTPE & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRGTPE_PRGTPE
//
//
// --------------------------- Register Item Address: FLASH_PRETPE ------------------------------
// SVD Line: 1072
unsigned int FLASH_PRETPE __AT (0x40022120);
// ----------------------------- Field Item: FLASH_PRETPE_PRETPE --------------------------------
// SVD Line: 1079
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
// PRETPE
//
// [Bits 13..0] RW (@ 0x40022120) FLash PRETPE register
//
// ( (unsigned short)((FLASH_PRETPE >> 0) & 0x3FFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x3FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: FLASH_PRETPE ----------------------------------
// SVD Line: 1072
// SFDITEM_REG__FLASH_PRETPE
// PRETPE
//
// [Bits 31..0] RW (@ 0x40022120) Flash PRETPE register
// ( (unsigned int)((FLASH_PRETPE >> 0) & 0xFFFFFFFF), ((FLASH_PRETPE = (FLASH_PRETPE & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__FLASH_PRETPE_PRETPE
//
//
// --------------------------------- Peripheral View: FLASH -------------------------------------
// SVD Line: 691
// FLASH
// FLASH
// - SFDITEM_REG__FLASH_ACR
// - SFDITEM_REG__FLASH_KEYR
// - SFDITEM_REG__FLASH_OPTKEYR
// - SFDITEM_REG__FLASH_SR
// - SFDITEM_REG__FLASH_CR
// - SFDITEM_REG__FLASH_OPTR
// - SFDITEM_REG__FLASH_SDKR
// - SFDITEM_REG__FLASH_BTCR
// - SFDITEM_REG__FLASH_WRPR
// - SFDITEM_REG__FLASH_STCR
// - SFDITEM_REG__FLASH_TS0
// - SFDITEM_REG__FLASH_TS1
// - SFDITEM_REG__FLASH_TS2P
// - SFDITEM_REG__FLASH_TPS3
// - SFDITEM_REG__FLASH_TS3
// - SFDITEM_REG__FLASH_PERTPE
// - SFDITEM_REG__FLASH_SMERTPE
// - SFDITEM_REG__FLASH_PRGTPE
// - SFDITEM_REG__FLASH_PRETPE
//
//
// --------------------------- Register Item Address: GPIOA_MODER -------------------------------
// SVD Line: 1099
unsigned int GPIOA_MODER __AT (0x50000000);
// ------------------------------ Field Item: GPIOA_MODER_MODE0 ---------------------------------
// SVD Line: 1106
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 0) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE1 ---------------------------------
// SVD Line: 1111
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 2) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE2 ---------------------------------
// SVD Line: 1116
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 4) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE3 ---------------------------------
// SVD Line: 1121
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 6) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE4 ---------------------------------
// SVD Line: 1126
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 8) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE5 ---------------------------------
// SVD Line: 1131
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 10) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE6 ---------------------------------
// SVD Line: 1136
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 12) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE7 ---------------------------------
// SVD Line: 1141
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 14) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE8 ---------------------------------
// SVD Line: 1146
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 16) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_MODER_MODE9 ---------------------------------
// SVD Line: 1151
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// MODE9
//
// [Bits 19..18] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 18) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE10 ---------------------------------
// SVD Line: 1156
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// MODE10
//
// [Bits 21..20] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 20) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE11 ---------------------------------
// SVD Line: 1161
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// MODE11
//
// [Bits 23..22] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 22) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE12 ---------------------------------
// SVD Line: 1166
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// MODE12
//
// [Bits 25..24] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 24) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE13 ---------------------------------
// SVD Line: 1171
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// MODE13
//
// [Bits 27..26] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 26) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE14 ---------------------------------
// SVD Line: 1176
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// MODE14
//
// [Bits 29..28] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 28) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_MODER_MODE15 ---------------------------------
// SVD Line: 1181
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
// MODE15
//
// [Bits 31..30] RW (@ 0x50000000) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_MODER >> 30) & 0x3), ((GPIOA_MODER = (GPIOA_MODER & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_MODER ----------------------------------
// SVD Line: 1099
// SFDITEM_REG__GPIOA_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000000) GPIO port mode register
// ( (unsigned int)((GPIOA_MODER >> 0) & 0xFFFFFFFF), ((GPIOA_MODER = (GPIOA_MODER & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_MODER_MODE0
// - SFDITEM_FIELD__GPIOA_MODER_MODE1
// - SFDITEM_FIELD__GPIOA_MODER_MODE2
// - SFDITEM_FIELD__GPIOA_MODER_MODE3
// - SFDITEM_FIELD__GPIOA_MODER_MODE4
// - SFDITEM_FIELD__GPIOA_MODER_MODE5
// - SFDITEM_FIELD__GPIOA_MODER_MODE6
// - SFDITEM_FIELD__GPIOA_MODER_MODE7
// - SFDITEM_FIELD__GPIOA_MODER_MODE8
// - SFDITEM_FIELD__GPIOA_MODER_MODE9
// - SFDITEM_FIELD__GPIOA_MODER_MODE10
// - SFDITEM_FIELD__GPIOA_MODER_MODE11
// - SFDITEM_FIELD__GPIOA_MODER_MODE12
// - SFDITEM_FIELD__GPIOA_MODER_MODE13
// - SFDITEM_FIELD__GPIOA_MODER_MODE14
// - SFDITEM_FIELD__GPIOA_MODER_MODE15
//
//
// --------------------------- Register Item Address: GPIOA_OTYPER ------------------------------
// SVD Line: 1188
unsigned int GPIOA_OTYPER __AT (0x50000004);
// ------------------------------ Field Item: GPIOA_OTYPER_OT0 ----------------------------------
// SVD Line: 1194
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT1 ----------------------------------
// SVD Line: 1199
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT2 ----------------------------------
// SVD Line: 1204
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT3 ----------------------------------
// SVD Line: 1209
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT4 ----------------------------------
// SVD Line: 1214
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT5 ----------------------------------
// SVD Line: 1219
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT6 ----------------------------------
// SVD Line: 1224
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT7 ----------------------------------
// SVD Line: 1229
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT8 ----------------------------------
// SVD Line: 1234
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT8
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT9 ----------------------------------
// SVD Line: 1239
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// OT9
//
// [Bit 9] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT9
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT10 ---------------------------------
// SVD Line: 1244
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// OT10
//
// [Bit 10] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT10
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT11 ---------------------------------
// SVD Line: 1249
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// OT11
//
// [Bit 11] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT11
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT12 ---------------------------------
// SVD Line: 1254
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// OT12
//
// [Bit 12] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT12
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT13 ---------------------------------
// SVD Line: 1259
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// OT13
//
// [Bit 13] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT13
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT14 ---------------------------------
// SVD Line: 1264
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// OT14
//
// [Bit 14] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT14
//
//
//
// ------------------------------ Field Item: GPIOA_OTYPER_OT15 ---------------------------------
// SVD Line: 1269
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
// OT15
//
// [Bit 15] RW (@ 0x50000004) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOA_OTYPER )
// OT15
//
//
//
// ------------------------------ Register RTree: GPIOA_OTYPER ----------------------------------
// SVD Line: 1188
// SFDITEM_REG__GPIOA_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000004) GPIO port output type register
// ( (unsigned int)((GPIOA_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOA_OTYPER = (GPIOA_OTYPER & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OTYPER_OT0
// - SFDITEM_FIELD__GPIOA_OTYPER_OT1
// - SFDITEM_FIELD__GPIOA_OTYPER_OT2
// - SFDITEM_FIELD__GPIOA_OTYPER_OT3
// - SFDITEM_FIELD__GPIOA_OTYPER_OT4
// - SFDITEM_FIELD__GPIOA_OTYPER_OT5
// - SFDITEM_FIELD__GPIOA_OTYPER_OT6
// - SFDITEM_FIELD__GPIOA_OTYPER_OT7
// - SFDITEM_FIELD__GPIOA_OTYPER_OT8
// - SFDITEM_FIELD__GPIOA_OTYPER_OT9
// - SFDITEM_FIELD__GPIOA_OTYPER_OT10
// - SFDITEM_FIELD__GPIOA_OTYPER_OT11
// - SFDITEM_FIELD__GPIOA_OTYPER_OT12
// - SFDITEM_FIELD__GPIOA_OTYPER_OT13
// - SFDITEM_FIELD__GPIOA_OTYPER_OT14
// - SFDITEM_FIELD__GPIOA_OTYPER_OT15
//
//
// -------------------------- Register Item Address: GPIOA_OSPEEDR ------------------------------
// SVD Line: 1276
unsigned int GPIOA_OSPEEDR __AT (0x50000008);
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 1283
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 0) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 1288
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 2) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 1293
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 4) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 1298
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 6) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 1303
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 8) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 1308
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 10) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 1313
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 12) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 1318
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 14) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 1323
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 16) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOA_OSPEEDR_OSPEED9 -------------------------------
// SVD Line: 1328
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// OSPEED9
//
// [Bits 19..18] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 18) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED10 -------------------------------
// SVD Line: 1333
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// OSPEED10
//
// [Bits 21..20] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 20) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED11 -------------------------------
// SVD Line: 1338
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// OSPEED11
//
// [Bits 23..22] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 22) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED12 -------------------------------
// SVD Line: 1343
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// OSPEED12
//
// [Bits 25..24] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 24) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED13 -------------------------------
// SVD Line: 1348
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// OSPEED13
//
// [Bits 27..26] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 26) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED14 -------------------------------
// SVD Line: 1353
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// OSPEED14
//
// [Bits 29..28] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 28) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// --------------------------- Field Item: GPIOA_OSPEEDR_OSPEED15 -------------------------------
// SVD Line: 1358
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
// OSPEED15
//
// [Bits 31..30] RW (@ 0x50000008) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_OSPEEDR >> 30) & 0x3), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOA_OSPEEDR ---------------------------------
// SVD Line: 1276
// SFDITEM_REG__GPIOA_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000008) GPIO port output speed register
// ( (unsigned int)((GPIOA_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOA_OSPEEDR = (GPIOA_OSPEEDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED8
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED9
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED10
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED11
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED12
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED13
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED14
// - SFDITEM_FIELD__GPIOA_OSPEEDR_OSPEED15
//
//
// --------------------------- Register Item Address: GPIOA_PUPDR -------------------------------
// SVD Line: 1365
unsigned int GPIOA_PUPDR __AT (0x5000000C);
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD0 ---------------------------------
// SVD Line: 1372
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 0) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD1 ---------------------------------
// SVD Line: 1377
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 2) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD2 ---------------------------------
// SVD Line: 1382
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 4) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD3 ---------------------------------
// SVD Line: 1387
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 6) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD4 ---------------------------------
// SVD Line: 1392
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 8) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD5 ---------------------------------
// SVD Line: 1397
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 10) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD6 ---------------------------------
// SVD Line: 1402
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 12) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD7 ---------------------------------
// SVD Line: 1407
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 14) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD8 ---------------------------------
// SVD Line: 1412
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 16) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_PUPDR_PUPD9 ---------------------------------
// SVD Line: 1417
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// PUPD9
//
// [Bits 19..18] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 18) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD10 ---------------------------------
// SVD Line: 1422
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// PUPD10
//
// [Bits 21..20] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 20) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD11 ---------------------------------
// SVD Line: 1427
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// PUPD11
//
// [Bits 23..22] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 22) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 22 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 22 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD12 ---------------------------------
// SVD Line: 1432
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// PUPD12
//
// [Bits 25..24] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 24) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD13 ---------------------------------
// SVD Line: 1437
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// PUPD13
//
// [Bits 27..26] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 26) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD14 ---------------------------------
// SVD Line: 1442
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// PUPD14
//
// [Bits 29..28] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 28) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 28 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_PUPDR_PUPD15 ---------------------------------
// SVD Line: 1447
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
// PUPD15
//
// [Bits 31..30] RW (@ 0x5000000C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOA_PUPDR >> 30) & 0x3), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0x3UL << 30 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 30 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_PUPDR ----------------------------------
// SVD Line: 1365
// SFDITEM_REG__GPIOA_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000000C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOA_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOA_PUPDR = (GPIOA_PUPDR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD8
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD9
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD10
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD11
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD12
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD13
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD14
// - SFDITEM_FIELD__GPIOA_PUPDR_PUPD15
//
//
// ---------------------------- Register Item Address: GPIOA_IDR --------------------------------
// SVD Line: 1454
unsigned int GPIOA_IDR __AT (0x50000010);
// -------------------------------- Field Item: GPIOA_IDR_ID0 -----------------------------------
// SVD Line: 1461
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID1 -----------------------------------
// SVD Line: 1466
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID2 -----------------------------------
// SVD Line: 1471
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID3 -----------------------------------
// SVD Line: 1476
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID4 -----------------------------------
// SVD Line: 1481
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID5 -----------------------------------
// SVD Line: 1486
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID6 -----------------------------------
// SVD Line: 1491
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID7 -----------------------------------
// SVD Line: 1496
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID8 -----------------------------------
// SVD Line: 1501
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID8
//
//
//
// -------------------------------- Field Item: GPIOA_IDR_ID9 -----------------------------------
// SVD Line: 1506
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// ID9
//
// [Bit 9] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID9
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID10 -----------------------------------
// SVD Line: 1511
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// ID10
//
// [Bit 10] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID10
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID11 -----------------------------------
// SVD Line: 1516
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// ID11
//
// [Bit 11] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID11
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID12 -----------------------------------
// SVD Line: 1521
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// ID12
//
// [Bit 12] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID12
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID13 -----------------------------------
// SVD Line: 1526
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// ID13
//
// [Bit 13] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID13
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID14 -----------------------------------
// SVD Line: 1531
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// ID14
//
// [Bit 14] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID14
//
//
//
// ------------------------------- Field Item: GPIOA_IDR_ID15 -----------------------------------
// SVD Line: 1536
// - SFDITEM_FIELD__GPIOA_IDR_ID15
// ID15
//
// [Bit 15] RO (@ 0x50000010) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOA_IDR )
// ID15
//
//
//
// -------------------------------- Register RTree: GPIOA_IDR -----------------------------------
// SVD Line: 1454
// SFDITEM_REG__GPIOA_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000010) GPIO port input data register
// ( (unsigned int)((GPIOA_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOA_IDR_ID0
// - SFDITEM_FIELD__GPIOA_IDR_ID1
// - SFDITEM_FIELD__GPIOA_IDR_ID2
// - SFDITEM_FIELD__GPIOA_IDR_ID3
// - SFDITEM_FIELD__GPIOA_IDR_ID4
// - SFDITEM_FIELD__GPIOA_IDR_ID5
// - SFDITEM_FIELD__GPIOA_IDR_ID6
// - SFDITEM_FIELD__GPIOA_IDR_ID7
// - SFDITEM_FIELD__GPIOA_IDR_ID8
// - SFDITEM_FIELD__GPIOA_IDR_ID9
// - SFDITEM_FIELD__GPIOA_IDR_ID10
// - SFDITEM_FIELD__GPIOA_IDR_ID11
// - SFDITEM_FIELD__GPIOA_IDR_ID12
// - SFDITEM_FIELD__GPIOA_IDR_ID13
// - SFDITEM_FIELD__GPIOA_IDR_ID14
// - SFDITEM_FIELD__GPIOA_IDR_ID15
//
//
// ---------------------------- Register Item Address: GPIOA_ODR --------------------------------
// SVD Line: 1543
unsigned int GPIOA_ODR __AT (0x50000014);
// -------------------------------- Field Item: GPIOA_ODR_OD0 -----------------------------------
// SVD Line: 1549
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD1 -----------------------------------
// SVD Line: 1554
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD2 -----------------------------------
// SVD Line: 1559
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD3 -----------------------------------
// SVD Line: 1564
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD4 -----------------------------------
// SVD Line: 1569
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD5 -----------------------------------
// SVD Line: 1574
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD6 -----------------------------------
// SVD Line: 1579
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD7 -----------------------------------
// SVD Line: 1584
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD8 -----------------------------------
// SVD Line: 1589
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD8
//
//
//
// -------------------------------- Field Item: GPIOA_ODR_OD9 -----------------------------------
// SVD Line: 1594
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// OD9
//
// [Bit 9] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD9
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD10 -----------------------------------
// SVD Line: 1599
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// OD10
//
// [Bit 10] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD10
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD11 -----------------------------------
// SVD Line: 1604
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// OD11
//
// [Bit 11] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD11
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD12 -----------------------------------
// SVD Line: 1609
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// OD12
//
// [Bit 12] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD12
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD13 -----------------------------------
// SVD Line: 1614
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// OD13
//
// [Bit 13] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD13
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD14 -----------------------------------
// SVD Line: 1619
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// OD14
//
// [Bit 14] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD14
//
//
//
// ------------------------------- Field Item: GPIOA_ODR_OD15 -----------------------------------
// SVD Line: 1624
// - SFDITEM_FIELD__GPIOA_ODR_OD15
// OD15
//
// [Bit 15] RW (@ 0x50000014) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOA_ODR )
// OD15
//
//
//
// -------------------------------- Register RTree: GPIOA_ODR -----------------------------------
// SVD Line: 1543
// SFDITEM_REG__GPIOA_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000014) GPIO port output data register
// ( (unsigned int)((GPIOA_ODR >> 0) & 0xFFFFFFFF), ((GPIOA_ODR = (GPIOA_ODR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_ODR_OD0
// - SFDITEM_FIELD__GPIOA_ODR_OD1
// - SFDITEM_FIELD__GPIOA_ODR_OD2
// - SFDITEM_FIELD__GPIOA_ODR_OD3
// - SFDITEM_FIELD__GPIOA_ODR_OD4
// - SFDITEM_FIELD__GPIOA_ODR_OD5
// - SFDITEM_FIELD__GPIOA_ODR_OD6
// - SFDITEM_FIELD__GPIOA_ODR_OD7
// - SFDITEM_FIELD__GPIOA_ODR_OD8
// - SFDITEM_FIELD__GPIOA_ODR_OD9
// - SFDITEM_FIELD__GPIOA_ODR_OD10
// - SFDITEM_FIELD__GPIOA_ODR_OD11
// - SFDITEM_FIELD__GPIOA_ODR_OD12
// - SFDITEM_FIELD__GPIOA_ODR_OD13
// - SFDITEM_FIELD__GPIOA_ODR_OD14
// - SFDITEM_FIELD__GPIOA_ODR_OD15
//
//
// ---------------------------- Register Item Address: GPIOA_BSRR -------------------------------
// SVD Line: 1631
unsigned int GPIOA_BSRR __AT (0x50000018);
// ------------------------------- Field Item: GPIOA_BSRR_BS0 -----------------------------------
// SVD Line: 1638
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS1 -----------------------------------
// SVD Line: 1643
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS2 -----------------------------------
// SVD Line: 1648
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS3 -----------------------------------
// SVD Line: 1653
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS4 -----------------------------------
// SVD Line: 1658
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS5 -----------------------------------
// SVD Line: 1663
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS6 -----------------------------------
// SVD Line: 1668
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS7 -----------------------------------
// SVD Line: 1673
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS8 -----------------------------------
// SVD Line: 1678
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS9 -----------------------------------
// SVD Line: 1683
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// BS9
//
// [Bit 9] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS10 ----------------------------------
// SVD Line: 1688
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// BS10
//
// [Bit 10] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS11 ----------------------------------
// SVD Line: 1693
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// BS11
//
// [Bit 11] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS12 ----------------------------------
// SVD Line: 1698
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// BS12
//
// [Bit 12] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS13 ----------------------------------
// SVD Line: 1703
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// BS13
//
// [Bit 13] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS14 ----------------------------------
// SVD Line: 1708
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// BS14
//
// [Bit 14] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BS15 ----------------------------------
// SVD Line: 1713
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// BS15
//
// [Bit 15] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BS15
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR0 -----------------------------------
// SVD Line: 1718
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000018) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR1 -----------------------------------
// SVD Line: 1723
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR2 -----------------------------------
// SVD Line: 1728
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR3 -----------------------------------
// SVD Line: 1733
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR4 -----------------------------------
// SVD Line: 1738
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR5 -----------------------------------
// SVD Line: 1743
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR6 -----------------------------------
// SVD Line: 1748
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR7 -----------------------------------
// SVD Line: 1753
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR8 -----------------------------------
// SVD Line: 1758
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR8
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR9 -----------------------------------
// SVD Line: 1763
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// BR9
//
// [Bit 25] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR10 ----------------------------------
// SVD Line: 1768
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// BR10
//
// [Bit 26] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR11 ----------------------------------
// SVD Line: 1773
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// BR11
//
// [Bit 27] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR12 ----------------------------------
// SVD Line: 1778
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// BR12
//
// [Bit 28] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR13 ----------------------------------
// SVD Line: 1783
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// BR13
//
// [Bit 29] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR14 ----------------------------------
// SVD Line: 1788
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// BR14
//
// [Bit 30] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BSRR_BR15 ----------------------------------
// SVD Line: 1793
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
// BR15
//
// [Bit 31] WO (@ 0x50000018) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOA_BSRR )
// BR15
//
//
//
// ------------------------------- Register RTree: GPIOA_BSRR -----------------------------------
// SVD Line: 1631
// SFDITEM_REG__GPIOA_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000018) GPIO port bit set/reset register
// ( (unsigned int)((GPIOA_BSRR >> 0) & 0xFFFFFFFF), ((GPIOA_BSRR = (GPIOA_BSRR & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BSRR_BS0
// - SFDITEM_FIELD__GPIOA_BSRR_BS1
// - SFDITEM_FIELD__GPIOA_BSRR_BS2
// - SFDITEM_FIELD__GPIOA_BSRR_BS3
// - SFDITEM_FIELD__GPIOA_BSRR_BS4
// - SFDITEM_FIELD__GPIOA_BSRR_BS5
// - SFDITEM_FIELD__GPIOA_BSRR_BS6
// - SFDITEM_FIELD__GPIOA_BSRR_BS7
// - SFDITEM_FIELD__GPIOA_BSRR_BS8
// - SFDITEM_FIELD__GPIOA_BSRR_BS9
// - SFDITEM_FIELD__GPIOA_BSRR_BS10
// - SFDITEM_FIELD__GPIOA_BSRR_BS11
// - SFDITEM_FIELD__GPIOA_BSRR_BS12
// - SFDITEM_FIELD__GPIOA_BSRR_BS13
// - SFDITEM_FIELD__GPIOA_BSRR_BS14
// - SFDITEM_FIELD__GPIOA_BSRR_BS15
// - SFDITEM_FIELD__GPIOA_BSRR_BR0
// - SFDITEM_FIELD__GPIOA_BSRR_BR1
// - SFDITEM_FIELD__GPIOA_BSRR_BR2
// - SFDITEM_FIELD__GPIOA_BSRR_BR3
// - SFDITEM_FIELD__GPIOA_BSRR_BR4
// - SFDITEM_FIELD__GPIOA_BSRR_BR5
// - SFDITEM_FIELD__GPIOA_BSRR_BR6
// - SFDITEM_FIELD__GPIOA_BSRR_BR7
// - SFDITEM_FIELD__GPIOA_BSRR_BR8
// - SFDITEM_FIELD__GPIOA_BSRR_BR9
// - SFDITEM_FIELD__GPIOA_BSRR_BR10
// - SFDITEM_FIELD__GPIOA_BSRR_BR11
// - SFDITEM_FIELD__GPIOA_BSRR_BR12
// - SFDITEM_FIELD__GPIOA_BSRR_BR13
// - SFDITEM_FIELD__GPIOA_BSRR_BR14
// - SFDITEM_FIELD__GPIOA_BSRR_BR15
//
//
// ---------------------------- Register Item Address: GPIOA_LCKR -------------------------------
// SVD Line: 1800
unsigned int GPIOA_LCKR __AT (0x5000001C);
// ------------------------------- Field Item: GPIOA_LCKR_LCK0 ----------------------------------
// SVD Line: 1806
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK1 ----------------------------------
// SVD Line: 1811
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK2 ----------------------------------
// SVD Line: 1816
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK3 ----------------------------------
// SVD Line: 1821
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK4 ----------------------------------
// SVD Line: 1826
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK5 ----------------------------------
// SVD Line: 1831
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK6 ----------------------------------
// SVD Line: 1836
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK7 ----------------------------------
// SVD Line: 1841
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK8 ----------------------------------
// SVD Line: 1846
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCK9 ----------------------------------
// SVD Line: 1851
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// LCK9
//
// [Bit 9] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK9
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK10 ----------------------------------
// SVD Line: 1856
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// LCK10
//
// [Bit 10] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK10
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK11 ----------------------------------
// SVD Line: 1861
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// LCK11
//
// [Bit 11] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK11
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK12 ----------------------------------
// SVD Line: 1866
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// LCK12
//
// [Bit 12] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK12
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK13 ----------------------------------
// SVD Line: 1871
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// LCK13
//
// [Bit 13] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK13
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK14 ----------------------------------
// SVD Line: 1876
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// LCK14
//
// [Bit 14] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK14
//
//
//
// ------------------------------ Field Item: GPIOA_LCKR_LCK15 ----------------------------------
// SVD Line: 1881
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// LCK15
//
// [Bit 15] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCK15
//
//
//
// ------------------------------- Field Item: GPIOA_LCKR_LCKK ----------------------------------
// SVD Line: 1886
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000001C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOA_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOA_LCKR -----------------------------------
// SVD Line: 1800
// SFDITEM_REG__GPIOA_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000001C) GPIO port configuration lock register
// ( (unsigned int)((GPIOA_LCKR >> 0) & 0xFFFFFFFF), ((GPIOA_LCKR = (GPIOA_LCKR & ~(0x1FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_LCKR_LCK0
// - SFDITEM_FIELD__GPIOA_LCKR_LCK1
// - SFDITEM_FIELD__GPIOA_LCKR_LCK2
// - SFDITEM_FIELD__GPIOA_LCKR_LCK3
// - SFDITEM_FIELD__GPIOA_LCKR_LCK4
// - SFDITEM_FIELD__GPIOA_LCKR_LCK5
// - SFDITEM_FIELD__GPIOA_LCKR_LCK6
// - SFDITEM_FIELD__GPIOA_LCKR_LCK7
// - SFDITEM_FIELD__GPIOA_LCKR_LCK8
// - SFDITEM_FIELD__GPIOA_LCKR_LCK9
// - SFDITEM_FIELD__GPIOA_LCKR_LCK10
// - SFDITEM_FIELD__GPIOA_LCKR_LCK11
// - SFDITEM_FIELD__GPIOA_LCKR_LCK12
// - SFDITEM_FIELD__GPIOA_LCKR_LCK13
// - SFDITEM_FIELD__GPIOA_LCKR_LCK14
// - SFDITEM_FIELD__GPIOA_LCKR_LCK15
// - SFDITEM_FIELD__GPIOA_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOA_AFRL -------------------------------
// SVD Line: 1893
unsigned int GPIOA_AFRL __AT (0x50000020);
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL0 ---------------------------------
// SVD Line: 1899
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 0) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL1 ---------------------------------
// SVD Line: 1904
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 4) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL2 ---------------------------------
// SVD Line: 1909
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 8) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL3 ---------------------------------
// SVD Line: 1914
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 12) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL4 ---------------------------------
// SVD Line: 1919
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 16) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL5 ---------------------------------
// SVD Line: 1924
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 20) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL6 ---------------------------------
// SVD Line: 1929
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 24) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRL_AFSEL7 ---------------------------------
// SVD Line: 1934
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000020) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOA_AFRL >> 28) & 0xF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRL -----------------------------------
// SVD Line: 1893
// SFDITEM_REG__GPIOA_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000020) GPIO alternate function low register
// ( (unsigned int)((GPIOA_AFRL >> 0) & 0xFFFFFFFF), ((GPIOA_AFRL = (GPIOA_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOA_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOA_AFRH -------------------------------
// SVD Line: 1941
unsigned int GPIOA_AFRH __AT (0x50000024);
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL8 ---------------------------------
// SVD Line: 1947
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 0) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOA_AFRH_AFSEL9 ---------------------------------
// SVD Line: 1952
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 4) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL10 ---------------------------------
// SVD Line: 1957
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 8) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL11 ---------------------------------
// SVD Line: 1962
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 12) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL12 ---------------------------------
// SVD Line: 1967
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 16) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL13 ---------------------------------
// SVD Line: 1972
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 20) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL14 ---------------------------------
// SVD Line: 1977
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 24) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOA_AFRH_AFSEL15 ---------------------------------
// SVD Line: 1982
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000024) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOA_AFRH >> 28) & 0xF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOA_AFRH -----------------------------------
// SVD Line: 1941
// SFDITEM_REG__GPIOA_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000024) GPIO alternate function high register
// ( (unsigned int)((GPIOA_AFRH >> 0) & 0xFFFFFFFF), ((GPIOA_AFRH = (GPIOA_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOA_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOA_BRR --------------------------------
// SVD Line: 1989
unsigned int GPIOA_BRR __AT (0x50000028);
// -------------------------------- Field Item: GPIOA_BRR_BR0 -----------------------------------
// SVD Line: 1996
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR1 -----------------------------------
// SVD Line: 2001
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR2 -----------------------------------
// SVD Line: 2006
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR3 -----------------------------------
// SVD Line: 2011
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR4 -----------------------------------
// SVD Line: 2016
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR5 -----------------------------------
// SVD Line: 2021
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR6 -----------------------------------
// SVD Line: 2026
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR7 -----------------------------------
// SVD Line: 2031
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR8 -----------------------------------
// SVD Line: 2036
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR8
//
//
//
// -------------------------------- Field Item: GPIOA_BRR_BR9 -----------------------------------
// SVD Line: 2041
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// BR9
//
// [Bit 9] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR9
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR10 -----------------------------------
// SVD Line: 2046
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// BR10
//
// [Bit 10] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR10
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR11 -----------------------------------
// SVD Line: 2051
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// BR11
//
// [Bit 11] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR11
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR12 -----------------------------------
// SVD Line: 2056
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// BR12
//
// [Bit 12] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR12
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR13 -----------------------------------
// SVD Line: 2061
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// BR13
//
// [Bit 13] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR13
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR14 -----------------------------------
// SVD Line: 2066
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// BR14
//
// [Bit 14] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR14
//
//
//
// ------------------------------- Field Item: GPIOA_BRR_BR15 -----------------------------------
// SVD Line: 2071
// - SFDITEM_FIELD__GPIOA_BRR_BR15
// BR15
//
// [Bit 15] WO (@ 0x50000028) Port Reset bit
//
// ( (unsigned int) GPIOA_BRR )
// BR15
//
//
//
// -------------------------------- Register RTree: GPIOA_BRR -----------------------------------
// SVD Line: 1989
// SFDITEM_REG__GPIOA_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000028) port bit reset register
// ( (unsigned int)((GPIOA_BRR >> 0) & 0xFFFFFFFF), ((GPIOA_BRR = (GPIOA_BRR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOA_BRR_BR0
// - SFDITEM_FIELD__GPIOA_BRR_BR1
// - SFDITEM_FIELD__GPIOA_BRR_BR2
// - SFDITEM_FIELD__GPIOA_BRR_BR3
// - SFDITEM_FIELD__GPIOA_BRR_BR4
// - SFDITEM_FIELD__GPIOA_BRR_BR5
// - SFDITEM_FIELD__GPIOA_BRR_BR6
// - SFDITEM_FIELD__GPIOA_BRR_BR7
// - SFDITEM_FIELD__GPIOA_BRR_BR8
// - SFDITEM_FIELD__GPIOA_BRR_BR9
// - SFDITEM_FIELD__GPIOA_BRR_BR10
// - SFDITEM_FIELD__GPIOA_BRR_BR11
// - SFDITEM_FIELD__GPIOA_BRR_BR12
// - SFDITEM_FIELD__GPIOA_BRR_BR13
// - SFDITEM_FIELD__GPIOA_BRR_BR14
// - SFDITEM_FIELD__GPIOA_BRR_BR15
//
//
// --------------------------------- Peripheral View: GPIOA -------------------------------------
// SVD Line: 1088
// GPIOA
// GPIOA
// - SFDITEM_REG__GPIOA_MODER
// - SFDITEM_REG__GPIOA_OTYPER
// - SFDITEM_REG__GPIOA_OSPEEDR
// - SFDITEM_REG__GPIOA_PUPDR
// - SFDITEM_REG__GPIOA_IDR
// - SFDITEM_REG__GPIOA_ODR
// - SFDITEM_REG__GPIOA_BSRR
// - SFDITEM_REG__GPIOA_LCKR
// - SFDITEM_REG__GPIOA_AFRL
// - SFDITEM_REG__GPIOA_AFRH
// - SFDITEM_REG__GPIOA_BRR
//
//
// --------------------------- Register Item Address: GPIOB_MODER -------------------------------
// SVD Line: 2091
unsigned int GPIOB_MODER __AT (0x50000400);
// ------------------------------ Field Item: GPIOB_MODER_MODE0 ---------------------------------
// SVD Line: 2098
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 0) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE1 ---------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 2) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE2 ---------------------------------
// SVD Line: 2108
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 4) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE3 ---------------------------------
// SVD Line: 2113
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 6) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE4 ---------------------------------
// SVD Line: 2118
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 8) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE5 ---------------------------------
// SVD Line: 2123
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 10) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE6 ---------------------------------
// SVD Line: 2128
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 12) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE7 ---------------------------------
// SVD Line: 2133
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 14) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_MODER_MODE8 ---------------------------------
// SVD Line: 2138
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000400) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_MODER >> 16) & 0x3), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_MODER ----------------------------------
// SVD Line: 2091
// SFDITEM_REG__GPIOB_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000400) GPIO port mode register
// ( (unsigned int)((GPIOB_MODER >> 0) & 0xFFFFFFFF), ((GPIOB_MODER = (GPIOB_MODER & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_MODER_MODE0
// - SFDITEM_FIELD__GPIOB_MODER_MODE1
// - SFDITEM_FIELD__GPIOB_MODER_MODE2
// - SFDITEM_FIELD__GPIOB_MODER_MODE3
// - SFDITEM_FIELD__GPIOB_MODER_MODE4
// - SFDITEM_FIELD__GPIOB_MODER_MODE5
// - SFDITEM_FIELD__GPIOB_MODER_MODE6
// - SFDITEM_FIELD__GPIOB_MODER_MODE7
// - SFDITEM_FIELD__GPIOB_MODER_MODE8
//
//
// --------------------------- Register Item Address: GPIOB_OTYPER ------------------------------
// SVD Line: 2145
unsigned int GPIOB_OTYPER __AT (0x50000404);
// ------------------------------ Field Item: GPIOB_OTYPER_OT0 ----------------------------------
// SVD Line: 2151
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT1 ----------------------------------
// SVD Line: 2156
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT2 ----------------------------------
// SVD Line: 2161
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT3 ----------------------------------
// SVD Line: 2166
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT4 ----------------------------------
// SVD Line: 2171
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT5 ----------------------------------
// SVD Line: 2176
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT6 ----------------------------------
// SVD Line: 2181
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT7 ----------------------------------
// SVD Line: 2186
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOB_OTYPER_OT8 ----------------------------------
// SVD Line: 2191
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000404) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOB_OTYPER )
// OT8
//
//
//
// ------------------------------ Register RTree: GPIOB_OTYPER ----------------------------------
// SVD Line: 2145
// SFDITEM_REG__GPIOB_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000404) GPIO port output type register
// ( (unsigned int)((GPIOB_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOB_OTYPER = (GPIOB_OTYPER & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OTYPER_OT0
// - SFDITEM_FIELD__GPIOB_OTYPER_OT1
// - SFDITEM_FIELD__GPIOB_OTYPER_OT2
// - SFDITEM_FIELD__GPIOB_OTYPER_OT3
// - SFDITEM_FIELD__GPIOB_OTYPER_OT4
// - SFDITEM_FIELD__GPIOB_OTYPER_OT5
// - SFDITEM_FIELD__GPIOB_OTYPER_OT6
// - SFDITEM_FIELD__GPIOB_OTYPER_OT7
// - SFDITEM_FIELD__GPIOB_OTYPER_OT8
//
//
// -------------------------- Register Item Address: GPIOB_OSPEEDR ------------------------------
// SVD Line: 2198
unsigned int GPIOB_OSPEEDR __AT (0x50000408);
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2204
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 0) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2209
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 2) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2214
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 4) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2219
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 6) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2224
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 8) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2229
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 10) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2234
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 12) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2239
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 14) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOB_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2244
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000408) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_OSPEEDR >> 16) & 0x3), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOB_OSPEEDR ---------------------------------
// SVD Line: 2198
// SFDITEM_REG__GPIOB_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000408) GPIO port output speed register
// ( (unsigned int)((GPIOB_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOB_OSPEEDR = (GPIOB_OSPEEDR & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOB_OSPEEDR_OSPEED8
//
//
// --------------------------- Register Item Address: GPIOB_PUPDR -------------------------------
// SVD Line: 2251
unsigned int GPIOB_PUPDR __AT (0x5000040C);
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2257
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 0) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2262
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 2) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2267
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 4) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2272
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 6) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2277
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 8) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2282
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 10) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2287
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 12) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2292
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 14) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2297
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000040C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOB_PUPDR >> 16) & 0x3), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_PUPDR ----------------------------------
// SVD Line: 2251
// SFDITEM_REG__GPIOB_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000040C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOB_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOB_PUPDR = (GPIOB_PUPDR & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOB_PUPDR_PUPD8
//
//
// ---------------------------- Register Item Address: GPIOB_IDR --------------------------------
// SVD Line: 2304
unsigned int GPIOB_IDR __AT (0x50000410);
// -------------------------------- Field Item: GPIOB_IDR_ID0 -----------------------------------
// SVD Line: 2311
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID1 -----------------------------------
// SVD Line: 2316
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID2 -----------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID3 -----------------------------------
// SVD Line: 2326
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID4 -----------------------------------
// SVD Line: 2331
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID5 -----------------------------------
// SVD Line: 2336
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID6 -----------------------------------
// SVD Line: 2341
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID7 -----------------------------------
// SVD Line: 2346
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOB_IDR_ID8 -----------------------------------
// SVD Line: 2351
// - SFDITEM_FIELD__GPIOB_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000410) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOB_IDR )
// ID8
//
//
//
// -------------------------------- Register RTree: GPIOB_IDR -----------------------------------
// SVD Line: 2304
// SFDITEM_REG__GPIOB_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000410) GPIO port input data register
// ( (unsigned int)((GPIOB_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOB_IDR_ID0
// - SFDITEM_FIELD__GPIOB_IDR_ID1
// - SFDITEM_FIELD__GPIOB_IDR_ID2
// - SFDITEM_FIELD__GPIOB_IDR_ID3
// - SFDITEM_FIELD__GPIOB_IDR_ID4
// - SFDITEM_FIELD__GPIOB_IDR_ID5
// - SFDITEM_FIELD__GPIOB_IDR_ID6
// - SFDITEM_FIELD__GPIOB_IDR_ID7
// - SFDITEM_FIELD__GPIOB_IDR_ID8
//
//
// ---------------------------- Register Item Address: GPIOB_ODR --------------------------------
// SVD Line: 2358
unsigned int GPIOB_ODR __AT (0x50000414);
// -------------------------------- Field Item: GPIOB_ODR_OD0 -----------------------------------
// SVD Line: 2364
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD1 -----------------------------------
// SVD Line: 2369
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD2 -----------------------------------
// SVD Line: 2374
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD3 -----------------------------------
// SVD Line: 2379
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD4 -----------------------------------
// SVD Line: 2384
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD5 -----------------------------------
// SVD Line: 2389
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD6 -----------------------------------
// SVD Line: 2394
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD7 -----------------------------------
// SVD Line: 2399
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOB_ODR_OD8 -----------------------------------
// SVD Line: 2404
// - SFDITEM_FIELD__GPIOB_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000414) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOB_ODR )
// OD8
//
//
//
// -------------------------------- Register RTree: GPIOB_ODR -----------------------------------
// SVD Line: 2358
// SFDITEM_REG__GPIOB_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000414) GPIO port output data register
// ( (unsigned int)((GPIOB_ODR >> 0) & 0xFFFFFFFF), ((GPIOB_ODR = (GPIOB_ODR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_ODR_OD0
// - SFDITEM_FIELD__GPIOB_ODR_OD1
// - SFDITEM_FIELD__GPIOB_ODR_OD2
// - SFDITEM_FIELD__GPIOB_ODR_OD3
// - SFDITEM_FIELD__GPIOB_ODR_OD4
// - SFDITEM_FIELD__GPIOB_ODR_OD5
// - SFDITEM_FIELD__GPIOB_ODR_OD6
// - SFDITEM_FIELD__GPIOB_ODR_OD7
// - SFDITEM_FIELD__GPIOB_ODR_OD8
//
//
// ---------------------------- Register Item Address: GPIOB_BSRR -------------------------------
// SVD Line: 2411
unsigned int GPIOB_BSRR __AT (0x50000418);
// ------------------------------- Field Item: GPIOB_BSRR_BS0 -----------------------------------
// SVD Line: 2418
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS1 -----------------------------------
// SVD Line: 2423
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS2 -----------------------------------
// SVD Line: 2428
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS3 -----------------------------------
// SVD Line: 2433
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS4 -----------------------------------
// SVD Line: 2438
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS5 -----------------------------------
// SVD Line: 2443
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS6 -----------------------------------
// SVD Line: 2448
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS7 -----------------------------------
// SVD Line: 2453
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BS8 -----------------------------------
// SVD Line: 2458
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR0 -----------------------------------
// SVD Line: 2463
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000418) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR1 -----------------------------------
// SVD Line: 2468
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR2 -----------------------------------
// SVD Line: 2473
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR3 -----------------------------------
// SVD Line: 2478
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR4 -----------------------------------
// SVD Line: 2483
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR5 -----------------------------------
// SVD Line: 2488
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR6 -----------------------------------
// SVD Line: 2493
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR7 -----------------------------------
// SVD Line: 2498
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOB_BSRR_BR8 -----------------------------------
// SVD Line: 2503
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000418) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOB_BSRR )
// BR8
//
//
//
// ------------------------------- Register RTree: GPIOB_BSRR -----------------------------------
// SVD Line: 2411
// SFDITEM_REG__GPIOB_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000418) GPIO port bit set/reset register
// ( (unsigned int)((GPIOB_BSRR >> 0) & 0xFFFFFFFF), ((GPIOB_BSRR = (GPIOB_BSRR & ~(0x1FF01FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF01FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BSRR_BS0
// - SFDITEM_FIELD__GPIOB_BSRR_BS1
// - SFDITEM_FIELD__GPIOB_BSRR_BS2
// - SFDITEM_FIELD__GPIOB_BSRR_BS3
// - SFDITEM_FIELD__GPIOB_BSRR_BS4
// - SFDITEM_FIELD__GPIOB_BSRR_BS5
// - SFDITEM_FIELD__GPIOB_BSRR_BS6
// - SFDITEM_FIELD__GPIOB_BSRR_BS7
// - SFDITEM_FIELD__GPIOB_BSRR_BS8
// - SFDITEM_FIELD__GPIOB_BSRR_BR0
// - SFDITEM_FIELD__GPIOB_BSRR_BR1
// - SFDITEM_FIELD__GPIOB_BSRR_BR2
// - SFDITEM_FIELD__GPIOB_BSRR_BR3
// - SFDITEM_FIELD__GPIOB_BSRR_BR4
// - SFDITEM_FIELD__GPIOB_BSRR_BR5
// - SFDITEM_FIELD__GPIOB_BSRR_BR6
// - SFDITEM_FIELD__GPIOB_BSRR_BR7
// - SFDITEM_FIELD__GPIOB_BSRR_BR8
//
//
// ---------------------------- Register Item Address: GPIOB_LCKR -------------------------------
// SVD Line: 2510
unsigned int GPIOB_LCKR __AT (0x5000041C);
// ------------------------------- Field Item: GPIOB_LCKR_LCK0 ----------------------------------
// SVD Line: 2516
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK1 ----------------------------------
// SVD Line: 2521
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK2 ----------------------------------
// SVD Line: 2526
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK3 ----------------------------------
// SVD Line: 2531
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK4 ----------------------------------
// SVD Line: 2536
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK5 ----------------------------------
// SVD Line: 2541
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK6 ----------------------------------
// SVD Line: 2546
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK7 ----------------------------------
// SVD Line: 2551
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCK8 ----------------------------------
// SVD Line: 2556
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOB_LCKR_LCKK ----------------------------------
// SVD Line: 2561
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000041C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOB_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOB_LCKR -----------------------------------
// SVD Line: 2510
// SFDITEM_REG__GPIOB_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000041C) GPIO port configuration lock register
// ( (unsigned int)((GPIOB_LCKR >> 0) & 0xFFFFFFFF), ((GPIOB_LCKR = (GPIOB_LCKR & ~(0x101FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_LCKR_LCK0
// - SFDITEM_FIELD__GPIOB_LCKR_LCK1
// - SFDITEM_FIELD__GPIOB_LCKR_LCK2
// - SFDITEM_FIELD__GPIOB_LCKR_LCK3
// - SFDITEM_FIELD__GPIOB_LCKR_LCK4
// - SFDITEM_FIELD__GPIOB_LCKR_LCK5
// - SFDITEM_FIELD__GPIOB_LCKR_LCK6
// - SFDITEM_FIELD__GPIOB_LCKR_LCK7
// - SFDITEM_FIELD__GPIOB_LCKR_LCK8
// - SFDITEM_FIELD__GPIOB_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOB_AFRL -------------------------------
// SVD Line: 2568
unsigned int GPIOB_AFRL __AT (0x50000420);
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL0 ---------------------------------
// SVD Line: 2574
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 0) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL1 ---------------------------------
// SVD Line: 2579
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 4) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL2 ---------------------------------
// SVD Line: 2584
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 8) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL3 ---------------------------------
// SVD Line: 2589
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 12) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL4 ---------------------------------
// SVD Line: 2594
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 16) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL5 ---------------------------------
// SVD Line: 2599
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 20) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL6 ---------------------------------
// SVD Line: 2604
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 24) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRL_AFSEL7 ---------------------------------
// SVD Line: 2609
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000420) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOB_AFRL >> 28) & 0xF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRL -----------------------------------
// SVD Line: 2568
// SFDITEM_REG__GPIOB_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000420) GPIO alternate function low register
// ( (unsigned int)((GPIOB_AFRL >> 0) & 0xFFFFFFFF), ((GPIOB_AFRL = (GPIOB_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOB_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOB_AFRH -------------------------------
// SVD Line: 2616
unsigned int GPIOB_AFRH __AT (0x50000424);
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL8 ---------------------------------
// SVD Line: 2622
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 0) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOB_AFRH_AFSEL9 ---------------------------------
// SVD Line: 2627
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 4) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL10 ---------------------------------
// SVD Line: 2632
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 8) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL11 ---------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 12) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL12 ---------------------------------
// SVD Line: 2642
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 16) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL13 ---------------------------------
// SVD Line: 2647
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 20) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL14 ---------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 24) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOB_AFRH_AFSEL15 ---------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000424) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOB_AFRH >> 28) & 0xF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOB_AFRH -----------------------------------
// SVD Line: 2616
// SFDITEM_REG__GPIOB_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000424) GPIO alternate function high register
// ( (unsigned int)((GPIOB_AFRH >> 0) & 0xFFFFFFFF), ((GPIOB_AFRH = (GPIOB_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOB_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOB_BRR --------------------------------
// SVD Line: 2664
unsigned int GPIOB_BRR __AT (0x50000428);
// -------------------------------- Field Item: GPIOB_BRR_BR0 -----------------------------------
// SVD Line: 2671
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR1 -----------------------------------
// SVD Line: 2676
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR2 -----------------------------------
// SVD Line: 2681
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR3 -----------------------------------
// SVD Line: 2686
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR4 -----------------------------------
// SVD Line: 2691
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR5 -----------------------------------
// SVD Line: 2696
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR6 -----------------------------------
// SVD Line: 2701
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR7 -----------------------------------
// SVD Line: 2706
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOB_BRR_BR8 -----------------------------------
// SVD Line: 2711
// - SFDITEM_FIELD__GPIOB_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50000428) Port Reset bit
//
// ( (unsigned int) GPIOB_BRR )
// BR8
//
//
//
// -------------------------------- Register RTree: GPIOB_BRR -----------------------------------
// SVD Line: 2664
// SFDITEM_REG__GPIOB_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000428) port bit reset register
// ( (unsigned int)((GPIOB_BRR >> 0) & 0xFFFFFFFF), ((GPIOB_BRR = (GPIOB_BRR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOB_BRR_BR0
// - SFDITEM_FIELD__GPIOB_BRR_BR1
// - SFDITEM_FIELD__GPIOB_BRR_BR2
// - SFDITEM_FIELD__GPIOB_BRR_BR3
// - SFDITEM_FIELD__GPIOB_BRR_BR4
// - SFDITEM_FIELD__GPIOB_BRR_BR5
// - SFDITEM_FIELD__GPIOB_BRR_BR6
// - SFDITEM_FIELD__GPIOB_BRR_BR7
// - SFDITEM_FIELD__GPIOB_BRR_BR8
//
//
// --------------------------------- Peripheral View: GPIOB -------------------------------------
// SVD Line: 2080
// GPIOB
// GPIOB
// - SFDITEM_REG__GPIOB_MODER
// - SFDITEM_REG__GPIOB_OTYPER
// - SFDITEM_REG__GPIOB_OSPEEDR
// - SFDITEM_REG__GPIOB_PUPDR
// - SFDITEM_REG__GPIOB_IDR
// - SFDITEM_REG__GPIOB_ODR
// - SFDITEM_REG__GPIOB_BSRR
// - SFDITEM_REG__GPIOB_LCKR
// - SFDITEM_REG__GPIOB_AFRL
// - SFDITEM_REG__GPIOB_AFRH
// - SFDITEM_REG__GPIOB_BRR
//
//
// --------------------------- Register Item Address: GPIOC_MODER -------------------------------
// SVD Line: 2091
unsigned int GPIOC_MODER __AT (0x50000800);
// ------------------------------ Field Item: GPIOC_MODER_MODE0 ---------------------------------
// SVD Line: 2098
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// MODE0
//
// [Bits 1..0] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 0) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE1 ---------------------------------
// SVD Line: 2103
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
// MODE1
//
// [Bits 3..2] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 2) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE2 ---------------------------------
// SVD Line: 2108
// - SFDITEM_FIELD__GPIOC_MODER_MODE2
// MODE2
//
// [Bits 5..4] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 4) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE3 ---------------------------------
// SVD Line: 2113
// - SFDITEM_FIELD__GPIOC_MODER_MODE3
// MODE3
//
// [Bits 7..6] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 6) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE4 ---------------------------------
// SVD Line: 2118
// - SFDITEM_FIELD__GPIOC_MODER_MODE4
// MODE4
//
// [Bits 9..8] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 8) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE5 ---------------------------------
// SVD Line: 2123
// - SFDITEM_FIELD__GPIOC_MODER_MODE5
// MODE5
//
// [Bits 11..10] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 10) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE6 ---------------------------------
// SVD Line: 2128
// - SFDITEM_FIELD__GPIOC_MODER_MODE6
// MODE6
//
// [Bits 13..12] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 12) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE7 ---------------------------------
// SVD Line: 2133
// - SFDITEM_FIELD__GPIOC_MODER_MODE7
// MODE7
//
// [Bits 15..14] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 14) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_MODER_MODE8 ---------------------------------
// SVD Line: 2138
// - SFDITEM_FIELD__GPIOC_MODER_MODE8
// MODE8
//
// [Bits 17..16] RW (@ 0x50000800) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_MODER >> 16) & 0x3), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_MODER ----------------------------------
// SVD Line: 2091
// SFDITEM_REG__GPIOC_MODER
// MODER
//
// [Bits 31..0] RW (@ 0x50000800) GPIO port mode register
// ( (unsigned int)((GPIOC_MODER >> 0) & 0xFFFFFFFF), ((GPIOC_MODER = (GPIOC_MODER & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_MODER_MODE0
// - SFDITEM_FIELD__GPIOC_MODER_MODE1
// - SFDITEM_FIELD__GPIOC_MODER_MODE2
// - SFDITEM_FIELD__GPIOC_MODER_MODE3
// - SFDITEM_FIELD__GPIOC_MODER_MODE4
// - SFDITEM_FIELD__GPIOC_MODER_MODE5
// - SFDITEM_FIELD__GPIOC_MODER_MODE6
// - SFDITEM_FIELD__GPIOC_MODER_MODE7
// - SFDITEM_FIELD__GPIOC_MODER_MODE8
//
//
// --------------------------- Register Item Address: GPIOC_OTYPER ------------------------------
// SVD Line: 2145
unsigned int GPIOC_OTYPER __AT (0x50000804);
// ------------------------------ Field Item: GPIOC_OTYPER_OT0 ----------------------------------
// SVD Line: 2151
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// OT0
//
// [Bit 0] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT0
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT1 ----------------------------------
// SVD Line: 2156
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
// OT1
//
// [Bit 1] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT1
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT2 ----------------------------------
// SVD Line: 2161
// - SFDITEM_FIELD__GPIOC_OTYPER_OT2
// OT2
//
// [Bit 2] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT2
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT3 ----------------------------------
// SVD Line: 2166
// - SFDITEM_FIELD__GPIOC_OTYPER_OT3
// OT3
//
// [Bit 3] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT3
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT4 ----------------------------------
// SVD Line: 2171
// - SFDITEM_FIELD__GPIOC_OTYPER_OT4
// OT4
//
// [Bit 4] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT4
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT5 ----------------------------------
// SVD Line: 2176
// - SFDITEM_FIELD__GPIOC_OTYPER_OT5
// OT5
//
// [Bit 5] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT5
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT6 ----------------------------------
// SVD Line: 2181
// - SFDITEM_FIELD__GPIOC_OTYPER_OT6
// OT6
//
// [Bit 6] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT6
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT7 ----------------------------------
// SVD Line: 2186
// - SFDITEM_FIELD__GPIOC_OTYPER_OT7
// OT7
//
// [Bit 7] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT7
//
//
//
// ------------------------------ Field Item: GPIOC_OTYPER_OT8 ----------------------------------
// SVD Line: 2191
// - SFDITEM_FIELD__GPIOC_OTYPER_OT8
// OT8
//
// [Bit 8] RW (@ 0x50000804) Port x configuration bits (y = 0..15)
//
// ( (unsigned int) GPIOC_OTYPER )
// OT8
//
//
//
// ------------------------------ Register RTree: GPIOC_OTYPER ----------------------------------
// SVD Line: 2145
// SFDITEM_REG__GPIOC_OTYPER
// OTYPER
//
// [Bits 31..0] RW (@ 0x50000804) GPIO port output type register
// ( (unsigned int)((GPIOC_OTYPER >> 0) & 0xFFFFFFFF), ((GPIOC_OTYPER = (GPIOC_OTYPER & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OTYPER_OT0
// - SFDITEM_FIELD__GPIOC_OTYPER_OT1
// - SFDITEM_FIELD__GPIOC_OTYPER_OT2
// - SFDITEM_FIELD__GPIOC_OTYPER_OT3
// - SFDITEM_FIELD__GPIOC_OTYPER_OT4
// - SFDITEM_FIELD__GPIOC_OTYPER_OT5
// - SFDITEM_FIELD__GPIOC_OTYPER_OT6
// - SFDITEM_FIELD__GPIOC_OTYPER_OT7
// - SFDITEM_FIELD__GPIOC_OTYPER_OT8
//
//
// -------------------------- Register Item Address: GPIOC_OSPEEDR ------------------------------
// SVD Line: 2198
unsigned int GPIOC_OSPEEDR __AT (0x50000808);
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED0 -------------------------------
// SVD Line: 2204
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// OSPEED0
//
// [Bits 1..0] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 0) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED1 -------------------------------
// SVD Line: 2209
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
// OSPEED1
//
// [Bits 3..2] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 2) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED2 -------------------------------
// SVD Line: 2214
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED2
// OSPEED2
//
// [Bits 5..4] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 4) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED3 -------------------------------
// SVD Line: 2219
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED3
// OSPEED3
//
// [Bits 7..6] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 6) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED4 -------------------------------
// SVD Line: 2224
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED4
// OSPEED4
//
// [Bits 9..8] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 8) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED5 -------------------------------
// SVD Line: 2229
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED5
// OSPEED5
//
// [Bits 11..10] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 10) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED6 -------------------------------
// SVD Line: 2234
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED6
// OSPEED6
//
// [Bits 13..12] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 12) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED7 -------------------------------
// SVD Line: 2239
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED7
// OSPEED7
//
// [Bits 15..14] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 14) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ---------------------------- Field Item: GPIOC_OSPEEDR_OSPEED8 -------------------------------
// SVD Line: 2244
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED8
// OSPEED8
//
// [Bits 17..16] RW (@ 0x50000808) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_OSPEEDR >> 16) & 0x3), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------ Register RTree: GPIOC_OSPEEDR ---------------------------------
// SVD Line: 2198
// SFDITEM_REG__GPIOC_OSPEEDR
// OSPEEDR
//
// [Bits 31..0] RW (@ 0x50000808) GPIO port output speed register
// ( (unsigned int)((GPIOC_OSPEEDR >> 0) & 0xFFFFFFFF), ((GPIOC_OSPEEDR = (GPIOC_OSPEEDR & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED0
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED1
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED2
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED3
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED4
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED5
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED6
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED7
// - SFDITEM_FIELD__GPIOC_OSPEEDR_OSPEED8
//
//
// --------------------------- Register Item Address: GPIOC_PUPDR -------------------------------
// SVD Line: 2251
unsigned int GPIOC_PUPDR __AT (0x5000080C);
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD0 ---------------------------------
// SVD Line: 2257
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// PUPD0
//
// [Bits 1..0] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 0) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD1 ---------------------------------
// SVD Line: 2262
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
// PUPD1
//
// [Bits 3..2] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 2) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD2 ---------------------------------
// SVD Line: 2267
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD2
// PUPD2
//
// [Bits 5..4] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 4) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD3 ---------------------------------
// SVD Line: 2272
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD3
// PUPD3
//
// [Bits 7..6] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 6) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 6 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 6 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD4 ---------------------------------
// SVD Line: 2277
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD4
// PUPD4
//
// [Bits 9..8] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 8) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD5 ---------------------------------
// SVD Line: 2282
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD5
// PUPD5
//
// [Bits 11..10] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 10) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD6 ---------------------------------
// SVD Line: 2287
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD6
// PUPD6
//
// [Bits 13..12] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 12) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD7 ---------------------------------
// SVD Line: 2292
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD7
// PUPD7
//
// [Bits 15..14] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 14) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_PUPDR_PUPD8 ---------------------------------
// SVD Line: 2297
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD8
// PUPD8
//
// [Bits 17..16] RW (@ 0x5000080C) Port x configuration bits (y = 0..15)
//
// ( (unsigned char)((GPIOC_PUPDR >> 16) & 0x3), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_PUPDR ----------------------------------
// SVD Line: 2251
// SFDITEM_REG__GPIOC_PUPDR
// PUPDR
//
// [Bits 31..0] RW (@ 0x5000080C) GPIO port pull-up/pull-down register
// ( (unsigned int)((GPIOC_PUPDR >> 0) & 0xFFFFFFFF), ((GPIOC_PUPDR = (GPIOC_PUPDR & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD0
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD1
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD2
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD3
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD4
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD5
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD6
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD7
// - SFDITEM_FIELD__GPIOC_PUPDR_PUPD8
//
//
// ---------------------------- Register Item Address: GPIOC_IDR --------------------------------
// SVD Line: 2304
unsigned int GPIOC_IDR __AT (0x50000810);
// -------------------------------- Field Item: GPIOC_IDR_ID0 -----------------------------------
// SVD Line: 2311
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// ID0
//
// [Bit 0] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID0
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID1 -----------------------------------
// SVD Line: 2316
// - SFDITEM_FIELD__GPIOC_IDR_ID1
// ID1
//
// [Bit 1] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID1
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID2 -----------------------------------
// SVD Line: 2321
// - SFDITEM_FIELD__GPIOC_IDR_ID2
// ID2
//
// [Bit 2] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID2
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID3 -----------------------------------
// SVD Line: 2326
// - SFDITEM_FIELD__GPIOC_IDR_ID3
// ID3
//
// [Bit 3] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID3
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID4 -----------------------------------
// SVD Line: 2331
// - SFDITEM_FIELD__GPIOC_IDR_ID4
// ID4
//
// [Bit 4] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID4
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID5 -----------------------------------
// SVD Line: 2336
// - SFDITEM_FIELD__GPIOC_IDR_ID5
// ID5
//
// [Bit 5] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID5
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID6 -----------------------------------
// SVD Line: 2341
// - SFDITEM_FIELD__GPIOC_IDR_ID6
// ID6
//
// [Bit 6] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID6
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID7 -----------------------------------
// SVD Line: 2346
// - SFDITEM_FIELD__GPIOC_IDR_ID7
// ID7
//
// [Bit 7] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID7
//
//
//
// -------------------------------- Field Item: GPIOC_IDR_ID8 -----------------------------------
// SVD Line: 2351
// - SFDITEM_FIELD__GPIOC_IDR_ID8
// ID8
//
// [Bit 8] RO (@ 0x50000810) Port input data (y = 0..15)
//
// ( (unsigned int) GPIOC_IDR )
// ID8
//
//
//
// -------------------------------- Register RTree: GPIOC_IDR -----------------------------------
// SVD Line: 2304
// SFDITEM_REG__GPIOC_IDR
// IDR
//
// [Bits 31..0] RO (@ 0x50000810) GPIO port input data register
// ( (unsigned int)((GPIOC_IDR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__GPIOC_IDR_ID0
// - SFDITEM_FIELD__GPIOC_IDR_ID1
// - SFDITEM_FIELD__GPIOC_IDR_ID2
// - SFDITEM_FIELD__GPIOC_IDR_ID3
// - SFDITEM_FIELD__GPIOC_IDR_ID4
// - SFDITEM_FIELD__GPIOC_IDR_ID5
// - SFDITEM_FIELD__GPIOC_IDR_ID6
// - SFDITEM_FIELD__GPIOC_IDR_ID7
// - SFDITEM_FIELD__GPIOC_IDR_ID8
//
//
// ---------------------------- Register Item Address: GPIOC_ODR --------------------------------
// SVD Line: 2358
unsigned int GPIOC_ODR __AT (0x50000814);
// -------------------------------- Field Item: GPIOC_ODR_OD0 -----------------------------------
// SVD Line: 2364
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// OD0
//
// [Bit 0] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD0
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD1 -----------------------------------
// SVD Line: 2369
// - SFDITEM_FIELD__GPIOC_ODR_OD1
// OD1
//
// [Bit 1] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD1
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD2 -----------------------------------
// SVD Line: 2374
// - SFDITEM_FIELD__GPIOC_ODR_OD2
// OD2
//
// [Bit 2] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD2
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD3 -----------------------------------
// SVD Line: 2379
// - SFDITEM_FIELD__GPIOC_ODR_OD3
// OD3
//
// [Bit 3] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD3
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD4 -----------------------------------
// SVD Line: 2384
// - SFDITEM_FIELD__GPIOC_ODR_OD4
// OD4
//
// [Bit 4] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD4
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD5 -----------------------------------
// SVD Line: 2389
// - SFDITEM_FIELD__GPIOC_ODR_OD5
// OD5
//
// [Bit 5] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD5
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD6 -----------------------------------
// SVD Line: 2394
// - SFDITEM_FIELD__GPIOC_ODR_OD6
// OD6
//
// [Bit 6] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD6
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD7 -----------------------------------
// SVD Line: 2399
// - SFDITEM_FIELD__GPIOC_ODR_OD7
// OD7
//
// [Bit 7] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD7
//
//
//
// -------------------------------- Field Item: GPIOC_ODR_OD8 -----------------------------------
// SVD Line: 2404
// - SFDITEM_FIELD__GPIOC_ODR_OD8
// OD8
//
// [Bit 8] RW (@ 0x50000814) Port output data (y = 0..15)
//
// ( (unsigned int) GPIOC_ODR )
// OD8
//
//
//
// -------------------------------- Register RTree: GPIOC_ODR -----------------------------------
// SVD Line: 2358
// SFDITEM_REG__GPIOC_ODR
// ODR
//
// [Bits 31..0] RW (@ 0x50000814) GPIO port output data register
// ( (unsigned int)((GPIOC_ODR >> 0) & 0xFFFFFFFF), ((GPIOC_ODR = (GPIOC_ODR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_ODR_OD0
// - SFDITEM_FIELD__GPIOC_ODR_OD1
// - SFDITEM_FIELD__GPIOC_ODR_OD2
// - SFDITEM_FIELD__GPIOC_ODR_OD3
// - SFDITEM_FIELD__GPIOC_ODR_OD4
// - SFDITEM_FIELD__GPIOC_ODR_OD5
// - SFDITEM_FIELD__GPIOC_ODR_OD6
// - SFDITEM_FIELD__GPIOC_ODR_OD7
// - SFDITEM_FIELD__GPIOC_ODR_OD8
//
//
// ---------------------------- Register Item Address: GPIOC_BSRR -------------------------------
// SVD Line: 2411
unsigned int GPIOC_BSRR __AT (0x50000818);
// ------------------------------- Field Item: GPIOC_BSRR_BS0 -----------------------------------
// SVD Line: 2418
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// BS0
//
// [Bit 0] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS1 -----------------------------------
// SVD Line: 2423
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// BS1
//
// [Bit 1] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS1
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS2 -----------------------------------
// SVD Line: 2428
// - SFDITEM_FIELD__GPIOC_BSRR_BS2
// BS2
//
// [Bit 2] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS2
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS3 -----------------------------------
// SVD Line: 2433
// - SFDITEM_FIELD__GPIOC_BSRR_BS3
// BS3
//
// [Bit 3] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS3
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS4 -----------------------------------
// SVD Line: 2438
// - SFDITEM_FIELD__GPIOC_BSRR_BS4
// BS4
//
// [Bit 4] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS4
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS5 -----------------------------------
// SVD Line: 2443
// - SFDITEM_FIELD__GPIOC_BSRR_BS5
// BS5
//
// [Bit 5] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS5
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS6 -----------------------------------
// SVD Line: 2448
// - SFDITEM_FIELD__GPIOC_BSRR_BS6
// BS6
//
// [Bit 6] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS6
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS7 -----------------------------------
// SVD Line: 2453
// - SFDITEM_FIELD__GPIOC_BSRR_BS7
// BS7
//
// [Bit 7] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS7
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BS8 -----------------------------------
// SVD Line: 2458
// - SFDITEM_FIELD__GPIOC_BSRR_BS8
// BS8
//
// [Bit 8] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BS8
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR0 -----------------------------------
// SVD Line: 2463
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// BR0
//
// [Bit 16] WO (@ 0x50000818) Port x set bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR0
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR1 -----------------------------------
// SVD Line: 2468
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
// BR1
//
// [Bit 17] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR1
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR2 -----------------------------------
// SVD Line: 2473
// - SFDITEM_FIELD__GPIOC_BSRR_BR2
// BR2
//
// [Bit 18] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR2
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR3 -----------------------------------
// SVD Line: 2478
// - SFDITEM_FIELD__GPIOC_BSRR_BR3
// BR3
//
// [Bit 19] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR3
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR4 -----------------------------------
// SVD Line: 2483
// - SFDITEM_FIELD__GPIOC_BSRR_BR4
// BR4
//
// [Bit 20] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR4
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR5 -----------------------------------
// SVD Line: 2488
// - SFDITEM_FIELD__GPIOC_BSRR_BR5
// BR5
//
// [Bit 21] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR5
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR6 -----------------------------------
// SVD Line: 2493
// - SFDITEM_FIELD__GPIOC_BSRR_BR6
// BR6
//
// [Bit 22] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR6
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR7 -----------------------------------
// SVD Line: 2498
// - SFDITEM_FIELD__GPIOC_BSRR_BR7
// BR7
//
// [Bit 23] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR7
//
//
//
// ------------------------------- Field Item: GPIOC_BSRR_BR8 -----------------------------------
// SVD Line: 2503
// - SFDITEM_FIELD__GPIOC_BSRR_BR8
// BR8
//
// [Bit 24] WO (@ 0x50000818) Port x reset bit y (y = 0..15)
//
// ( (unsigned int) GPIOC_BSRR )
// BR8
//
//
//
// ------------------------------- Register RTree: GPIOC_BSRR -----------------------------------
// SVD Line: 2411
// SFDITEM_REG__GPIOC_BSRR
// BSRR
//
// [Bits 31..0] WO (@ 0x50000818) GPIO port bit set/reset register
// ( (unsigned int)((GPIOC_BSRR >> 0) & 0xFFFFFFFF), ((GPIOC_BSRR = (GPIOC_BSRR & ~(0x1FF01FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF01FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BSRR_BS0
// - SFDITEM_FIELD__GPIOC_BSRR_BS1
// - SFDITEM_FIELD__GPIOC_BSRR_BS2
// - SFDITEM_FIELD__GPIOC_BSRR_BS3
// - SFDITEM_FIELD__GPIOC_BSRR_BS4
// - SFDITEM_FIELD__GPIOC_BSRR_BS5
// - SFDITEM_FIELD__GPIOC_BSRR_BS6
// - SFDITEM_FIELD__GPIOC_BSRR_BS7
// - SFDITEM_FIELD__GPIOC_BSRR_BS8
// - SFDITEM_FIELD__GPIOC_BSRR_BR0
// - SFDITEM_FIELD__GPIOC_BSRR_BR1
// - SFDITEM_FIELD__GPIOC_BSRR_BR2
// - SFDITEM_FIELD__GPIOC_BSRR_BR3
// - SFDITEM_FIELD__GPIOC_BSRR_BR4
// - SFDITEM_FIELD__GPIOC_BSRR_BR5
// - SFDITEM_FIELD__GPIOC_BSRR_BR6
// - SFDITEM_FIELD__GPIOC_BSRR_BR7
// - SFDITEM_FIELD__GPIOC_BSRR_BR8
//
//
// ---------------------------- Register Item Address: GPIOC_LCKR -------------------------------
// SVD Line: 2510
unsigned int GPIOC_LCKR __AT (0x5000081C);
// ------------------------------- Field Item: GPIOC_LCKR_LCK0 ----------------------------------
// SVD Line: 2516
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// LCK0
//
// [Bit 0] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK0
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK1 ----------------------------------
// SVD Line: 2521
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// LCK1
//
// [Bit 1] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK1
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK2 ----------------------------------
// SVD Line: 2526
// - SFDITEM_FIELD__GPIOC_LCKR_LCK2
// LCK2
//
// [Bit 2] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK2
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK3 ----------------------------------
// SVD Line: 2531
// - SFDITEM_FIELD__GPIOC_LCKR_LCK3
// LCK3
//
// [Bit 3] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK3
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK4 ----------------------------------
// SVD Line: 2536
// - SFDITEM_FIELD__GPIOC_LCKR_LCK4
// LCK4
//
// [Bit 4] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK4
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK5 ----------------------------------
// SVD Line: 2541
// - SFDITEM_FIELD__GPIOC_LCKR_LCK5
// LCK5
//
// [Bit 5] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK5
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK6 ----------------------------------
// SVD Line: 2546
// - SFDITEM_FIELD__GPIOC_LCKR_LCK6
// LCK6
//
// [Bit 6] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK6
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK7 ----------------------------------
// SVD Line: 2551
// - SFDITEM_FIELD__GPIOC_LCKR_LCK7
// LCK7
//
// [Bit 7] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK7
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCK8 ----------------------------------
// SVD Line: 2556
// - SFDITEM_FIELD__GPIOC_LCKR_LCK8
// LCK8
//
// [Bit 8] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCK8
//
//
//
// ------------------------------- Field Item: GPIOC_LCKR_LCKK ----------------------------------
// SVD Line: 2561
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
// LCKK
//
// [Bit 16] RW (@ 0x5000081C) Port x lock bit y (y= 0..15)
//
// ( (unsigned int) GPIOC_LCKR )
// LCKK
//
//
//
// ------------------------------- Register RTree: GPIOC_LCKR -----------------------------------
// SVD Line: 2510
// SFDITEM_REG__GPIOC_LCKR
// LCKR
//
// [Bits 31..0] RW (@ 0x5000081C) GPIO port configuration lock register
// ( (unsigned int)((GPIOC_LCKR >> 0) & 0xFFFFFFFF), ((GPIOC_LCKR = (GPIOC_LCKR & ~(0x101FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x101FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_LCKR_LCK0
// - SFDITEM_FIELD__GPIOC_LCKR_LCK1
// - SFDITEM_FIELD__GPIOC_LCKR_LCK2
// - SFDITEM_FIELD__GPIOC_LCKR_LCK3
// - SFDITEM_FIELD__GPIOC_LCKR_LCK4
// - SFDITEM_FIELD__GPIOC_LCKR_LCK5
// - SFDITEM_FIELD__GPIOC_LCKR_LCK6
// - SFDITEM_FIELD__GPIOC_LCKR_LCK7
// - SFDITEM_FIELD__GPIOC_LCKR_LCK8
// - SFDITEM_FIELD__GPIOC_LCKR_LCKK
//
//
// ---------------------------- Register Item Address: GPIOC_AFRL -------------------------------
// SVD Line: 2568
unsigned int GPIOC_AFRL __AT (0x50000820);
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL0 ---------------------------------
// SVD Line: 2574
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// AFSEL0
//
// [Bits 3..0] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 0) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL1 ---------------------------------
// SVD Line: 2579
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
// AFSEL1
//
// [Bits 7..4] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 4) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL2 ---------------------------------
// SVD Line: 2584
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL2
// AFSEL2
//
// [Bits 11..8] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 8) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL3 ---------------------------------
// SVD Line: 2589
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL3
// AFSEL3
//
// [Bits 15..12] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 12) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL4 ---------------------------------
// SVD Line: 2594
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL4
// AFSEL4
//
// [Bits 19..16] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 16) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL5 ---------------------------------
// SVD Line: 2599
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL5
// AFSEL5
//
// [Bits 23..20] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 20) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL6 ---------------------------------
// SVD Line: 2604
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL6
// AFSEL6
//
// [Bits 27..24] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 24) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRL_AFSEL7 ---------------------------------
// SVD Line: 2609
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL7
// AFSEL7
//
// [Bits 31..28] RW (@ 0x50000820) Alternate function selection for port x bit y (y = 0..7)
//
// ( (unsigned char)((GPIOC_AFRL >> 28) & 0xF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_AFRL -----------------------------------
// SVD Line: 2568
// SFDITEM_REG__GPIOC_AFRL
// AFRL
//
// [Bits 31..0] RW (@ 0x50000820) GPIO alternate function low register
// ( (unsigned int)((GPIOC_AFRL >> 0) & 0xFFFFFFFF), ((GPIOC_AFRL = (GPIOC_AFRL & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL0
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL1
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL2
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL3
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL4
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL5
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL6
// - SFDITEM_FIELD__GPIOC_AFRL_AFSEL7
//
//
// ---------------------------- Register Item Address: GPIOC_AFRH -------------------------------
// SVD Line: 2616
unsigned int GPIOC_AFRH __AT (0x50000824);
// ------------------------------ Field Item: GPIOC_AFRH_AFSEL8 ---------------------------------
// SVD Line: 2622
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL8
// AFSEL8
//
// [Bits 3..0] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 0) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: GPIOC_AFRH_AFSEL9 ---------------------------------
// SVD Line: 2627
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL9
// AFSEL9
//
// [Bits 7..4] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 4) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL10 ---------------------------------
// SVD Line: 2632
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL10
// AFSEL10
//
// [Bits 11..8] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 8) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL11 ---------------------------------
// SVD Line: 2637
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL11
// AFSEL11
//
// [Bits 15..12] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 12) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL12 ---------------------------------
// SVD Line: 2642
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL12
// AFSEL12
//
// [Bits 19..16] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 16) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL13 ---------------------------------
// SVD Line: 2647
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL13
// AFSEL13
//
// [Bits 23..20] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 20) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 20 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 20 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL14 ---------------------------------
// SVD Line: 2652
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL14
// AFSEL14
//
// [Bits 27..24] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 24) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 24 ) ) ))
//
//
//
// ----------------------------- Field Item: GPIOC_AFRH_AFSEL15 ---------------------------------
// SVD Line: 2657
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL15
// AFSEL15
//
// [Bits 31..28] RW (@ 0x50000824) Alternate function selection for port x bit y (y = 8..15)
//
// ( (unsigned char)((GPIOC_AFRH >> 28) & 0xF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFUL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 28 ) ) ))
//
//
//
// ------------------------------- Register RTree: GPIOC_AFRH -----------------------------------
// SVD Line: 2616
// SFDITEM_REG__GPIOC_AFRH
// AFRH
//
// [Bits 31..0] RW (@ 0x50000824) GPIO alternate function high register
// ( (unsigned int)((GPIOC_AFRH >> 0) & 0xFFFFFFFF), ((GPIOC_AFRH = (GPIOC_AFRH & ~(0xFFFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL8
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL9
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL10
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL11
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL12
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL13
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL14
// - SFDITEM_FIELD__GPIOC_AFRH_AFSEL15
//
//
// ---------------------------- Register Item Address: GPIOC_BRR --------------------------------
// SVD Line: 2664
unsigned int GPIOC_BRR __AT (0x50000828);
// -------------------------------- Field Item: GPIOC_BRR_BR0 -----------------------------------
// SVD Line: 2671
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// BR0
//
// [Bit 0] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR0
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR1 -----------------------------------
// SVD Line: 2676
// - SFDITEM_FIELD__GPIOC_BRR_BR1
// BR1
//
// [Bit 1] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR1
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR2 -----------------------------------
// SVD Line: 2681
// - SFDITEM_FIELD__GPIOC_BRR_BR2
// BR2
//
// [Bit 2] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR2
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR3 -----------------------------------
// SVD Line: 2686
// - SFDITEM_FIELD__GPIOC_BRR_BR3
// BR3
//
// [Bit 3] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR3
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR4 -----------------------------------
// SVD Line: 2691
// - SFDITEM_FIELD__GPIOC_BRR_BR4
// BR4
//
// [Bit 4] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR4
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR5 -----------------------------------
// SVD Line: 2696
// - SFDITEM_FIELD__GPIOC_BRR_BR5
// BR5
//
// [Bit 5] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR5
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR6 -----------------------------------
// SVD Line: 2701
// - SFDITEM_FIELD__GPIOC_BRR_BR6
// BR6
//
// [Bit 6] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR6
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR7 -----------------------------------
// SVD Line: 2706
// - SFDITEM_FIELD__GPIOC_BRR_BR7
// BR7
//
// [Bit 7] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR7
//
//
//
// -------------------------------- Field Item: GPIOC_BRR_BR8 -----------------------------------
// SVD Line: 2711
// - SFDITEM_FIELD__GPIOC_BRR_BR8
// BR8
//
// [Bit 8] WO (@ 0x50000828) Port Reset bit
//
// ( (unsigned int) GPIOC_BRR )
// BR8
//
//
//
// -------------------------------- Register RTree: GPIOC_BRR -----------------------------------
// SVD Line: 2664
// SFDITEM_REG__GPIOC_BRR
// BRR
//
// [Bits 31..0] WO (@ 0x50000828) port bit reset register
// ( (unsigned int)((GPIOC_BRR >> 0) & 0xFFFFFFFF), ((GPIOC_BRR = (GPIOC_BRR & ~(0x1FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1FF) << 0 ) ) ))
// - SFDITEM_FIELD__GPIOC_BRR_BR0
// - SFDITEM_FIELD__GPIOC_BRR_BR1
// - SFDITEM_FIELD__GPIOC_BRR_BR2
// - SFDITEM_FIELD__GPIOC_BRR_BR3
// - SFDITEM_FIELD__GPIOC_BRR_BR4
// - SFDITEM_FIELD__GPIOC_BRR_BR5
// - SFDITEM_FIELD__GPIOC_BRR_BR6
// - SFDITEM_FIELD__GPIOC_BRR_BR7
// - SFDITEM_FIELD__GPIOC_BRR_BR8
//
//
// --------------------------------- Peripheral View: GPIOC -------------------------------------
// SVD Line: 2720
// GPIOC
// GPIOC
// - SFDITEM_REG__GPIOC_MODER
// - SFDITEM_REG__GPIOC_OTYPER
// - SFDITEM_REG__GPIOC_OSPEEDR
// - SFDITEM_REG__GPIOC_PUPDR
// - SFDITEM_REG__GPIOC_IDR
// - SFDITEM_REG__GPIOC_ODR
// - SFDITEM_REG__GPIOC_BSRR
// - SFDITEM_REG__GPIOC_LCKR
// - SFDITEM_REG__GPIOC_AFRL
// - SFDITEM_REG__GPIOC_AFRH
// - SFDITEM_REG__GPIOC_BRR
//
//
// ----------------------------- Register Item Address: IWDG_KR ---------------------------------
// SVD Line: 2735
unsigned int IWDG_KR __AT (0x40003000);
// --------------------------------- Field Item: IWDG_KR_KEY ------------------------------------
// SVD Line: 2742
// - SFDITEM_FIELD__IWDG_KR_KEY
// KEY
//
// [Bits 15..0] WO (@ 0x40003000) Key value
//
// ( (unsigned short)((IWDG_KR >> 0) & 0x0), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_KR ------------------------------------
// SVD Line: 2735
// SFDITEM_REG__IWDG_KR
// KR
//
// [Bits 31..0] WO (@ 0x40003000) Key register (IWDG_KR)
// ( (unsigned int)((IWDG_KR >> 0) & 0xFFFFFFFF), ((IWDG_KR = (IWDG_KR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_KR_KEY
//
//
// ----------------------------- Register Item Address: IWDG_PR ---------------------------------
// SVD Line: 2749
unsigned int IWDG_PR __AT (0x40003004);
// --------------------------------- Field Item: IWDG_PR_PR -------------------------------------
// SVD Line: 2755
// - SFDITEM_FIELD__IWDG_PR_PR
// PR
//
// [Bits 2..0] RW (@ 0x40003004) Prescaler divider
//
// ( (unsigned char)((IWDG_PR >> 0) & 0x7), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// --------------------------------- Register RTree: IWDG_PR ------------------------------------
// SVD Line: 2749
// SFDITEM_REG__IWDG_PR
// PR
//
// [Bits 31..0] RW (@ 0x40003004) Prescaler register (IWDG_PR)
// ( (unsigned int)((IWDG_PR >> 0) & 0xFFFFFFFF), ((IWDG_PR = (IWDG_PR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_PR_PR
//
//
// ----------------------------- Register Item Address: IWDG_RLR --------------------------------
// SVD Line: 2762
unsigned int IWDG_RLR __AT (0x40003008);
// --------------------------------- Field Item: IWDG_RLR_RL ------------------------------------
// SVD Line: 2769
// - SFDITEM_FIELD__IWDG_RLR_RL
// RL
//
// [Bits 11..0] RW (@ 0x40003008) Watchdog counter reload value
//
// ( (unsigned short)((IWDG_RLR >> 0) & 0xFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: IWDG_RLR ------------------------------------
// SVD Line: 2762
// SFDITEM_REG__IWDG_RLR
// RLR
//
// [Bits 31..0] RW (@ 0x40003008) Reload register (IWDG_RLR)
// ( (unsigned int)((IWDG_RLR >> 0) & 0xFFFFFFFF), ((IWDG_RLR = (IWDG_RLR & ~(0xFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF) << 0 ) ) ))
// - SFDITEM_FIELD__IWDG_RLR_RL
//
//
// ----------------------------- Register Item Address: IWDG_SR ---------------------------------
// SVD Line: 2776
unsigned int IWDG_SR __AT (0x4000300C);
// --------------------------------- Field Item: IWDG_SR_PVU ------------------------------------
// SVD Line: 2783
// - SFDITEM_FIELD__IWDG_SR_PVU
// PVU
//
// [Bit 0] RO (@ 0x4000300C) Watchdog prescaler value update
//
// ( (unsigned int) IWDG_SR )
// PVU
//
//
//
// --------------------------------- Field Item: IWDG_SR_RVU ------------------------------------
// SVD Line: 2788
// - SFDITEM_FIELD__IWDG_SR_RVU
// RVU
//
// [Bit 1] RO (@ 0x4000300C) Watchdog counter reload value update
//
// ( (unsigned int) IWDG_SR )
// RVU
//
//
//
// --------------------------------- Register RTree: IWDG_SR ------------------------------------
// SVD Line: 2776
// SFDITEM_REG__IWDG_SR
// SR
//
// [Bits 31..0] RO (@ 0x4000300C) Status register (IWDG_SR)
// ( (unsigned int)((IWDG_SR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__IWDG_SR_PVU
// - SFDITEM_FIELD__IWDG_SR_RVU
//
//
// ---------------------------------- Peripheral View: IWDG -------------------------------------
// SVD Line: 2724
// IWDG
// IWDG
// - SFDITEM_REG__IWDG_KR
// - SFDITEM_REG__IWDG_PR
// - SFDITEM_REG__IWDG_RLR
// - SFDITEM_REG__IWDG_SR
//
//
// ---------------------------- Register Item Address: LPTIM1_ISR -------------------------------
// SVD Line: 2813
unsigned int LPTIM1_ISR __AT (0x40007C00);
// ------------------------------- Field Item: LPTIM1_ISR_ARRM ----------------------------------
// SVD Line: 2820
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// ARRM
//
// [Bit 1] RO (@ 0x40007C00) Autoreload match
//
// ( (unsigned int) LPTIM1_ISR )
// ARRM
//
//
//
// ------------------------------ Field Item: LPTIM1_ISR_ARROK ----------------------------------
// SVD Line: 2825
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
// ARROK
//
// [Bit 4] RO (@ 0x40007C00) Autoreload match update OK
//
// ( (unsigned int) LPTIM1_ISR )
// ARROK
//
//
//
// ------------------------------- Register RTree: LPTIM1_ISR -----------------------------------
// SVD Line: 2813
// SFDITEM_REG__LPTIM1_ISR
// ISR
//
// [Bits 31..0] RO (@ 0x40007C00) Interrupt and Status Register
// ( (unsigned int)((LPTIM1_ISR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_ISR_ARRM
// - SFDITEM_FIELD__LPTIM1_ISR_ARROK
//
//
// ---------------------------- Register Item Address: LPTIM1_ICR -------------------------------
// SVD Line: 2832
unsigned int LPTIM1_ICR __AT (0x40007C04);
// ------------------------------ Field Item: LPTIM1_ICR_ARRMCF ---------------------------------
// SVD Line: 2839
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// ARRMCF
//
// [Bit 1] WO (@ 0x40007C04) Autoreload match Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARRMCF
//
//
//
// ----------------------------- Field Item: LPTIM1_ICR_ARROKCF ---------------------------------
// SVD Line: 2844
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
// ARROKCF
//
// [Bit 4] WO (@ 0x40007C04) Autoreload match update OK Clear Flag
//
// ( (unsigned int) LPTIM1_ICR )
// ARROKCF
//
//
//
// ------------------------------- Register RTree: LPTIM1_ICR -----------------------------------
// SVD Line: 2832
// SFDITEM_REG__LPTIM1_ICR
// ICR
//
// [Bits 31..0] WO (@ 0x40007C04) Interrupt Clear Register
// ( (unsigned int)((LPTIM1_ICR >> 0) & 0xFFFFFFFF), ((LPTIM1_ICR = (LPTIM1_ICR & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ICR_ARRMCF
// - SFDITEM_FIELD__LPTIM1_ICR_ARROKCF
//
//
// ---------------------------- Register Item Address: LPTIM1_IER -------------------------------
// SVD Line: 2851
unsigned int LPTIM1_IER __AT (0x40007C08);
// ------------------------------ Field Item: LPTIM1_IER_ARRMIE ---------------------------------
// SVD Line: 2857
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// ARRMIE
//
// [Bit 1] RW (@ 0x40007C08) Autoreload matchInterrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARRMIE
//
//
//
// ----------------------------- Field Item: LPTIM1_IER_ARROKIE ---------------------------------
// SVD Line: 2862
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
// ARROKIE
//
// [Bit 4] RW (@ 0x40007C08) Autoreload match update OK Interrupt Enable
//
// ( (unsigned int) LPTIM1_IER )
// ARROKIE
//
//
//
// ------------------------------- Register RTree: LPTIM1_IER -----------------------------------
// SVD Line: 2851
// SFDITEM_REG__LPTIM1_IER
// IER
//
// [Bits 31..0] RW (@ 0x40007C08) Interrupt Enable Register
// ( (unsigned int)((LPTIM1_IER >> 0) & 0xFFFFFFFF), ((LPTIM1_IER = (LPTIM1_IER & ~(0x12UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x12) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_IER_ARRMIE
// - SFDITEM_FIELD__LPTIM1_IER_ARROKIE
//
//
// --------------------------- Register Item Address: LPTIM1_CFGR -------------------------------
// SVD Line: 2869
unsigned int LPTIM1_CFGR __AT (0x40007C0C);
// ------------------------------ Field Item: LPTIM1_CFGR_PRESC ---------------------------------
// SVD Line: 2875
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// PRESC
//
// [Bits 11..9] RW (@ 0x40007C0C) Clock prescaler
//
// ( (unsigned char)((LPTIM1_CFGR >> 9) & 0x7), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// ----------------------------- Field Item: LPTIM1_CFGR_PRELOAD --------------------------------
// SVD Line: 2880
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
// PRELOAD
//
// [Bit 22] RW (@ 0x40007C0C) Registers update mode
//
// ( (unsigned int) LPTIM1_CFGR )
// PRELOAD
//
//
//
// ------------------------------- Register RTree: LPTIM1_CFGR ----------------------------------
// SVD Line: 2869
// SFDITEM_REG__LPTIM1_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40007C0C) Configuration Register
// ( (unsigned int)((LPTIM1_CFGR >> 0) & 0xFFFFFFFF), ((LPTIM1_CFGR = (LPTIM1_CFGR & ~(0x400E00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x400E00) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CFGR_PRESC
// - SFDITEM_FIELD__LPTIM1_CFGR_PRELOAD
//
//
// ---------------------------- Register Item Address: LPTIM1_CR --------------------------------
// SVD Line: 2887
unsigned int LPTIM1_CR __AT (0x40007C10);
// ------------------------------ Field Item: LPTIM1_CR_ENABLE ----------------------------------
// SVD Line: 2893
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// ENABLE
//
// [Bit 0] RW (@ 0x40007C10) LPTIM Enable
//
// ( (unsigned int) LPTIM1_CR )
// ENABLE
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_SNGSTRT ---------------------------------
// SVD Line: 2898
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// SNGSTRT
//
// [Bit 1] RW (@ 0x40007C10) LPTIM start in single mode
//
// ( (unsigned int) LPTIM1_CR )
// SNGSTRT
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_CNTSTRT ---------------------------------
// SVD Line: 2903
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// CNTSTRT
//
// [Bit 2] RW (@ 0x40007C10) CNTSTRT
//
// ( (unsigned int) LPTIM1_CR )
// CNTSTRT
//
//
//
// ----------------------------- Field Item: LPTIM1_CR_COUNTRST ---------------------------------
// SVD Line: 2908
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// COUNTRST
//
// [Bit 3] RW (@ 0x40007C10) LPTIM counter reset
//
// ( (unsigned int) LPTIM1_CR )
// COUNTRST
//
//
//
// ------------------------------ Field Item: LPTIM1_CR_RSTARE ----------------------------------
// SVD Line: 2913
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
// RSTARE
//
// [Bit 4] RW (@ 0x40007C10) Reset after read enable
//
// ( (unsigned int) LPTIM1_CR )
// RSTARE
//
//
//
// -------------------------------- Register RTree: LPTIM1_CR -----------------------------------
// SVD Line: 2887
// SFDITEM_REG__LPTIM1_CR
// CR
//
// [Bits 31..0] RW (@ 0x40007C10) Control Register
// ( (unsigned int)((LPTIM1_CR >> 0) & 0xFFFFFFFF), ((LPTIM1_CR = (LPTIM1_CR & ~(0x1FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1F) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_CR_ENABLE
// - SFDITEM_FIELD__LPTIM1_CR_SNGSTRT
// - SFDITEM_FIELD__LPTIM1_CR_CNTSTRT
// - SFDITEM_FIELD__LPTIM1_CR_COUNTRST
// - SFDITEM_FIELD__LPTIM1_CR_RSTARE
//
//
// ---------------------------- Register Item Address: LPTIM1_ARR -------------------------------
// SVD Line: 2920
unsigned int LPTIM1_ARR __AT (0x40007C18);
// ------------------------------- Field Item: LPTIM1_ARR_ARR -----------------------------------
// SVD Line: 2927
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40007C18) Auto reload value
//
// ( (unsigned short)((LPTIM1_ARR >> 0) & 0xFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: LPTIM1_ARR -----------------------------------
// SVD Line: 2920
// SFDITEM_REG__LPTIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40007C18) Autoreload Register
// ( (unsigned int)((LPTIM1_ARR >> 0) & 0xFFFFFFFF), ((LPTIM1_ARR = (LPTIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__LPTIM1_ARR_ARR
//
//
// ---------------------------- Register Item Address: LPTIM1_CNT -------------------------------
// SVD Line: 2934
unsigned int LPTIM1_CNT __AT (0x40007C1C);
// ------------------------------- Field Item: LPTIM1_CNT_CNT -----------------------------------
// SVD Line: 2941
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RO (@ 0x40007C1C) Counter value
//
// ( (unsigned short)((LPTIM1_CNT >> 0) & 0xFFFF) )
//
//
//
// ------------------------------- Register RTree: LPTIM1_CNT -----------------------------------
// SVD Line: 2934
// SFDITEM_REG__LPTIM1_CNT
// CNT
//
// [Bits 31..0] RO (@ 0x40007C1C) Counter Register
// ( (unsigned int)((LPTIM1_CNT >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__LPTIM1_CNT_CNT
//
//
// --------------------------------- Peripheral View: LPTIM1 ------------------------------------
// SVD Line: 2797
// LPTIM1
// LPTIM1
// - SFDITEM_REG__LPTIM1_ISR
// - SFDITEM_REG__LPTIM1_ICR
// - SFDITEM_REG__LPTIM1_IER
// - SFDITEM_REG__LPTIM1_CFGR
// - SFDITEM_REG__LPTIM1_CR
// - SFDITEM_REG__LPTIM1_ARR
// - SFDITEM_REG__LPTIM1_CNT
//
//
// ----------------------------- Register Item Address: PWR_CR1 ---------------------------------
// SVD Line: 2961
unsigned int PWR_CR1 __AT (0x40007000);
// ------------------------------- Field Item: PWR_CR1_BIAS_CR ----------------------------------
// SVD Line: 2968
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR
// BIAS_CR
//
// [Bits 3..0] RW (@ 0x40007000) MR Bias current
//
// ( (unsigned char)((PWR_CR1 >> 0) & 0xF), ((PWR_CR1 = (PWR_CR1 & ~(0xFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 0 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_BIAS_CR_SEL --------------------------------
// SVD Line: 2973
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR_SEL
// BIAS_CR_SEL
//
// [Bit 4] RW (@ 0x40007000) MR Bias current selection
//
// ( (unsigned int) PWR_CR1 )
// BIAS_CR_SEL
//
//
//
// --------------------------------- Field Item: PWR_CR1_DBP ------------------------------------
// SVD Line: 2978
// - SFDITEM_FIELD__PWR_CR1_DBP
// DBP
//
// [Bit 7] RW (@ 0x40007000) Disable backup domain write protection
//
// ( (unsigned int) PWR_CR1 )
// DBP
//
//
//
// --------------------------------- Field Item: PWR_CR1_VOS ------------------------------------
// SVD Line: 2983
// - SFDITEM_FIELD__PWR_CR1_VOS
// VOS
//
// [Bits 9..8] RW (@ 0x40007000) Voltage scaling range selection
//
// ( (unsigned char)((PWR_CR1 >> 8) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_MRRDY_TIME ---------------------------------
// SVD Line: 2988
// - SFDITEM_FIELD__PWR_CR1_MRRDY_TIME
// MRRDY_TIME
//
// [Bits 11..10] RW (@ 0x40007000) Time selection wakeup from LP to VR
//
// ( (unsigned char)((PWR_CR1 >> 10) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_FLS_SLPTIME --------------------------------
// SVD Line: 2993
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// FLS_SLPTIME
//
// [Bits 13..12] RW (@ 0x40007000) Flash wait time after wakeup from the stop mode
//
// ( (unsigned char)((PWR_CR1 >> 12) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// --------------------------------- Field Item: PWR_CR1_LPR ------------------------------------
// SVD Line: 2998
// - SFDITEM_FIELD__PWR_CR1_LPR
// LPR
//
// [Bits 15..14] RW (@ 0x40007000) Low-power run
//
// ( (unsigned char)((PWR_CR1 >> 14) & 0x3), ((PWR_CR1 = (PWR_CR1 & ~(0x3UL << 14 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 14 ) ) ))
//
//
//
// ------------------------------ Field Item: PWR_CR1_SRAM_RETV ---------------------------------
// SVD Line: 3003
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV
// SRAM_RETV
//
// [Bits 18..16] RW (@ 0x40007000) SRAM retention voltage control
//
// ( (unsigned char)((PWR_CR1 >> 16) & 0x7), ((PWR_CR1 = (PWR_CR1 & ~(0x7UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 16 ) ) ))
//
//
//
// ----------------------------- Field Item: PWR_CR1_HSION_CTRL ---------------------------------
// SVD Line: 3008
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
// HSION_CTRL
//
// [Bit 19] RW (@ 0x40007000) HSI open time control
//
// ( (unsigned int) PWR_CR1 )
// HSION_CTRL
//
//
//
// --------------------------------- Register RTree: PWR_CR1 ------------------------------------
// SVD Line: 2961
// SFDITEM_REG__PWR_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40007000) Power control register 1
// ( (unsigned int)((PWR_CR1 >> 0) & 0xFFFFFFFF), ((PWR_CR1 = (PWR_CR1 & ~(0xFFF9FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFF9F) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR
// - SFDITEM_FIELD__PWR_CR1_BIAS_CR_SEL
// - SFDITEM_FIELD__PWR_CR1_DBP
// - SFDITEM_FIELD__PWR_CR1_VOS
// - SFDITEM_FIELD__PWR_CR1_MRRDY_TIME
// - SFDITEM_FIELD__PWR_CR1_FLS_SLPTIME
// - SFDITEM_FIELD__PWR_CR1_LPR
// - SFDITEM_FIELD__PWR_CR1_SRAM_RETV
// - SFDITEM_FIELD__PWR_CR1_HSION_CTRL
//
//
// ----------------------------- Register Item Address: PWR_CR2 ---------------------------------
// SVD Line: 3015
unsigned int PWR_CR2 __AT (0x40007004);
// -------------------------------- Field Item: PWR_CR2_FLTEN -----------------------------------
// SVD Line: 3022
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// FLTEN
//
// [Bit 8] RW (@ 0x40007004) Digital filter enable
//
// ( (unsigned int) PWR_CR2 )
// FLTEN
//
//
//
// ------------------------------ Field Item: PWR_CR2_FLT_TIME ----------------------------------
// SVD Line: 3027
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
// FLT_TIME
//
// [Bits 11..9] RW (@ 0x40007004) Digital filter time configuration
//
// ( (unsigned char)((PWR_CR2 >> 9) & 0x7), ((PWR_CR2 = (PWR_CR2 & ~(0x7UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 9 ) ) ))
//
//
//
// --------------------------------- Register RTree: PWR_CR2 ------------------------------------
// SVD Line: 3015
// SFDITEM_REG__PWR_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40007004) Power control register 2
// ( (unsigned int)((PWR_CR2 >> 0) & 0xFFFFFFFF), ((PWR_CR2 = (PWR_CR2 & ~(0xF00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xF00) << 0 ) ) ))
// - SFDITEM_FIELD__PWR_CR2_FLTEN
// - SFDITEM_FIELD__PWR_CR2_FLT_TIME
//
//
// ---------------------------------- Peripheral View: PWR --------------------------------------
// SVD Line: 2950
// PWR
// PWR
// - SFDITEM_REG__PWR_CR1
// - SFDITEM_REG__PWR_CR2
//
//
// ------------------------------ Register Item Address: RCC_CR ---------------------------------
// SVD Line: 3052
unsigned int RCC_CR __AT (0x40021000);
// -------------------------------- Field Item: RCC_CR_HSION ------------------------------------
// SVD Line: 3059
// - SFDITEM_FIELD__RCC_CR_HSION
// HSION
//
// [Bit 8] RW (@ 0x40021000) HSI16 clock enable
//
// ( (unsigned int) RCC_CR )
// HSION
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIRDY -----------------------------------
// SVD Line: 3064
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// HSIRDY
//
// [Bit 10] RW (@ 0x40021000) HSI16 clock ready flag
//
// ( (unsigned int) RCC_CR )
// HSIRDY
//
//
//
// -------------------------------- Field Item: RCC_CR_HSIDIV -----------------------------------
// SVD Line: 3069
// - SFDITEM_FIELD__RCC_CR_HSIDIV
// HSIDIV
//
// [Bits 13..11] RW (@ 0x40021000) HSI16 clock division factor
//
// ( (unsigned char)((RCC_CR >> 11) & 0x7), ((RCC_CR = (RCC_CR & ~(0x7UL << 11 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 11 ) ) ))
//
//
//
// --------------------------------- Register RTree: RCC_CR -------------------------------------
// SVD Line: 3052
// SFDITEM_REG__RCC_CR
// CR
//
// [Bits 31..0] RW (@ 0x40021000) Clock control register
// ( (unsigned int)((RCC_CR >> 0) & 0xFFFFFFFF), ((RCC_CR = (RCC_CR & ~(0x3D00UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3D00) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CR_HSION
// - SFDITEM_FIELD__RCC_CR_HSIRDY
// - SFDITEM_FIELD__RCC_CR_HSIDIV
//
//
// ---------------------------- Register Item Address: RCC_ICSCR --------------------------------
// SVD Line: 3076
unsigned int RCC_ICSCR __AT (0x40021004);
// ----------------------------- Field Item: RCC_ICSCR_HSI_TRIM ---------------------------------
// SVD Line: 3083
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// HSI_TRIM
//
// [Bits 12..0] RW (@ 0x40021004) HSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 0) & 0x1FFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FFF) << 0 ) ) ))
//
//
//
// ------------------------------ Field Item: RCC_ICSCR_HSI_FS ----------------------------------
// SVD Line: 3088
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// HSI_FS
//
// [Bits 15..13] RW (@ 0x40021004) HSI frequency selection
//
// ( (unsigned char)((RCC_ICSCR >> 13) & 0x7), ((RCC_ICSCR = (RCC_ICSCR & ~(0x7UL << 13 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 13 ) ) ))
//
//
//
// ----------------------------- Field Item: RCC_ICSCR_LSI_TRIM ---------------------------------
// SVD Line: 3093
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// LSI_TRIM
//
// [Bits 24..16] RW (@ 0x40021004) LSI clock trimming
//
// ( (unsigned short)((RCC_ICSCR >> 16) & 0x1FF), ((RCC_ICSCR = (RCC_ICSCR & ~(0x1FFUL << 16 )) | ((unsigned long)(Gui_u16:GuiVal & 0x1FF) << 16 ) ) ))
//
//
//
// ---------------------------- Field Item: RCC_ICSCR_LSI_STARTUP -------------------------------
// SVD Line: 3098
// - SFDITEM_FIELD__RCC_ICSCR_LSI_STARTUP
// LSI_STARTUP
//
// [Bits 27..26] RW (@ 0x40021004) LSI startup time
//
// ( (unsigned char)((RCC_ICSCR >> 26) & 0x3), ((RCC_ICSCR = (RCC_ICSCR & ~(0x3UL << 26 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 26 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ICSCR -----------------------------------
// SVD Line: 3076
// SFDITEM_REG__RCC_ICSCR
// ICSCR
//
// [Bits 31..0] RW (@ 0x40021004) Internal clock sources calibration register
// ( (unsigned int)((RCC_ICSCR >> 0) & 0xFFFFFFFF), ((RCC_ICSCR = (RCC_ICSCR & ~(0xDFFFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xDFFFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ICSCR_HSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_HSI_FS
// - SFDITEM_FIELD__RCC_ICSCR_LSI_TRIM
// - SFDITEM_FIELD__RCC_ICSCR_LSI_STARTUP
//
//
// ----------------------------- Register Item Address: RCC_CFGR --------------------------------
// SVD Line: 3105
unsigned int RCC_CFGR __AT (0x40021008);
// --------------------------------- Field Item: RCC_CFGR_SW ------------------------------------
// SVD Line: 3111
// - SFDITEM_FIELD__RCC_CFGR_SW
// SW
//
// [Bits 2..0] RW (@ 0x40021008) System clock switch
//
// ( (unsigned char)((RCC_CFGR >> 0) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_SWS ------------------------------------
// SVD Line: 3116
// - SFDITEM_FIELD__RCC_CFGR_SWS
// SWS
//
// [Bits 5..3] RO (@ 0x40021008) System clock switch status
//
// ( (unsigned char)((RCC_CFGR >> 3) & 0x7) )
//
//
//
// -------------------------------- Field Item: RCC_CFGR_HPRE -----------------------------------
// SVD Line: 3122
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// HPRE
//
// [Bits 11..8] RW (@ 0x40021008) AHB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 8) & 0xF), ((RCC_CFGR = (RCC_CFGR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// -------------------------------- Field Item: RCC_CFGR_PPRE -----------------------------------
// SVD Line: 3127
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// PPRE
//
// [Bits 14..12] RW (@ 0x40021008) APB prescaler
//
// ( (unsigned char)((RCC_CFGR >> 12) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOSEL ----------------------------------
// SVD Line: 3132
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// MCOSEL
//
// [Bits 26..24] RW (@ 0x40021008) Microcontroller clock output
//
// ( (unsigned char)((RCC_CFGR >> 24) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 24 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 24 ) ) ))
//
//
//
// ------------------------------- Field Item: RCC_CFGR_MCOPRE ----------------------------------
// SVD Line: 3137
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
// MCOPRE
//
// [Bits 30..28] RW (@ 0x40021008) Microcontroller clock output prescaler
//
// ( (unsigned char)((RCC_CFGR >> 28) & 0x7), ((RCC_CFGR = (RCC_CFGR & ~(0x7UL << 28 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 28 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CFGR ------------------------------------
// SVD Line: 3105
// SFDITEM_REG__RCC_CFGR
// CFGR
//
// [Bits 31..0] RW (@ 0x40021008) Clock configuration register
// ( (unsigned int)((RCC_CFGR >> 0) & 0xFFFFFFFF), ((RCC_CFGR = (RCC_CFGR & ~(0x77007F07UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x77007F07) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CFGR_SW
// - SFDITEM_FIELD__RCC_CFGR_SWS
// - SFDITEM_FIELD__RCC_CFGR_HPRE
// - SFDITEM_FIELD__RCC_CFGR_PPRE
// - SFDITEM_FIELD__RCC_CFGR_MCOSEL
// - SFDITEM_FIELD__RCC_CFGR_MCOPRE
//
//
// ---------------------------- Register Item Address: RCC_ECSCR --------------------------------
// SVD Line: 3144
unsigned int RCC_ECSCR __AT (0x40021010);
// ---------------------------- Field Item: RCC_ECSCR_LSE_DRIVER --------------------------------
// SVD Line: 3150
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
// LSE_DRIVER
//
// [Bits 17..16] RW (@ 0x40021010) desc LSE_DRIVER
//
// ( (unsigned char)((RCC_ECSCR >> 16) & 0x3), ((RCC_ECSCR = (RCC_ECSCR & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_ECSCR -----------------------------------
// SVD Line: 3144
// SFDITEM_REG__RCC_ECSCR
// ECSCR
//
// [Bits 31..0] RW (@ 0x40021010) External clock source control register
// ( (unsigned int)((RCC_ECSCR >> 0) & 0xFFFFFFFF), ((RCC_ECSCR = (RCC_ECSCR & ~(0x30000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x30000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_ECSCR_LSE_DRIVER
//
//
// ----------------------------- Register Item Address: RCC_CIER --------------------------------
// SVD Line: 3157
unsigned int RCC_CIER __AT (0x40021018);
// ------------------------------ Field Item: RCC_CIER_LSIRDYIE ---------------------------------
// SVD Line: 3163
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// LSIRDYIE
//
// [Bit 0] RW (@ 0x40021018) LSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// LSIRDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_LSERDYIE ---------------------------------
// SVD Line: 3168
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// LSERDYIE
//
// [Bit 1] RW (@ 0x40021018) LSE ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// LSERDYIE
//
//
//
// ------------------------------ Field Item: RCC_CIER_HSIRDYIE ---------------------------------
// SVD Line: 3173
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
// HSIRDYIE
//
// [Bit 3] RW (@ 0x40021018) HSI ready interrupt enable
//
// ( (unsigned int) RCC_CIER )
// HSIRDYIE
//
//
//
// -------------------------------- Register RTree: RCC_CIER ------------------------------------
// SVD Line: 3157
// SFDITEM_REG__RCC_CIER
// CIER
//
// [Bits 31..0] RW (@ 0x40021018) Clock interrupt enable register
// ( (unsigned int)((RCC_CIER >> 0) & 0xFFFFFFFF), ((RCC_CIER = (RCC_CIER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CIER_LSIRDYIE
// - SFDITEM_FIELD__RCC_CIER_LSERDYIE
// - SFDITEM_FIELD__RCC_CIER_HSIRDYIE
//
//
// ----------------------------- Register Item Address: RCC_CIFR --------------------------------
// SVD Line: 3180
unsigned int RCC_CIFR __AT (0x4002101C);
// ------------------------------ Field Item: RCC_CIFR_LSIRDYF ----------------------------------
// SVD Line: 3187
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// LSIRDYF
//
// [Bit 0] RO (@ 0x4002101C) LSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSERDYF ----------------------------------
// SVD Line: 3192
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// LSERDYF
//
// [Bit 2] RO (@ 0x4002101C) LSE ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSERDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_HSIRDYF ----------------------------------
// SVD Line: 3197
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// HSIRDYF
//
// [Bit 3] RO (@ 0x4002101C) HSI ready interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// HSIRDYF
//
//
//
// ------------------------------ Field Item: RCC_CIFR_LSECSSF ----------------------------------
// SVD Line: 3202
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
// LSECSSF
//
// [Bit 9] RO (@ 0x4002101C) LSE clock secure system interrupt flag
//
// ( (unsigned int) RCC_CIFR )
// LSECSSF
//
//
//
// -------------------------------- Register RTree: RCC_CIFR ------------------------------------
// SVD Line: 3180
// SFDITEM_REG__RCC_CIFR
// CIFR
//
// [Bits 31..0] RO (@ 0x4002101C) Clock interrupt flag register
// ( (unsigned int)((RCC_CIFR >> 0) & 0xFFFFFFFF) )
// - SFDITEM_FIELD__RCC_CIFR_LSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSERDYF
// - SFDITEM_FIELD__RCC_CIFR_HSIRDYF
// - SFDITEM_FIELD__RCC_CIFR_LSECSSF
//
//
// ----------------------------- Register Item Address: RCC_CICR --------------------------------
// SVD Line: 3209
unsigned int RCC_CICR __AT (0x40021020);
// ------------------------------ Field Item: RCC_CICR_LSIRDYC ----------------------------------
// SVD Line: 3216
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// LSIRDYC
//
// [Bit 0] WO (@ 0x40021020) LSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// LSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSERDYC ----------------------------------
// SVD Line: 3221
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// LSERDYC
//
// [Bit 1] WO (@ 0x40021020) LSE ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// LSERDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_HSIRDYC ----------------------------------
// SVD Line: 3226
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// HSIRDYC
//
// [Bit 3] WO (@ 0x40021020) HSI ready interrupt clear
//
// ( (unsigned int) RCC_CICR )
// HSIRDYC
//
//
//
// ------------------------------ Field Item: RCC_CICR_LSECSSC ----------------------------------
// SVD Line: 3231
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
// LSECSSC
//
// [Bit 9] WO (@ 0x40021020) LSE clock secure system interrupt flag clear
//
// ( (unsigned int) RCC_CICR )
// LSECSSC
//
//
//
// -------------------------------- Register RTree: RCC_CICR ------------------------------------
// SVD Line: 3209
// SFDITEM_REG__RCC_CICR
// CICR
//
// [Bits 31..0] WO (@ 0x40021020) Clock interrupt clear register
// ( (unsigned int)((RCC_CICR >> 0) & 0xFFFFFFFF), ((RCC_CICR = (RCC_CICR & ~(0x20BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x20B) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CICR_LSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSERDYC
// - SFDITEM_FIELD__RCC_CICR_HSIRDYC
// - SFDITEM_FIELD__RCC_CICR_LSECSSC
//
//
// --------------------------- Register Item Address: RCC_IOPRSTR -------------------------------
// SVD Line: 3238
unsigned int RCC_IOPRSTR __AT (0x40021024);
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOARST --------------------------------
// SVD Line: 3244
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// GPIOARST
//
// [Bit 0] RW (@ 0x40021024) I/O port A reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOARST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOBRST --------------------------------
// SVD Line: 3249
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// GPIOBRST
//
// [Bit 1] RW (@ 0x40021024) I/O port B reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOBRST
//
//
//
// ---------------------------- Field Item: RCC_IOPRSTR_GPIOCRST --------------------------------
// SVD Line: 3254
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
// GPIOCRST
//
// [Bit 2] RW (@ 0x40021024) I/O port C reset
//
// ( (unsigned int) RCC_IOPRSTR )
// GPIOCRST
//
//
//
// ------------------------------- Register RTree: RCC_IOPRSTR ----------------------------------
// SVD Line: 3238
// SFDITEM_REG__RCC_IOPRSTR
// IOPRSTR
//
// [Bits 31..0] RW (@ 0x40021024) GPIO reset register
// ( (unsigned int)((RCC_IOPRSTR >> 0) & 0xFFFFFFFF), ((RCC_IOPRSTR = (RCC_IOPRSTR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOARST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOBRST
// - SFDITEM_FIELD__RCC_IOPRSTR_GPIOCRST
//
//
// --------------------------- Register Item Address: RCC_AHBRSTR -------------------------------
// SVD Line: 3261
unsigned int RCC_AHBRSTR __AT (0x40021028);
// ----------------------------- Field Item: RCC_AHBRSTR_DMARST ---------------------------------
// SVD Line: 3267
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// DMARST
//
// [Bit 0] RW (@ 0x40021028) DMA reset
//
// ( (unsigned int) RCC_AHBRSTR )
// DMARST
//
//
//
// ---------------------------- Field Item: RCC_AHBRSTR_FLASHRST --------------------------------
// SVD Line: 3272
// - SFDITEM_FIELD__RCC_AHBRSTR_FLASHRST
// FLASHRST
//
// [Bit 8] RW (@ 0x40021028) FLASH reset
//
// ( (unsigned int) RCC_AHBRSTR )
// FLASHRST
//
//
//
// ----------------------------- Field Item: RCC_AHBRSTR_CRCRST ---------------------------------
// SVD Line: 3277
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
// CRCRST
//
// [Bit 12] RW (@ 0x40021028) CRC reset
//
// ( (unsigned int) RCC_AHBRSTR )
// CRCRST
//
//
//
// ------------------------------- Register RTree: RCC_AHBRSTR ----------------------------------
// SVD Line: 3261
// SFDITEM_REG__RCC_AHBRSTR
// AHBRSTR
//
// [Bits 31..0] RW (@ 0x40021028) AHB peripheral reset register
// ( (unsigned int)((RCC_AHBRSTR >> 0) & 0xFFFFFFFF), ((RCC_AHBRSTR = (RCC_AHBRSTR & ~(0x1101UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1101) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBRSTR_DMARST
// - SFDITEM_FIELD__RCC_AHBRSTR_FLASHRST
// - SFDITEM_FIELD__RCC_AHBRSTR_CRCRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR1 ------------------------------
// SVD Line: 3284
unsigned int RCC_APBRSTR1 __AT (0x4002102C);
// ----------------------------- Field Item: RCC_APBRSTR1_DBGRST --------------------------------
// SVD Line: 3290
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// DBGRST
//
// [Bit 27] RW (@ 0x4002102C) Debug support reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// DBGRST
//
//
//
// ----------------------------- Field Item: RCC_APBRSTR1_PWRRST --------------------------------
// SVD Line: 3295
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// PWRRST
//
// [Bit 28] RW (@ 0x4002102C) Power interface reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// PWRRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR1_LPTIMRST -------------------------------
// SVD Line: 3300
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
// LPTIMRST
//
// [Bit 31] RW (@ 0x4002102C) Low Power Timer reset
//
// ( (unsigned int) RCC_APBRSTR1 )
// LPTIMRST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR1 ----------------------------------
// SVD Line: 3284
// SFDITEM_REG__RCC_APBRSTR1
// APBRSTR1
//
// [Bits 31..0] RW (@ 0x4002102C) APB peripheral reset register 1
// ( (unsigned int)((RCC_APBRSTR1 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR1 = (RCC_APBRSTR1 & ~(0x98000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98000000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR1_DBGRST
// - SFDITEM_FIELD__RCC_APBRSTR1_PWRRST
// - SFDITEM_FIELD__RCC_APBRSTR1_LPTIMRST
//
//
// --------------------------- Register Item Address: RCC_APBRSTR2 ------------------------------
// SVD Line: 3307
unsigned int RCC_APBRSTR2 __AT (0x40021030);
// --------------------------- Field Item: RCC_APBRSTR2_SYSCFGRST -------------------------------
// SVD Line: 3313
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// SYSCFGRST
//
// [Bit 0] RW (@ 0x40021030) SYSCFG and COMP reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// SYSCFGRST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM1RST --------------------------------
// SVD Line: 3318
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// TIM1RST
//
// [Bit 11] RW (@ 0x40021030) TIM1 timer reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM1RST
//
//
//
// ---------------------------- Field Item: RCC_APBRSTR2_TIM14RST -------------------------------
// SVD Line: 3323
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
// TIM14RST
//
// [Bit 15] RW (@ 0x40021030) TIM14 reset
//
// ( (unsigned int) RCC_APBRSTR2 )
// TIM14RST
//
//
//
// ------------------------------ Register RTree: RCC_APBRSTR2 ----------------------------------
// SVD Line: 3307
// SFDITEM_REG__RCC_APBRSTR2
// APBRSTR2
//
// [Bits 31..0] RW (@ 0x40021030) APB peripheral reset register 2
// ( (unsigned int)((RCC_APBRSTR2 >> 0) & 0xFFFFFFFF), ((RCC_APBRSTR2 = (RCC_APBRSTR2 & ~(0x8801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x8801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBRSTR2_SYSCFGRST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM1RST
// - SFDITEM_FIELD__RCC_APBRSTR2_TIM14RST
//
//
// ---------------------------- Register Item Address: RCC_IOPENR -------------------------------
// SVD Line: 3330
unsigned int RCC_IOPENR __AT (0x40021034);
// ----------------------------- Field Item: RCC_IOPENR_GPIOAEN ---------------------------------
// SVD Line: 3336
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// GPIOAEN
//
// [Bit 0] RW (@ 0x40021034) I/O port A clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOAEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOBEN ---------------------------------
// SVD Line: 3341
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// GPIOBEN
//
// [Bit 1] RW (@ 0x40021034) I/O port B clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOBEN
//
//
//
// ----------------------------- Field Item: RCC_IOPENR_GPIOCEN ---------------------------------
// SVD Line: 3346
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
// GPIOCEN
//
// [Bit 2] RW (@ 0x40021034) I/O port C clock enable
//
// ( (unsigned int) RCC_IOPENR )
// GPIOCEN
//
//
//
// ------------------------------- Register RTree: RCC_IOPENR -----------------------------------
// SVD Line: 3330
// SFDITEM_REG__RCC_IOPENR
// IOPENR
//
// [Bits 31..0] RW (@ 0x40021034) GPIO clock enable register
// ( (unsigned int)((RCC_IOPENR >> 0) & 0xFFFFFFFF), ((RCC_IOPENR = (RCC_IOPENR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_IOPENR_GPIOAEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOBEN
// - SFDITEM_FIELD__RCC_IOPENR_GPIOCEN
//
//
// ---------------------------- Register Item Address: RCC_AHBENR -------------------------------
// SVD Line: 3353
unsigned int RCC_AHBENR __AT (0x40021038);
// ------------------------------ Field Item: RCC_AHBENR_DMAEN ----------------------------------
// SVD Line: 3359
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// DMAEN
//
// [Bit 0] RW (@ 0x40021038) DMA interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// DMAEN
//
//
//
// ----------------------------- Field Item: RCC_AHBENR_FLASHEN ---------------------------------
// SVD Line: 3364
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// FLASHEN
//
// [Bit 8] RW (@ 0x40021038) Flash memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// FLASHEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_SRAMEN ---------------------------------
// SVD Line: 3369
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// SRAMEN
//
// [Bit 9] RW (@ 0x40021038) SRAM memory interface clock enable
//
// ( (unsigned int) RCC_AHBENR )
// SRAMEN
//
//
//
// ------------------------------ Field Item: RCC_AHBENR_CRCEN ----------------------------------
// SVD Line: 3374
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
// CRCEN
//
// [Bit 12] RW (@ 0x40021038) CRC clock enable
//
// ( (unsigned int) RCC_AHBENR )
// CRCEN
//
//
//
// ------------------------------- Register RTree: RCC_AHBENR -----------------------------------
// SVD Line: 3353
// SFDITEM_REG__RCC_AHBENR
// AHBENR
//
// [Bits 31..0] RW (@ 0x40021038) AHB peripheral clock enable register
// ( (unsigned int)((RCC_AHBENR >> 0) & 0xFFFFFFFF), ((RCC_AHBENR = (RCC_AHBENR & ~(0x1301UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x1301) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_AHBENR_DMAEN
// - SFDITEM_FIELD__RCC_AHBENR_FLASHEN
// - SFDITEM_FIELD__RCC_AHBENR_SRAMEN
// - SFDITEM_FIELD__RCC_AHBENR_CRCEN
//
//
// --------------------------- Register Item Address: RCC_APBENR1 -------------------------------
// SVD Line: 3381
unsigned int RCC_APBENR1 __AT (0x4002103C);
// ------------------------------ Field Item: RCC_APBENR1_DBGEN ---------------------------------
// SVD Line: 3387
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// DBGEN
//
// [Bit 27] RW (@ 0x4002103C) Debug support clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// DBGEN
//
//
//
// ------------------------------ Field Item: RCC_APBENR1_PWREN ---------------------------------
// SVD Line: 3392
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// PWREN
//
// [Bit 28] RW (@ 0x4002103C) Power interface clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// PWREN
//
//
//
// ----------------------------- Field Item: RCC_APBENR1_LPTIMEN --------------------------------
// SVD Line: 3397
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
// LPTIMEN
//
// [Bit 31] RW (@ 0x4002103C) LPTIM clock enable
//
// ( (unsigned int) RCC_APBENR1 )
// LPTIMEN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR1 ----------------------------------
// SVD Line: 3381
// SFDITEM_REG__RCC_APBENR1
// APBENR1
//
// [Bits 31..0] RW (@ 0x4002103C) APB peripheral clock enable register 1
// ( (unsigned int)((RCC_APBENR1 >> 0) & 0xFFFFFFFF), ((RCC_APBENR1 = (RCC_APBENR1 & ~(0x98000000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x98000000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR1_DBGEN
// - SFDITEM_FIELD__RCC_APBENR1_PWREN
// - SFDITEM_FIELD__RCC_APBENR1_LPTIMEN
//
//
// --------------------------- Register Item Address: RCC_APBENR2 -------------------------------
// SVD Line: 3404
unsigned int RCC_APBENR2 __AT (0x40021040);
// ---------------------------- Field Item: RCC_APBENR2_SYSCFGEN --------------------------------
// SVD Line: 3410
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// SYSCFGEN
//
// [Bit 0] RW (@ 0x40021040) SYSCFG, COMP and VREFBUF clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// SYSCFGEN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM1EN ---------------------------------
// SVD Line: 3415
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// TIM1EN
//
// [Bit 11] RW (@ 0x40021040) TIM1 timer clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_TIM14EN --------------------------------
// SVD Line: 3420
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// TIM14EN
//
// [Bit 15] RW (@ 0x40021040) TIM14 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// TIM14EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP1EN --------------------------------
// SVD Line: 3425
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// COMP1EN
//
// [Bit 21] RW (@ 0x40021040) COMP1 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP1EN
//
//
//
// ----------------------------- Field Item: RCC_APBENR2_COMP2EN --------------------------------
// SVD Line: 3430
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
// COMP2EN
//
// [Bit 22] RW (@ 0x40021040) COMP2 clock enable
//
// ( (unsigned int) RCC_APBENR2 )
// COMP2EN
//
//
//
// ------------------------------- Register RTree: RCC_APBENR2 ----------------------------------
// SVD Line: 3404
// SFDITEM_REG__RCC_APBENR2
// APBENR2
//
// [Bits 31..0] RW (@ 0x40021040) APB peripheral clock enable register 2
// ( (unsigned int)((RCC_APBENR2 >> 0) & 0xFFFFFFFF), ((RCC_APBENR2 = (RCC_APBENR2 & ~(0x608801UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x608801) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_APBENR2_SYSCFGEN
// - SFDITEM_FIELD__RCC_APBENR2_TIM1EN
// - SFDITEM_FIELD__RCC_APBENR2_TIM14EN
// - SFDITEM_FIELD__RCC_APBENR2_COMP1EN
// - SFDITEM_FIELD__RCC_APBENR2_COMP2EN
//
//
// ---------------------------- Register Item Address: RCC_CCIPR --------------------------------
// SVD Line: 3437
unsigned int RCC_CCIPR __AT (0x40021054);
// ----------------------------- Field Item: RCC_CCIPR_LPTIM1SEL --------------------------------
// SVD Line: 3443
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
// LPTIM1SEL
//
// [Bits 19..18] RW (@ 0x40021054) LPTIM1 clock source selection
//
// ( (unsigned char)((RCC_CCIPR >> 18) & 0x3), ((RCC_CCIPR = (RCC_CCIPR & ~(0x3UL << 18 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 18 ) ) ))
//
//
//
// -------------------------------- Register RTree: RCC_CCIPR -----------------------------------
// SVD Line: 3437
// SFDITEM_REG__RCC_CCIPR
// CCIPR
//
// [Bits 31..0] RW (@ 0x40021054) Peripherals independent clock configuration register
// ( (unsigned int)((RCC_CCIPR >> 0) & 0xFFFFFFFF), ((RCC_CCIPR = (RCC_CCIPR & ~(0xC0000UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xC0000) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CCIPR_LPTIM1SEL
//
//
// ----------------------------- Register Item Address: RCC_BDCR --------------------------------
// SVD Line: 3450
unsigned int RCC_BDCR __AT (0x4002105C);
// ------------------------------- Field Item: RCC_BDCR_LSEON -----------------------------------
// SVD Line: 3456
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// LSEON
//
// [Bit 0] RW (@ 0x4002105C) LSE oscillator enable
//
// ( (unsigned int) RCC_BDCR )
// LSEON
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSERDY ----------------------------------
// SVD Line: 3461
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// LSERDY
//
// [Bit 1] RW (@ 0x4002105C) LSE oscillator ready
//
// ( (unsigned int) RCC_BDCR )
// LSERDY
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSEBYP ----------------------------------
// SVD Line: 3466
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// LSEBYP
//
// [Bit 2] RW (@ 0x4002105C) LSE oscillator bypass
//
// ( (unsigned int) RCC_BDCR )
// LSEBYP
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSON ---------------------------------
// SVD Line: 3471
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// LSECSSON
//
// [Bit 5] RW (@ 0x4002105C) LSE CSS enable
//
// ( (unsigned int) RCC_BDCR )
// LSECSSON
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSECSSD ----------------------------------
// SVD Line: 3476
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// LSECSSD
//
// [Bit 6] RW (@ 0x4002105C) LSE CSS detect
//
// ( (unsigned int) RCC_BDCR )
// LSECSSD
//
//
//
// ------------------------------- Field Item: RCC_BDCR_LSCOEN ----------------------------------
// SVD Line: 3481
// - SFDITEM_FIELD__RCC_BDCR_LSCOEN
// LSCOEN
//
// [Bit 24] RW (@ 0x4002105C) Low-speed clock output (LSCO) enable
//
// ( (unsigned int) RCC_BDCR )
// LSCOEN
//
//
//
// ------------------------------ Field Item: RCC_BDCR_LSCOSEL ----------------------------------
// SVD Line: 3486
// - SFDITEM_FIELD__RCC_BDCR_LSCOSEL
// LSCOSEL
//
// [Bit 25] RW (@ 0x4002105C) Low-speed clock output selection
//
// ( (unsigned int) RCC_BDCR )
// LSCOSEL
//
//
//
// -------------------------------- Register RTree: RCC_BDCR ------------------------------------
// SVD Line: 3450
// SFDITEM_REG__RCC_BDCR
// BDCR
//
// [Bits 31..0] RW (@ 0x4002105C) RTC domain control register
// ( (unsigned int)((RCC_BDCR >> 0) & 0xFFFFFFFF), ((RCC_BDCR = (RCC_BDCR & ~(0x3000067UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3000067) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_BDCR_LSEON
// - SFDITEM_FIELD__RCC_BDCR_LSERDY
// - SFDITEM_FIELD__RCC_BDCR_LSEBYP
// - SFDITEM_FIELD__RCC_BDCR_LSECSSON
// - SFDITEM_FIELD__RCC_BDCR_LSECSSD
// - SFDITEM_FIELD__RCC_BDCR_LSCOEN
// - SFDITEM_FIELD__RCC_BDCR_LSCOSEL
//
//
// ----------------------------- Register Item Address: RCC_CSR ---------------------------------
// SVD Line: 3493
unsigned int RCC_CSR __AT (0x40021060);
// -------------------------------- Field Item: RCC_CSR_LSION -----------------------------------
// SVD Line: 3499
// - SFDITEM_FIELD__RCC_CSR_LSION
// LSION
//
// [Bit 0] RW (@ 0x40021060) LSI oscillator enable
//
// ( (unsigned int) RCC_CSR )
// LSION
//
//
//
// ------------------------------- Field Item: RCC_CSR_LSIRDY -----------------------------------
// SVD Line: 3504
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// LSIRDY
//
// [Bit 1] RW (@ 0x40021060) LSI oscillator ready
//
// ( (unsigned int) RCC_CSR )
// LSIRDY
//
//
//
// ---------------------------- Field Item: RCC_CSR_PINRST_FLTDIS -------------------------------
// SVD Line: 3509
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// PINRST_FLTDIS
//
// [Bit 8] RW (@ 0x40021060) desc PINRST_FLTDIS
//
// ( (unsigned int) RCC_CSR )
// PINRST_FLTDIS
//
//
//
// -------------------------------- Field Item: RCC_CSR_RMVF ------------------------------------
// SVD Line: 3514
// - SFDITEM_FIELD__RCC_CSR_RMVF
// RMVF
//
// [Bit 23] RW (@ 0x40021060) Remove reset flags
//
// ( (unsigned int) RCC_CSR )
// RMVF
//
//
//
// ------------------------------- Field Item: RCC_CSR_OBLRSTF ----------------------------------
// SVD Line: 3519
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// OBLRSTF
//
// [Bit 25] RW (@ 0x40021060) Option byte loader reset flag
//
// ( (unsigned int) RCC_CSR )
// OBLRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PINRSTF ----------------------------------
// SVD Line: 3524
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// PINRSTF
//
// [Bit 26] RW (@ 0x40021060) Pin reset flag
//
// ( (unsigned int) RCC_CSR )
// PINRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_PWRRSTF ----------------------------------
// SVD Line: 3529
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// PWRRSTF
//
// [Bit 27] RW (@ 0x40021060) BOR or POR/PDR flag
//
// ( (unsigned int) RCC_CSR )
// PWRRSTF
//
//
//
// ------------------------------- Field Item: RCC_CSR_SFTRSTF ----------------------------------
// SVD Line: 3534
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// SFTRSTF
//
// [Bit 28] RW (@ 0x40021060) Software reset flag
//
// ( (unsigned int) RCC_CSR )
// SFTRSTF
//
//
//
// ------------------------------ Field Item: RCC_CSR_IWDGRSTF ----------------------------------
// SVD Line: 3539
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
// IWDGRSTF
//
// [Bit 29] RW (@ 0x40021060) Independent window watchdog reset flag
//
// ( (unsigned int) RCC_CSR )
// IWDGRSTF
//
//
//
// --------------------------------- Register RTree: RCC_CSR ------------------------------------
// SVD Line: 3493
// SFDITEM_REG__RCC_CSR
// CSR
//
// [Bits 31..0] RW (@ 0x40021060) Control/status register
// ( (unsigned int)((RCC_CSR >> 0) & 0xFFFFFFFF), ((RCC_CSR = (RCC_CSR & ~(0x3E800103UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3E800103) << 0 ) ) ))
// - SFDITEM_FIELD__RCC_CSR_LSION
// - SFDITEM_FIELD__RCC_CSR_LSIRDY
// - SFDITEM_FIELD__RCC_CSR_PINRST_FLTDIS
// - SFDITEM_FIELD__RCC_CSR_RMVF
// - SFDITEM_FIELD__RCC_CSR_OBLRSTF
// - SFDITEM_FIELD__RCC_CSR_PINRSTF
// - SFDITEM_FIELD__RCC_CSR_PWRRSTF
// - SFDITEM_FIELD__RCC_CSR_SFTRSTF
// - SFDITEM_FIELD__RCC_CSR_IWDGRSTF
//
//
// ---------------------------------- Peripheral View: RCC --------------------------------------
// SVD Line: 3036
// RCC
// RCC
// - SFDITEM_REG__RCC_CR
// - SFDITEM_REG__RCC_ICSCR
// - SFDITEM_REG__RCC_CFGR
// - SFDITEM_REG__RCC_ECSCR
// - SFDITEM_REG__RCC_CIER
// - SFDITEM_REG__RCC_CIFR
// - SFDITEM_REG__RCC_CICR
// - SFDITEM_REG__RCC_IOPRSTR
// - SFDITEM_REG__RCC_AHBRSTR
// - SFDITEM_REG__RCC_APBRSTR1
// - SFDITEM_REG__RCC_APBRSTR2
// - SFDITEM_REG__RCC_IOPENR
// - SFDITEM_REG__RCC_AHBENR
// - SFDITEM_REG__RCC_APBENR1
// - SFDITEM_REG__RCC_APBENR2
// - SFDITEM_REG__RCC_CCIPR
// - SFDITEM_REG__RCC_BDCR
// - SFDITEM_REG__RCC_CSR
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR1 ------------------------------
// SVD Line: 3559
unsigned int SYSCFG_CFGR1 __AT (0x40010000);
// ---------------------------- Field Item: SYSCFG_CFGR1_MEM_MODE -------------------------------
// SVD Line: 3565
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
// MEM_MODE
//
// [Bits 1..0] RW (@ 0x40010000) Memory mapping selection bits
//
// ( (unsigned char)((SYSCFG_CFGR1 >> 0) & 0x3), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR1 ----------------------------------
// SVD Line: 3559
// SFDITEM_REG__SYSCFG_CFGR1
// CFGR1
//
// [Bits 31..0] RW (@ 0x40010000) SYSCFG configuration register 1
// ( (unsigned int)((SYSCFG_CFGR1 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR1 = (SYSCFG_CFGR1 & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR1_MEM_MODE
//
//
// --------------------------- Register Item Address: SYSCFG_CFGR2 ------------------------------
// SVD Line: 3572
unsigned int SYSCFG_CFGR2 __AT (0x40010018);
// -------------------------- Field Item: SYSCFG_CFGR2_LOCKUP_LOCK ------------------------------
// SVD Line: 3578
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// LOCKUP_LOCK
//
// [Bit 0] RW (@ 0x40010018) Cortex-M0+ LOCKUP bit enable bit
//
// ( (unsigned int) SYSCFG_CFGR2 )
// LOCKUP_LOCK
//
//
//
// -------------------------- Field Item: SYSCFG_CFGR2_ETR_SRC_TIM1 -----------------------------
// SVD Line: 3583
// - SFDITEM_FIELD__SYSCFG_CFGR2_ETR_SRC_TIM1
// ETR_SRC_TIM1
//
// [Bits 10..9] RW (@ 0x40010018) TIM1 ETR source selection
//
// ( (unsigned char)((SYSCFG_CFGR2 >> 9) & 0x3), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x3UL << 9 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 9 ) ) ))
//
//
//
// ------------------------------ Register RTree: SYSCFG_CFGR2 ----------------------------------
// SVD Line: 3572
// SFDITEM_REG__SYSCFG_CFGR2
// CFGR2
//
// [Bits 31..0] RW (@ 0x40010018) SYSCFG configuration register 2
// ( (unsigned int)((SYSCFG_CFGR2 >> 0) & 0xFFFFFFFF), ((SYSCFG_CFGR2 = (SYSCFG_CFGR2 & ~(0x601UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x601) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_CFGR2_LOCKUP_LOCK
// - SFDITEM_FIELD__SYSCFG_CFGR2_ETR_SRC_TIM1
//
//
// ------------------------- Register Item Address: SYSCFG_GPIO_ENS -----------------------------
// SVD Line: 3590
unsigned int SYSCFG_GPIO_ENS __AT (0x4001001C);
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PA_ENS -------------------------------
// SVD Line: 3595
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// PA_ENS
//
// [Bits 7..0] RW (@ 0x4001001C) desc PA_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 0) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PB_ENS -------------------------------
// SVD Line: 3600
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// PB_ENS
//
// [Bits 15..8] RW (@ 0x4001001C) desc PB_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 8) & 0xFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0xFFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: SYSCFG_GPIO_ENS_PC_ENS -------------------------------
// SVD Line: 3605
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
// PC_ENS
//
// [Bits 17..16] RW (@ 0x4001001C) desc PC_ENS
//
// ( (unsigned char)((SYSCFG_GPIO_ENS >> 16) & 0x3), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3UL << 16 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 16 ) ) ))
//
//
//
// ----------------------------- Register RTree: SYSCFG_GPIO_ENS --------------------------------
// SVD Line: 3590
// SFDITEM_REG__SYSCFG_GPIO_ENS
// GPIO_ENS
//
// [Bits 31..0] RW (@ 0x4001001C) desc GPIO_ENS
// ( (unsigned int)((SYSCFG_GPIO_ENS >> 0) & 0xFFFFFFFF), ((SYSCFG_GPIO_ENS = (SYSCFG_GPIO_ENS & ~(0x3FFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFFF) << 0 ) ) ))
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PA_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PB_ENS
// - SFDITEM_FIELD__SYSCFG_GPIO_ENS_PC_ENS
//
//
// --------------------------------- Peripheral View: SYSCFG ------------------------------------
// SVD Line: 3548
// SYSCFG
// SYSCFG
// - SFDITEM_REG__SYSCFG_CFGR1
// - SFDITEM_REG__SYSCFG_CFGR2
// - SFDITEM_REG__SYSCFG_GPIO_ENS
//
//
// ----------------------------- Register Item Address: TIM1_CR1 --------------------------------
// SVD Line: 3635
unsigned int TIM1_CR1 __AT (0x40012C00);
// -------------------------------- Field Item: TIM1_CR1_CEN ------------------------------------
// SVD Line: 3641
// - SFDITEM_FIELD__TIM1_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40012C00) desc CEN
//
// ( (unsigned int) TIM1_CR1 )
// CEN
//
//
//
// -------------------------------- Field Item: TIM1_CR1_UDIS -----------------------------------
// SVD Line: 3646
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40012C00) desc UDIS
//
// ( (unsigned int) TIM1_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_URS ------------------------------------
// SVD Line: 3651
// - SFDITEM_FIELD__TIM1_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40012C00) desc URS
//
// ( (unsigned int) TIM1_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM1_CR1_OPM ------------------------------------
// SVD Line: 3656
// - SFDITEM_FIELD__TIM1_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40012C00) desc OPM
//
// ( (unsigned int) TIM1_CR1 )
// OPM
//
//
//
// -------------------------------- Field Item: TIM1_CR1_DIR ------------------------------------
// SVD Line: 3661
// - SFDITEM_FIELD__TIM1_CR1_DIR
// DIR
//
// [Bit 4] RW (@ 0x40012C00) desc DIR
//
// ( (unsigned int) TIM1_CR1 )
// DIR
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CMS ------------------------------------
// SVD Line: 3666
// - SFDITEM_FIELD__TIM1_CR1_CMS
// CMS
//
// [Bits 6..5] RW (@ 0x40012C00) desc CMS
//
// ( (unsigned char)((TIM1_CR1 >> 5) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 5 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 5 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR1_ARPE -----------------------------------
// SVD Line: 3671
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40012C00) desc ARPE
//
// ( (unsigned int) TIM1_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM1_CR1_CKD ------------------------------------
// SVD Line: 3676
// - SFDITEM_FIELD__TIM1_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40012C00) desc CKD
//
// ( (unsigned char)((TIM1_CR1 >> 8) & 0x3), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CR1 ------------------------------------
// SVD Line: 3635
// SFDITEM_REG__TIM1_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40012C00) desc CR1
// ( (unsigned int)((TIM1_CR1 >> 0) & 0xFFFFFFFF), ((TIM1_CR1 = (TIM1_CR1 & ~(0x3FFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR1_CEN
// - SFDITEM_FIELD__TIM1_CR1_UDIS
// - SFDITEM_FIELD__TIM1_CR1_URS
// - SFDITEM_FIELD__TIM1_CR1_OPM
// - SFDITEM_FIELD__TIM1_CR1_DIR
// - SFDITEM_FIELD__TIM1_CR1_CMS
// - SFDITEM_FIELD__TIM1_CR1_ARPE
// - SFDITEM_FIELD__TIM1_CR1_CKD
//
//
// ----------------------------- Register Item Address: TIM1_CR2 --------------------------------
// SVD Line: 3683
unsigned int TIM1_CR2 __AT (0x40012C04);
// -------------------------------- Field Item: TIM1_CR2_CCPC -----------------------------------
// SVD Line: 3689
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// CCPC
//
// [Bit 0] RW (@ 0x40012C04) desc CCPC
//
// ( (unsigned int) TIM1_CR2 )
// CCPC
//
//
//
// -------------------------------- Field Item: TIM1_CR2_CCUS -----------------------------------
// SVD Line: 3694
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// CCUS
//
// [Bit 2] RW (@ 0x40012C04) desc CCUS
//
// ( (unsigned int) TIM1_CR2 )
// CCUS
//
//
//
// -------------------------------- Field Item: TIM1_CR2_MMS ------------------------------------
// SVD Line: 3699
// - SFDITEM_FIELD__TIM1_CR2_MMS
// MMS
//
// [Bits 6..4] RW (@ 0x40012C04) desc MMS
//
// ( (unsigned char)((TIM1_CR2 >> 4) & 0x7), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_CR2_TI1S -----------------------------------
// SVD Line: 3704
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// TI1S
//
// [Bit 7] RW (@ 0x40012C04) desc TI1S
//
// ( (unsigned int) TIM1_CR2 )
// TI1S
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS1 -----------------------------------
// SVD Line: 3709
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// OIS1
//
// [Bit 8] RW (@ 0x40012C04) desc OIS1
//
// ( (unsigned int) TIM1_CR2 )
// OIS1
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS1N -----------------------------------
// SVD Line: 3714
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// OIS1N
//
// [Bit 9] RW (@ 0x40012C04) desc OIS1N
//
// ( (unsigned int) TIM1_CR2 )
// OIS1N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS2 -----------------------------------
// SVD Line: 3719
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// OIS2
//
// [Bit 10] RW (@ 0x40012C04) desc OIS2
//
// ( (unsigned int) TIM1_CR2 )
// OIS2
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS2N -----------------------------------
// SVD Line: 3724
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// OIS2N
//
// [Bit 11] RW (@ 0x40012C04) desc OIS2N
//
// ( (unsigned int) TIM1_CR2 )
// OIS2N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS3 -----------------------------------
// SVD Line: 3729
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// OIS3
//
// [Bit 12] RW (@ 0x40012C04) desc OIS3
//
// ( (unsigned int) TIM1_CR2 )
// OIS3
//
//
//
// ------------------------------- Field Item: TIM1_CR2_OIS3N -----------------------------------
// SVD Line: 3734
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// OIS3N
//
// [Bit 13] RW (@ 0x40012C04) desc OIS3N
//
// ( (unsigned int) TIM1_CR2 )
// OIS3N
//
//
//
// -------------------------------- Field Item: TIM1_CR2_OIS4 -----------------------------------
// SVD Line: 3739
// - SFDITEM_FIELD__TIM1_CR2_OIS4
// OIS4
//
// [Bit 14] RW (@ 0x40012C04) desc OIS4
//
// ( (unsigned int) TIM1_CR2 )
// OIS4
//
//
//
// -------------------------------- Register RTree: TIM1_CR2 ------------------------------------
// SVD Line: 3683
// SFDITEM_REG__TIM1_CR2
// CR2
//
// [Bits 31..0] RW (@ 0x40012C04) desc CR2
// ( (unsigned int)((TIM1_CR2 >> 0) & 0xFFFFFFFF), ((TIM1_CR2 = (TIM1_CR2 & ~(0x7FF5UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7FF5) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CR2_CCPC
// - SFDITEM_FIELD__TIM1_CR2_CCUS
// - SFDITEM_FIELD__TIM1_CR2_MMS
// - SFDITEM_FIELD__TIM1_CR2_TI1S
// - SFDITEM_FIELD__TIM1_CR2_OIS1
// - SFDITEM_FIELD__TIM1_CR2_OIS1N
// - SFDITEM_FIELD__TIM1_CR2_OIS2
// - SFDITEM_FIELD__TIM1_CR2_OIS2N
// - SFDITEM_FIELD__TIM1_CR2_OIS3
// - SFDITEM_FIELD__TIM1_CR2_OIS3N
// - SFDITEM_FIELD__TIM1_CR2_OIS4
//
//
// ---------------------------- Register Item Address: TIM1_SMCR --------------------------------
// SVD Line: 3746
unsigned int TIM1_SMCR __AT (0x40012C08);
// -------------------------------- Field Item: TIM1_SMCR_SMS -----------------------------------
// SVD Line: 3752
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// SMS
//
// [Bits 2..0] RW (@ 0x40012C08) desc SMS
//
// ( (unsigned char)((TIM1_SMCR >> 0) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_OCCS -----------------------------------
// SVD Line: 3757
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// OCCS
//
// [Bit 3] RW (@ 0x40012C08) desc OCCS
//
// ( (unsigned int) TIM1_SMCR )
// OCCS
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_TS ------------------------------------
// SVD Line: 3762
// - SFDITEM_FIELD__TIM1_SMCR_TS
// TS
//
// [Bits 6..4] RW (@ 0x40012C08) desc TS
//
// ( (unsigned char)((TIM1_SMCR >> 4) & 0x7), ((TIM1_SMCR = (TIM1_SMCR & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_MSM -----------------------------------
// SVD Line: 3767
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// MSM
//
// [Bit 7] RW (@ 0x40012C08) desc MSM
//
// ( (unsigned int) TIM1_SMCR )
// MSM
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETF -----------------------------------
// SVD Line: 3772
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// ETF
//
// [Bits 11..8] RW (@ 0x40012C08) desc ETF
//
// ( (unsigned char)((TIM1_SMCR >> 8) & 0xF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFUL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_SMCR_ETPS -----------------------------------
// SVD Line: 3777
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// ETPS
//
// [Bits 13..12] RW (@ 0x40012C08) desc ETPS
//
// ( (unsigned char)((TIM1_SMCR >> 12) & 0x3), ((TIM1_SMCR = (TIM1_SMCR & ~(0x3UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 12 ) ) ))
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ECE -----------------------------------
// SVD Line: 3782
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// ECE
//
// [Bit 14] RW (@ 0x40012C08) desc ECE
//
// ( (unsigned int) TIM1_SMCR )
// ECE
//
//
//
// -------------------------------- Field Item: TIM1_SMCR_ETP -----------------------------------
// SVD Line: 3787
// - SFDITEM_FIELD__TIM1_SMCR_ETP
// ETP
//
// [Bit 15] RW (@ 0x40012C08) desc ETP
//
// ( (unsigned int) TIM1_SMCR )
// ETP
//
//
//
// -------------------------------- Register RTree: TIM1_SMCR -----------------------------------
// SVD Line: 3746
// SFDITEM_REG__TIM1_SMCR
// SMCR
//
// [Bits 31..0] RW (@ 0x40012C08) desc SMCR
// ( (unsigned int)((TIM1_SMCR >> 0) & 0xFFFFFFFF), ((TIM1_SMCR = (TIM1_SMCR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SMCR_SMS
// - SFDITEM_FIELD__TIM1_SMCR_OCCS
// - SFDITEM_FIELD__TIM1_SMCR_TS
// - SFDITEM_FIELD__TIM1_SMCR_MSM
// - SFDITEM_FIELD__TIM1_SMCR_ETF
// - SFDITEM_FIELD__TIM1_SMCR_ETPS
// - SFDITEM_FIELD__TIM1_SMCR_ECE
// - SFDITEM_FIELD__TIM1_SMCR_ETP
//
//
// ---------------------------- Register Item Address: TIM1_DIER --------------------------------
// SVD Line: 3794
unsigned int TIM1_DIER __AT (0x40012C0C);
// -------------------------------- Field Item: TIM1_DIER_UIE -----------------------------------
// SVD Line: 3800
// - SFDITEM_FIELD__TIM1_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x40012C0C) desc UIE
//
// ( (unsigned int) TIM1_DIER )
// UIE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC1IE ----------------------------------
// SVD Line: 3805
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x40012C0C) desc CC1IE
//
// ( (unsigned int) TIM1_DIER )
// CC1IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC2IE ----------------------------------
// SVD Line: 3810
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// CC2IE
//
// [Bit 2] RW (@ 0x40012C0C) desc CC2IE
//
// ( (unsigned int) TIM1_DIER )
// CC2IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC3IE ----------------------------------
// SVD Line: 3815
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// CC3IE
//
// [Bit 3] RW (@ 0x40012C0C) desc CC3IE
//
// ( (unsigned int) TIM1_DIER )
// CC3IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_CC4IE ----------------------------------
// SVD Line: 3820
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// CC4IE
//
// [Bit 4] RW (@ 0x40012C0C) desc CC4IE
//
// ( (unsigned int) TIM1_DIER )
// CC4IE
//
//
//
// ------------------------------- Field Item: TIM1_DIER_COMIE ----------------------------------
// SVD Line: 3825
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// COMIE
//
// [Bit 5] RW (@ 0x40012C0C) desc COMIE
//
// ( (unsigned int) TIM1_DIER )
// COMIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_TIE -----------------------------------
// SVD Line: 3830
// - SFDITEM_FIELD__TIM1_DIER_TIE
// TIE
//
// [Bit 6] RW (@ 0x40012C0C) desc TIE
//
// ( (unsigned int) TIM1_DIER )
// TIE
//
//
//
// -------------------------------- Field Item: TIM1_DIER_BIE -----------------------------------
// SVD Line: 3835
// - SFDITEM_FIELD__TIM1_DIER_BIE
// BIE
//
// [Bit 7] RW (@ 0x40012C0C) desc BIE
//
// ( (unsigned int) TIM1_DIER )
// BIE
//
//
//
// -------------------------------- Register RTree: TIM1_DIER -----------------------------------
// SVD Line: 3794
// SFDITEM_REG__TIM1_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x40012C0C) desc DIER
// ( (unsigned int)((TIM1_DIER >> 0) & 0xFFFFFFFF), ((TIM1_DIER = (TIM1_DIER & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_DIER_UIE
// - SFDITEM_FIELD__TIM1_DIER_CC1IE
// - SFDITEM_FIELD__TIM1_DIER_CC2IE
// - SFDITEM_FIELD__TIM1_DIER_CC3IE
// - SFDITEM_FIELD__TIM1_DIER_CC4IE
// - SFDITEM_FIELD__TIM1_DIER_COMIE
// - SFDITEM_FIELD__TIM1_DIER_TIE
// - SFDITEM_FIELD__TIM1_DIER_BIE
//
//
// ----------------------------- Register Item Address: TIM1_SR ---------------------------------
// SVD Line: 3842
unsigned int TIM1_SR __AT (0x40012C10);
// --------------------------------- Field Item: TIM1_SR_UIF ------------------------------------
// SVD Line: 3848
// - SFDITEM_FIELD__TIM1_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40012C10) desc UIF
//
// ( (unsigned int) TIM1_SR )
// UIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1IF -----------------------------------
// SVD Line: 3853
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40012C10) desc CC1IF
//
// ( (unsigned int) TIM1_SR )
// CC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2IF -----------------------------------
// SVD Line: 3858
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// CC2IF
//
// [Bit 2] RW (@ 0x40012C10) desc CC2IF
//
// ( (unsigned int) TIM1_SR )
// CC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3IF -----------------------------------
// SVD Line: 3863
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// CC3IF
//
// [Bit 3] RW (@ 0x40012C10) desc CC3IF
//
// ( (unsigned int) TIM1_SR )
// CC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4IF -----------------------------------
// SVD Line: 3868
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// CC4IF
//
// [Bit 4] RW (@ 0x40012C10) desc CC4IF
//
// ( (unsigned int) TIM1_SR )
// CC4IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_COMIF -----------------------------------
// SVD Line: 3873
// - SFDITEM_FIELD__TIM1_SR_COMIF
// COMIF
//
// [Bit 5] RW (@ 0x40012C10) desc COMIF
//
// ( (unsigned int) TIM1_SR )
// COMIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_TIF ------------------------------------
// SVD Line: 3878
// - SFDITEM_FIELD__TIM1_SR_TIF
// TIF
//
// [Bit 6] RW (@ 0x40012C10) desc TIF
//
// ( (unsigned int) TIM1_SR )
// TIF
//
//
//
// --------------------------------- Field Item: TIM1_SR_BIF ------------------------------------
// SVD Line: 3883
// - SFDITEM_FIELD__TIM1_SR_BIF
// BIF
//
// [Bit 7] RW (@ 0x40012C10) desc BIF
//
// ( (unsigned int) TIM1_SR )
// BIF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC1OF -----------------------------------
// SVD Line: 3888
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40012C10) desc CC1OF
//
// ( (unsigned int) TIM1_SR )
// CC1OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC2OF -----------------------------------
// SVD Line: 3893
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// CC2OF
//
// [Bit 10] RW (@ 0x40012C10) desc CC2OF
//
// ( (unsigned int) TIM1_SR )
// CC2OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC3OF -----------------------------------
// SVD Line: 3898
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// CC3OF
//
// [Bit 11] RW (@ 0x40012C10) desc CC3OF
//
// ( (unsigned int) TIM1_SR )
// CC3OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_CC4OF -----------------------------------
// SVD Line: 3903
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// CC4OF
//
// [Bit 12] RW (@ 0x40012C10) desc CC4OF
//
// ( (unsigned int) TIM1_SR )
// CC4OF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IR -----------------------------------
// SVD Line: 3908
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40012C10) desc IC1IR
//
// ( (unsigned int) TIM1_SR )
// IC1IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IR -----------------------------------
// SVD Line: 3913
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// IC2IR
//
// [Bit 17] RW (@ 0x40012C10) desc IC2IR
//
// ( (unsigned int) TIM1_SR )
// IC2IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IR -----------------------------------
// SVD Line: 3918
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// IC3IR
//
// [Bit 18] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC3IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IR -----------------------------------
// SVD Line: 3923
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// IC4IR
//
// [Bit 19] RW (@ 0x40012C10) desc IC3IR
//
// ( (unsigned int) TIM1_SR )
// IC4IR
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC1IF -----------------------------------
// SVD Line: 3928
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40012C10) desc IC1IF
//
// ( (unsigned int) TIM1_SR )
// IC1IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC2IF -----------------------------------
// SVD Line: 3933
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// IC2IF
//
// [Bit 21] RW (@ 0x40012C10) desc IC2IF
//
// ( (unsigned int) TIM1_SR )
// IC2IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC3IF -----------------------------------
// SVD Line: 3938
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// IC3IF
//
// [Bit 22] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC3IF
//
//
//
// -------------------------------- Field Item: TIM1_SR_IC4IF -----------------------------------
// SVD Line: 3943
// - SFDITEM_FIELD__TIM1_SR_IC4IF
// IC4IF
//
// [Bit 23] RW (@ 0x40012C10) desc IC3IF
//
// ( (unsigned int) TIM1_SR )
// IC4IF
//
//
//
// --------------------------------- Register RTree: TIM1_SR ------------------------------------
// SVD Line: 3842
// SFDITEM_REG__TIM1_SR
// SR
//
// [Bits 31..0] RW (@ 0x40012C10) desc SR
// ( (unsigned int)((TIM1_SR >> 0) & 0xFFFFFFFF), ((TIM1_SR = (TIM1_SR & ~(0xFF1EFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF1EFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_SR_UIF
// - SFDITEM_FIELD__TIM1_SR_CC1IF
// - SFDITEM_FIELD__TIM1_SR_CC2IF
// - SFDITEM_FIELD__TIM1_SR_CC3IF
// - SFDITEM_FIELD__TIM1_SR_CC4IF
// - SFDITEM_FIELD__TIM1_SR_COMIF
// - SFDITEM_FIELD__TIM1_SR_TIF
// - SFDITEM_FIELD__TIM1_SR_BIF
// - SFDITEM_FIELD__TIM1_SR_CC1OF
// - SFDITEM_FIELD__TIM1_SR_CC2OF
// - SFDITEM_FIELD__TIM1_SR_CC3OF
// - SFDITEM_FIELD__TIM1_SR_CC4OF
// - SFDITEM_FIELD__TIM1_SR_IC1IR
// - SFDITEM_FIELD__TIM1_SR_IC2IR
// - SFDITEM_FIELD__TIM1_SR_IC3IR
// - SFDITEM_FIELD__TIM1_SR_IC4IR
// - SFDITEM_FIELD__TIM1_SR_IC1IF
// - SFDITEM_FIELD__TIM1_SR_IC2IF
// - SFDITEM_FIELD__TIM1_SR_IC3IF
// - SFDITEM_FIELD__TIM1_SR_IC4IF
//
//
// ----------------------------- Register Item Address: TIM1_EGR --------------------------------
// SVD Line: 3950
unsigned int TIM1_EGR __AT (0x40012C14);
// --------------------------------- Field Item: TIM1_EGR_UG ------------------------------------
// SVD Line: 3957
// - SFDITEM_FIELD__TIM1_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40012C14) desc UG
//
// ( (unsigned int) TIM1_EGR )
// UG
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC1G -----------------------------------
// SVD Line: 3963
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40012C14) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM1_EGR )
// CC1G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC2G -----------------------------------
// SVD Line: 3969
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// CC2G
//
// [Bit 2] WO (@ 0x40012C14) desc CC2G
//
// ( (unsigned int) TIM1_EGR )
// CC2G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC3G -----------------------------------
// SVD Line: 3975
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// CC3G
//
// [Bit 3] WO (@ 0x40012C14) desc CC3G
//
// ( (unsigned int) TIM1_EGR )
// CC3G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_CC4G -----------------------------------
// SVD Line: 3981
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// CC4G
//
// [Bit 4] WO (@ 0x40012C14) desc CC4G
//
// ( (unsigned int) TIM1_EGR )
// CC4G
//
//
//
// -------------------------------- Field Item: TIM1_EGR_COMG -----------------------------------
// SVD Line: 3987
// - SFDITEM_FIELD__TIM1_EGR_COMG
// COMG
//
// [Bit 5] WO (@ 0x40012C14) desc COMG
//
// ( (unsigned int) TIM1_EGR )
// COMG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_TG ------------------------------------
// SVD Line: 3993
// - SFDITEM_FIELD__TIM1_EGR_TG
// TG
//
// [Bit 6] WO (@ 0x40012C14) desc TG
//
// ( (unsigned int) TIM1_EGR )
// TG
//
//
//
// --------------------------------- Field Item: TIM1_EGR_BG ------------------------------------
// SVD Line: 3999
// - SFDITEM_FIELD__TIM1_EGR_BG
// BG
//
// [Bit 7] WO (@ 0x40012C14) desc BG
//
// ( (unsigned int) TIM1_EGR )
// BG
//
//
//
// -------------------------------- Register RTree: TIM1_EGR ------------------------------------
// SVD Line: 3950
// SFDITEM_REG__TIM1_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40012C14) desc EGR
// ( (unsigned int)((TIM1_EGR >> 0) & 0xFFFFFFFF), ((TIM1_EGR = (TIM1_EGR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_EGR_UG
// - SFDITEM_FIELD__TIM1_EGR_CC1G
// - SFDITEM_FIELD__TIM1_EGR_CC2G
// - SFDITEM_FIELD__TIM1_EGR_CC3G
// - SFDITEM_FIELD__TIM1_EGR_CC4G
// - SFDITEM_FIELD__TIM1_EGR_COMG
// - SFDITEM_FIELD__TIM1_EGR_TG
// - SFDITEM_FIELD__TIM1_EGR_BG
//
//
// ------------------------ Register Item Address: TIM1_CCMR1_OUTPUT ----------------------------
// SVD Line: 4007
unsigned int TIM1_CCMR1_OUTPUT __AT (0x40012C18);
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC1S -------------------------------
// SVD Line: 4013
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 0) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1FE ------------------------------
// SVD Line: 4018
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// OC1FE
//
// [Bit 2] RW (@ 0x40012C18) desc OC1FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 4023
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40012C18) desc OC1PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1M -------------------------------
// SVD Line: 4028
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40012C18) desc OC1M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 4) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC1CE ------------------------------
// SVD Line: 4033
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// OC1CE
//
// [Bit 7] RW (@ 0x40012C18) desc OC1CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC1CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_CC2S -------------------------------
// SVD Line: 4038
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 8) & 0x3), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2FE ------------------------------
// SVD Line: 4043
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// OC2FE
//
// [Bit 10] RW (@ 0x40012C18) desc OC2FE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2PE ------------------------------
// SVD Line: 4048
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// OC2PE
//
// [Bit 11] RW (@ 0x40012C18) desc OC2PE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2M -------------------------------
// SVD Line: 4053
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// OC2M
//
// [Bits 14..12] RW (@ 0x40012C18) desc OC2M
//
// ( (unsigned char)((TIM1_CCMR1_OUTPUT >> 12) & 0x7), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_OUTPUT_OC2CE ------------------------------
// SVD Line: 4058
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
// OC2CE
//
// [Bit 15] RW (@ 0x40012C18) desc OC2CE
//
// ( (unsigned int) TIM1_CCMR1_OUTPUT )
// OC2CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_OUTPUT -------------------------------
// SVD Line: 4007
// SFDITEM_REG__TIM1_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:OUTPUT
// ( (unsigned int)((TIM1_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_OUTPUT = (TIM1_CCMR1_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC1CE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2FE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2PE
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2M
// - SFDITEM_FIELD__TIM1_CCMR1_OUTPUT_OC2CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR1_INPUT ----------------------------
// SVD Line: 4065
unsigned int TIM1_CCMR1_INPUT __AT (0x40012C18);
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 4072
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40012C18) desc CC1S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 0) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 4077
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40012C18) desc IC1PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 2) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 4082
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40012C18) desc IC1F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 4) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_CC2S -------------------------------
// SVD Line: 4087
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// CC2S
//
// [Bits 9..8] RW (@ 0x40012C18) desc CC2S
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 8) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR1_INPUT_IC2PSC ------------------------------
// SVD Line: 4092
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// IC2PSC
//
// [Bits 11..10] RW (@ 0x40012C18) desc IC2PSC
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 10) & 0x3), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR1_INPUT_IC2F -------------------------------
// SVD Line: 4097
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
// IC2F
//
// [Bits 15..12] RW (@ 0x40012C18) desc IC2F
//
// ( (unsigned char)((TIM1_CCMR1_INPUT >> 12) & 0xF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR1_INPUT --------------------------------
// SVD Line: 4065
// SFDITEM_REG__TIM1_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40012C18) desc CCMR1:INPUT
// ( (unsigned int)((TIM1_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR1_INPUT = (TIM1_CCMR1_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC1F
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_CC2S
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2PSC
// - SFDITEM_FIELD__TIM1_CCMR1_INPUT_IC2F
//
//
// ------------------------ Register Item Address: TIM1_CCMR2_OUTPUT ----------------------------
// SVD Line: 4104
unsigned int TIM1_CCMR2_OUTPUT __AT (0x40012C1C);
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC3S -------------------------------
// SVD Line: 4110
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 0) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3FE ------------------------------
// SVD Line: 4115
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// OC3FE
//
// [Bit 2] RW (@ 0x40012C1C) desc OC3FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3PE ------------------------------
// SVD Line: 4120
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// OC3PE
//
// [Bit 3] RW (@ 0x40012C1C) desc OC3PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3M -------------------------------
// SVD Line: 4125
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// OC3M
//
// [Bits 6..4] RW (@ 0x40012C1C) desc OC3M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 4) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC3CE ------------------------------
// SVD Line: 4130
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// OC3CE
//
// [Bit 7] RW (@ 0x40012C1C) desc OC3CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC3CE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_CC4S -------------------------------
// SVD Line: 4135
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 8) & 0x3), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4FE ------------------------------
// SVD Line: 4140
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// OC4FE
//
// [Bit 10] RW (@ 0x40012C1C) desc OC4FE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4FE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4PE ------------------------------
// SVD Line: 4145
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// OC4PE
//
// [Bit 11] RW (@ 0x40012C1C) desc OC4PE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4PE
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4M -------------------------------
// SVD Line: 4150
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// OC4M
//
// [Bits 14..12] RW (@ 0x40012C1C) desc OC4M
//
// ( (unsigned char)((TIM1_CCMR2_OUTPUT >> 12) & 0x7), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0x7UL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 12 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_OUTPUT_OC4CE ------------------------------
// SVD Line: 4155
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
// OC4CE
//
// [Bit 15] RW (@ 0x40012C1C) desc OC4CE
//
// ( (unsigned int) TIM1_CCMR2_OUTPUT )
// OC4CE
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_OUTPUT -------------------------------
// SVD Line: 4104
// SFDITEM_REG__TIM1_CCMR2_OUTPUT
// CCMR2_OUTPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:OUTPUT
// ( (unsigned int)((TIM1_CCMR2_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_OUTPUT = (TIM1_CCMR2_OUTPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC3CE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4FE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4PE
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4M
// - SFDITEM_FIELD__TIM1_CCMR2_OUTPUT_OC4CE
//
//
// ------------------------- Register Item Address: TIM1_CCMR2_INPUT ----------------------------
// SVD Line: 4162
unsigned int TIM1_CCMR2_INPUT __AT (0x40012C1C);
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC3S -------------------------------
// SVD Line: 4169
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// CC3S
//
// [Bits 1..0] RW (@ 0x40012C1C) desc CC3S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 0) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC3PSC ------------------------------
// SVD Line: 4174
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// IC3PSC
//
// [Bits 3..2] RW (@ 0x40012C1C) desc IC3PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 2) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC3F -------------------------------
// SVD Line: 4179
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// IC3F
//
// [Bits 7..4] RW (@ 0x40012C1C) desc IC3F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 4) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_CC4S -------------------------------
// SVD Line: 4184
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// CC4S
//
// [Bits 9..8] RW (@ 0x40012C1C) desc CC4S
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 8) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// --------------------------- Field Item: TIM1_CCMR2_INPUT_IC4PSC ------------------------------
// SVD Line: 4189
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// IC4PSC
//
// [Bits 11..10] RW (@ 0x40012C1C) desc IC4PSC
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 10) & 0x3), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0x3UL << 10 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 10 ) ) ))
//
//
//
// ---------------------------- Field Item: TIM1_CCMR2_INPUT_IC4F -------------------------------
// SVD Line: 4194
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
// IC4F
//
// [Bits 15..12] RW (@ 0x40012C1C) desc IC4F
//
// ( (unsigned char)((TIM1_CCMR2_INPUT >> 12) & 0xF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFUL << 12 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 12 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM1_CCMR2_INPUT --------------------------------
// SVD Line: 4162
// SFDITEM_REG__TIM1_CCMR2_INPUT
// CCMR2_INPUT
//
// [Bits 31..0] RW (@ 0x40012C1C) desc CCMR2:INPUT
// ( (unsigned int)((TIM1_CCMR2_INPUT >> 0) & 0xFFFFFFFF), ((TIM1_CCMR2_INPUT = (TIM1_CCMR2_INPUT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC3S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC3F
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_CC4S
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4PSC
// - SFDITEM_FIELD__TIM1_CCMR2_INPUT_IC4F
//
//
// ---------------------------- Register Item Address: TIM1_CCER --------------------------------
// SVD Line: 4201
unsigned int TIM1_CCER __AT (0x40012C20);
// ------------------------------- Field Item: TIM1_CCER_CC1E -----------------------------------
// SVD Line: 4207
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40012C20) desc CC1E
//
// ( (unsigned int) TIM1_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1P -----------------------------------
// SVD Line: 4212
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40012C20) desc CC1P
//
// ( (unsigned int) TIM1_CCER )
// CC1P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NE ----------------------------------
// SVD Line: 4217
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// CC1NE
//
// [Bit 2] RW (@ 0x40012C20) desc CC1NE
//
// ( (unsigned int) TIM1_CCER )
// CC1NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC1NP ----------------------------------
// SVD Line: 4222
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40012C20) desc CC1NP
//
// ( (unsigned int) TIM1_CCER )
// CC1NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2E -----------------------------------
// SVD Line: 4227
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// CC2E
//
// [Bit 4] RW (@ 0x40012C20) desc CC2E
//
// ( (unsigned int) TIM1_CCER )
// CC2E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2P -----------------------------------
// SVD Line: 4232
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// CC2P
//
// [Bit 5] RW (@ 0x40012C20) desc CC2P
//
// ( (unsigned int) TIM1_CCER )
// CC2P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NE ----------------------------------
// SVD Line: 4237
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// CC2NE
//
// [Bit 6] RW (@ 0x40012C20) desc CC2NE
//
// ( (unsigned int) TIM1_CCER )
// CC2NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC2NP ----------------------------------
// SVD Line: 4242
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// CC2NP
//
// [Bit 7] RW (@ 0x40012C20) desc CC2NP
//
// ( (unsigned int) TIM1_CCER )
// CC2NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3E -----------------------------------
// SVD Line: 4247
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// CC3E
//
// [Bit 8] RW (@ 0x40012C20) desc CC3E
//
// ( (unsigned int) TIM1_CCER )
// CC3E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3P -----------------------------------
// SVD Line: 4252
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// CC3P
//
// [Bit 9] RW (@ 0x40012C20) desc CC3P
//
// ( (unsigned int) TIM1_CCER )
// CC3P
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NE ----------------------------------
// SVD Line: 4257
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// CC3NE
//
// [Bit 10] RW (@ 0x40012C20) desc CC3NE
//
// ( (unsigned int) TIM1_CCER )
// CC3NE
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC3NP ----------------------------------
// SVD Line: 4262
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// CC3NP
//
// [Bit 11] RW (@ 0x40012C20) desc CC3NP
//
// ( (unsigned int) TIM1_CCER )
// CC3NP
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4E -----------------------------------
// SVD Line: 4267
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// CC4E
//
// [Bit 12] RW (@ 0x40012C20) desc CC4E
//
// ( (unsigned int) TIM1_CCER )
// CC4E
//
//
//
// ------------------------------- Field Item: TIM1_CCER_CC4P -----------------------------------
// SVD Line: 4272
// - SFDITEM_FIELD__TIM1_CCER_CC4P
// CC4P
//
// [Bit 13] RW (@ 0x40012C20) desc CC4P
//
// ( (unsigned int) TIM1_CCER )
// CC4P
//
//
//
// -------------------------------- Register RTree: TIM1_CCER -----------------------------------
// SVD Line: 4201
// SFDITEM_REG__TIM1_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40012C20) desc CCER
// ( (unsigned int)((TIM1_CCER >> 0) & 0xFFFFFFFF), ((TIM1_CCER = (TIM1_CCER & ~(0x3FFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3FFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCER_CC1E
// - SFDITEM_FIELD__TIM1_CCER_CC1P
// - SFDITEM_FIELD__TIM1_CCER_CC1NE
// - SFDITEM_FIELD__TIM1_CCER_CC1NP
// - SFDITEM_FIELD__TIM1_CCER_CC2E
// - SFDITEM_FIELD__TIM1_CCER_CC2P
// - SFDITEM_FIELD__TIM1_CCER_CC2NE
// - SFDITEM_FIELD__TIM1_CCER_CC2NP
// - SFDITEM_FIELD__TIM1_CCER_CC3E
// - SFDITEM_FIELD__TIM1_CCER_CC3P
// - SFDITEM_FIELD__TIM1_CCER_CC3NE
// - SFDITEM_FIELD__TIM1_CCER_CC3NP
// - SFDITEM_FIELD__TIM1_CCER_CC4E
// - SFDITEM_FIELD__TIM1_CCER_CC4P
//
//
// ----------------------------- Register Item Address: TIM1_CNT --------------------------------
// SVD Line: 4279
unsigned int TIM1_CNT __AT (0x40012C24);
// -------------------------------- Field Item: TIM1_CNT_CNT ------------------------------------
// SVD Line: 4285
// - SFDITEM_FIELD__TIM1_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40012C24) desc CNT
//
// ( (unsigned short)((TIM1_CNT >> 0) & 0xFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CNT ------------------------------------
// SVD Line: 4279
// SFDITEM_REG__TIM1_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40012C24) desc CNT
// ( (unsigned int)((TIM1_CNT >> 0) & 0xFFFFFFFF), ((TIM1_CNT = (TIM1_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CNT_CNT
//
//
// ----------------------------- Register Item Address: TIM1_PSC --------------------------------
// SVD Line: 4292
unsigned int TIM1_PSC __AT (0x40012C28);
// -------------------------------- Field Item: TIM1_PSC_PSC ------------------------------------
// SVD Line: 4298
// - SFDITEM_FIELD__TIM1_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40012C28) desc PSC
//
// ( (unsigned short)((TIM1_PSC >> 0) & 0xFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_PSC ------------------------------------
// SVD Line: 4292
// SFDITEM_REG__TIM1_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40012C28) desc PSC
// ( (unsigned int)((TIM1_PSC >> 0) & 0xFFFFFFFF), ((TIM1_PSC = (TIM1_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_PSC_PSC
//
//
// ----------------------------- Register Item Address: TIM1_ARR --------------------------------
// SVD Line: 4305
unsigned int TIM1_ARR __AT (0x40012C2C);
// -------------------------------- Field Item: TIM1_ARR_ARR ------------------------------------
// SVD Line: 4312
// - SFDITEM_FIELD__TIM1_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x40012C2C) desc ARR
//
// ( (unsigned short)((TIM1_ARR >> 0) & 0xFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_ARR ------------------------------------
// SVD Line: 4305
// SFDITEM_REG__TIM1_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x40012C2C) desc ARR
// ( (unsigned int)((TIM1_ARR >> 0) & 0xFFFFFFFF), ((TIM1_ARR = (TIM1_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_ARR_ARR
//
//
// ----------------------------- Register Item Address: TIM1_RCR --------------------------------
// SVD Line: 4319
unsigned int TIM1_RCR __AT (0x40012C30);
// -------------------------------- Field Item: TIM1_RCR_REP ------------------------------------
// SVD Line: 4326
// - SFDITEM_FIELD__TIM1_RCR_REP
// REP
//
// [Bits 7..0] RW (@ 0x40012C30) desc REP
//
// ( (unsigned char)((TIM1_RCR >> 0) & 0xFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_RCR ------------------------------------
// SVD Line: 4319
// SFDITEM_REG__TIM1_RCR
// RCR
//
// [Bits 31..0] RW (@ 0x40012C30) desc RCR
// ( (unsigned int)((TIM1_RCR >> 0) & 0xFFFFFFFF), ((TIM1_RCR = (TIM1_RCR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_RCR_REP
//
//
// ---------------------------- Register Item Address: TIM1_CCR1 --------------------------------
// SVD Line: 4333
unsigned int TIM1_CCR1 __AT (0x40012C34);
// ------------------------------- Field Item: TIM1_CCR1_CCR1 -----------------------------------
// SVD Line: 4339
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40012C34) desc CCR1
//
// ( (unsigned short)((TIM1_CCR1 >> 0) & 0xFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR1 -----------------------------------
// SVD Line: 4333
// SFDITEM_REG__TIM1_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40012C34) desc CCR1
// ( (unsigned int)((TIM1_CCR1 >> 0) & 0xFFFFFFFF), ((TIM1_CCR1 = (TIM1_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR1_CCR1
//
//
// ---------------------------- Register Item Address: TIM1_CCR2 --------------------------------
// SVD Line: 4346
unsigned int TIM1_CCR2 __AT (0x40012C38);
// ------------------------------- Field Item: TIM1_CCR2_CCR2 -----------------------------------
// SVD Line: 4352
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
// CCR2
//
// [Bits 15..0] RW (@ 0x40012C38) desc CCR2
//
// ( (unsigned short)((TIM1_CCR2 >> 0) & 0xFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR2 -----------------------------------
// SVD Line: 4346
// SFDITEM_REG__TIM1_CCR2
// CCR2
//
// [Bits 31..0] RW (@ 0x40012C38) desc CCR2
// ( (unsigned int)((TIM1_CCR2 >> 0) & 0xFFFFFFFF), ((TIM1_CCR2 = (TIM1_CCR2 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR2_CCR2
//
//
// ---------------------------- Register Item Address: TIM1_CCR3 --------------------------------
// SVD Line: 4359
unsigned int TIM1_CCR3 __AT (0x40012C3C);
// ------------------------------- Field Item: TIM1_CCR3_CCR3 -----------------------------------
// SVD Line: 4365
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
// CCR3
//
// [Bits 15..0] RW (@ 0x40012C3C) desc CCR3
//
// ( (unsigned short)((TIM1_CCR3 >> 0) & 0xFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR3 -----------------------------------
// SVD Line: 4359
// SFDITEM_REG__TIM1_CCR3
// CCR3
//
// [Bits 31..0] RW (@ 0x40012C3C) desc CCR3
// ( (unsigned int)((TIM1_CCR3 >> 0) & 0xFFFFFFFF), ((TIM1_CCR3 = (TIM1_CCR3 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR3_CCR3
//
//
// ---------------------------- Register Item Address: TIM1_CCR4 --------------------------------
// SVD Line: 4372
unsigned int TIM1_CCR4 __AT (0x40012C40);
// ------------------------------- Field Item: TIM1_CCR4_CCR4 -----------------------------------
// SVD Line: 4378
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
// CCR4
//
// [Bits 15..0] RW (@ 0x40012C40) desc CCR4
//
// ( (unsigned short)((TIM1_CCR4 >> 0) & 0xFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM1_CCR4 -----------------------------------
// SVD Line: 4372
// SFDITEM_REG__TIM1_CCR4
// CCR4
//
// [Bits 31..0] RW (@ 0x40012C40) desc CCR4
// ( (unsigned int)((TIM1_CCR4 >> 0) & 0xFFFFFFFF), ((TIM1_CCR4 = (TIM1_CCR4 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_CCR4_CCR4
//
//
// ---------------------------- Register Item Address: TIM1_BDTR --------------------------------
// SVD Line: 4385
unsigned int TIM1_BDTR __AT (0x40012C44);
// -------------------------------- Field Item: TIM1_BDTR_DTG -----------------------------------
// SVD Line: 4391
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// DTG
//
// [Bits 7..0] RW (@ 0x40012C44) desc DTG
//
// ( (unsigned char)((TIM1_BDTR >> 0) & 0xFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0xFF) << 0 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_LOCK -----------------------------------
// SVD Line: 4396
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// LOCK
//
// [Bits 9..8] RW (@ 0x40012C44) desc LOCK
//
// ( (unsigned char)((TIM1_BDTR >> 8) & 0x3), ((TIM1_BDTR = (TIM1_BDTR & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSI -----------------------------------
// SVD Line: 4401
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// OSSI
//
// [Bit 10] RW (@ 0x40012C44) desc OSSI
//
// ( (unsigned int) TIM1_BDTR )
// OSSI
//
//
//
// ------------------------------- Field Item: TIM1_BDTR_OSSR -----------------------------------
// SVD Line: 4406
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// OSSR
//
// [Bit 11] RW (@ 0x40012C44) desc OSSR
//
// ( (unsigned int) TIM1_BDTR )
// OSSR
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKE -----------------------------------
// SVD Line: 4411
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// BKE
//
// [Bit 12] RW (@ 0x40012C44) desc BKE
//
// ( (unsigned int) TIM1_BDTR )
// BKE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_BKP -----------------------------------
// SVD Line: 4416
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// BKP
//
// [Bit 13] RW (@ 0x40012C44) desc BKP
//
// ( (unsigned int) TIM1_BDTR )
// BKP
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_AOE -----------------------------------
// SVD Line: 4421
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// AOE
//
// [Bit 14] RW (@ 0x40012C44) desc AOE
//
// ( (unsigned int) TIM1_BDTR )
// AOE
//
//
//
// -------------------------------- Field Item: TIM1_BDTR_MOE -----------------------------------
// SVD Line: 4426
// - SFDITEM_FIELD__TIM1_BDTR_MOE
// MOE
//
// [Bit 15] RW (@ 0x40012C44) desc MOE
//
// ( (unsigned int) TIM1_BDTR )
// MOE
//
//
//
// -------------------------------- Register RTree: TIM1_BDTR -----------------------------------
// SVD Line: 4385
// SFDITEM_REG__TIM1_BDTR
// BDTR
//
// [Bits 31..0] RW (@ 0x40012C44) desc BDTR
// ( (unsigned int)((TIM1_BDTR >> 0) & 0xFFFFFFFF), ((TIM1_BDTR = (TIM1_BDTR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM1_BDTR_DTG
// - SFDITEM_FIELD__TIM1_BDTR_LOCK
// - SFDITEM_FIELD__TIM1_BDTR_OSSI
// - SFDITEM_FIELD__TIM1_BDTR_OSSR
// - SFDITEM_FIELD__TIM1_BDTR_BKE
// - SFDITEM_FIELD__TIM1_BDTR_BKP
// - SFDITEM_FIELD__TIM1_BDTR_AOE
// - SFDITEM_FIELD__TIM1_BDTR_MOE
//
//
// ---------------------------------- Peripheral View: TIM1 -------------------------------------
// SVD Line: 3614
// TIM1
// TIM1
// - SFDITEM_REG__TIM1_CR1
// - SFDITEM_REG__TIM1_CR2
// - SFDITEM_REG__TIM1_SMCR
// - SFDITEM_REG__TIM1_DIER
// - SFDITEM_REG__TIM1_SR
// - SFDITEM_REG__TIM1_EGR
// - SFDITEM_REG__TIM1_CCMR1_OUTPUT
// - SFDITEM_REG__TIM1_CCMR1_INPUT
// - SFDITEM_REG__TIM1_CCMR2_OUTPUT
// - SFDITEM_REG__TIM1_CCMR2_INPUT
// - SFDITEM_REG__TIM1_CCER
// - SFDITEM_REG__TIM1_CNT
// - SFDITEM_REG__TIM1_PSC
// - SFDITEM_REG__TIM1_ARR
// - SFDITEM_REG__TIM1_RCR
// - SFDITEM_REG__TIM1_CCR1
// - SFDITEM_REG__TIM1_CCR2
// - SFDITEM_REG__TIM1_CCR3
// - SFDITEM_REG__TIM1_CCR4
// - SFDITEM_REG__TIM1_BDTR
//
//
// ---------------------------- Register Item Address: TIM14_CR1 --------------------------------
// SVD Line: 4451
unsigned int TIM14_CR1 __AT (0x40002000);
// -------------------------------- Field Item: TIM14_CR1_CEN -----------------------------------
// SVD Line: 4457
// - SFDITEM_FIELD__TIM14_CR1_CEN
// CEN
//
// [Bit 0] RW (@ 0x40002000) desc CEN
//
// ( (unsigned int) TIM14_CR1 )
// CEN
//
//
//
// ------------------------------- Field Item: TIM14_CR1_UDIS -----------------------------------
// SVD Line: 4462
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// UDIS
//
// [Bit 1] RW (@ 0x40002000) desc UDIS
//
// ( (unsigned int) TIM14_CR1 )
// UDIS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_URS -----------------------------------
// SVD Line: 4467
// - SFDITEM_FIELD__TIM14_CR1_URS
// URS
//
// [Bit 2] RW (@ 0x40002000) desc URS
//
// ( (unsigned int) TIM14_CR1 )
// URS
//
//
//
// -------------------------------- Field Item: TIM14_CR1_OPM -----------------------------------
// SVD Line: 4472
// - SFDITEM_FIELD__TIM14_CR1_OPM
// OPM
//
// [Bit 3] RW (@ 0x40002000) desc OPM
//
// ( (unsigned int) TIM14_CR1 )
// OPM
//
//
//
// ------------------------------- Field Item: TIM14_CR1_ARPE -----------------------------------
// SVD Line: 4477
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// ARPE
//
// [Bit 7] RW (@ 0x40002000) desc ARPE
//
// ( (unsigned int) TIM14_CR1 )
// ARPE
//
//
//
// -------------------------------- Field Item: TIM14_CR1_CKD -----------------------------------
// SVD Line: 4482
// - SFDITEM_FIELD__TIM14_CR1_CKD
// CKD
//
// [Bits 9..8] RW (@ 0x40002000) desc CKD
//
// ( (unsigned char)((TIM14_CR1 >> 8) & 0x3), ((TIM14_CR1 = (TIM14_CR1 & ~(0x3UL << 8 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 8 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CR1 -----------------------------------
// SVD Line: 4451
// SFDITEM_REG__TIM14_CR1
// CR1
//
// [Bits 31..0] RW (@ 0x40002000) desc CR1
// ( (unsigned int)((TIM14_CR1 >> 0) & 0xFFFFFFFF), ((TIM14_CR1 = (TIM14_CR1 & ~(0x38FUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x38F) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CR1_CEN
// - SFDITEM_FIELD__TIM14_CR1_UDIS
// - SFDITEM_FIELD__TIM14_CR1_URS
// - SFDITEM_FIELD__TIM14_CR1_OPM
// - SFDITEM_FIELD__TIM14_CR1_ARPE
// - SFDITEM_FIELD__TIM14_CR1_CKD
//
//
// ---------------------------- Register Item Address: TIM14_DIER -------------------------------
// SVD Line: 4489
unsigned int TIM14_DIER __AT (0x4000200C);
// ------------------------------- Field Item: TIM14_DIER_UIE -----------------------------------
// SVD Line: 4495
// - SFDITEM_FIELD__TIM14_DIER_UIE
// UIE
//
// [Bit 0] RW (@ 0x4000200C) desc UIE
//
// ( (unsigned int) TIM14_DIER )
// UIE
//
//
//
// ------------------------------ Field Item: TIM14_DIER_CC1IE ----------------------------------
// SVD Line: 4500
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
// CC1IE
//
// [Bit 1] RW (@ 0x4000200C) desc CC1IE
//
// ( (unsigned int) TIM14_DIER )
// CC1IE
//
//
//
// ------------------------------- Register RTree: TIM14_DIER -----------------------------------
// SVD Line: 4489
// SFDITEM_REG__TIM14_DIER
// DIER
//
// [Bits 31..0] RW (@ 0x4000200C) desc DIER
// ( (unsigned int)((TIM14_DIER >> 0) & 0xFFFFFFFF), ((TIM14_DIER = (TIM14_DIER & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_DIER_UIE
// - SFDITEM_FIELD__TIM14_DIER_CC1IE
//
//
// ----------------------------- Register Item Address: TIM14_SR --------------------------------
// SVD Line: 4507
unsigned int TIM14_SR __AT (0x40002010);
// -------------------------------- Field Item: TIM14_SR_UIF ------------------------------------
// SVD Line: 4513
// - SFDITEM_FIELD__TIM14_SR_UIF
// UIF
//
// [Bit 0] RW (@ 0x40002010) desc UIF
//
// ( (unsigned int) TIM14_SR )
// UIF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1IF -----------------------------------
// SVD Line: 4518
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// CC1IF
//
// [Bit 1] RW (@ 0x40002010) desc CC1IF
//
// ( (unsigned int) TIM14_SR )
// CC1IF
//
//
//
// ------------------------------- Field Item: TIM14_SR_CC1OF -----------------------------------
// SVD Line: 4523
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// CC1OF
//
// [Bit 9] RW (@ 0x40002010) desc CC1OF
//
// ( (unsigned int) TIM14_SR )
// CC1OF
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IR -----------------------------------
// SVD Line: 4528
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// IC1IR
//
// [Bit 16] RW (@ 0x40002010) desc IC1IR
//
// ( (unsigned int) TIM14_SR )
// IC1IR
//
//
//
// ------------------------------- Field Item: TIM14_SR_IC1IF -----------------------------------
// SVD Line: 4533
// - SFDITEM_FIELD__TIM14_SR_IC1IF
// IC1IF
//
// [Bit 20] RW (@ 0x40002010) desc IC1IF
//
// ( (unsigned int) TIM14_SR )
// IC1IF
//
//
//
// -------------------------------- Register RTree: TIM14_SR ------------------------------------
// SVD Line: 4507
// SFDITEM_REG__TIM14_SR
// SR
//
// [Bits 31..0] RW (@ 0x40002010) desc SR
// ( (unsigned int)((TIM14_SR >> 0) & 0xFFFFFFFF), ((TIM14_SR = (TIM14_SR & ~(0x110203UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x110203) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_SR_UIF
// - SFDITEM_FIELD__TIM14_SR_CC1IF
// - SFDITEM_FIELD__TIM14_SR_CC1OF
// - SFDITEM_FIELD__TIM14_SR_IC1IR
// - SFDITEM_FIELD__TIM14_SR_IC1IF
//
//
// ---------------------------- Register Item Address: TIM14_EGR --------------------------------
// SVD Line: 4540
unsigned int TIM14_EGR __AT (0x40002014);
// -------------------------------- Field Item: TIM14_EGR_UG ------------------------------------
// SVD Line: 4547
// - SFDITEM_FIELD__TIM14_EGR_UG
// UG
//
// [Bit 0] WO (@ 0x40002014) desc UG
//
// ( (unsigned int) TIM14_EGR )
// UG
//
//
//
// ------------------------------- Field Item: TIM14_EGR_CC1G -----------------------------------
// SVD Line: 4553
// - SFDITEM_FIELD__TIM14_EGR_CC1G
// CC1G
//
// [Bit 1] WO (@ 0x40002014) Capture/Compare 1 Generation
//
// ( (unsigned int) TIM14_EGR )
// CC1G
//
//
//
// -------------------------------- Register RTree: TIM14_EGR -----------------------------------
// SVD Line: 4540
// SFDITEM_REG__TIM14_EGR
// EGR
//
// [Bits 31..0] WO (@ 0x40002014) desc EGR
// ( (unsigned int)((TIM14_EGR >> 0) & 0xFFFFFFFF), ((TIM14_EGR = (TIM14_EGR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_EGR_UG
// - SFDITEM_FIELD__TIM14_EGR_CC1G
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_OUTPUT ---------------------------
// SVD Line: 4561
unsigned int TIM14_CCMR1_OUTPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_CC1S ------------------------------
// SVD Line: 4567
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 0) & 0x3), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1PE ------------------------------
// SVD Line: 4572
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// OC1PE
//
// [Bit 3] RW (@ 0x40002018) desc OC1PE
//
// ( (unsigned int) TIM14_CCMR1_OUTPUT )
// OC1PE
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_OUTPUT_OC1M ------------------------------
// SVD Line: 4577
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
// OC1M
//
// [Bits 6..4] RW (@ 0x40002018) desc OC1M
//
// ( (unsigned char)((TIM14_CCMR1_OUTPUT >> 4) & 0x7), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7UL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0x7) << 4 ) ) ))
//
//
//
// --------------------------- Register RTree: TIM14_CCMR1_OUTPUT -------------------------------
// SVD Line: 4561
// SFDITEM_REG__TIM14_CCMR1_OUTPUT
// CCMR1_OUTPUT
//
// [Bits 31..0] RW (@ 0x40002018) desc CCMR1:OUTPUT
// ( (unsigned int)((TIM14_CCMR1_OUTPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_OUTPUT = (TIM14_CCMR1_OUTPUT & ~(0x7BUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x7B) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1PE
// - SFDITEM_FIELD__TIM14_CCMR1_OUTPUT_OC1M
//
//
// ------------------------ Register Item Address: TIM14_CCMR1_INPUT ----------------------------
// SVD Line: 4584
unsigned int TIM14_CCMR1_INPUT __AT (0x40002018);
// --------------------------- Field Item: TIM14_CCMR1_INPUT_CC1S -------------------------------
// SVD Line: 4591
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// CC1S
//
// [Bits 1..0] RW (@ 0x40002018) desc CC1S
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 0) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------- Field Item: TIM14_CCMR1_INPUT_IC1PSC ------------------------------
// SVD Line: 4596
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// IC1PSC
//
// [Bits 3..2] RW (@ 0x40002018) desc IC1PSC
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 2) & 0x3), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0x3UL << 2 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 2 ) ) ))
//
//
//
// --------------------------- Field Item: TIM14_CCMR1_INPUT_IC1F -------------------------------
// SVD Line: 4601
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
// IC1F
//
// [Bits 7..4] RW (@ 0x40002018) desc IC1F
//
// ( (unsigned char)((TIM14_CCMR1_INPUT >> 4) & 0xF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFUL << 4 )) | ((unsigned long)(Gui_u8:GuiVal & 0xF) << 4 ) ) ))
//
//
//
// ---------------------------- Register RTree: TIM14_CCMR1_INPUT -------------------------------
// SVD Line: 4584
// SFDITEM_REG__TIM14_CCMR1_INPUT
// CCMR1_INPUT
//
// [Bits 31..0] RW (@ 0x40002018) desc CCMR1:INPUT
// ( (unsigned int)((TIM14_CCMR1_INPUT >> 0) & 0xFFFFFFFF), ((TIM14_CCMR1_INPUT = (TIM14_CCMR1_INPUT & ~(0xFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_CC1S
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1PSC
// - SFDITEM_FIELD__TIM14_CCMR1_INPUT_IC1F
//
//
// ---------------------------- Register Item Address: TIM14_CCER -------------------------------
// SVD Line: 4608
unsigned int TIM14_CCER __AT (0x40002020);
// ------------------------------- Field Item: TIM14_CCER_CC1E ----------------------------------
// SVD Line: 4614
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// CC1E
//
// [Bit 0] RW (@ 0x40002020) desc CC1E
//
// ( (unsigned int) TIM14_CCER )
// CC1E
//
//
//
// ------------------------------- Field Item: TIM14_CCER_CC1P ----------------------------------
// SVD Line: 4619
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// CC1P
//
// [Bit 1] RW (@ 0x40002020) desc CC1P
//
// ( (unsigned int) TIM14_CCER )
// CC1P
//
//
//
// ------------------------------ Field Item: TIM14_CCER_CC1NP ----------------------------------
// SVD Line: 4624
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
// CC1NP
//
// [Bit 3] RW (@ 0x40002020) desc CC1NP
//
// ( (unsigned int) TIM14_CCER )
// CC1NP
//
//
//
// ------------------------------- Register RTree: TIM14_CCER -----------------------------------
// SVD Line: 4608
// SFDITEM_REG__TIM14_CCER
// CCER
//
// [Bits 31..0] RW (@ 0x40002020) desc CCER
// ( (unsigned int)((TIM14_CCER >> 0) & 0xFFFFFFFF), ((TIM14_CCER = (TIM14_CCER & ~(0xBUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xB) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCER_CC1E
// - SFDITEM_FIELD__TIM14_CCER_CC1P
// - SFDITEM_FIELD__TIM14_CCER_CC1NP
//
//
// ---------------------------- Register Item Address: TIM14_CNT --------------------------------
// SVD Line: 4631
unsigned int TIM14_CNT __AT (0x40002024);
// -------------------------------- Field Item: TIM14_CNT_CNT -----------------------------------
// SVD Line: 4637
// - SFDITEM_FIELD__TIM14_CNT_CNT
// CNT
//
// [Bits 15..0] RW (@ 0x40002024) desc CNT
//
// ( (unsigned short)((TIM14_CNT >> 0) & 0xFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_CNT -----------------------------------
// SVD Line: 4631
// SFDITEM_REG__TIM14_CNT
// CNT
//
// [Bits 31..0] RW (@ 0x40002024) desc CNT
// ( (unsigned int)((TIM14_CNT >> 0) & 0xFFFFFFFF), ((TIM14_CNT = (TIM14_CNT & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CNT_CNT
//
//
// ---------------------------- Register Item Address: TIM14_PSC --------------------------------
// SVD Line: 4644
unsigned int TIM14_PSC __AT (0x40002028);
// -------------------------------- Field Item: TIM14_PSC_PSC -----------------------------------
// SVD Line: 4650
// - SFDITEM_FIELD__TIM14_PSC_PSC
// PSC
//
// [Bits 15..0] RW (@ 0x40002028) desc PSC
//
// ( (unsigned short)((TIM14_PSC >> 0) & 0xFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_PSC -----------------------------------
// SVD Line: 4644
// SFDITEM_REG__TIM14_PSC
// PSC
//
// [Bits 31..0] RW (@ 0x40002028) desc PSC
// ( (unsigned int)((TIM14_PSC >> 0) & 0xFFFFFFFF), ((TIM14_PSC = (TIM14_PSC & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_PSC_PSC
//
//
// ---------------------------- Register Item Address: TIM14_ARR --------------------------------
// SVD Line: 4657
unsigned int TIM14_ARR __AT (0x4000202C);
// -------------------------------- Field Item: TIM14_ARR_ARR -----------------------------------
// SVD Line: 4664
// - SFDITEM_FIELD__TIM14_ARR_ARR
// ARR
//
// [Bits 15..0] RW (@ 0x4000202C) desc ARR
//
// ( (unsigned short)((TIM14_ARR >> 0) & 0xFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_ARR -----------------------------------
// SVD Line: 4657
// SFDITEM_REG__TIM14_ARR
// ARR
//
// [Bits 31..0] RW (@ 0x4000202C) desc ARR
// ( (unsigned int)((TIM14_ARR >> 0) & 0xFFFFFFFF), ((TIM14_ARR = (TIM14_ARR & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_ARR_ARR
//
//
// ---------------------------- Register Item Address: TIM14_CCR1 -------------------------------
// SVD Line: 4671
unsigned int TIM14_CCR1 __AT (0x40002034);
// ------------------------------- Field Item: TIM14_CCR1_CCR1 ----------------------------------
// SVD Line: 4677
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
// CCR1
//
// [Bits 15..0] RW (@ 0x40002034) desc CCR1
//
// ( (unsigned short)((TIM14_CCR1 >> 0) & 0xFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u16:GuiVal & 0xFFFF) << 0 ) ) ))
//
//
//
// ------------------------------- Register RTree: TIM14_CCR1 -----------------------------------
// SVD Line: 4671
// SFDITEM_REG__TIM14_CCR1
// CCR1
//
// [Bits 31..0] RW (@ 0x40002034) desc CCR1
// ( (unsigned int)((TIM14_CCR1 >> 0) & 0xFFFFFFFF), ((TIM14_CCR1 = (TIM14_CCR1 & ~(0xFFFFUL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0xFFFF) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_CCR1_CCR1
//
//
// ----------------------------- Register Item Address: TIM14_OR --------------------------------
// SVD Line: 4684
unsigned int TIM14_OR __AT (0x40002050);
// ------------------------------ Field Item: TIM14_OR_TI1_RMP ----------------------------------
// SVD Line: 4689
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
// TI1_RMP
//
// [Bits 1..0] RW (@ 0x40002050) desc TI1_RMP
//
// ( (unsigned char)((TIM14_OR >> 0) & 0x3), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u8:GuiVal & 0x3) << 0 ) ) ))
//
//
//
// -------------------------------- Register RTree: TIM14_OR ------------------------------------
// SVD Line: 4684
// SFDITEM_REG__TIM14_OR
// OR
//
// [Bits 31..0] RW (@ 0x40002050) desc OR
// ( (unsigned int)((TIM14_OR >> 0) & 0xFFFFFFFF), ((TIM14_OR = (TIM14_OR & ~(0x3UL << 0 )) | ((unsigned long)(Gui_u32:GuiVal & 0x3) << 0 ) ) ))
// - SFDITEM_FIELD__TIM14_OR_TI1_RMP
//
//
// --------------------------------- Peripheral View: TIM14 -------------------------------------
// SVD Line: 4435
// TIM14
// TIM14
// - SFDITEM_REG__TIM14_CR1
// - SFDITEM_REG__TIM14_DIER
// - SFDITEM_REG__TIM14_SR
// - SFDITEM_REG__TIM14_EGR
// - SFDITEM_REG__TIM14_CCMR1_OUTPUT
// - SFDITEM_REG__TIM14_CCMR1_INPUT
// - SFDITEM_REG__TIM14_CCER
// - SFDITEM_REG__TIM14_CNT
// - SFDITEM_REG__TIM14_PSC
// - SFDITEM_REG__TIM14_ARR
// - SFDITEM_REG__TIM14_CCR1
// - SFDITEM_REG__TIM14_OR
//
//
// ----------------------------- IRQ Num definition: PY32F001xx --------------------------------
// SVD Line: 2
// ------------------------------------------------------------------------------------------------
// ----- Interrupt Number Definition -----
// ------------------------------------------------------------------------------------------------
// ------------------------ ARM Cortex-M0+ Specific Interrupt Numbers ---------------------------
// Reset_IRQ
// Reset
// Reset Vector, invoked on Power up and warm reset
// 1
//
//
// NonMaskableInt_IRQ
// NonMaskableInt
// Non maskable Interrupt, cannot be stopped or preempted
// 2
//
//
// HardFault_IRQ
// HardFault
// Hard Fault, all classes of Fault
// 3
//
//
// SVCall_IRQ
// SVCall
// System Service Call via SVC instruction
// 11
//
//
// PendSV_IRQ
// PendSV
// Pendable request for system service
// 14
//
//
// SysTick_IRQ
// SysTick
// System Tick Timer
// 15
//
//
// -------------------------- PY32F001xx Specific Interrupt Numbers -----------------------------
// FLASH_IRQ
// FLASH
// FLASH global Interrupt
// 19
//
//
// RCC_IRQ
// RCC
// RCC global Interrupt
// 20
//
//
// EXTI0_1_IRQ
// EXTI0_1
// EXTI Line 0 and 1 Interrupt
// 21
//
//
// EXTI2_3_IRQ
// EXTI2_3
// EXTI Line 2 and 3 Interrupt
// 22
//
//
// EXTI4_15_IRQ
// EXTI4_15
// EXTI Line 4 to 15 Interrupt
// 23
//
//
// ADC_COMP_IRQ
// ADC_COMP
// ADC and COMP Interrupts
// 28
//
//
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_BRK_UP_TRG_COM
// TIM1 Break, Update, Trigger and Commutation Interrupt
// 29
//
//
// TIM1_CC_IRQ
// TIM1_CC
// TIM1 Capture Compare Interrupt
// 30
//
//
// LPTIM1_DAC_IRQ
// LPTIM1_DAC
// LPTIM1, DAC global Interrupts
// 33
//
//
// TIM14_IRQ
// TIM14
// TIM14 global Interrupt
// 35
//
//
// PY32F001xx_IRQTable
// PY32F001xx Interrupt Table
// 4
// Reset_IRQ
// NonMaskableInt_IRQ
// HardFault_IRQ
// SVCall_IRQ
// PendSV_IRQ
// SysTick_IRQ
// FLASH_IRQ
// RCC_IRQ
// EXTI0_1_IRQ
// EXTI2_3_IRQ
// EXTI4_15_IRQ
// ADC_COMP_IRQ
// TIM1_BRK_UP_TRG_COM_IRQ
// TIM1_CC_IRQ
// LPTIM1_DAC_IRQ
// TIM14_IRQ
//
// ------------------------------------ Menu: PY32F001xx ---------------------------------------
// SVD Line: 2
// ------------------------------ Peripheral Menu: 'PY32F001xx' ---------------------------------
// ------------------------------------------------------------------------------------------------
// ----- Main Menu -----
// ------------------------------------------------------------------------------------------------
// COMP
// COMP1
// COMP2
//
//
// CRC
// CRC
//
//
// DBGMCU
// DBGMCU
//
//
// EXTI
// EXTI
//
//
// Flash
// FLASH
//
//
// GPIO
// GPIOA
// GPIOB
// GPIOC
//
//
// IWDG
// IWDG
//
//
// LPTIM1
// LPTIM1
//
//
// PWR
// PWR
//
//
// RCC
// RCC
//
//
// SYSCFG
// SYSCFG
//
//
// TIM
// TIM1
// TIM14
//
//