main.c 2.7 KB

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  1. /* LED blink project for the STM32L031 */
  2. #include "stm32l031xx.h"
  3. #include "delay.h"
  4. volatile unsigned long SysTickCount = 0;
  5. void __attribute__ ((interrupt, used)) SysTick_Handler(void)
  6. {
  7. SysTickCount++;
  8. }
  9. void setHSIClock()
  10. {
  11. /* test if the current clock source is something else than HSI */
  12. if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
  13. {
  14. /* enable HSI */
  15. RCC->CR |= RCC_CR_HSION;
  16. /* wait until HSI becomes ready */
  17. while ( (RCC->CR & RCC_CR_HSIRDY) == 0 )
  18. ;
  19. /* enable the HSI "divide by 4" bit */
  20. RCC->CR |= (uint32_t)(RCC_CR_HSIDIVEN);
  21. /* wait until the "divide by 4" flag is enabled */
  22. while((RCC->CR & RCC_CR_HSIDIVF) == 0)
  23. ;
  24. /* then use the HSI clock */
  25. RCC->CFGR = (RCC->CFGR & (uint32_t) (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSI;
  26. /* wait until HSI clock is used */
  27. while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
  28. ;
  29. }
  30. /* disable PLL */
  31. RCC->CR &= (uint32_t)(~RCC_CR_PLLON);
  32. /* wait until PLL is inactive */
  33. while((RCC->CR & RCC_CR_PLLRDY) != 0)
  34. ;
  35. /* set latency to 1 wait state */
  36. FLASH->ACR |= FLASH_ACR_LATENCY;
  37. /* At this point the HSI runs with 4 MHz */
  38. /* Multiply by 16 device by 2 --> 32 MHz */
  39. RCC->CFGR = (RCC->CFGR & (~(RCC_CFGR_PLLMUL| RCC_CFGR_PLLDIV ))) | (RCC_CFGR_PLLMUL16 | RCC_CFGR_PLLDIV2);
  40. /* enable PLL */
  41. RCC->CR |= RCC_CR_PLLON;
  42. /* wait until the PLL is ready */
  43. while ((RCC->CR & RCC_CR_PLLRDY) == 0)
  44. ;
  45. /* use the PLL has clock source */
  46. RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL);
  47. /* wait until the PLL source is active */
  48. while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
  49. ;
  50. }
  51. int main()
  52. {
  53. setHSIClock();
  54. SystemCoreClockUpdate(); /* Update SystemCoreClock() */
  55. //SystemCoreClock = 32000000UL;
  56. RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
  57. __NOP();
  58. __NOP();
  59. GPIOA->MODER &= ~GPIO_MODER_MODE13; /* clear mode for PA13 */
  60. GPIOA->MODER |= GPIO_MODER_MODE13_0; /* Output mode for PA13 */
  61. GPIOA->OTYPER &= ~GPIO_OTYPER_OT_13; /* no Push/Pull for PA13 */
  62. GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED13; /* low speed for PA13 */
  63. GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD13; /* no pullup/pulldown for PA13 */
  64. GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */
  65. SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */
  66. SysTick->VAL = 0;
  67. SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */
  68. for(;;)
  69. {
  70. delay_micro_seconds(500000);
  71. GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic set PA13 */
  72. delay_micro_seconds(500000);
  73. GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */
  74. }
  75. }