main.c 12 KB

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  1. /*
  2. RTC for the STM32L031
  3. EXTI line
  4. 17 RTC alarm
  5. 19 RTC tamper & timestamp & CSS_LSE
  6. 20 RTC wakeup timer
  7. __enable_irq()
  8. __disable_irq()
  9. */
  10. #include "stm32l031xx.h"
  11. #include "delay.h"
  12. #include "u8g2.h"
  13. #include "rtc.h"
  14. #include "key.h"
  15. /*=======================================================================*/
  16. /* external functions */
  17. uint8_t u8x8_gpio_and_delay_stm32l0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr);
  18. /*=======================================================================*/
  19. /* global variables */
  20. #define TAMPER_SYSTICK_DELAY 5
  21. volatile unsigned long SysTickCount = 0;
  22. volatile unsigned long RTCIRQCount = 0;
  23. volatile unsigned long Tamper2Count = 0;
  24. volatile unsigned long Tamper3Count = 0;
  25. rtc_t rtc;
  26. u8g2_t u8g2;
  27. /*=======================================================================*/
  28. /* utility function */
  29. void enableRCCRTCWrite(void) U8G2_NOINLINE;
  30. void enableRCCRTCWrite(void)
  31. {
  32. //RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
  33. //PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
  34. }
  35. void disableRCCRTCWrite(void) U8G2_NOINLINE;
  36. void disableRCCRTCWrite(void)
  37. {
  38. //PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR and RTC */
  39. //RCC->APB1ENR &= ~RCC_APB1ENR_PWREN; /* disable power interface */
  40. }
  41. /*=======================================================================*/
  42. void __attribute__ ((interrupt, used)) SysTick_Handler(void)
  43. {
  44. SysTickCount++;
  45. if ( Tamper3Count > 0 )
  46. {
  47. Tamper3Count--;
  48. if ( Tamper3Count == 0 )
  49. {
  50. //enableRCCRTCWrite();
  51. RTC->ISR &= ~RTC_ISR_TAMP3F; /* clear tamper flag, allow new tamper event */
  52. //disableRCCRTCWrite();
  53. }
  54. }
  55. else
  56. {
  57. RTC->ISR &= ~RTC_ISR_TAMP3F; /* clear tamper flag, allow new tamper event */
  58. }
  59. if ( Tamper2Count > 0 )
  60. {
  61. Tamper2Count--;
  62. if ( Tamper2Count == 0 )
  63. {
  64. //enableRCCRTCWrite();
  65. RTC->ISR &= ~RTC_ISR_TAMP2F; /* clear tamper flag, allow new tamper event */
  66. //disableRCCRTCWrite();
  67. }
  68. }
  69. else
  70. {
  71. RTC->ISR &= ~RTC_ISR_TAMP2F; /* clear tamper flag, allow new tamper event */
  72. }
  73. }
  74. void __attribute__ ((interrupt, used)) RTC_IRQHandler(void)
  75. {
  76. //enableRCCRTCWrite();
  77. if ( (EXTI->PR & EXTI_PR_PIF20) != 0 ) /* interrupt caused by wake up */
  78. {
  79. EXTI->PR = EXTI_PR_PIF20; /* wake up is connected to line 20, clear this IRQ */
  80. }
  81. /* the wake up time flag must be cleared, otherwise no further IRQ will happen */
  82. /* in principle, this should happen only when a IRQ line 20 IRQ happens, but */
  83. /* it will be more safe to clear this flag for any interrupt */
  84. RTC->ISR &= ~RTC_ISR_WUTF; /* clear the wake up flag */
  85. if ( (EXTI->PR & EXTI_PR_PIF19) != 0 ) /* interrupt caused by tamper event */
  86. {
  87. EXTI->PR = EXTI_PR_PIF19; /* clear tamper IRQ */
  88. /* The TAMPxF flag has to be cleared, but this is done in the systick handler after some delay */
  89. //RTC->ISR &= ~RTC_ISR_TAMP3F;
  90. //RTC->ISR &= ~RTC_ISR_TAMP2F;
  91. if ( RTC->ISR & RTC_ISR_TAMP3F )
  92. {
  93. key_add(KEY_NEXT);
  94. Tamper3Count = TAMPER_SYSTICK_DELAY;
  95. }
  96. if ( RTC->ISR & RTC_ISR_TAMP2F )
  97. {
  98. key_add(KEY_SELECT);
  99. Tamper2Count = TAMPER_SYSTICK_DELAY;
  100. }
  101. }
  102. //disableRCCRTCWrite();
  103. RTCIRQCount++;
  104. }
  105. /*=======================================================================*/
  106. /*
  107. Enable several power regions: PWR, GPIOA
  108. Enable write access to RTC
  109. This must be executed after each reset.
  110. */
  111. void startUp(void)
  112. {
  113. RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
  114. RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */
  115. PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */
  116. }
  117. /*=======================================================================*/
  118. /*
  119. Set internal high speed clock as clock for the system
  120. Also call SystemCoreClockUpdate()
  121. This must be executed after each reset.
  122. */
  123. void startHSIClock()
  124. {
  125. /* test if the current clock source is something else than HSI */
  126. if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
  127. {
  128. /* enable HSI */
  129. RCC->CR |= RCC_CR_HSION;
  130. /* wait until HSI becomes ready */
  131. while ( (RCC->CR & RCC_CR_HSIRDY) == 0 )
  132. ;
  133. /* enable the HSI "divide by 4" bit */
  134. RCC->CR |= (uint32_t)(RCC_CR_HSIDIVEN);
  135. /* wait until the "divide by 4" flag is enabled */
  136. while((RCC->CR & RCC_CR_HSIDIVF) == 0)
  137. ;
  138. /* then use the HSI clock */
  139. RCC->CFGR = (RCC->CFGR & (uint32_t) (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSI;
  140. /* wait until HSI clock is used */
  141. while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
  142. ;
  143. }
  144. /* disable PLL */
  145. RCC->CR &= (uint32_t)(~RCC_CR_PLLON);
  146. /* wait until PLL is inactive */
  147. while((RCC->CR & RCC_CR_PLLRDY) != 0)
  148. ;
  149. /* set latency to 1 wait state */
  150. FLASH->ACR |= FLASH_ACR_LATENCY;
  151. /* At this point the HSI runs with 4 MHz */
  152. /* Multiply by 16 device by 2 --> 32 MHz */
  153. RCC->CFGR = (RCC->CFGR & (~(RCC_CFGR_PLLMUL| RCC_CFGR_PLLDIV ))) | (RCC_CFGR_PLLMUL16 | RCC_CFGR_PLLDIV2);
  154. /* enable PLL */
  155. RCC->CR |= RCC_CR_PLLON;
  156. /* wait until the PLL is ready */
  157. while ((RCC->CR & RCC_CR_PLLRDY) == 0)
  158. ;
  159. /* use the PLL has clock source */
  160. RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL);
  161. /* wait until the PLL source is active */
  162. while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
  163. ;
  164. }
  165. /*=======================================================================*/
  166. /*
  167. Setup systick interrupt.
  168. A call to SystemCoreClockUpdate() is required before calling this function.
  169. This must be executed after each reset.
  170. */
  171. void startSysTick(void)
  172. {
  173. SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */
  174. SysTick->VAL = 0;
  175. SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */
  176. }
  177. /*=======================================================================*/
  178. /*
  179. Setup u8g2
  180. This must be executed only after POR reset.
  181. */
  182. void initDisplay(void)
  183. {
  184. /* setup display */
  185. u8g2_Setup_ssd1306_i2c_128x64_noname_f(&u8g2, U8G2_R0, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0);
  186. u8g2_InitDisplay(&u8g2);
  187. u8g2_SetPowerSave(&u8g2, 0);
  188. u8g2_SetFont(&u8g2, u8g2_font_6x12_tf);
  189. u8g2_ClearBuffer(&u8g2);
  190. u8g2_DrawStr(&u8g2, 0,12, "STM32L031");
  191. u8g2_DrawStr(&u8g2, 0,24, u8x8_u8toa(SystemCoreClock/1000000, 2));
  192. u8g2_DrawStr(&u8g2, 20,24, "MHz");
  193. u8g2_SendBuffer(&u8g2);
  194. }
  195. /*=======================================================================*/
  196. /*
  197. configure and start RTC
  198. This must be executed only after POR reset.
  199. */
  200. void initRTC(void)
  201. {
  202. /* real time clock enable */
  203. //enableRCCRTCWrite();
  204. RTC->WPR = 0x0ca; /* disable RTC write protection */
  205. RTC->WPR = 0x053;
  206. /* externel 32K clock source */
  207. RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */
  208. /* externel 32K oscillator */
  209. //RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */
  210. //RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */
  211. //RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */
  212. RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */
  213. delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */
  214. /*
  215. if ( RCC->CSR & RCC_CSR_LSERDY )
  216. display_Write("32K Clock Ready\n");
  217. else
  218. display_Write("32K Clock Error\n");
  219. */
  220. RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */
  221. RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */
  222. RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */
  223. /* RTC Start */
  224. RTC->ISR = RTC_ISR_INIT; /* request RTC stop */
  225. while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */
  226. ;
  227. RTC->PRER = 0x07f00ff;
  228. RTC->TR = 0;
  229. RTC->ISR =~ RTC_ISR_INIT; /* start RTC */
  230. RTC->WPR = 0; /* enable RTC write protection */
  231. RTC->WPR = 0;
  232. //disableRCCRTCWrite();
  233. }
  234. /*=======================================================================*/
  235. /*
  236. enable RTC wakeup and interrupt
  237. This must be executed after any reset.
  238. */
  239. void startRTCWakeUp(void)
  240. {
  241. /* wake up time setup & start */
  242. //enableRCCRTCWrite();
  243. RTC->WPR = 0x0ca; /* disable RTC write protection */
  244. RTC->WPR = 0x053;
  245. RTC->CR &=~ RTC_CR_WUTE; /* disable wakeup timer for reprogramming */
  246. while((RTC->ISR & RTC_ISR_WUTWF) != RTC_ISR_WUTWF)
  247. ;
  248. RTC->WUTR = 0; /* reload is 1: 1Hz with the 1Hz clock */
  249. RTC->CR &= ~RTC_CR_WUCKSEL; /* clear selection register */
  250. RTC->CR |= RTC_CR_WUCKSEL_2; /* select the 1Hz clock */
  251. RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE ;
  252. RTC->ISR &= ~RTC_ISR_WUTF; /* clear the wake up flag... is this required? */
  253. /* tamper (button) detection */
  254. /* low level, filtered, pullup enabled, IRQ enabled, Sample Freq is 128Hz */
  255. RTC->TAMPCR =
  256. RTC_TAMPCR_TAMP3NOERASE | RTC_TAMPCR_TAMP3IE | RTC_TAMPCR_TAMP3E |
  257. RTC_TAMPCR_TAMP2NOERASE | RTC_TAMPCR_TAMP2IE | RTC_TAMPCR_TAMP2E |
  258. RTC_TAMPCR_TAMPPRCH_0 | RTC_TAMPCR_TAMPFLT_1 | RTC_TAMPCR_TAMPFREQ;
  259. /* wake up IRQ is connected to line 20 */
  260. EXTI->RTSR |= EXTI_RTSR_RT20; /* rising edge for wake up line */
  261. EXTI->IMR |= EXTI_IMR_IM20; /* interrupt enable */
  262. /* tamper IRQ is connected to line 19 */
  263. EXTI->RTSR |= EXTI_RTSR_RT19; /* rising edge for wake up line */
  264. EXTI->IMR |= EXTI_IMR_IM19; /* interrupt enable */
  265. RTC->WPR = 0; /* enable RTC write protection */
  266. RTC->WPR = 0;
  267. //disableRCCRTCWrite();
  268. }
  269. int cursor_pos = 0;
  270. int select_pos = 0;
  271. /*=======================================================================*/
  272. int main()
  273. {
  274. int i;
  275. startHSIClock();
  276. SystemCoreClockUpdate(); /* Update SystemCoreClock() */
  277. startUp();
  278. //SystemCoreClock = 32000000UL;
  279. startSysTick();
  280. RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
  281. __NOP();
  282. __NOP();
  283. /* LED output line */
  284. GPIOA->MODER &= ~GPIO_MODER_MODE13; /* clear mode for PA13 */
  285. GPIOA->MODER |= GPIO_MODER_MODE13_0; /* Output mode for PA13 */
  286. GPIOA->OTYPER &= ~GPIO_OTYPER_OT_13; /* Push/Pull for PA13 */
  287. GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED13; /* low speed for PA13 */
  288. GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD13; /* no pullup/pulldown for PA13 */
  289. GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */
  290. GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic set PA13 */
  291. /* PA0, button input */
  292. GPIOA->MODER &= ~GPIO_MODER_MODE0; /* clear mode for PA0 */
  293. GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD0; /* no pullup/pulldown for PA0 */
  294. GPIOA->PUPDR |= GPIO_PUPDR_PUPD0_0; /* pullup for PA0 */
  295. /* PA2, button input */
  296. GPIOA->MODER &= ~GPIO_MODER_MODE2; /* clear mode for PA2 */
  297. GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD2; /* no pullup/pulldown for PA2 */
  298. GPIOA->PUPDR |= GPIO_PUPDR_PUPD2_0; /* pullup for PA2 */
  299. initDisplay();
  300. initRTC();
  301. startRTCWakeUp();
  302. NVIC_SetPriority(RTC_IRQn, 0);
  303. NVIC_EnableIRQ(RTC_IRQn);
  304. for(;;)
  305. {
  306. u8g2_ClearBuffer(&u8g2);
  307. rtc_register_to_bcd(&rtc);
  308. rtc_bcd_to_ymd_hms(&rtc);
  309. rtc_draw_time(&rtc, &u8g2);
  310. RTC->WPR = 0x0ca; /* disable RTC write protection */
  311. RTC->WPR = 0x053;
  312. RTC->TAMPCR &= ~RTC_TAMPCR_TAMP3E;
  313. RTC->TAMPCR &= ~RTC_TAMPCR_TAMP2E;
  314. __NOP(); /* add delay after disable tamper so that GPO can read the value */
  315. __NOP();
  316. if ( GPIOA->IDR & GPIO_IDR_ID0 )
  317. u8g2_DrawStr(&u8g2, 15, 45, "+");
  318. else
  319. u8g2_DrawStr(&u8g2, 15, 45, "-");
  320. if ( GPIOA->IDR & GPIO_IDR_ID2 )
  321. u8g2_DrawStr(&u8g2, 0, 45, "+");
  322. else
  323. u8g2_DrawStr(&u8g2, 0, 45, "-");
  324. RTC->TAMPCR |= RTC_TAMPCR_TAMP3E;
  325. RTC->TAMPCR |= RTC_TAMPCR_TAMP2E;
  326. RTC->WPR = 0; /* enable RTC write protection */
  327. RTC->WPR = 0;
  328. u8g2_DrawStr(&u8g2, 30,45, u8x8_u8toa(RTCIRQCount, 3));
  329. u8g2_DrawStr(&u8g2, 90,45, u8x8_u8toa(key_queue_start, 2));
  330. for( i = 0; i < 4; i++ )
  331. {
  332. if ( i == select_pos )
  333. u8g2_DrawBox(&u8g2, i*20+10, 50, 10, 10);
  334. else
  335. u8g2_DrawFrame(&u8g2, i*20+10, 50, 10, 10);
  336. if ( i == cursor_pos )
  337. u8g2_DrawFrame(&u8g2, i*20+10-1, 50-1, 10+2, 10+2);
  338. }
  339. u8g2_SendBuffer(&u8g2);
  340. delay_micro_seconds(50000);
  341. GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic set PA13 */
  342. delay_micro_seconds(50000);
  343. GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic clr PA13 */
  344. for(;;)
  345. {
  346. i = key_get();
  347. if ( i == KEY_NONE )
  348. break;
  349. if ( i == KEY_SELECT )
  350. select_pos = cursor_pos;
  351. if ( i == KEY_NEXT )
  352. cursor_pos = ( cursor_pos + 1 ) & 3;
  353. }
  354. //display_WriteUnsigned(RTC->TR);
  355. //display_Write("\n");
  356. }
  357. }